1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
37 #include <linux/string_choices.h>
38
39 #include "i2c-stm32.h"
40
41 /* STM32F7 I2C registers */
42 #define STM32F7_I2C_CR1 0x00
43 #define STM32F7_I2C_CR2 0x04
44 #define STM32F7_I2C_OAR1 0x08
45 #define STM32F7_I2C_OAR2 0x0C
46 #define STM32F7_I2C_PECR 0x20
47 #define STM32F7_I2C_TIMINGR 0x10
48 #define STM32F7_I2C_ISR 0x18
49 #define STM32F7_I2C_ICR 0x1C
50 #define STM32F7_I2C_RXDR 0x24
51 #define STM32F7_I2C_TXDR 0x28
52
53 /* STM32F7 I2C control 1 */
54 #define STM32_I2C_CR1_FMP BIT(24)
55 #define STM32F7_I2C_CR1_PECEN BIT(23)
56 #define STM32F7_I2C_CR1_ALERTEN BIT(22)
57 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
58 #define STM32F7_I2C_CR1_WUPEN BIT(18)
59 #define STM32F7_I2C_CR1_SBC BIT(16)
60 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
61 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
62 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
63 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
64 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
65 #define STM32F7_I2C_CR1_ERRIE BIT(7)
66 #define STM32F7_I2C_CR1_TCIE BIT(6)
67 #define STM32F7_I2C_CR1_STOPIE BIT(5)
68 #define STM32F7_I2C_CR1_NACKIE BIT(4)
69 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
70 #define STM32F7_I2C_CR1_RXIE BIT(2)
71 #define STM32F7_I2C_CR1_TXIE BIT(1)
72 #define STM32F7_I2C_CR1_PE BIT(0)
73 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
74 | STM32F7_I2C_CR1_TCIE \
75 | STM32F7_I2C_CR1_STOPIE \
76 | STM32F7_I2C_CR1_NACKIE \
77 | STM32F7_I2C_CR1_RXIE \
78 | STM32F7_I2C_CR1_TXIE)
79 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
80 | STM32F7_I2C_CR1_STOPIE \
81 | STM32F7_I2C_CR1_NACKIE \
82 | STM32F7_I2C_CR1_RXIE \
83 | STM32F7_I2C_CR1_TXIE)
84
85 /* STM32F7 I2C control 2 */
86 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
87 #define STM32F7_I2C_CR2_RELOAD BIT(24)
88 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
89 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
90 #define STM32F7_I2C_CR2_NACK BIT(15)
91 #define STM32F7_I2C_CR2_STOP BIT(14)
92 #define STM32F7_I2C_CR2_START BIT(13)
93 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
94 #define STM32F7_I2C_CR2_ADD10 BIT(11)
95 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
96 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
97 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
98 STM32F7_I2C_CR2_SADD10_MASK))
99 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
100 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
101
102 /* STM32F7 I2C Own Address 1 */
103 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
104 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
105 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
106 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
107 STM32F7_I2C_OAR1_OA1_10_MASK))
108 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
109 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
110 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
111 | STM32F7_I2C_OAR1_OA1_10_MASK \
112 | STM32F7_I2C_OAR1_OA1EN \
113 | STM32F7_I2C_OAR1_OA1MODE)
114
115 /* STM32F7 I2C Own Address 2 */
116 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
117 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
118 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
119 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
120 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
121 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
122 | STM32F7_I2C_OAR2_OA2_7_MASK \
123 | STM32F7_I2C_OAR2_OA2EN)
124
125 /* STM32F7 I2C Interrupt Status */
126 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
127 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
128 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
129 #define STM32F7_I2C_ISR_DIR BIT(16)
130 #define STM32F7_I2C_ISR_BUSY BIT(15)
131 #define STM32F7_I2C_ISR_ALERT BIT(13)
132 #define STM32F7_I2C_ISR_PECERR BIT(11)
133 #define STM32F7_I2C_ISR_ARLO BIT(9)
134 #define STM32F7_I2C_ISR_BERR BIT(8)
135 #define STM32F7_I2C_ISR_TCR BIT(7)
136 #define STM32F7_I2C_ISR_TC BIT(6)
137 #define STM32F7_I2C_ISR_STOPF BIT(5)
138 #define STM32F7_I2C_ISR_NACKF BIT(4)
139 #define STM32F7_I2C_ISR_ADDR BIT(3)
140 #define STM32F7_I2C_ISR_RXNE BIT(2)
141 #define STM32F7_I2C_ISR_TXIS BIT(1)
142 #define STM32F7_I2C_ISR_TXE BIT(0)
143
144 /* STM32F7 I2C Interrupt Clear */
145 #define STM32F7_I2C_ICR_ALERTCF BIT(13)
146 #define STM32F7_I2C_ICR_PECCF BIT(11)
147 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
148 #define STM32F7_I2C_ICR_BERRCF BIT(8)
149 #define STM32F7_I2C_ICR_STOPCF BIT(5)
150 #define STM32F7_I2C_ICR_NACKCF BIT(4)
151 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
152
153 /* STM32F7 I2C Timing */
154 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
155 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
156 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
157 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
158 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
159
160 #define STM32F7_I2C_MAX_LEN 0xff
161 #define STM32F7_I2C_DMA_LEN_MIN 0x16
162 enum {
163 STM32F7_SLAVE_HOSTNOTIFY,
164 STM32F7_SLAVE_7_10_BITS_ADDR,
165 STM32F7_SLAVE_7_BITS_ADDR,
166 STM32F7_I2C_MAX_SLAVE
167 };
168
169 #define STM32F7_I2C_DNF_DEFAULT 0
170 #define STM32F7_I2C_DNF_MAX 15
171
172 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
173 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
174
175 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
176 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
177
178 #define STM32F7_PRESC_MAX BIT(4)
179 #define STM32F7_SCLDEL_MAX BIT(4)
180 #define STM32F7_SDADEL_MAX BIT(4)
181 #define STM32F7_SCLH_MAX BIT(8)
182 #define STM32F7_SCLL_MAX BIT(8)
183
184 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
185
186 /**
187 * struct stm32f7_i2c_regs - i2c f7 registers backup
188 * @cr1: Control register 1
189 * @cr2: Control register 2
190 * @oar1: Own address 1 register
191 * @oar2: Own address 2 register
192 * @tmgr: Timing register
193 */
194 struct stm32f7_i2c_regs {
195 u32 cr1;
196 u32 cr2;
197 u32 oar1;
198 u32 oar2;
199 u32 tmgr;
200 };
201
202 /**
203 * struct stm32f7_i2c_spec - private i2c specification timing
204 * @rate: I2C bus speed (Hz)
205 * @fall_max: Max fall time of both SDA and SCL signals (ns)
206 * @rise_max: Max rise time of both SDA and SCL signals (ns)
207 * @hddat_min: Min data hold time (ns)
208 * @vddat_max: Max data valid time (ns)
209 * @sudat_min: Min data setup time (ns)
210 * @l_min: Min low period of the SCL clock (ns)
211 * @h_min: Min high period of the SCL clock (ns)
212 */
213 struct stm32f7_i2c_spec {
214 u32 rate;
215 u32 fall_max;
216 u32 rise_max;
217 u32 hddat_min;
218 u32 vddat_max;
219 u32 sudat_min;
220 u32 l_min;
221 u32 h_min;
222 };
223
224 /**
225 * struct stm32f7_i2c_setup - private I2C timing setup parameters
226 * @speed_freq: I2C speed frequency (Hz)
227 * @clock_src: I2C clock source frequency (Hz)
228 * @rise_time: Rise time (ns)
229 * @fall_time: Fall time (ns)
230 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
231 * @single_it_line: Only a single IT line is used for both events/errors
232 * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1
233 */
234 struct stm32f7_i2c_setup {
235 u32 speed_freq;
236 u32 clock_src;
237 u32 rise_time;
238 u32 fall_time;
239 u32 fmp_clr_offset;
240 bool single_it_line;
241 bool fmp_cr1_bit;
242 };
243
244 /**
245 * struct stm32f7_i2c_timings - private I2C output parameters
246 * @node: List entry
247 * @presc: Prescaler value
248 * @scldel: Data setup time
249 * @sdadel: Data hold time
250 * @sclh: SCL high period (master mode)
251 * @scll: SCL low period (master mode)
252 */
253 struct stm32f7_i2c_timings {
254 struct list_head node;
255 u8 presc;
256 u8 scldel;
257 u8 sdadel;
258 u8 sclh;
259 u8 scll;
260 };
261
262 /**
263 * struct stm32f7_i2c_msg - client specific data
264 * @addr: 8-bit or 10-bit slave addr, including r/w bit
265 * @count: number of bytes to be transferred
266 * @buf: data buffer
267 * @result: result of the transfer
268 * @stop: last I2C msg to be sent, i.e. STOP to be generated
269 * @smbus: boolean to know if the I2C IP is used in SMBus mode
270 * @size: type of SMBus protocol
271 * @read_write: direction of SMBus protocol
272 * SMBus block read and SMBus block write - block read process call protocols
273 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
274 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
275 * This buffer has to be 32-bit aligned to be compliant with memory address
276 * register in DMA mode.
277 */
278 struct stm32f7_i2c_msg {
279 u16 addr;
280 u32 count;
281 u8 *buf;
282 int result;
283 bool stop;
284 bool smbus;
285 int size;
286 char read_write;
287 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
288 };
289
290 /**
291 * struct stm32f7_i2c_alert - SMBus alert specific data
292 * @setup: platform data for the smbus_alert i2c client
293 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
294 * Response Address
295 */
296 struct stm32f7_i2c_alert {
297 struct i2c_smbus_alert_setup setup;
298 struct i2c_client *ara;
299 };
300
301 /**
302 * struct stm32f7_i2c_dev - private data of the controller
303 * @adap: I2C adapter for this controller
304 * @dev: device for this controller
305 * @base: virtual memory area
306 * @complete: completion of I2C message
307 * @clk: hw i2c clock
308 * @bus_rate: I2C clock frequency of the controller
309 * @msg: Pointer to data to be written
310 * @msg_num: number of I2C messages to be executed
311 * @msg_id: message identifiant
312 * @f7_msg: customized i2c msg for driver usage
313 * @setup: I2C timing input setup
314 * @timing: I2C computed timings
315 * @slave: list of slave devices registered on the I2C bus
316 * @slave_running: slave device currently used
317 * @backup_regs: backup of i2c controller registers (for suspend/resume)
318 * @slave_dir: transfer direction for the current slave device
319 * @master_mode: boolean to know in which mode the I2C is running (master or
320 * slave)
321 * @dma: dma data
322 * @use_dma: boolean to know if dma is used in the current transfer
323 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
324 * @fmp_sreg: register address for setting Fast Mode Plus bits
325 * @fmp_creg: register address for clearing Fast Mode Plus bits
326 * @fmp_mask: mask for Fast Mode Plus bits in set register
327 * @wakeup_src: boolean to know if the device is a wakeup source
328 * @smbus_mode: states that the controller is configured in SMBus mode
329 * @host_notify_client: SMBus host-notify client
330 * @analog_filter: boolean to indicate enabling of the analog filter
331 * @dnf_dt: value of digital filter requested via dt
332 * @dnf: value of digital filter to apply
333 * @alert: SMBus alert specific data
334 * @atomic: boolean indicating that current transfer is atomic
335 */
336 struct stm32f7_i2c_dev {
337 struct i2c_adapter adap;
338 struct device *dev;
339 void __iomem *base;
340 struct completion complete;
341 struct clk *clk;
342 unsigned int bus_rate;
343 struct i2c_msg *msg;
344 unsigned int msg_num;
345 unsigned int msg_id;
346 struct stm32f7_i2c_msg f7_msg;
347 struct stm32f7_i2c_setup setup;
348 struct stm32f7_i2c_timings timing;
349 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
350 struct i2c_client *slave_running;
351 struct stm32f7_i2c_regs backup_regs;
352 u32 slave_dir;
353 bool master_mode;
354 struct stm32_i2c_dma *dma;
355 bool use_dma;
356 struct regmap *regmap;
357 u32 fmp_sreg;
358 u32 fmp_creg;
359 u32 fmp_mask;
360 bool wakeup_src;
361 bool smbus_mode;
362 struct i2c_client *host_notify_client;
363 bool analog_filter;
364 u32 dnf_dt;
365 u32 dnf;
366 struct stm32f7_i2c_alert *alert;
367 bool atomic;
368 };
369
370 /*
371 * All these values are coming from I2C Specification, Version 6.0, 4th of
372 * April 2014.
373 *
374 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
375 * and Fast-mode Plus I2C-bus devices
376 */
377 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
378 {
379 .rate = I2C_MAX_STANDARD_MODE_FREQ,
380 .fall_max = 300,
381 .rise_max = 1000,
382 .hddat_min = 0,
383 .vddat_max = 3450,
384 .sudat_min = 250,
385 .l_min = 4700,
386 .h_min = 4000,
387 },
388 {
389 .rate = I2C_MAX_FAST_MODE_FREQ,
390 .fall_max = 300,
391 .rise_max = 300,
392 .hddat_min = 0,
393 .vddat_max = 900,
394 .sudat_min = 100,
395 .l_min = 1300,
396 .h_min = 600,
397 },
398 {
399 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
400 .fall_max = 100,
401 .rise_max = 120,
402 .hddat_min = 0,
403 .vddat_max = 450,
404 .sudat_min = 50,
405 .l_min = 500,
406 .h_min = 260,
407 },
408 };
409
410 static const struct stm32f7_i2c_setup stm32f7_setup = {
411 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
412 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
413 };
414
415 static const struct stm32f7_i2c_setup stm32mp15_setup = {
416 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
417 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
418 .fmp_clr_offset = 0x40,
419 };
420
421 static const struct stm32f7_i2c_setup stm32mp13_setup = {
422 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
423 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
424 .fmp_clr_offset = 0x4,
425 };
426
427 static const struct stm32f7_i2c_setup stm32mp25_setup = {
428 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
429 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
430 .single_it_line = true,
431 .fmp_cr1_bit = true,
432 };
433
stm32f7_i2c_set_bits(void __iomem * reg,u32 mask)434 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
435 {
436 writel_relaxed(readl_relaxed(reg) | mask, reg);
437 }
438
stm32f7_i2c_clr_bits(void __iomem * reg,u32 mask)439 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
440 {
441 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
442 }
443
stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev * i2c_dev,u32 mask)444 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
445 {
446 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
447 }
448
stm32f7_get_specs(u32 rate)449 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
450 {
451 int i;
452
453 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
454 if (rate <= stm32f7_i2c_specs[i].rate)
455 return &stm32f7_i2c_specs[i];
456
457 return ERR_PTR(-EINVAL);
458 }
459
460 #define RATE_MIN(rate) ((rate) * 8 / 10)
stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup,struct stm32f7_i2c_timings * output)461 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
462 struct stm32f7_i2c_setup *setup,
463 struct stm32f7_i2c_timings *output)
464 {
465 struct stm32f7_i2c_spec *specs;
466 u32 p_prev = STM32F7_PRESC_MAX;
467 /*
468 * Truncate instead of rounding to closest: if the clock period is
469 * overestimated, the computed SCL timings will come out shorter on
470 * the wire, which can push the bus above the target rate and below
471 * the spec's tLOW/tHIGH minimums.
472 */
473 u32 i2cclk = NSEC_PER_SEC / setup->clock_src;
474 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
475 setup->speed_freq);
476 u32 clk_error_prev = i2cbus;
477 u32 tsync;
478 u32 af_delay_min, af_delay_max;
479 u32 dnf_delay;
480 u32 clk_min, clk_max;
481 int sdadel_min, sdadel_max;
482 int scldel_min;
483 struct stm32f7_i2c_timings *v, *_v, *s;
484 struct list_head solutions;
485 u16 p, l, a, h;
486 int ret = 0;
487
488 specs = stm32f7_get_specs(setup->speed_freq);
489 if (specs == ERR_PTR(-EINVAL))
490 return dev_err_probe(i2c_dev->dev, -EINVAL, "speed out of bound {%d}\n",
491 setup->speed_freq);
492
493 if ((setup->rise_time > specs->rise_max) ||
494 (setup->fall_time > specs->fall_max))
495 return dev_err_probe(i2c_dev->dev, -EINVAL,
496 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
497 setup->rise_time, specs->rise_max,
498 setup->fall_time, specs->fall_max);
499
500 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
501 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX)
502 return dev_err_probe(i2c_dev->dev, -EINVAL,
503 "DNF out of bound %d/%d\n", i2c_dev->dnf * i2cclk,
504 STM32F7_I2C_DNF_MAX * i2cclk);
505
506 /* Analog and Digital Filters */
507 af_delay_min =
508 (i2c_dev->analog_filter ?
509 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
510 af_delay_max =
511 (i2c_dev->analog_filter ?
512 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
513 dnf_delay = i2c_dev->dnf * i2cclk;
514
515 sdadel_min = specs->hddat_min + setup->fall_time -
516 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
517
518 sdadel_max = specs->vddat_max - setup->rise_time -
519 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
520
521 scldel_min = setup->rise_time + specs->sudat_min;
522
523 if (sdadel_min < 0)
524 sdadel_min = 0;
525 if (sdadel_max < 0)
526 sdadel_max = 0;
527
528 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
529 sdadel_min, sdadel_max, scldel_min);
530
531 INIT_LIST_HEAD(&solutions);
532 /* Compute possible values for PRESC, SCLDEL and SDADEL */
533 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
534 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
535 u32 scldel = (l + 1) * (p + 1) * i2cclk;
536
537 if (scldel < scldel_min)
538 continue;
539
540 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
541 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
542
543 if (((sdadel >= sdadel_min) &&
544 (sdadel <= sdadel_max)) &&
545 (p != p_prev)) {
546 v = kmalloc_obj(*v);
547 if (!v) {
548 ret = -ENOMEM;
549 goto exit;
550 }
551
552 v->presc = p;
553 v->scldel = l;
554 v->sdadel = a;
555 p_prev = p;
556
557 list_add_tail(&v->node,
558 &solutions);
559 break;
560 }
561 }
562
563 if (p_prev == p)
564 break;
565 }
566 }
567
568 if (list_empty(&solutions)) {
569 ret = dev_err_probe(i2c_dev->dev, -EPERM, "no Prescaler solution\n");
570 goto exit;
571 }
572
573 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
574 s = NULL;
575 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
576 clk_min = NSEC_PER_SEC / setup->speed_freq;
577
578 /*
579 * Among Prescaler possibilities discovered above figures out SCL Low
580 * and High Period. Provided:
581 * - SCL Low Period has to be higher than SCL Clock Low Period
582 * defined by I2C Specification. I2C Clock has to be lower than
583 * (SCL Low Period - Analog/Digital filters) / 4.
584 * - SCL High Period has to be lower than SCL Clock High Period
585 * defined by I2C Specification
586 * - I2C Clock has to be lower than SCL High Period
587 */
588 list_for_each_entry(v, &solutions, node) {
589 u32 prescaler = (v->presc + 1) * i2cclk;
590
591 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
592 u32 tscl_l = (l + 1) * prescaler + tsync;
593
594 if ((tscl_l < specs->l_min) ||
595 (i2cclk >=
596 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
597 continue;
598 }
599
600 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
601 u32 tscl_h = (h + 1) * prescaler + tsync;
602 u32 tscl = tscl_l + tscl_h +
603 setup->rise_time + setup->fall_time;
604
605 if ((tscl >= clk_min) && (tscl <= clk_max) &&
606 (tscl_h >= specs->h_min) &&
607 (i2cclk < tscl_h)) {
608 int clk_error = tscl - i2cbus;
609
610 if (clk_error < 0)
611 clk_error = -clk_error;
612
613 if (clk_error < clk_error_prev) {
614 clk_error_prev = clk_error;
615 v->scll = l;
616 v->sclh = h;
617 s = v;
618 }
619 }
620 }
621 }
622 }
623
624 if (!s) {
625 ret = dev_err_probe(i2c_dev->dev, -EPERM, "no solution at all\n");
626 goto exit;
627 }
628
629 output->presc = s->presc;
630 output->scldel = s->scldel;
631 output->sdadel = s->sdadel;
632 output->scll = s->scll;
633 output->sclh = s->sclh;
634
635 dev_dbg(i2c_dev->dev,
636 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
637 output->presc,
638 output->scldel, output->sdadel,
639 output->scll, output->sclh);
640
641 exit:
642 /* Release list and memory */
643 list_for_each_entry_safe(v, _v, &solutions, node) {
644 list_del(&v->node);
645 kfree(v);
646 }
647
648 return ret;
649 }
650
stm32f7_get_lower_rate(u32 rate)651 static u32 stm32f7_get_lower_rate(u32 rate)
652 {
653 int i = ARRAY_SIZE(stm32f7_i2c_specs);
654
655 while (--i)
656 if (stm32f7_i2c_specs[i].rate < rate)
657 break;
658
659 return stm32f7_i2c_specs[i].rate;
660 }
661
stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup)662 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
663 struct stm32f7_i2c_setup *setup)
664 {
665 struct i2c_timings timings, *t = &timings;
666 int ret = 0;
667
668 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
669 t->scl_rise_ns = i2c_dev->setup.rise_time;
670 t->scl_fall_ns = i2c_dev->setup.fall_time;
671
672 i2c_parse_fw_timings(i2c_dev->dev, t, false);
673
674 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
675 return dev_err_probe(i2c_dev->dev, -EINVAL, "Invalid bus speed (%i>%i)\n",
676 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
677
678 setup->speed_freq = t->bus_freq_hz;
679 i2c_dev->setup.rise_time = t->scl_rise_ns;
680 i2c_dev->setup.fall_time = t->scl_fall_ns;
681 i2c_dev->dnf_dt = t->digital_filter_width_ns;
682 setup->clock_src = clk_get_rate(i2c_dev->clk);
683
684 if (!setup->clock_src)
685 return dev_err_probe(i2c_dev->dev, -EINVAL, "clock rate is 0\n");
686
687 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
688 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
689
690 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
691 "i2c-analog-filter");
692
693 do {
694 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
695 &i2c_dev->timing);
696 if (ret) {
697 dev_err_probe(i2c_dev->dev, ret,
698 "failed to compute I2C timings.\n");
699 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
700 break;
701 setup->speed_freq =
702 stm32f7_get_lower_rate(setup->speed_freq);
703 dev_warn(i2c_dev->dev,
704 "downgrade I2C Speed Freq to (%i)\n",
705 setup->speed_freq);
706 }
707 } while (ret);
708
709 if (ret)
710 return dev_err_probe(i2c_dev->dev, ret, "Impossible to compute I2C timings.\n");
711
712 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
713 setup->speed_freq, setup->clock_src);
714 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
715 setup->rise_time, setup->fall_time);
716 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
717 str_on_off(i2c_dev->analog_filter), i2c_dev->dnf);
718
719 i2c_dev->bus_rate = setup->speed_freq;
720
721 return 0;
722 }
723
stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev * i2c_dev)724 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
725 {
726 void __iomem *base = i2c_dev->base;
727 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
728
729 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
730 }
731
stm32f7_i2c_dma_callback(void * arg)732 static void stm32f7_i2c_dma_callback(void *arg)
733 {
734 struct stm32f7_i2c_dev *i2c_dev = arg;
735 struct stm32_i2c_dma *dma = i2c_dev->dma;
736 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
737
738 stm32f7_i2c_disable_dma_req(i2c_dev);
739 dmaengine_terminate_async(dma->chan_using);
740 dma_unmap_single(i2c_dev->dev, dma->dma_buf, dma->dma_len,
741 dma->dma_data_dir);
742 if (!f7_msg->smbus)
743 i2c_put_dma_safe_msg_buf(f7_msg->buf, i2c_dev->msg, true);
744 complete(&dma->dma_complete);
745 }
746
stm32f7_i2c_hw_config(struct stm32f7_i2c_dev * i2c_dev)747 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
748 {
749 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
750 u32 timing = 0;
751
752 /* Timing settings */
753 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
754 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
755 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
756 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
757 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
758 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
759
760 /* Configure the Analog Filter */
761 if (i2c_dev->analog_filter)
762 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
763 STM32F7_I2C_CR1_ANFOFF);
764 else
765 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
766 STM32F7_I2C_CR1_ANFOFF);
767
768 /* Program the Digital Filter */
769 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
770 STM32F7_I2C_CR1_DNF_MASK);
771 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
772 STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
773
774 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
775 STM32F7_I2C_CR1_PE);
776 }
777
stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev * i2c_dev)778 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
779 {
780 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
781 void __iomem *base = i2c_dev->base;
782
783 if (f7_msg->count) {
784 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
785 f7_msg->count--;
786 }
787 }
788
stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev * i2c_dev)789 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
790 {
791 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
792 void __iomem *base = i2c_dev->base;
793
794 if (f7_msg->count) {
795 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
796 f7_msg->count--;
797 } else {
798 /* Flush RX buffer has no data is expected */
799 readb_relaxed(base + STM32F7_I2C_RXDR);
800 }
801 }
802
stm32f7_i2c_reload(struct stm32f7_i2c_dev * i2c_dev)803 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
804 {
805 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
806 u32 cr2;
807
808 if (i2c_dev->use_dma)
809 f7_msg->count -= STM32F7_I2C_MAX_LEN;
810
811 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
812
813 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
814 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
815 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
816 } else {
817 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
818 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
819 }
820
821 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
822 }
823
stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev * i2c_dev)824 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
825 {
826 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
827 u32 cr2;
828 u8 *val;
829
830 /*
831 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
832 * data received inform us how many data will follow.
833 */
834 stm32f7_i2c_read_rx_data(i2c_dev);
835
836 /*
837 * Update NBYTES with the value read to continue the transfer
838 */
839 val = f7_msg->buf - sizeof(u8);
840 f7_msg->count = *val;
841 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
842 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
843 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
844 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
845 }
846
stm32f7_i2c_release_bus(struct i2c_adapter * i2c_adap)847 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
848 {
849 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
850
851 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
852 STM32F7_I2C_CR1_PE);
853
854 stm32f7_i2c_hw_config(i2c_dev);
855 }
856
stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev * i2c_dev)857 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
858 {
859 u32 status;
860 int ret;
861
862 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
863 status,
864 !(status & STM32F7_I2C_ISR_BUSY),
865 10, 1000);
866 if (!ret)
867 return 0;
868
869 stm32f7_i2c_release_bus(&i2c_dev->adap);
870
871 return -EBUSY;
872 }
873
stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,struct i2c_msg * msg)874 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
875 struct i2c_msg *msg)
876 {
877 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
878 void __iomem *base = i2c_dev->base;
879 u8 *dma_buf;
880 u32 cr1, cr2;
881 int ret;
882
883 f7_msg->addr = msg->addr;
884 f7_msg->buf = msg->buf;
885 f7_msg->count = msg->len;
886 f7_msg->result = 0;
887 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
888
889 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
890 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
891
892 /* Set transfer direction */
893 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
894 if (msg->flags & I2C_M_RD)
895 cr2 |= STM32F7_I2C_CR2_RD_WRN;
896
897 /* Set slave address */
898 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
899 if (msg->flags & I2C_M_TEN) {
900 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
901 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
902 cr2 |= STM32F7_I2C_CR2_ADD10;
903 } else {
904 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
905 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
906 }
907
908 /* Set nb bytes to transfer and reload if needed */
909 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
910 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
911 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
912 cr2 |= STM32F7_I2C_CR2_RELOAD;
913 } else {
914 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
915 }
916
917 /* Enable NACK, STOP, error and transfer complete interrupts */
918 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
919 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
920
921 /* Clear DMA req and TX/RX interrupt */
922 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
923 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
924
925 /* Configure DMA or enable RX/TX interrupt */
926 i2c_dev->use_dma = false;
927 if (i2c_dev->dma && !i2c_dev->atomic) {
928 dma_buf = i2c_get_dma_safe_msg_buf(msg, STM32F7_I2C_DMA_LEN_MIN);
929 if (dma_buf) {
930 f7_msg->buf = dma_buf;
931 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
932 msg->flags & I2C_M_RD,
933 f7_msg->count, f7_msg->buf,
934 stm32f7_i2c_dma_callback,
935 i2c_dev);
936 if (ret) {
937 dev_warn(i2c_dev->dev, "can't use DMA\n");
938 i2c_put_dma_safe_msg_buf(f7_msg->buf, msg, false);
939 f7_msg->buf = msg->buf;
940 } else {
941 i2c_dev->use_dma = true;
942 }
943 }
944 }
945
946 if (!i2c_dev->use_dma) {
947 if (msg->flags & I2C_M_RD)
948 cr1 |= STM32F7_I2C_CR1_RXIE;
949 else
950 cr1 |= STM32F7_I2C_CR1_TXIE;
951 } else {
952 if (msg->flags & I2C_M_RD)
953 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
954 else
955 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
956 }
957
958 if (i2c_dev->atomic)
959 cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */
960
961 /* Configure Start/Repeated Start */
962 cr2 |= STM32F7_I2C_CR2_START;
963
964 i2c_dev->master_mode = true;
965
966 /* Write configurations registers */
967 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
968 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
969 }
970
stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,unsigned short flags,u8 command,union i2c_smbus_data * data)971 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
972 unsigned short flags, u8 command,
973 union i2c_smbus_data *data)
974 {
975 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
976 struct device *dev = i2c_dev->dev;
977 void __iomem *base = i2c_dev->base;
978 u32 cr1, cr2;
979 int i, ret;
980
981 f7_msg->result = 0;
982 reinit_completion(&i2c_dev->complete);
983
984 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
985 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
986
987 /* Set transfer direction */
988 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
989 if (f7_msg->read_write)
990 cr2 |= STM32F7_I2C_CR2_RD_WRN;
991
992 /* Set slave address */
993 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
994 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
995
996 f7_msg->smbus_buf[0] = command;
997 switch (f7_msg->size) {
998 case I2C_SMBUS_QUICK:
999 f7_msg->stop = true;
1000 f7_msg->count = 0;
1001 break;
1002 case I2C_SMBUS_BYTE:
1003 f7_msg->stop = true;
1004 f7_msg->count = 1;
1005 break;
1006 case I2C_SMBUS_BYTE_DATA:
1007 if (f7_msg->read_write) {
1008 f7_msg->stop = false;
1009 f7_msg->count = 1;
1010 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1011 } else {
1012 f7_msg->stop = true;
1013 f7_msg->count = 2;
1014 f7_msg->smbus_buf[1] = data->byte;
1015 }
1016 break;
1017 case I2C_SMBUS_WORD_DATA:
1018 if (f7_msg->read_write) {
1019 f7_msg->stop = false;
1020 f7_msg->count = 1;
1021 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1022 } else {
1023 f7_msg->stop = true;
1024 f7_msg->count = 3;
1025 f7_msg->smbus_buf[1] = data->word & 0xff;
1026 f7_msg->smbus_buf[2] = data->word >> 8;
1027 }
1028 break;
1029 case I2C_SMBUS_BLOCK_DATA:
1030 if (f7_msg->read_write) {
1031 f7_msg->stop = false;
1032 f7_msg->count = 1;
1033 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1034 } else {
1035 f7_msg->stop = true;
1036 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1037 !data->block[0]) {
1038 dev_err(dev, "Invalid block write size %d\n",
1039 data->block[0]);
1040 return -EINVAL;
1041 }
1042 f7_msg->count = data->block[0] + 2;
1043 for (i = 1; i < f7_msg->count; i++)
1044 f7_msg->smbus_buf[i] = data->block[i - 1];
1045 }
1046 break;
1047 case I2C_SMBUS_PROC_CALL:
1048 f7_msg->stop = false;
1049 f7_msg->count = 3;
1050 f7_msg->smbus_buf[1] = data->word & 0xff;
1051 f7_msg->smbus_buf[2] = data->word >> 8;
1052 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1053 f7_msg->read_write = I2C_SMBUS_READ;
1054 break;
1055 case I2C_SMBUS_BLOCK_PROC_CALL:
1056 f7_msg->stop = false;
1057 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1058 dev_err(dev, "Invalid block write size %d\n",
1059 data->block[0]);
1060 return -EINVAL;
1061 }
1062 f7_msg->count = data->block[0] + 2;
1063 for (i = 1; i < f7_msg->count; i++)
1064 f7_msg->smbus_buf[i] = data->block[i - 1];
1065 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1066 f7_msg->read_write = I2C_SMBUS_READ;
1067 break;
1068 case I2C_SMBUS_I2C_BLOCK_DATA:
1069 /* Rely on emulated i2c transfer (through master_xfer) */
1070 return -EOPNOTSUPP;
1071 default:
1072 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1073 return -EOPNOTSUPP;
1074 }
1075
1076 f7_msg->buf = f7_msg->smbus_buf;
1077
1078 /* Configure PEC */
1079 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1080 cr1 |= STM32F7_I2C_CR1_PECEN;
1081 if (!f7_msg->read_write) {
1082 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1083 f7_msg->count++;
1084 }
1085 } else {
1086 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1087 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1088 }
1089
1090 /* Set number of bytes to be transferred */
1091 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1092 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1093
1094 /* Enable NACK, STOP, error and transfer complete interrupts */
1095 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1096 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1097
1098 /* Clear DMA req and TX/RX interrupt */
1099 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1100 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1101
1102 /* Configure DMA or enable RX/TX interrupt */
1103 i2c_dev->use_dma = false;
1104 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1105 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1106 cr2 & STM32F7_I2C_CR2_RD_WRN,
1107 f7_msg->count, f7_msg->buf,
1108 stm32f7_i2c_dma_callback,
1109 i2c_dev);
1110 if (!ret)
1111 i2c_dev->use_dma = true;
1112 else
1113 dev_warn(i2c_dev->dev, "can't use DMA\n");
1114 }
1115
1116 if (!i2c_dev->use_dma) {
1117 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1118 cr1 |= STM32F7_I2C_CR1_RXIE;
1119 else
1120 cr1 |= STM32F7_I2C_CR1_TXIE;
1121 } else {
1122 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1123 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1124 else
1125 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1126 }
1127
1128 /* Set Start bit */
1129 cr2 |= STM32F7_I2C_CR2_START;
1130
1131 i2c_dev->master_mode = true;
1132
1133 /* Write configurations registers */
1134 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1135 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1136
1137 return 0;
1138 }
1139
stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev * i2c_dev)1140 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1141 {
1142 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1143 void __iomem *base = i2c_dev->base;
1144 u32 cr1, cr2;
1145 int ret;
1146
1147 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1148 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1149
1150 /* Set transfer direction */
1151 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1152
1153 switch (f7_msg->size) {
1154 case I2C_SMBUS_BYTE_DATA:
1155 f7_msg->count = 1;
1156 break;
1157 case I2C_SMBUS_WORD_DATA:
1158 case I2C_SMBUS_PROC_CALL:
1159 f7_msg->count = 2;
1160 break;
1161 case I2C_SMBUS_BLOCK_DATA:
1162 case I2C_SMBUS_BLOCK_PROC_CALL:
1163 f7_msg->count = 1;
1164 cr2 |= STM32F7_I2C_CR2_RELOAD;
1165 break;
1166 }
1167
1168 f7_msg->buf = f7_msg->smbus_buf;
1169 f7_msg->stop = true;
1170
1171 /* Add one byte for PEC if needed */
1172 if (cr1 & STM32F7_I2C_CR1_PECEN) {
1173 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1174 f7_msg->count++;
1175 }
1176
1177 /* Set number of bytes to be transferred */
1178 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1179 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1180
1181 /*
1182 * Configure RX/TX interrupt:
1183 */
1184 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1185 cr1 |= STM32F7_I2C_CR1_RXIE;
1186
1187 /*
1188 * Configure DMA or enable RX/TX interrupt:
1189 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1190 * dma as we don't know in advance how many data will be received
1191 */
1192 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1193 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1194
1195 i2c_dev->use_dma = false;
1196 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1197 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1198 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1199 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1200 cr2 & STM32F7_I2C_CR2_RD_WRN,
1201 f7_msg->count, f7_msg->buf,
1202 stm32f7_i2c_dma_callback,
1203 i2c_dev);
1204
1205 if (!ret)
1206 i2c_dev->use_dma = true;
1207 else
1208 dev_warn(i2c_dev->dev, "can't use DMA\n");
1209 }
1210
1211 if (!i2c_dev->use_dma)
1212 cr1 |= STM32F7_I2C_CR1_RXIE;
1213 else
1214 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1215
1216 /* Configure Repeated Start */
1217 cr2 |= STM32F7_I2C_CR2_START;
1218
1219 /* Write configurations registers */
1220 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1221 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1222 }
1223
stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev * i2c_dev)1224 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1225 {
1226 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1227 u8 count, internal_pec, received_pec;
1228
1229 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1230
1231 switch (f7_msg->size) {
1232 case I2C_SMBUS_BYTE:
1233 case I2C_SMBUS_BYTE_DATA:
1234 received_pec = f7_msg->smbus_buf[1];
1235 break;
1236 case I2C_SMBUS_WORD_DATA:
1237 case I2C_SMBUS_PROC_CALL:
1238 received_pec = f7_msg->smbus_buf[2];
1239 break;
1240 case I2C_SMBUS_BLOCK_DATA:
1241 case I2C_SMBUS_BLOCK_PROC_CALL:
1242 count = f7_msg->smbus_buf[0];
1243 received_pec = f7_msg->smbus_buf[count];
1244 break;
1245 default:
1246 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1247 return -EINVAL;
1248 }
1249
1250 if (internal_pec != received_pec) {
1251 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1252 internal_pec, received_pec);
1253 return -EBADMSG;
1254 }
1255
1256 return 0;
1257 }
1258
stm32f7_i2c_is_addr_match(struct i2c_client * slave,u32 addcode)1259 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1260 {
1261 u32 addr;
1262
1263 if (!slave)
1264 return false;
1265
1266 if (slave->flags & I2C_CLIENT_TEN) {
1267 /*
1268 * For 10-bit addr, addcode = 11110XY with
1269 * X = Bit 9 of slave address
1270 * Y = Bit 8 of slave address
1271 */
1272 addr = slave->addr >> 8;
1273 addr |= 0x78;
1274 if (addr == addcode)
1275 return true;
1276 } else {
1277 addr = slave->addr & 0x7f;
1278 if (addr == addcode)
1279 return true;
1280 }
1281
1282 return false;
1283 }
1284
stm32f7_i2c_slave_start(struct stm32f7_i2c_dev * i2c_dev)1285 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1286 {
1287 struct i2c_client *slave = i2c_dev->slave_running;
1288 void __iomem *base = i2c_dev->base;
1289 u32 mask;
1290 u8 value = 0;
1291
1292 if (i2c_dev->slave_dir) {
1293 /* Notify i2c slave that new read transfer is starting */
1294 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1295
1296 /*
1297 * Disable slave TX config in case of I2C combined message
1298 * (I2C Write followed by I2C Read)
1299 */
1300 mask = STM32F7_I2C_CR2_RELOAD;
1301 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1302 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1303 STM32F7_I2C_CR1_TCIE;
1304 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1305
1306 /* Enable TX empty, STOP, NACK interrupts */
1307 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1308 STM32F7_I2C_CR1_TXIE;
1309 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1310
1311 /* Write 1st data byte */
1312 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1313 } else {
1314 /* Notify i2c slave that new write transfer is starting */
1315 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1316
1317 /* Set reload mode to be able to ACK/NACK each received byte */
1318 mask = STM32F7_I2C_CR2_RELOAD;
1319 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1320
1321 /*
1322 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1323 * Set Slave Byte Control to be able to ACK/NACK each data
1324 * byte received
1325 */
1326 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1327 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1328 STM32F7_I2C_CR1_TCIE;
1329 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1330 }
1331 }
1332
stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev * i2c_dev)1333 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1334 {
1335 void __iomem *base = i2c_dev->base;
1336 u32 isr, addcode, dir, mask;
1337 int i;
1338
1339 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1340 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1341 dir = isr & STM32F7_I2C_ISR_DIR;
1342
1343 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1344 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1345 i2c_dev->slave_running = i2c_dev->slave[i];
1346 i2c_dev->slave_dir = dir;
1347
1348 /* Start I2C slave processing */
1349 stm32f7_i2c_slave_start(i2c_dev);
1350
1351 /* Clear ADDR flag */
1352 mask = STM32F7_I2C_ICR_ADDRCF;
1353 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1354 break;
1355 }
1356 }
1357 }
1358
stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1359 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1360 struct i2c_client *slave, int *id)
1361 {
1362 int i;
1363
1364 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1365 if (i2c_dev->slave[i] == slave) {
1366 *id = i;
1367 return 0;
1368 }
1369 }
1370
1371 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1372
1373 return -ENODEV;
1374 }
1375
stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1376 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1377 struct i2c_client *slave, int *id)
1378 {
1379 struct device *dev = i2c_dev->dev;
1380 int i;
1381
1382 /*
1383 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1384 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1385 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1386 */
1387 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1388 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1389 goto fail;
1390 *id = STM32F7_SLAVE_HOSTNOTIFY;
1391 return 0;
1392 }
1393
1394 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1395 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1396 (slave->flags & I2C_CLIENT_TEN))
1397 continue;
1398 if (!i2c_dev->slave[i]) {
1399 *id = i;
1400 return 0;
1401 }
1402 }
1403
1404 fail:
1405 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1406
1407 return -EINVAL;
1408 }
1409
stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev * i2c_dev)1410 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1411 {
1412 int i;
1413
1414 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1415 if (i2c_dev->slave[i])
1416 return true;
1417 }
1418
1419 return false;
1420 }
1421
stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev * i2c_dev)1422 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1423 {
1424 int i, busy;
1425
1426 busy = 0;
1427 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1428 if (i2c_dev->slave[i])
1429 busy++;
1430 }
1431
1432 return i == busy;
1433 }
1434
stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev * i2c_dev,u32 status)1435 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1436 {
1437 void __iomem *base = i2c_dev->base;
1438 u32 cr2, mask;
1439 u8 val;
1440 int ret;
1441
1442 /* Slave transmitter mode */
1443 if (status & STM32F7_I2C_ISR_TXIS) {
1444 i2c_slave_event(i2c_dev->slave_running,
1445 I2C_SLAVE_READ_PROCESSED,
1446 &val);
1447
1448 /* Write data byte */
1449 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1450 }
1451
1452 /* Transfer Complete Reload for Slave receiver mode */
1453 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1454 /*
1455 * Read data byte then set NBYTES to receive next byte or NACK
1456 * the current received byte
1457 */
1458 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1459 ret = i2c_slave_event(i2c_dev->slave_running,
1460 I2C_SLAVE_WRITE_RECEIVED,
1461 &val);
1462 if (!ret) {
1463 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1464 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1465 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1466 } else {
1467 mask = STM32F7_I2C_CR2_NACK;
1468 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1469 }
1470 }
1471
1472 /* NACK received */
1473 if (status & STM32F7_I2C_ISR_NACKF) {
1474 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1475 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1476 }
1477
1478 /* STOP received */
1479 if (status & STM32F7_I2C_ISR_STOPF) {
1480 /* Disable interrupts */
1481 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1482
1483 if (i2c_dev->slave_dir) {
1484 /*
1485 * Flush TX buffer in order to not used the byte in
1486 * TXDR for the next transfer
1487 */
1488 mask = STM32F7_I2C_ISR_TXE;
1489 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1490 }
1491
1492 /* Clear STOP flag */
1493 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1494
1495 /* Notify i2c slave that a STOP flag has been detected */
1496 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1497
1498 i2c_dev->slave_running = NULL;
1499 }
1500
1501 /* Address match received */
1502 if (status & STM32F7_I2C_ISR_ADDR)
1503 stm32f7_i2c_slave_addr(i2c_dev);
1504
1505 return IRQ_HANDLED;
1506 }
1507
stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev * i2c_dev,u32 status)1508 static irqreturn_t stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1509 {
1510 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1511 u16 addr = f7_msg->addr;
1512 void __iomem *base = i2c_dev->base;
1513 struct device *dev = i2c_dev->dev;
1514
1515 /* Bus error */
1516 if (status & STM32F7_I2C_ISR_BERR) {
1517 dev_err(dev, "Bus error accessing addr 0x%x\n", addr);
1518 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1519 stm32f7_i2c_release_bus(&i2c_dev->adap);
1520 f7_msg->result = -EIO;
1521 }
1522
1523 /* Arbitration loss */
1524 if (status & STM32F7_I2C_ISR_ARLO) {
1525 dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr);
1526 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1527 f7_msg->result = -EAGAIN;
1528 }
1529
1530 if (status & STM32F7_I2C_ISR_PECERR) {
1531 dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr);
1532 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1533 f7_msg->result = -EINVAL;
1534 }
1535
1536 if (status & STM32F7_I2C_ISR_ALERT) {
1537 dev_dbg(dev, "SMBus alert received\n");
1538 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1539 i2c_handle_smbus_alert(i2c_dev->alert->ara);
1540 return IRQ_HANDLED;
1541 }
1542
1543 if (!i2c_dev->slave_running) {
1544 u32 mask;
1545 /* Disable interrupts */
1546 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1547 mask = STM32F7_I2C_XFER_IRQ_MASK;
1548 else
1549 mask = STM32F7_I2C_ALL_IRQ_MASK;
1550 stm32f7_i2c_disable_irq(i2c_dev, mask);
1551 }
1552
1553 /* Disable dma */
1554 if (i2c_dev->use_dma)
1555 stm32f7_i2c_dma_callback(i2c_dev);
1556
1557 i2c_dev->master_mode = false;
1558 complete(&i2c_dev->complete);
1559
1560 return IRQ_HANDLED;
1561 }
1562
1563 #define STM32F7_ERR_EVENTS (STM32F7_I2C_ISR_BERR | STM32F7_I2C_ISR_ARLO |\
1564 STM32F7_I2C_ISR_PECERR | STM32F7_I2C_ISR_ALERT)
stm32f7_i2c_isr_event(int irq,void * data)1565 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1566 {
1567 struct stm32f7_i2c_dev *i2c_dev = data;
1568 u32 status;
1569
1570 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1571
1572 /*
1573 * Check if the interrupt is for a slave device or related
1574 * to errors flags (in case of single it line mode)
1575 */
1576 if (!i2c_dev->master_mode ||
1577 (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS)))
1578 return IRQ_WAKE_THREAD;
1579
1580 /* Tx empty */
1581 if (status & STM32F7_I2C_ISR_TXIS)
1582 stm32f7_i2c_write_tx_data(i2c_dev);
1583
1584 /* RX not empty */
1585 if (status & STM32F7_I2C_ISR_RXNE)
1586 stm32f7_i2c_read_rx_data(i2c_dev);
1587
1588 /* Wake up the thread if other flags are raised */
1589 if (status &
1590 (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF |
1591 STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR))
1592 return IRQ_WAKE_THREAD;
1593
1594 return IRQ_HANDLED;
1595 }
1596
stm32f7_i2c_isr_event_thread(int irq,void * data)1597 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1598 {
1599 struct stm32f7_i2c_dev *i2c_dev = data;
1600 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1601 void __iomem *base = i2c_dev->base;
1602 u32 status, mask;
1603 int ret;
1604
1605 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1606
1607 if (!i2c_dev->master_mode)
1608 return stm32f7_i2c_slave_isr_event(i2c_dev, status);
1609
1610 /* Handle errors in case of this handler is used for events/errors */
1611 if (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS))
1612 return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1613
1614 /* NACK received */
1615 if (status & STM32F7_I2C_ISR_NACKF) {
1616 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1617 __func__, f7_msg->addr);
1618 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1619 if (i2c_dev->use_dma)
1620 stm32f7_i2c_dma_callback(i2c_dev);
1621 f7_msg->result = -ENXIO;
1622 }
1623
1624 if (status & STM32F7_I2C_ISR_TCR) {
1625 if (f7_msg->smbus)
1626 stm32f7_i2c_smbus_reload(i2c_dev);
1627 else
1628 stm32f7_i2c_reload(i2c_dev);
1629 }
1630
1631 /* Transfer complete */
1632 if (status & STM32F7_I2C_ISR_TC) {
1633 /* Wait for dma transfer completion before sending next message */
1634 if (i2c_dev->use_dma && !f7_msg->result) {
1635 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1636 if (!ret) {
1637 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1638 stm32f7_i2c_dma_callback(i2c_dev);
1639 f7_msg->result = -ETIMEDOUT;
1640 }
1641 }
1642 if (f7_msg->stop) {
1643 mask = STM32F7_I2C_CR2_STOP;
1644 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1645 } else if (f7_msg->smbus) {
1646 stm32f7_i2c_smbus_rep_start(i2c_dev);
1647 } else {
1648 i2c_dev->msg_id++;
1649 i2c_dev->msg++;
1650 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1651 }
1652 }
1653
1654 /* STOP detection flag */
1655 if (status & STM32F7_I2C_ISR_STOPF) {
1656 /* Disable interrupts */
1657 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1658 mask = STM32F7_I2C_XFER_IRQ_MASK;
1659 else
1660 mask = STM32F7_I2C_ALL_IRQ_MASK;
1661 stm32f7_i2c_disable_irq(i2c_dev, mask);
1662
1663 /* Clear STOP flag */
1664 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1665
1666 i2c_dev->master_mode = false;
1667 complete(&i2c_dev->complete);
1668 }
1669
1670 return IRQ_HANDLED;
1671 }
1672
stm32f7_i2c_isr_error_thread(int irq,void * data)1673 static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data)
1674 {
1675 struct stm32f7_i2c_dev *i2c_dev = data;
1676 u32 status;
1677
1678 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1679
1680 return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1681 }
1682
stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev * i2c_dev)1683 static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev)
1684 {
1685 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout);
1686
1687 while (ktime_compare(ktime_get(), timeout) < 0) {
1688 udelay(5);
1689 stm32f7_i2c_isr_event(0, i2c_dev);
1690
1691 if (completion_done(&i2c_dev->complete))
1692 return 1;
1693 }
1694
1695 return 0;
1696 }
1697
stm32f7_i2c_xfer_core(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1698 static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap,
1699 struct i2c_msg msgs[], int num)
1700 {
1701 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1702 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1703 struct stm32_i2c_dma *dma = i2c_dev->dma;
1704 unsigned long time_left;
1705 int ret;
1706
1707 i2c_dev->msg = msgs;
1708 i2c_dev->msg_num = num;
1709 i2c_dev->msg_id = 0;
1710 f7_msg->smbus = false;
1711
1712 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1713 if (ret < 0)
1714 return ret;
1715
1716 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1717 if (ret)
1718 goto pm_free;
1719
1720 reinit_completion(&i2c_dev->complete);
1721
1722 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1723
1724 if (!i2c_dev->atomic)
1725 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1726 i2c_dev->adap.timeout);
1727 else
1728 time_left = stm32f7_i2c_wait_polling(i2c_dev);
1729
1730 ret = f7_msg->result;
1731 if (ret) {
1732 if (i2c_dev->use_dma)
1733 dmaengine_synchronize(dma->chan_using);
1734
1735 /*
1736 * It is possible that some unsent data have already been
1737 * written into TXDR. To avoid sending old data in a
1738 * further transfer, flush TXDR in case of any error
1739 */
1740 writel_relaxed(STM32F7_I2C_ISR_TXE,
1741 i2c_dev->base + STM32F7_I2C_ISR);
1742 goto pm_free;
1743 }
1744
1745 if (!time_left) {
1746 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1747 i2c_dev->msg->addr);
1748 if (i2c_dev->use_dma)
1749 dmaengine_terminate_sync(dma->chan_using);
1750 stm32f7_i2c_wait_free_bus(i2c_dev);
1751 ret = -ETIMEDOUT;
1752 }
1753
1754 pm_free:
1755 pm_runtime_put_autosuspend(i2c_dev->dev);
1756
1757 return (ret < 0) ? ret : num;
1758 }
1759
stm32f7_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1760 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1761 struct i2c_msg msgs[], int num)
1762 {
1763 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1764
1765 i2c_dev->atomic = false;
1766 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1767 }
1768
stm32f7_i2c_xfer_atomic(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1769 static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap,
1770 struct i2c_msg msgs[], int num)
1771 {
1772 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1773
1774 i2c_dev->atomic = true;
1775 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1776 }
1777
stm32f7_i2c_smbus_xfer(struct i2c_adapter * adapter,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)1778 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1779 unsigned short flags, char read_write,
1780 u8 command, int size,
1781 union i2c_smbus_data *data)
1782 {
1783 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1784 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1785 struct stm32_i2c_dma *dma = i2c_dev->dma;
1786 struct device *dev = i2c_dev->dev;
1787 unsigned long time_left;
1788 int i, ret;
1789
1790 f7_msg->addr = addr;
1791 f7_msg->size = size;
1792 f7_msg->read_write = read_write;
1793 f7_msg->smbus = true;
1794
1795 ret = pm_runtime_resume_and_get(dev);
1796 if (ret < 0)
1797 return ret;
1798
1799 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1800 if (ret)
1801 goto pm_free;
1802
1803 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1804 if (ret)
1805 goto pm_free;
1806
1807 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1808 i2c_dev->adap.timeout);
1809 ret = f7_msg->result;
1810 if (ret) {
1811 if (i2c_dev->use_dma)
1812 dmaengine_synchronize(dma->chan_using);
1813
1814 /*
1815 * It is possible that some unsent data have already been
1816 * written into TXDR. To avoid sending old data in a
1817 * further transfer, flush TXDR in case of any error
1818 */
1819 writel_relaxed(STM32F7_I2C_ISR_TXE,
1820 i2c_dev->base + STM32F7_I2C_ISR);
1821 goto pm_free;
1822 }
1823
1824 if (!time_left) {
1825 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1826 if (i2c_dev->use_dma)
1827 dmaengine_terminate_sync(dma->chan_using);
1828 stm32f7_i2c_wait_free_bus(i2c_dev);
1829 ret = -ETIMEDOUT;
1830 goto pm_free;
1831 }
1832
1833 /* Check PEC */
1834 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1835 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1836 if (ret)
1837 goto pm_free;
1838 }
1839
1840 if (read_write && size != I2C_SMBUS_QUICK) {
1841 switch (size) {
1842 case I2C_SMBUS_BYTE:
1843 case I2C_SMBUS_BYTE_DATA:
1844 data->byte = f7_msg->smbus_buf[0];
1845 break;
1846 case I2C_SMBUS_WORD_DATA:
1847 case I2C_SMBUS_PROC_CALL:
1848 data->word = f7_msg->smbus_buf[0] |
1849 (f7_msg->smbus_buf[1] << 8);
1850 break;
1851 case I2C_SMBUS_BLOCK_DATA:
1852 case I2C_SMBUS_BLOCK_PROC_CALL:
1853 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1854 data->block[i] = f7_msg->smbus_buf[i];
1855 break;
1856 default:
1857 dev_err(dev, "Unsupported smbus transaction\n");
1858 ret = -EINVAL;
1859 }
1860 }
1861
1862 pm_free:
1863 pm_runtime_put_autosuspend(dev);
1864 return ret;
1865 }
1866
stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev * i2c_dev,bool enable)1867 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1868 bool enable)
1869 {
1870 void __iomem *base = i2c_dev->base;
1871 u32 mask = STM32F7_I2C_CR1_WUPEN;
1872
1873 if (!i2c_dev->wakeup_src)
1874 return;
1875
1876 if (enable) {
1877 device_set_wakeup_enable(i2c_dev->dev, true);
1878 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1879 } else {
1880 device_set_wakeup_enable(i2c_dev->dev, false);
1881 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1882 }
1883 }
1884
stm32f7_i2c_reg_slave(struct i2c_client * slave)1885 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1886 {
1887 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1888 void __iomem *base = i2c_dev->base;
1889 struct device *dev = i2c_dev->dev;
1890 u32 oar1, oar2, mask;
1891 int id, ret;
1892
1893 if (slave->flags & I2C_CLIENT_PEC) {
1894 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1895 return -EINVAL;
1896 }
1897
1898 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1899 dev_err(dev, "Too much slave registered\n");
1900 return -EBUSY;
1901 }
1902
1903 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1904 if (ret)
1905 return ret;
1906
1907 ret = pm_runtime_resume_and_get(dev);
1908 if (ret < 0)
1909 return ret;
1910
1911 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1912 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1913
1914 switch (id) {
1915 case 0:
1916 /* Slave SMBus Host */
1917 i2c_dev->slave[id] = slave;
1918 break;
1919
1920 case 1:
1921 /* Configure Own Address 1 */
1922 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1923 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1924 if (slave->flags & I2C_CLIENT_TEN) {
1925 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1926 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1927 } else {
1928 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1929 }
1930 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1931 i2c_dev->slave[id] = slave;
1932 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1933 break;
1934
1935 case 2:
1936 /* Configure Own Address 2 */
1937 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1938 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1939 if (slave->flags & I2C_CLIENT_TEN) {
1940 ret = -EOPNOTSUPP;
1941 goto pm_free;
1942 }
1943
1944 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1945 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1946 i2c_dev->slave[id] = slave;
1947 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1948 break;
1949
1950 default:
1951 dev_err(dev, "I2C slave id not supported\n");
1952 ret = -ENODEV;
1953 goto pm_free;
1954 }
1955
1956 /* Enable ACK */
1957 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1958
1959 /* Enable Address match interrupt, error interrupt and enable I2C */
1960 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1961 STM32F7_I2C_CR1_PE;
1962 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1963
1964 ret = 0;
1965 pm_free:
1966 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1967 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1968
1969 pm_runtime_put_autosuspend(dev);
1970
1971 return ret;
1972 }
1973
stm32f7_i2c_unreg_slave(struct i2c_client * slave)1974 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1975 {
1976 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1977 void __iomem *base = i2c_dev->base;
1978 u32 mask;
1979 int id, ret;
1980
1981 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1982 if (ret)
1983 return ret;
1984
1985 WARN_ON(!i2c_dev->slave[id]);
1986
1987 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1988 if (ret < 0)
1989 return ret;
1990
1991 if (id == 1) {
1992 mask = STM32F7_I2C_OAR1_OA1EN;
1993 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1994 } else if (id == 2) {
1995 mask = STM32F7_I2C_OAR2_OA2EN;
1996 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1997 }
1998
1999 i2c_dev->slave[id] = NULL;
2000
2001 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2002 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
2003 stm32f7_i2c_enable_wakeup(i2c_dev, false);
2004 }
2005
2006 pm_runtime_put_autosuspend(i2c_dev->dev);
2007
2008 return 0;
2009 }
2010
stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev * i2c_dev,bool enable)2011 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
2012 bool enable)
2013 {
2014 int ret = 0;
2015
2016 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
2017 (!i2c_dev->setup.fmp_cr1_bit && IS_ERR_OR_NULL(i2c_dev->regmap)))
2018 /* Optional */
2019 return 0;
2020
2021 if (i2c_dev->setup.fmp_cr1_bit) {
2022 if (enable)
2023 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2024 else
2025 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2026 } else {
2027 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
2028 ret = regmap_update_bits(i2c_dev->regmap, i2c_dev->fmp_sreg,
2029 i2c_dev->fmp_mask, enable ? i2c_dev->fmp_mask : 0);
2030 else
2031 ret = regmap_write(i2c_dev->regmap,
2032 enable ? i2c_dev->fmp_sreg : i2c_dev->fmp_creg,
2033 i2c_dev->fmp_mask);
2034 }
2035
2036 return ret;
2037 }
2038
stm32f7_i2c_setup_fm_plus_bits(struct platform_device * pdev,struct stm32f7_i2c_dev * i2c_dev)2039 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
2040 struct stm32f7_i2c_dev *i2c_dev)
2041 {
2042 struct device_node *np = pdev->dev.of_node;
2043 int ret;
2044
2045 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
2046 if (IS_ERR(i2c_dev->regmap))
2047 /* Optional */
2048 return 0;
2049
2050 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2051 &i2c_dev->fmp_sreg);
2052 if (ret)
2053 return ret;
2054
2055 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2056 i2c_dev->setup.fmp_clr_offset;
2057
2058 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2059 &i2c_dev->fmp_mask);
2060 }
2061
stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2062 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2063 {
2064 struct i2c_adapter *adap = &i2c_dev->adap;
2065 void __iomem *base = i2c_dev->base;
2066 struct i2c_client *client;
2067
2068 client = i2c_new_slave_host_notify_device(adap);
2069 if (IS_ERR(client))
2070 return PTR_ERR(client);
2071
2072 i2c_dev->host_notify_client = client;
2073
2074 /* Enable SMBus Host address */
2075 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2076
2077 return 0;
2078 }
2079
stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2080 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2081 {
2082 void __iomem *base = i2c_dev->base;
2083
2084 if (i2c_dev->host_notify_client) {
2085 /* Disable SMBus Host address */
2086 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2087 STM32F7_I2C_CR1_SMBHEN);
2088 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2089 }
2090 }
2091
stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2092 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2093 {
2094 struct stm32f7_i2c_alert *alert;
2095 struct i2c_adapter *adap = &i2c_dev->adap;
2096 struct device *dev = i2c_dev->dev;
2097 void __iomem *base = i2c_dev->base;
2098
2099 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2100 if (!alert)
2101 return -ENOMEM;
2102
2103 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2104 if (IS_ERR(alert->ara))
2105 return PTR_ERR(alert->ara);
2106
2107 i2c_dev->alert = alert;
2108
2109 /* Enable SMBus Alert */
2110 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2111
2112 return 0;
2113 }
2114
stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2115 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2116 {
2117 struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2118 void __iomem *base = i2c_dev->base;
2119
2120 if (alert) {
2121 /* Disable SMBus Alert */
2122 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2123 STM32F7_I2C_CR1_ALERTEN);
2124 i2c_unregister_device(alert->ara);
2125 }
2126 }
2127
stm32f7_i2c_func(struct i2c_adapter * adap)2128 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2129 {
2130 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2131
2132 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2133 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2134 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2135 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2136 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2137 I2C_FUNC_SMBUS_I2C_BLOCK;
2138
2139 if (i2c_dev->smbus_mode)
2140 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2141
2142 return func;
2143 }
2144
2145 static const struct i2c_algorithm stm32f7_i2c_algo = {
2146 .xfer = stm32f7_i2c_xfer,
2147 .xfer_atomic = stm32f7_i2c_xfer_atomic,
2148 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2149 .functionality = stm32f7_i2c_func,
2150 .reg_slave = stm32f7_i2c_reg_slave,
2151 .unreg_slave = stm32f7_i2c_unreg_slave,
2152 };
2153
stm32f7_i2c_probe(struct platform_device * pdev)2154 static int stm32f7_i2c_probe(struct platform_device *pdev)
2155 {
2156 struct stm32f7_i2c_dev *i2c_dev;
2157 const struct stm32f7_i2c_setup *setup;
2158 struct resource *res;
2159 struct i2c_adapter *adap;
2160 struct reset_control *rst;
2161 dma_addr_t phy_addr;
2162 int irq_error, irq_event, ret;
2163
2164 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2165 if (!i2c_dev)
2166 return -ENOMEM;
2167
2168 setup = of_device_get_match_data(&pdev->dev);
2169 if (!setup)
2170 return dev_err_probe(&pdev->dev, -ENODEV, "Can't get device data\n");
2171 i2c_dev->setup = *setup;
2172
2173 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2174 if (IS_ERR(i2c_dev->base))
2175 return PTR_ERR(i2c_dev->base);
2176 phy_addr = (dma_addr_t)res->start;
2177
2178 irq_event = platform_get_irq(pdev, 0);
2179 if (irq_event < 0)
2180 return irq_event;
2181
2182 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2183 "wakeup-source");
2184
2185 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL);
2186 if (IS_ERR(i2c_dev->clk))
2187 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2188 "Failed to enable controller clock\n");
2189
2190 rst = devm_reset_control_get(&pdev->dev, NULL);
2191 if (IS_ERR(rst))
2192 return dev_err_probe(&pdev->dev, PTR_ERR(rst),
2193 "Error: Missing reset ctrl\n");
2194
2195 reset_control_assert(rst);
2196 udelay(2);
2197 reset_control_deassert(rst);
2198
2199 i2c_dev->dev = &pdev->dev;
2200
2201 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2202 stm32f7_i2c_isr_event,
2203 stm32f7_i2c_isr_event_thread,
2204 IRQF_ONESHOT,
2205 pdev->name, i2c_dev);
2206 if (ret)
2207 return ret;
2208
2209 if (!i2c_dev->setup.single_it_line) {
2210 irq_error = platform_get_irq(pdev, 1);
2211 if (irq_error < 0)
2212 return irq_error;
2213
2214 ret = devm_request_threaded_irq(&pdev->dev, irq_error,
2215 NULL,
2216 stm32f7_i2c_isr_error_thread,
2217 IRQF_ONESHOT,
2218 pdev->name, i2c_dev);
2219 if (ret)
2220 return ret;
2221 }
2222
2223 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2224 if (ret)
2225 return ret;
2226
2227 /* Setup Fast mode plus if necessary */
2228 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2229 if (!i2c_dev->setup.fmp_cr1_bit) {
2230 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2231 if (ret)
2232 return ret;
2233 }
2234
2235 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2236 if (ret)
2237 return ret;
2238 }
2239
2240 adap = &i2c_dev->adap;
2241 i2c_set_adapdata(adap, i2c_dev);
2242 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2243 &res->start);
2244 adap->owner = THIS_MODULE;
2245 adap->timeout = 8 * HZ;
2246 adap->retries = 3;
2247 adap->algo = &stm32f7_i2c_algo;
2248 adap->dev.parent = &pdev->dev;
2249 adap->dev.of_node = pdev->dev.of_node;
2250
2251 init_completion(&i2c_dev->complete);
2252
2253 /* Init DMA config if supported */
2254 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2255 STM32F7_I2C_TXDR,
2256 STM32F7_I2C_RXDR);
2257 if (IS_ERR(i2c_dev->dma)) {
2258 ret = PTR_ERR(i2c_dev->dma);
2259 /* DMA support is optional, only report other errors */
2260 if (ret != -ENODEV)
2261 goto fmp_clear;
2262 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2263 i2c_dev->dma = NULL;
2264 }
2265
2266 if (i2c_dev->wakeup_src) {
2267 device_set_wakeup_capable(i2c_dev->dev, true);
2268
2269 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2270 if (ret) {
2271 dev_err_probe(i2c_dev->dev, ret, "Failed to set wake up irq\n");
2272 goto clr_wakeup_capable;
2273 }
2274 }
2275
2276 platform_set_drvdata(pdev, i2c_dev);
2277
2278 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2279 STM32F7_AUTOSUSPEND_DELAY);
2280 pm_runtime_use_autosuspend(i2c_dev->dev);
2281 pm_runtime_set_active(i2c_dev->dev);
2282 pm_runtime_enable(i2c_dev->dev);
2283
2284 pm_runtime_get_noresume(&pdev->dev);
2285
2286 stm32f7_i2c_hw_config(i2c_dev);
2287
2288 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2289
2290 ret = i2c_add_adapter(adap);
2291 if (ret)
2292 goto pm_disable;
2293
2294 if (i2c_dev->smbus_mode) {
2295 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2296 if (ret) {
2297 dev_err_probe(i2c_dev->dev, ret,
2298 "failed to enable SMBus Host-Notify protocol\n");
2299 goto i2c_adapter_remove;
2300 }
2301 }
2302
2303 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2304 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2305 if (ret) {
2306 dev_err_probe(i2c_dev->dev, ret,
2307 "failed to enable SMBus alert protocol\n");
2308 goto i2c_disable_smbus_host;
2309 }
2310 }
2311
2312 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2313
2314 pm_runtime_put_autosuspend(i2c_dev->dev);
2315
2316 return 0;
2317
2318 i2c_disable_smbus_host:
2319 stm32f7_i2c_disable_smbus_host(i2c_dev);
2320
2321 i2c_adapter_remove:
2322 i2c_del_adapter(adap);
2323
2324 pm_disable:
2325 pm_runtime_put_noidle(i2c_dev->dev);
2326 pm_runtime_disable(i2c_dev->dev);
2327 pm_runtime_set_suspended(i2c_dev->dev);
2328 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2329
2330 if (i2c_dev->wakeup_src)
2331 dev_pm_clear_wake_irq(i2c_dev->dev);
2332
2333 clr_wakeup_capable:
2334 if (i2c_dev->wakeup_src)
2335 device_set_wakeup_capable(i2c_dev->dev, false);
2336
2337 if (i2c_dev->dma) {
2338 stm32_i2c_dma_free(i2c_dev->dma);
2339 i2c_dev->dma = NULL;
2340 }
2341
2342 fmp_clear:
2343 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2344
2345 return ret;
2346 }
2347
stm32f7_i2c_remove(struct platform_device * pdev)2348 static void stm32f7_i2c_remove(struct platform_device *pdev)
2349 {
2350 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2351
2352 stm32f7_i2c_disable_smbus_alert(i2c_dev);
2353 stm32f7_i2c_disable_smbus_host(i2c_dev);
2354
2355 i2c_del_adapter(&i2c_dev->adap);
2356 pm_runtime_get_sync(i2c_dev->dev);
2357
2358 if (i2c_dev->wakeup_src) {
2359 dev_pm_clear_wake_irq(i2c_dev->dev);
2360 /*
2361 * enforce that wakeup is disabled and that the device
2362 * is marked as non wakeup capable
2363 */
2364 device_init_wakeup(i2c_dev->dev, false);
2365 }
2366
2367 pm_runtime_put_noidle(i2c_dev->dev);
2368 pm_runtime_disable(i2c_dev->dev);
2369 pm_runtime_set_suspended(i2c_dev->dev);
2370 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2371
2372 if (i2c_dev->dma) {
2373 stm32_i2c_dma_free(i2c_dev->dma);
2374 i2c_dev->dma = NULL;
2375 }
2376
2377 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2378 }
2379
stm32f7_i2c_runtime_suspend(struct device * dev)2380 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2381 {
2382 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2383
2384 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2385 clk_disable(i2c_dev->clk);
2386
2387 return 0;
2388 }
2389
stm32f7_i2c_runtime_resume(struct device * dev)2390 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2391 {
2392 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2393 int ret;
2394
2395 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2396 ret = clk_enable(i2c_dev->clk);
2397 if (ret) {
2398 dev_err(dev, "failed to enable clock\n");
2399 return ret;
2400 }
2401 }
2402
2403 return 0;
2404 }
2405
stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev * i2c_dev)2406 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2407 {
2408 int ret;
2409 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2410
2411 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2412 if (ret < 0)
2413 return ret;
2414
2415 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2416 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2417 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2418 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2419 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2420 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2421
2422 pm_runtime_put_sync(i2c_dev->dev);
2423
2424 return ret;
2425 }
2426
stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev * i2c_dev)2427 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2428 {
2429 u32 cr1;
2430 int ret;
2431 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2432
2433 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2434 if (ret < 0)
2435 return ret;
2436
2437 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2438 if (cr1 & STM32F7_I2C_CR1_PE)
2439 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2440 STM32F7_I2C_CR1_PE);
2441
2442 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2443 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2444 i2c_dev->base + STM32F7_I2C_CR1);
2445 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2446 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2447 STM32F7_I2C_CR1_PE);
2448 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2449 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2450 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2451 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2452
2453 pm_runtime_put_sync(i2c_dev->dev);
2454
2455 return ret;
2456 }
2457
stm32f7_i2c_suspend(struct device * dev)2458 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2459 {
2460 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2461 int ret;
2462
2463 i2c_mark_adapter_suspended(&i2c_dev->adap);
2464
2465 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2466 ret = stm32f7_i2c_regs_backup(i2c_dev);
2467 if (ret < 0) {
2468 i2c_mark_adapter_resumed(&i2c_dev->adap);
2469 return ret;
2470 }
2471
2472 pinctrl_pm_select_sleep_state(dev);
2473 pm_runtime_force_suspend(dev);
2474 }
2475
2476 return 0;
2477 }
2478
stm32f7_i2c_resume(struct device * dev)2479 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2480 {
2481 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2482 int ret;
2483
2484 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2485 ret = pm_runtime_force_resume(dev);
2486 if (ret < 0)
2487 return ret;
2488 pinctrl_pm_select_default_state(dev);
2489
2490 ret = stm32f7_i2c_regs_restore(i2c_dev);
2491 if (ret < 0)
2492 return ret;
2493 }
2494
2495 i2c_mark_adapter_resumed(&i2c_dev->adap);
2496
2497 return 0;
2498 }
2499
2500 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2501 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2502 stm32f7_i2c_runtime_resume, NULL)
2503 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2504 };
2505
2506 static const struct of_device_id stm32f7_i2c_match[] = {
2507 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2508 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2509 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2510 { .compatible = "st,stm32mp25-i2c", .data = &stm32mp25_setup},
2511 {},
2512 };
2513 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2514
2515 static struct platform_driver stm32f7_i2c_driver = {
2516 .driver = {
2517 .name = "stm32f7-i2c",
2518 .of_match_table = stm32f7_i2c_match,
2519 .pm = &stm32f7_i2c_pm_ops,
2520 },
2521 .probe = stm32f7_i2c_probe,
2522 .remove = stm32f7_i2c_remove,
2523 };
2524
2525 module_platform_driver(stm32f7_i2c_driver);
2526
2527 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2528 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2529 MODULE_LICENSE("GPL v2");
2530