1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Clock control for Cirrus EP93xx chips.
4 * Copyright (C) 2021 Nikita Shubin <nikita.shubin@maquefel.me>
5 *
6 * Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
7 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
8 */
9 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
10
11 #include <linux/bits.h>
12 #include <linux/cleanup.h>
13 #include <linux/clk-provider.h>
14 #include <linux/math.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/spinlock.h>
18
19 #include <linux/soc/cirrus/ep93xx.h>
20 #include <dt-bindings/clock/cirrus,ep9301-syscon.h>
21
22 #include <asm/div64.h>
23
24 #define EP93XX_EXT_CLK_RATE 14745600
25 #define EP93XX_EXT_RTC_RATE 32768
26
27 #define EP93XX_SYSCON_POWER_STATE 0x00
28 #define EP93XX_SYSCON_PWRCNT 0x04
29 #define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29)
30 #define EP93XX_SYSCON_PWRCNT_USH_EN 28
31 #define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27
32 #define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26
33 #define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25
34 #define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24
35 #define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23
36 #define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22
37 #define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21
38 #define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20
39 #define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19
40 #define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18
41 #define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17
42 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16
43 #define EP93XX_SYSCON_CLKSET1 0x20
44 #define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23)
45 #define EP93XX_SYSCON_CLKSET2 0x24
46 #define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19)
47 #define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18)
48 #define EP93XX_SYSCON_DEVCFG 0x80
49 #define EP93XX_SYSCON_DEVCFG_U3EN 24
50 #define EP93XX_SYSCON_DEVCFG_U2EN 20
51 #define EP93XX_SYSCON_DEVCFG_U1EN 18
52 #define EP93XX_SYSCON_VIDCLKDIV 0x84
53 #define EP93XX_SYSCON_CLKDIV_ENABLE 15
54 #define EP93XX_SYSCON_CLKDIV_ESEL BIT(14)
55 #define EP93XX_SYSCON_CLKDIV_PSEL BIT(13)
56 #define EP93XX_SYSCON_CLKDIV_MASK GENMASK(14, 13)
57 #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
58 #define EP93XX_SYSCON_I2SCLKDIV 0x8c
59 #define EP93XX_SYSCON_I2SCLKDIV_SENA 31
60 #define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29)
61 #define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19)
62 #define EP93XX_SYSCON_KEYTCHCLKDIV 0x90
63 #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31
64 #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16
65 #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
66 #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV 0
67 #define EP93XX_SYSCON_CHIPID 0x94
68 #define EP93XX_SYSCON_CHIPID_ID 0x9213
69
70 #define EP93XX_FIXED_CLK_COUNT 21
71
72 static const char ep93xx_adc_divisors[] = { 16, 4 };
73 static const char ep93xx_sclk_divisors[] = { 2, 4 };
74 static const char ep93xx_lrclk_divisors[] = { 32, 64, 128 };
75
76 struct ep93xx_clk {
77 struct clk_hw hw;
78 u16 idx;
79 u16 reg;
80 u32 mask;
81 u8 bit_idx;
82 u8 shift;
83 u8 width;
84 u8 num_div;
85 const char *div;
86 };
87
88 struct ep93xx_clk_priv {
89 spinlock_t lock;
90 struct ep93xx_regmap_adev *aux_dev;
91 struct device *dev;
92 void __iomem *base;
93 struct regmap *map;
94 struct clk_hw *fixed[EP93XX_FIXED_CLK_COUNT];
95 struct ep93xx_clk reg[];
96 };
97
ep93xx_clk_from(struct clk_hw * hw)98 static struct ep93xx_clk *ep93xx_clk_from(struct clk_hw *hw)
99 {
100 return container_of(hw, struct ep93xx_clk, hw);
101 }
102
ep93xx_priv_from(struct ep93xx_clk * clk)103 static struct ep93xx_clk_priv *ep93xx_priv_from(struct ep93xx_clk *clk)
104 {
105 return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]);
106 }
107
ep93xx_clk_write(struct ep93xx_clk_priv * priv,unsigned int reg,unsigned int val)108 static void ep93xx_clk_write(struct ep93xx_clk_priv *priv, unsigned int reg, unsigned int val)
109 {
110 struct ep93xx_regmap_adev *aux = priv->aux_dev;
111
112 aux->write(aux->map, aux->lock, reg, val);
113 }
114
ep93xx_clk_is_enabled(struct clk_hw * hw)115 static int ep93xx_clk_is_enabled(struct clk_hw *hw)
116 {
117 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
118 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
119 u32 val;
120
121 regmap_read(priv->map, clk->reg, &val);
122
123 return !!(val & BIT(clk->bit_idx));
124 }
125
ep93xx_clk_enable(struct clk_hw * hw)126 static int ep93xx_clk_enable(struct clk_hw *hw)
127 {
128 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
129 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
130 u32 val;
131
132 guard(spinlock_irqsave)(&priv->lock);
133
134 regmap_read(priv->map, clk->reg, &val);
135 val |= BIT(clk->bit_idx);
136
137 ep93xx_clk_write(priv, clk->reg, val);
138
139 return 0;
140 }
141
ep93xx_clk_disable(struct clk_hw * hw)142 static void ep93xx_clk_disable(struct clk_hw *hw)
143 {
144 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
145 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
146 u32 val;
147
148 guard(spinlock_irqsave)(&priv->lock);
149
150 regmap_read(priv->map, clk->reg, &val);
151 val &= ~BIT(clk->bit_idx);
152
153 ep93xx_clk_write(priv, clk->reg, val);
154 }
155
156 static const struct clk_ops clk_ep93xx_gate_ops = {
157 .enable = ep93xx_clk_enable,
158 .disable = ep93xx_clk_disable,
159 .is_enabled = ep93xx_clk_is_enabled,
160 };
161
ep93xx_clk_register_gate(struct ep93xx_clk * clk,const char * name,struct clk_parent_data * parent_data,unsigned long flags,unsigned int reg,u8 bit_idx)162 static int ep93xx_clk_register_gate(struct ep93xx_clk *clk,
163 const char *name,
164 struct clk_parent_data *parent_data,
165 unsigned long flags,
166 unsigned int reg,
167 u8 bit_idx)
168 {
169 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
170 struct clk_init_data init = { };
171
172 init.name = name;
173 init.ops = &clk_ep93xx_gate_ops;
174 init.flags = flags;
175 init.parent_data = parent_data;
176 init.num_parents = 1;
177
178 clk->reg = reg;
179 clk->bit_idx = bit_idx;
180 clk->hw.init = &init;
181
182 return devm_clk_hw_register(priv->dev, &clk->hw);
183 }
184
ep93xx_mux_get_parent(struct clk_hw * hw)185 static u8 ep93xx_mux_get_parent(struct clk_hw *hw)
186 {
187 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
188 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
189 u32 val;
190
191 regmap_read(priv->map, clk->reg, &val);
192
193 val &= EP93XX_SYSCON_CLKDIV_MASK;
194
195 switch (val) {
196 case EP93XX_SYSCON_CLKDIV_ESEL:
197 return 1; /* PLL1 */
198 case EP93XX_SYSCON_CLKDIV_MASK:
199 return 2; /* PLL2 */
200 default:
201 return 0; /* XTALI */
202 };
203 }
204
ep93xx_mux_set_parent_lock(struct clk_hw * hw,u8 index)205 static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index)
206 {
207 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
208 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
209 u32 val;
210
211 if (index >= 3)
212 return -EINVAL;
213
214 guard(spinlock_irqsave)(&priv->lock);
215
216 regmap_read(priv->map, clk->reg, &val);
217 val &= ~(EP93XX_SYSCON_CLKDIV_MASK);
218 val |= index > 0 ? EP93XX_SYSCON_CLKDIV_ESEL : 0;
219 val |= index > 1 ? EP93XX_SYSCON_CLKDIV_PSEL : 0;
220
221 ep93xx_clk_write(priv, clk->reg, val);
222
223 return 0;
224 }
225
is_best(unsigned long rate,unsigned long now,unsigned long best)226 static bool is_best(unsigned long rate, unsigned long now,
227 unsigned long best)
228 {
229 return abs_diff(rate, now) < abs_diff(rate, best);
230 }
231
ep93xx_mux_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)232 static int ep93xx_mux_determine_rate(struct clk_hw *hw,
233 struct clk_rate_request *req)
234 {
235 unsigned long best_rate = 0, actual_rate, mclk_rate;
236 unsigned long rate = req->rate;
237 struct clk_hw *parent_best = NULL;
238 unsigned long parent_rate_best;
239 unsigned long parent_rate;
240 int div, pdiv;
241 unsigned int i;
242
243 /*
244 * Try the two pll's and the external clock,
245 * because the valid predividers are 2, 2.5 and 3, we multiply
246 * all the clocks by 2 to avoid floating point math.
247 *
248 * This is based on the algorithm in the ep93xx raster guide:
249 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
250 *
251 */
252 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
253 struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
254
255 parent_rate = clk_hw_get_rate(parent);
256 mclk_rate = parent_rate * 2;
257
258 /* Try each predivider value */
259 for (pdiv = 4; pdiv <= 6; pdiv++) {
260 div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv);
261 if (!in_range(div, 1, 127))
262 continue;
263
264 actual_rate = DIV_ROUND_CLOSEST(mclk_rate, pdiv * div);
265 if (is_best(rate, actual_rate, best_rate)) {
266 best_rate = actual_rate;
267 parent_rate_best = parent_rate;
268 parent_best = parent;
269 }
270 }
271 }
272
273 if (!parent_best)
274 return -EINVAL;
275
276 req->best_parent_rate = parent_rate_best;
277 req->best_parent_hw = parent_best;
278 req->rate = best_rate;
279
280 return 0;
281 }
282
ep93xx_ddiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)283 static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw,
284 unsigned long parent_rate)
285 {
286 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
287 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
288 unsigned int pdiv, div;
289 u32 val;
290
291 regmap_read(priv->map, clk->reg, &val);
292 pdiv = (val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & GENMASK(1, 0);
293 div = val & GENMASK(6, 0);
294 if (!div)
295 return 0;
296
297 return DIV_ROUND_CLOSEST(parent_rate * 2, (pdiv + 3) * div);
298 }
299
ep93xx_ddiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)300 static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
301 unsigned long parent_rate)
302 {
303 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
304 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
305 int pdiv, div, npdiv, ndiv;
306 unsigned long actual_rate, mclk_rate, rate_err = ULONG_MAX;
307 u32 val;
308
309 regmap_read(priv->map, clk->reg, &val);
310 mclk_rate = parent_rate * 2;
311
312 for (pdiv = 4; pdiv <= 6; pdiv++) {
313 div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv);
314 if (!in_range(div, 1, 127))
315 continue;
316
317 actual_rate = DIV_ROUND_CLOSEST(mclk_rate, pdiv * div);
318 if (abs(actual_rate - rate) < rate_err) {
319 npdiv = pdiv - 3;
320 ndiv = div;
321 rate_err = abs(actual_rate - rate);
322 }
323 }
324
325 if (rate_err == ULONG_MAX)
326 return -EINVAL;
327
328 /*
329 * Clear old dividers.
330 * Bit 7 is reserved bit in all ClkDiv registers.
331 */
332 val &= ~(GENMASK(9, 0) & ~BIT(7));
333
334 /* Set the new pdiv and div bits for the new clock rate */
335 val |= (npdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | ndiv;
336
337 ep93xx_clk_write(priv, clk->reg, val);
338
339 return 0;
340 }
341
342 static const struct clk_ops clk_ddiv_ops = {
343 .enable = ep93xx_clk_enable,
344 .disable = ep93xx_clk_disable,
345 .is_enabled = ep93xx_clk_is_enabled,
346 .get_parent = ep93xx_mux_get_parent,
347 .set_parent = ep93xx_mux_set_parent_lock,
348 .determine_rate = ep93xx_mux_determine_rate,
349 .recalc_rate = ep93xx_ddiv_recalc_rate,
350 .set_rate = ep93xx_ddiv_set_rate,
351 };
352
ep93xx_clk_register_ddiv(struct ep93xx_clk * clk,const char * name,struct clk_parent_data * parent_data,u8 num_parents,unsigned int reg,u8 bit_idx)353 static int ep93xx_clk_register_ddiv(struct ep93xx_clk *clk,
354 const char *name,
355 struct clk_parent_data *parent_data,
356 u8 num_parents,
357 unsigned int reg,
358 u8 bit_idx)
359 {
360 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
361 struct clk_init_data init = { };
362
363 init.name = name;
364 init.ops = &clk_ddiv_ops;
365 init.flags = 0;
366 init.parent_data = parent_data;
367 init.num_parents = num_parents;
368
369 clk->reg = reg;
370 clk->bit_idx = bit_idx;
371 clk->hw.init = &init;
372
373 return devm_clk_hw_register(priv->dev, &clk->hw);
374 }
375
ep93xx_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)376 static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw,
377 unsigned long parent_rate)
378 {
379 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
380 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
381 u32 val;
382 u8 index;
383
384 regmap_read(priv->map, clk->reg, &val);
385 index = (val & clk->mask) >> clk->shift;
386 if (index >= clk->num_div)
387 return 0;
388
389 return DIV_ROUND_CLOSEST(parent_rate, clk->div[index]);
390 }
391
ep93xx_div_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)392 static int ep93xx_div_determine_rate(struct clk_hw *hw,
393 struct clk_rate_request *req)
394 {
395 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
396 unsigned long best = 0, now;
397 unsigned int i;
398
399 for (i = 0; i < clk->num_div; i++) {
400 if (req->rate * clk->div[i] == req->best_parent_rate)
401 return 0;
402
403 now = DIV_ROUND_CLOSEST(req->best_parent_rate, clk->div[i]);
404 if (!best || is_best(req->rate, now, best))
405 best = now;
406 }
407
408 req->rate = best;
409
410 return 0;
411 }
412
ep93xx_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)413 static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate,
414 unsigned long parent_rate)
415 {
416 struct ep93xx_clk *clk = ep93xx_clk_from(hw);
417 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
418 unsigned int i;
419 u32 val;
420
421 regmap_read(priv->map, clk->reg, &val);
422 val &= ~clk->mask;
423 for (i = 0; i < clk->num_div; i++)
424 if (rate == DIV_ROUND_CLOSEST(parent_rate, clk->div[i]))
425 break;
426
427 if (i == clk->num_div)
428 return -EINVAL;
429
430 val |= i << clk->shift;
431
432 ep93xx_clk_write(priv, clk->reg, val);
433
434 return 0;
435 }
436
437 static const struct clk_ops ep93xx_div_ops = {
438 .enable = ep93xx_clk_enable,
439 .disable = ep93xx_clk_disable,
440 .is_enabled = ep93xx_clk_is_enabled,
441 .recalc_rate = ep93xx_div_recalc_rate,
442 .determine_rate = ep93xx_div_determine_rate,
443 .set_rate = ep93xx_div_set_rate,
444 };
445
ep93xx_register_div(struct ep93xx_clk * clk,const char * name,const struct clk_parent_data * parent_data,unsigned int reg,u8 enable_bit,u8 shift,u8 width,const char * clk_divisors,u8 num_div)446 static int ep93xx_register_div(struct ep93xx_clk *clk,
447 const char *name,
448 const struct clk_parent_data *parent_data,
449 unsigned int reg,
450 u8 enable_bit,
451 u8 shift,
452 u8 width,
453 const char *clk_divisors,
454 u8 num_div)
455 {
456 struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
457 struct clk_init_data init = { };
458
459 init.name = name;
460 init.ops = &ep93xx_div_ops;
461 init.flags = 0;
462 init.parent_data = parent_data;
463 init.num_parents = 1;
464
465 clk->reg = reg;
466 clk->bit_idx = enable_bit;
467 clk->mask = GENMASK(shift + width - 1, shift);
468 clk->shift = shift;
469 clk->div = clk_divisors;
470 clk->num_div = num_div;
471 clk->hw.init = &init;
472
473 return devm_clk_hw_register(priv->dev, &clk->hw);
474 }
475
476 struct ep93xx_gate {
477 unsigned int idx;
478 unsigned int bit;
479 const char *name;
480 };
481
482 static const struct ep93xx_gate ep93xx_uarts[] = {
483 { EP93XX_CLK_UART1, EP93XX_SYSCON_DEVCFG_U1EN, "uart1" },
484 { EP93XX_CLK_UART2, EP93XX_SYSCON_DEVCFG_U2EN, "uart2" },
485 { EP93XX_CLK_UART3, EP93XX_SYSCON_DEVCFG_U3EN, "uart3" },
486 };
487
ep93xx_uart_clock_init(struct ep93xx_clk_priv * priv)488 static int ep93xx_uart_clock_init(struct ep93xx_clk_priv *priv)
489 {
490 struct clk_parent_data parent_data = { };
491 unsigned int i, idx, clk_uart_div;
492 struct ep93xx_clk *clk;
493 u32 val;
494 int ret;
495
496 regmap_read(priv->map, EP93XX_SYSCON_PWRCNT, &val);
497 if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD)
498 clk_uart_div = 1;
499 else
500 clk_uart_div = 2;
501
502 priv->fixed[EP93XX_CLK_UART] =
503 devm_clk_hw_register_fixed_factor_index(priv->dev, "uart",
504 0, /* XTALI external clock */
505 0, 1, clk_uart_div);
506 parent_data.hw = priv->fixed[EP93XX_CLK_UART];
507
508 /* parenting uart gate clocks to uart clock */
509 for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) {
510 idx = ep93xx_uarts[i].idx - EP93XX_CLK_UART1;
511 clk = &priv->reg[idx];
512 clk->idx = idx;
513 ret = ep93xx_clk_register_gate(clk,
514 ep93xx_uarts[i].name,
515 &parent_data, CLK_SET_RATE_PARENT,
516 EP93XX_SYSCON_DEVCFG,
517 ep93xx_uarts[i].bit);
518 if (ret)
519 return dev_err_probe(priv->dev, ret,
520 "failed to register uart[%d] clock\n", i);
521 }
522
523 return 0;
524 }
525
526 static const struct ep93xx_gate ep93xx_dmas[] = {
527 { EP93XX_CLK_M2M0, EP93XX_SYSCON_PWRCNT_DMA_M2M0, "m2m0" },
528 { EP93XX_CLK_M2M1, EP93XX_SYSCON_PWRCNT_DMA_M2M1, "m2m1" },
529 { EP93XX_CLK_M2P0, EP93XX_SYSCON_PWRCNT_DMA_M2P0, "m2p0" },
530 { EP93XX_CLK_M2P1, EP93XX_SYSCON_PWRCNT_DMA_M2P1, "m2p1" },
531 { EP93XX_CLK_M2P2, EP93XX_SYSCON_PWRCNT_DMA_M2P2, "m2p2" },
532 { EP93XX_CLK_M2P3, EP93XX_SYSCON_PWRCNT_DMA_M2P3, "m2p3" },
533 { EP93XX_CLK_M2P4, EP93XX_SYSCON_PWRCNT_DMA_M2P4, "m2p4" },
534 { EP93XX_CLK_M2P5, EP93XX_SYSCON_PWRCNT_DMA_M2P5, "m2p5" },
535 { EP93XX_CLK_M2P6, EP93XX_SYSCON_PWRCNT_DMA_M2P6, "m2p6" },
536 { EP93XX_CLK_M2P7, EP93XX_SYSCON_PWRCNT_DMA_M2P7, "m2p7" },
537 { EP93XX_CLK_M2P8, EP93XX_SYSCON_PWRCNT_DMA_M2P8, "m2p8" },
538 { EP93XX_CLK_M2P9, EP93XX_SYSCON_PWRCNT_DMA_M2P9, "m2p9" },
539 };
540
ep93xx_dma_clock_init(struct ep93xx_clk_priv * priv)541 static int ep93xx_dma_clock_init(struct ep93xx_clk_priv *priv)
542 {
543 struct clk_parent_data parent_data = { };
544 unsigned int i, idx;
545
546 parent_data.hw = priv->fixed[EP93XX_CLK_HCLK];
547 for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) {
548 idx = ep93xx_dmas[i].idx;
549 priv->fixed[idx] = devm_clk_hw_register_gate_parent_data(priv->dev,
550 ep93xx_dmas[i].name,
551 &parent_data, 0,
552 priv->base + EP93XX_SYSCON_PWRCNT,
553 ep93xx_dmas[i].bit,
554 0,
555 &priv->lock);
556 if (IS_ERR(priv->fixed[idx]))
557 return PTR_ERR(priv->fixed[idx]);
558 }
559
560 return 0;
561 }
562
of_clk_ep93xx_get(struct of_phandle_args * clkspec,void * data)563 static struct clk_hw *of_clk_ep93xx_get(struct of_phandle_args *clkspec, void *data)
564 {
565 struct ep93xx_clk_priv *priv = data;
566 unsigned int idx = clkspec->args[0];
567
568 if (idx < EP93XX_CLK_UART1)
569 return priv->fixed[idx];
570
571 if (idx <= EP93XX_CLK_I2S_LRCLK)
572 return &priv->reg[idx - EP93XX_CLK_UART1].hw;
573
574 return ERR_PTR(-EINVAL);
575 }
576
577 /*
578 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
579 */
calc_pll_rate(u64 rate,u32 config_word)580 static unsigned long calc_pll_rate(u64 rate, u32 config_word)
581 {
582 rate *= ((config_word >> 11) & GENMASK(4, 0)) + 1; /* X1FBD */
583 rate *= ((config_word >> 5) & GENMASK(5, 0)) + 1; /* X2FBD */
584 do_div(rate, (config_word & GENMASK(4, 0)) + 1); /* X2IPD */
585 rate >>= (config_word >> 16) & GENMASK(1, 0); /* PS */
586
587 return rate;
588 }
589
ep93xx_plls_init(struct ep93xx_clk_priv * priv)590 static int ep93xx_plls_init(struct ep93xx_clk_priv *priv)
591 {
592 static const char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
593 static const char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
594 static const char pclk_divisors[] = { 1, 2, 4, 8 };
595 struct clk_parent_data xtali = { .index = 0 };
596 unsigned int clk_f_div, clk_h_div, clk_p_div;
597 unsigned long clk_pll1_rate, clk_pll2_rate;
598 struct device *dev = priv->dev;
599 struct clk_hw *hw, *pll1;
600 u32 value;
601
602 /* Determine the bootloader configured pll1 rate */
603 regmap_read(priv->map, EP93XX_SYSCON_CLKSET1, &value);
604
605 if (value & EP93XX_SYSCON_CLKSET1_NBYP1)
606 clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
607 else
608 clk_pll1_rate = EP93XX_EXT_CLK_RATE;
609
610 pll1 = devm_clk_hw_register_fixed_rate_parent_data(dev, "pll1", &xtali,
611 0, clk_pll1_rate);
612 if (IS_ERR(pll1))
613 return PTR_ERR(pll1);
614
615 priv->fixed[EP93XX_CLK_PLL1] = pll1;
616
617 /* Initialize the pll1 derived clocks */
618 clk_f_div = fclk_divisors[(value >> 25) & GENMASK(2, 0)];
619 clk_h_div = hclk_divisors[(value >> 20) & GENMASK(2, 0)];
620 clk_p_div = pclk_divisors[(value >> 18) & GENMASK(1, 0)];
621
622 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "fclk", pll1, 0, 1, clk_f_div);
623 if (IS_ERR(hw))
624 return PTR_ERR(hw);
625
626 priv->fixed[EP93XX_CLK_FCLK] = hw;
627
628 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "hclk", pll1, 0, 1, clk_h_div);
629 if (IS_ERR(hw))
630 return PTR_ERR(hw);
631
632 priv->fixed[EP93XX_CLK_HCLK] = hw;
633
634 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "pclk", hw, 0, 1, clk_p_div);
635 if (IS_ERR(hw))
636 return PTR_ERR(hw);
637
638 priv->fixed[EP93XX_CLK_PCLK] = hw;
639
640 /* Determine the bootloader configured pll2 rate */
641 regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
642 if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
643 clk_pll2_rate = EP93XX_EXT_CLK_RATE;
644 else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
645 clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
646 else
647 clk_pll2_rate = 0;
648
649 hw = devm_clk_hw_register_fixed_rate_parent_data(dev, "pll2", &xtali,
650 0, clk_pll2_rate);
651 if (IS_ERR(hw))
652 return PTR_ERR(hw);
653
654 priv->fixed[EP93XX_CLK_PLL2] = hw;
655
656 return 0;
657 }
658
ep93xx_clk_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)659 static int ep93xx_clk_probe(struct auxiliary_device *adev,
660 const struct auxiliary_device_id *id)
661 {
662 struct ep93xx_regmap_adev *rdev = to_ep93xx_regmap_adev(adev);
663 struct clk_parent_data xtali = { .index = 0 };
664 struct clk_parent_data ddiv_pdata[3] = { };
665 unsigned int clk_spi_div, clk_usb_div;
666 struct clk_parent_data pdata = {};
667 struct device *dev = &adev->dev;
668 struct ep93xx_clk_priv *priv;
669 struct ep93xx_clk *clk;
670 struct clk_hw *hw;
671 unsigned int idx;
672 int ret;
673 u32 value;
674
675 priv = devm_kzalloc(dev, struct_size(priv, reg, 10), GFP_KERNEL);
676 if (!priv)
677 return -ENOMEM;
678
679 spin_lock_init(&priv->lock);
680 priv->dev = dev;
681 priv->aux_dev = rdev;
682 priv->map = rdev->map;
683 priv->base = rdev->base;
684
685 ret = ep93xx_plls_init(priv);
686 if (ret)
687 return ret;
688
689 regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
690 clk_usb_div = (value >> 28 & GENMASK(3, 0)) + 1;
691 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "usb_clk",
692 priv->fixed[EP93XX_CLK_PLL2], 0, 1,
693 clk_usb_div);
694 if (IS_ERR(hw))
695 return PTR_ERR(hw);
696
697 priv->fixed[EP93XX_CLK_USB] = hw;
698
699 ret = ep93xx_uart_clock_init(priv);
700 if (ret)
701 return ret;
702
703 ret = ep93xx_dma_clock_init(priv);
704 if (ret)
705 return ret;
706
707 clk_spi_div = id->driver_data;
708 hw = devm_clk_hw_register_fixed_factor_index(dev, "ep93xx-spi.0",
709 0, /* XTALI external clock */
710 0, 1, clk_spi_div);
711 if (IS_ERR(hw))
712 return PTR_ERR(hw);
713
714 priv->fixed[EP93XX_CLK_SPI] = hw;
715
716 /* PWM clock */
717 hw = devm_clk_hw_register_fixed_factor_index(dev, "pwm_clk", 0, /* XTALI external clock */
718 0, 1, 1);
719 if (IS_ERR(hw))
720 return PTR_ERR(hw);
721
722 priv->fixed[EP93XX_CLK_PWM] = hw;
723
724 /* USB clock */
725 pdata.hw = priv->fixed[EP93XX_CLK_USB];
726 hw = devm_clk_hw_register_gate_parent_data(priv->dev, "ohci-platform", &pdata,
727 0, priv->base + EP93XX_SYSCON_PWRCNT,
728 EP93XX_SYSCON_PWRCNT_USH_EN, 0,
729 &priv->lock);
730 if (IS_ERR(hw))
731 return PTR_ERR(hw);
732
733 priv->fixed[EP93XX_CLK_USB] = hw;
734
735 ddiv_pdata[0].index = 0; /* XTALI external clock */
736 ddiv_pdata[1].hw = priv->fixed[EP93XX_CLK_PLL1];
737 ddiv_pdata[2].hw = priv->fixed[EP93XX_CLK_PLL2];
738
739 /* touchscreen/ADC clock */
740 idx = EP93XX_CLK_ADC - EP93XX_CLK_UART1;
741 clk = &priv->reg[idx];
742 clk->idx = idx;
743 ret = ep93xx_register_div(clk, "ep93xx-adc", &xtali,
744 EP93XX_SYSCON_KEYTCHCLKDIV,
745 EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
746 EP93XX_SYSCON_KEYTCHCLKDIV_ADIV,
747 1,
748 ep93xx_adc_divisors,
749 ARRAY_SIZE(ep93xx_adc_divisors));
750
751
752 /* keypad clock */
753 idx = EP93XX_CLK_KEYPAD - EP93XX_CLK_UART1;
754 clk = &priv->reg[idx];
755 clk->idx = idx;
756 ret = ep93xx_register_div(clk, "ep93xx-keypad", &xtali,
757 EP93XX_SYSCON_KEYTCHCLKDIV,
758 EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
759 EP93XX_SYSCON_KEYTCHCLKDIV_KDIV,
760 1,
761 ep93xx_adc_divisors,
762 ARRAY_SIZE(ep93xx_adc_divisors));
763
764 /*
765 * On reset PDIV and VDIV is set to zero, while PDIV zero
766 * means clock disable, VDIV shouldn't be zero.
767 * So we set both video and i2s dividers to minimum.
768 * ENA - Enable CLK divider.
769 * PDIV - 00 - Disable clock
770 * VDIV - at least 2
771 */
772
773 /* Check and enable video clk registers */
774 regmap_read(priv->map, EP93XX_SYSCON_VIDCLKDIV, &value);
775 value |= BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
776 ep93xx_clk_write(priv, EP93XX_SYSCON_VIDCLKDIV, value);
777
778 /* Check and enable i2s clk registers */
779 regmap_read(priv->map, EP93XX_SYSCON_I2SCLKDIV, &value);
780 value |= BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
781
782 /*
783 * Override the SAI_MSTR_CLK_CFG from the I2S block and use the
784 * I2SClkDiv Register settings. LRCLK transitions on the falling SCLK
785 * edge.
786 */
787 value |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
788 ep93xx_clk_write(priv, EP93XX_SYSCON_I2SCLKDIV, value);
789
790 /* video clk */
791 idx = EP93XX_CLK_VIDEO - EP93XX_CLK_UART1;
792 clk = &priv->reg[idx];
793 clk->idx = idx;
794 ret = ep93xx_clk_register_ddiv(clk, "ep93xx-fb",
795 ddiv_pdata, ARRAY_SIZE(ddiv_pdata),
796 EP93XX_SYSCON_VIDCLKDIV,
797 EP93XX_SYSCON_CLKDIV_ENABLE);
798
799 /* i2s clk */
800 idx = EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1;
801 clk = &priv->reg[idx];
802 clk->idx = idx;
803 ret = ep93xx_clk_register_ddiv(clk, "mclk",
804 ddiv_pdata, ARRAY_SIZE(ddiv_pdata),
805 EP93XX_SYSCON_I2SCLKDIV,
806 EP93XX_SYSCON_CLKDIV_ENABLE);
807
808 /* i2s sclk */
809 idx = EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1;
810 clk = &priv->reg[idx];
811 clk->idx = idx;
812 pdata.hw = &priv->reg[EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1].hw;
813 ret = ep93xx_register_div(clk, "sclk", &pdata,
814 EP93XX_SYSCON_I2SCLKDIV,
815 EP93XX_SYSCON_I2SCLKDIV_SENA,
816 16, /* EP93XX_I2SCLKDIV_SDIV_SHIFT */
817 1, /* EP93XX_I2SCLKDIV_SDIV_WIDTH */
818 ep93xx_sclk_divisors,
819 ARRAY_SIZE(ep93xx_sclk_divisors));
820
821 /* i2s lrclk */
822 idx = EP93XX_CLK_I2S_LRCLK - EP93XX_CLK_UART1;
823 clk = &priv->reg[idx];
824 clk->idx = idx;
825 pdata.hw = &priv->reg[EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1].hw;
826 ret = ep93xx_register_div(clk, "lrclk", &pdata,
827 EP93XX_SYSCON_I2SCLKDIV,
828 EP93XX_SYSCON_I2SCLKDIV_SENA,
829 17, /* EP93XX_I2SCLKDIV_LRDIV32_SHIFT */
830 2, /* EP93XX_I2SCLKDIV_LRDIV32_WIDTH */
831 ep93xx_lrclk_divisors,
832 ARRAY_SIZE(ep93xx_lrclk_divisors));
833
834 /* IrDa clk uses same pattern but no init code presents in original clock driver */
835 return devm_of_clk_add_hw_provider(priv->dev, of_clk_ep93xx_get, priv);
836 }
837
838 static const struct auxiliary_device_id ep93xx_clk_ids[] = {
839 { .name = "soc_ep93xx.clk-ep93xx", .driver_data = 2, },
840 { .name = "soc_ep93xx.clk-ep93xx.e2", .driver_data = 1, },
841 { /* sentinel */ }
842 };
843 MODULE_DEVICE_TABLE(auxiliary, ep93xx_clk_ids);
844
845 static struct auxiliary_driver ep93xx_clk_driver = {
846 .probe = ep93xx_clk_probe,
847 .id_table = ep93xx_clk_ids,
848 };
849 module_auxiliary_driver(ep93xx_clk_driver);
850
851 MODULE_LICENSE("GPL");
852 MODULE_AUTHOR("Nikita Shubin <nikita.shubin@maquefel.me>");
853 MODULE_DESCRIPTION("Clock control for Cirrus EP93xx chips");
854