1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Bus error event handling code for systems equipped with ECC 4 * handling logic, i.e. DECstation/DECsystem 5000/200 (KN02), 5 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03), 6 * 5900/260 (KN05) systems. 7 * 8 * Copyright (c) 2003, 2005, 2026 Maciej W. Rozycki 9 */ 10 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/ratelimit.h> 15 #include <linux/sched.h> 16 #include <linux/types.h> 17 18 #include <asm/addrspace.h> 19 #include <asm/bootinfo.h> 20 #include <asm/cpu.h> 21 #include <asm/cpu-type.h> 22 #include <asm/irq_regs.h> 23 #include <asm/processor.h> 24 #include <asm/ptrace.h> 25 #include <asm/traps.h> 26 27 #include <asm/dec/ecc.h> 28 #include <asm/dec/kn02.h> 29 #include <asm/dec/kn03.h> 30 #include <asm/dec/kn05.h> 31 32 static volatile u32 *kn0x_erraddr; 33 static volatile u32 *kn0x_chksyn; 34 35 static inline void dec_ecc_be_ack(void) 36 { 37 *kn0x_erraddr = 0; /* any write clears the IRQ */ 38 iob(); 39 } 40 41 static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) 42 { 43 static const char excstr[] = "exception"; 44 static const char intstr[] = "interrupt"; 45 static const char cpustr[] = "CPU"; 46 static const char dmastr[] = "DMA"; 47 static const char readstr[] = "read"; 48 static const char mreadstr[] = "memory read"; 49 static const char writestr[] = "write"; 50 static const char mwritstr[] = "partial memory write"; 51 static const char timestr[] = "timeout"; 52 static const char overstr[] = "overrun"; 53 static const char eccstr[] = "ECC error"; 54 55 static DEFINE_RATELIMIT_STATE(rs, 56 DEFAULT_RATELIMIT_INTERVAL, 57 DEFAULT_RATELIMIT_BURST); 58 59 const char *kind, *agent, *cycle, *event; 60 const char *status = "", *xbit = "", *fmt = ""; 61 unsigned long address; 62 u16 syn = 0, sngl; 63 64 int i = 0; 65 66 u32 erraddr = *kn0x_erraddr; 67 u32 chksyn = *kn0x_chksyn; 68 int action = MIPS_BE_FATAL; 69 70 /* For non-ECC ack ASAP, so that any subsequent errors get caught. */ 71 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID) 72 dec_ecc_be_ack(); 73 74 kind = invoker ? intstr : excstr; 75 76 if (!(erraddr & KN0X_EAR_VALID)) { 77 /* No idea what happened. */ 78 pr_alert_ratelimited("Unidentified bus error %s\n", kind); 79 return action; 80 } 81 82 agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr; 83 84 if (erraddr & KN0X_EAR_ECCERR) { 85 /* An ECC error on a CPU or DMA transaction. */ 86 cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr; 87 event = eccstr; 88 } else { 89 /* A CPU timeout or a DMA overrun. */ 90 cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr; 91 event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr; 92 } 93 94 address = erraddr & KN0X_EAR_ADDRESS; 95 /* For ECC errors on reads adjust for MT pipelining. */ 96 if ((erraddr & (KN0X_EAR_WRITE | KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR) 97 address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL); 98 address <<= 2; 99 100 /* Only CPU errors are fixable. */ 101 if (erraddr & KN0X_EAR_CPU && is_fixup) 102 action = MIPS_BE_FIXUP; 103 104 if (erraddr & KN0X_EAR_ECCERR) { 105 static const u8 data_sbit[32] = { 106 0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d, 107 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34, 108 0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c, 109 0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75, 110 }; 111 static const u8 data_mbit[25] = { 112 0x07, 0x0d, 0x1f, 113 0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e, 114 0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e, 115 0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f, 116 }; 117 static const char sbestr[] = "corrected single"; 118 static const char dbestr[] = "uncorrectable double"; 119 static const char mbestr[] = "uncorrectable multiple"; 120 121 if (!(address & 0x4)) 122 syn = chksyn; /* Low bank. */ 123 else 124 syn = chksyn >> 16; /* High bank. */ 125 126 if (!(syn & KN0X_ESR_VLDLO)) { 127 /* Ack now, no rewrite will happen. */ 128 dec_ecc_be_ack(); 129 130 fmt = KERN_ALERT "%s" "invalid\n"; 131 } else { 132 sngl = syn & KN0X_ESR_SNGLO; 133 syn &= KN0X_ESR_SYNLO; 134 135 /* 136 * Multibit errors may be tagged incorrectly; 137 * check the syndrome explicitly. 138 */ 139 for (i = 0; i < 25; i++) 140 if (syn == data_mbit[i]) 141 break; 142 143 if (i < 25) { 144 status = mbestr; 145 } else if (!sngl) { 146 status = dbestr; 147 } else { 148 volatile u32 *ptr = 149 (void *)CKSEG1ADDR(address); 150 151 *ptr = *ptr; /* Rewrite. */ 152 iob(); 153 154 status = sbestr; 155 action = MIPS_BE_DISCARD; 156 } 157 158 /* Ack now, now we've rewritten (or not). */ 159 dec_ecc_be_ack(); 160 161 if (syn && syn == (syn & -syn)) { 162 if (syn == 0x01) { 163 fmt = KERN_ALERT "%s" 164 "%#04x -- %s bit error " 165 "at check bit C%s\n"; 166 xbit = "X"; 167 } else { 168 fmt = KERN_ALERT "%s" 169 "%#04x -- %s bit error " 170 "at check bit C%s%u\n"; 171 } 172 i = syn >> 2; 173 } else { 174 for (i = 0; i < 32; i++) 175 if (syn == data_sbit[i]) 176 break; 177 if (i < 32) 178 fmt = KERN_ALERT "%s" 179 "%#04x -- %s bit error " 180 "at data bit D%s%u\n"; 181 else 182 fmt = KERN_ALERT "%s" 183 "%#04x -- %s bit error\n"; 184 } 185 } 186 } 187 188 if (action != MIPS_BE_FIXUP && __ratelimit(&rs)) { 189 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", 190 kind, agent, cycle, event, address); 191 192 if (erraddr & KN0X_EAR_ECCERR) 193 printk(fmt, " ECC syndrome ", syn, status, xbit, i); 194 } 195 196 return action; 197 } 198 199 int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup) 200 { 201 return dec_ecc_be_backend(regs, is_fixup, 0); 202 } 203 204 irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id) 205 { 206 struct pt_regs *regs = get_irq_regs(); 207 208 int action = dec_ecc_be_backend(regs, 0, 1); 209 210 if (action == MIPS_BE_DISCARD) 211 return IRQ_HANDLED; 212 213 /* 214 * FIXME: Find the affected processes and kill them, otherwise 215 * we must die. 216 * 217 * The interrupt is asynchronously delivered thus EPC and RA 218 * may be irrelevant, but are printed for a reference. 219 */ 220 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", 221 regs->cp0_epc, regs->regs[31]); 222 die("Unrecoverable bus error", regs); 223 } 224 225 226 /* 227 * Initialization differs a bit between KN02 and KN03/KN05, so we 228 * need two variants. Once set up, all systems can be handled the 229 * same way. 230 */ 231 static inline void dec_kn02_be_init(void) 232 { 233 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); 234 235 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); 236 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); 237 238 /* Preset write-only bits of the Control Register cache. */ 239 cached_kn02_csr = *csr | KN02_CSR_LEDS; 240 241 /* Set normal ECC detection and generation. */ 242 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN); 243 /* Enable ECC correction. */ 244 cached_kn02_csr |= KN02_CSR_CORRECT; 245 *csr = cached_kn02_csr; 246 iob(); 247 } 248 249 static inline void dec_kn03_be_init(void) 250 { 251 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); 252 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); 253 254 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); 255 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); 256 257 /* 258 * Set normal ECC detection and generation, enable ECC correction. 259 * For KN05 we also need to make sure EE (?) is enabled in the MB. 260 * Otherwise DBE/IBE exceptions would be masked but bus error 261 * interrupts would still arrive, resulting in an inevitable crash 262 * if get_dbe() triggers one. 263 */ 264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | 265 KN03_MCR_CORRECT; 266 if (current_cpu_type() == CPU_R4400SC) 267 *mbcs |= KN4K_MB_CSR_EE; 268 fast_iob(); 269 } 270 271 void __init dec_ecc_be_init(void) 272 { 273 if (mips_machtype == MACH_DS5000_200) 274 dec_kn02_be_init(); 275 else 276 dec_kn03_be_init(); 277 278 /* Clear any leftover errors from the firmware. */ 279 dec_ecc_be_ack(); 280 } 281