1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * max22007.c - MAX22007 DAC driver
4 *
5 * Driver for Analog Devices MAX22007 Digital to Analog Converter.
6 *
7 * Copyright (c) 2026 Analog Devices Inc.
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/crc8.h>
13 #include <linux/delay.h>
14 #include <linux/dev_printk.h>
15 #include <linux/device/devres.h>
16 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/iio/iio.h>
20 #include <linux/kstrtox.h>
21 #include <linux/minmax.h>
22 #include <linux/module.h>
23 #include <linux/property.h>
24 #include <linux/regmap.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/slab.h>
27 #include <linux/spi/spi.h>
28 #include <linux/string.h>
29 #include <linux/sysfs.h>
30 #include <linux/types.h>
31
32 #include <dt-bindings/iio/addac/adi,ad74413r.h>
33 struct device;
34
35 #define MAX22007_NUM_CHANNELS 4
36 #define MAX22007_REV_ID_REG 0x00
37 #define MAX22007_STAT_INTR_REG 0x01
38 #define MAX22007_INTERRUPT_EN_REG 0x02
39 #define MAX22007_CONFIG_REG 0x03
40 #define MAX22007_CONTROL_REG 0x04
41 #define MAX22007_CHANNEL_MODE_REG 0x05
42 #define MAX22007_SOFT_RESET_REG 0x06
43 #define MAX22007_DAC_CHANNEL_REG(ch) (0x07 + (ch))
44 #define MAX22007_GPIO_CTRL_REG 0x0B
45 #define MAX22007_GPIO_DATA_REG 0x0C
46 #define MAX22007_GPI_EDGE_INT_CTRL_REG 0x0D
47 #define MAX22007_GPI_INT_STATUS_REG 0x0E
48
49 /* Channel mask definitions */
50 #define MAX22007_CH_MODE_CH_MASK(ch) BIT(12 + (ch))
51 #define MAX22007_CH_PWRON_CH_MASK(ch) BIT(8 + (ch))
52 #define MAX22007_DAC_LATCH_MODE_MASK(ch) BIT(12 + (ch))
53 #define MAX22007_LDAC_UPDATE_MASK(ch) BIT(12 + (ch))
54 #define MAX22007_SW_RST_MASK BIT(8)
55 #define MAX22007_SW_CLR_MASK BIT(12)
56 #define MAX22007_SOFT_RESET_BITS_MASK (MAX22007_SW_RST_MASK | \
57 MAX22007_SW_CLR_MASK)
58 #define MAX22007_DAC_DATA_MASK GENMASK(15, 4)
59 #define MAX22007_DAC_MAX_RAW GENMASK(11, 0)
60 #define MAX22007_CRC8_POLYNOMIAL 0x8C
61 #define MAX22007_CRC_EN_MASK BIT(0)
62 #define MAX22007_RW_MASK BIT(0)
63 #define MAX22007_CRC_OVERHEAD 1
64 #define MAX22007_NUM_SUPPLIES 3
65 #define MAX22007_REF_MV 2500
66
67 /* Field value preparation macros with masking */
68 #define MAX22007_CH_PWR_VAL(ch, val) (((val) & 0x1) << (8 + (ch)))
69 #define MAX22007_CH_MODE_VAL(ch, val) (((val) & 0x1) << (12 + (ch)))
70 #define MAX22007_DAC_LATCH_MODE_VAL(ch, val) (((val) & 0x1) << (12 + (ch)))
71
72 static u8 max22007_crc8_table[CRC8_TABLE_SIZE];
73
74 static const char * const max22007_supply_names[MAX22007_NUM_SUPPLIES] = {
75 "vdd",
76 "hvdd",
77 "hvss",
78 };
79
80 struct max22007_state {
81 struct spi_device *spi;
82 struct regmap *regmap;
83 struct iio_chan_spec *iio_chans;
84 u8 tx_buf[4] __aligned(IIO_DMA_MINALIGN);
85 u8 rx_buf[4];
86 };
87
max22007_spi_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)88 static int max22007_spi_read(void *context, const void *reg, size_t reg_size,
89 void *val, size_t val_size)
90 {
91 struct max22007_state *st = context;
92 u8 calculated_crc, received_crc;
93 u8 rx_buf[4];
94 u8 reg_byte;
95 int ret;
96
97 if (reg_size != 1)
98 return -EINVAL;
99
100 if (val_size == 0 || val_size > 3)
101 return -EINVAL;
102
103 memcpy(®_byte, reg, 1);
104
105 ret = spi_write_then_read(st->spi, ®_byte, 1, rx_buf,
106 val_size + MAX22007_CRC_OVERHEAD);
107 if (ret) {
108 dev_err(&st->spi->dev, "SPI transfer failed: %d\n", ret);
109 return ret;
110 }
111
112 calculated_crc = crc8(max22007_crc8_table, ®_byte, 1, 0x00);
113 calculated_crc = crc8(max22007_crc8_table, rx_buf, 2, calculated_crc);
114 received_crc = rx_buf[val_size];
115
116 if (calculated_crc != received_crc) {
117 dev_err(&st->spi->dev, "CRC mismatch on read register %02x\n", reg_byte);
118 return -EIO;
119 }
120
121 memcpy(val, rx_buf, val_size);
122
123 return 0;
124 }
125
max22007_spi_write(void * context,const void * data,size_t count)126 static int max22007_spi_write(void *context, const void *data, size_t count)
127 {
128 struct max22007_state *st = context;
129 struct spi_transfer xfer = {
130 .tx_buf = st->tx_buf,
131 .rx_buf = st->rx_buf,
132 };
133
134 if (count + MAX22007_CRC_OVERHEAD > sizeof(st->tx_buf))
135 return -EINVAL;
136
137 memset(st->tx_buf, 0, sizeof(st->tx_buf));
138
139 xfer.len = count + MAX22007_CRC_OVERHEAD;
140
141 memcpy(st->tx_buf, data, count);
142 st->tx_buf[count] = crc8(max22007_crc8_table, st->tx_buf,
143 sizeof(st->tx_buf) - 1, 0x00);
144
145 return spi_sync_transfer(st->spi, &xfer, 1);
146 }
147
max22007_reg_readable(struct device * dev,unsigned int reg)148 static bool max22007_reg_readable(struct device *dev, unsigned int reg)
149 {
150 switch (reg) {
151 case MAX22007_REV_ID_REG:
152 case MAX22007_STAT_INTR_REG:
153 case MAX22007_CONFIG_REG:
154 case MAX22007_CONTROL_REG:
155 case MAX22007_CHANNEL_MODE_REG:
156 case MAX22007_SOFT_RESET_REG:
157 case MAX22007_GPIO_CTRL_REG:
158 case MAX22007_GPIO_DATA_REG:
159 case MAX22007_GPI_EDGE_INT_CTRL_REG:
160 case MAX22007_GPI_INT_STATUS_REG:
161 return true;
162 case MAX22007_DAC_CHANNEL_REG(0) ... MAX22007_DAC_CHANNEL_REG(MAX22007_NUM_CHANNELS - 1):
163 return true;
164 default:
165 return false;
166 }
167 }
168
max22007_reg_writable(struct device * dev,unsigned int reg)169 static bool max22007_reg_writable(struct device *dev, unsigned int reg)
170 {
171 switch (reg) {
172 case MAX22007_CONFIG_REG:
173 case MAX22007_CONTROL_REG:
174 case MAX22007_CHANNEL_MODE_REG:
175 case MAX22007_SOFT_RESET_REG:
176 case MAX22007_GPIO_CTRL_REG:
177 case MAX22007_GPIO_DATA_REG:
178 case MAX22007_GPI_EDGE_INT_CTRL_REG:
179 return true;
180 case MAX22007_DAC_CHANNEL_REG(0) ... MAX22007_DAC_CHANNEL_REG(MAX22007_NUM_CHANNELS - 1):
181 return true;
182 default:
183 return false;
184 }
185 }
186
187 static const struct regmap_bus max22007_regmap_bus = {
188 .read = max22007_spi_read,
189 .write = max22007_spi_write,
190 .read_flag_mask = MAX22007_RW_MASK,
191 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
192 .val_format_endian_default = REGMAP_ENDIAN_BIG,
193 };
194
195 static const struct regmap_config max22007_regmap_config = {
196 .reg_bits = 8,
197 .val_bits = 16,
198 .reg_shift = -1,
199 .readable_reg = max22007_reg_readable,
200 .writeable_reg = max22007_reg_writable,
201 .max_register = 0x0E,
202 };
203
max22007_write_channel_data(struct max22007_state * st,unsigned int channel,int data)204 static int max22007_write_channel_data(struct max22007_state *st,
205 unsigned int channel, int data)
206 {
207 unsigned int reg_val;
208
209 if (data < 0 || data > MAX22007_DAC_MAX_RAW)
210 return -EINVAL;
211
212 reg_val = FIELD_PREP(MAX22007_DAC_DATA_MASK, data);
213
214 return regmap_write(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), reg_val);
215 }
216
max22007_read_channel_data(struct max22007_state * st,unsigned int channel,int * data)217 static int max22007_read_channel_data(struct max22007_state *st,
218 unsigned int channel, int *data)
219 {
220 unsigned int reg_val;
221 int ret;
222
223 ret = regmap_read(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), ®_val);
224 if (ret)
225 return ret;
226
227 *data = FIELD_GET(MAX22007_DAC_DATA_MASK, reg_val);
228
229 return 0;
230 }
231
max22007_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)232 static int max22007_read_raw(struct iio_dev *indio_dev,
233 struct iio_chan_spec const *chan,
234 int *val, int *val2, long mask)
235 {
236 struct max22007_state *st = iio_priv(indio_dev);
237 int ret;
238
239 switch (mask) {
240 case IIO_CHAN_INFO_RAW:
241 ret = max22007_read_channel_data(st, chan->channel, val);
242 if (ret)
243 return ret;
244 return IIO_VAL_INT;
245 case IIO_CHAN_INFO_SCALE:
246 if (chan->type == IIO_VOLTAGE)
247 *val = 5 * MAX22007_REF_MV; /* 5 * Vref in mV */
248 else
249 *val = 25; /* Vref / (2 * Rsense) = MAX22007_REF_MV / 100 */
250 *val2 = 12; /* 12-bit DAC resolution */
251 return IIO_VAL_FRACTIONAL_LOG2;
252 default:
253 return -EINVAL;
254 }
255 }
256
max22007_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)257 static int max22007_write_raw(struct iio_dev *indio_dev,
258 struct iio_chan_spec const *chan,
259 int val, int val2, long mask)
260 {
261 struct max22007_state *st = iio_priv(indio_dev);
262
263 switch (mask) {
264 case IIO_CHAN_INFO_RAW:
265 return max22007_write_channel_data(st, chan->channel, val);
266 default:
267 return -EINVAL;
268 }
269 }
270
271 static const struct iio_info max22007_info = {
272 .read_raw = max22007_read_raw,
273 .write_raw = max22007_write_raw,
274 };
275
max22007_read_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)276 static ssize_t max22007_read_dac_powerdown(struct iio_dev *indio_dev,
277 uintptr_t private,
278 const struct iio_chan_spec *chan,
279 char *buf)
280 {
281 struct max22007_state *st = iio_priv(indio_dev);
282 unsigned int reg_val;
283 bool powerdown;
284 int ret;
285
286 ret = regmap_read(st->regmap, MAX22007_CHANNEL_MODE_REG, ®_val);
287 if (ret)
288 return ret;
289
290 powerdown = !(reg_val & MAX22007_CH_PWRON_CH_MASK(chan->channel));
291
292 return sysfs_emit(buf, "%d\n", powerdown);
293 }
294
max22007_write_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)295 static ssize_t max22007_write_dac_powerdown(struct iio_dev *indio_dev,
296 uintptr_t private,
297 const struct iio_chan_spec *chan,
298 const char *buf, size_t len)
299 {
300 struct max22007_state *st = iio_priv(indio_dev);
301 bool powerdown;
302 int ret;
303
304 ret = kstrtobool(buf, &powerdown);
305 if (ret)
306 return ret;
307
308 ret = regmap_update_bits(st->regmap, MAX22007_CHANNEL_MODE_REG,
309 MAX22007_CH_PWRON_CH_MASK(chan->channel),
310 MAX22007_CH_PWR_VAL(chan->channel, powerdown ? 0 : 1));
311 if (ret)
312 return ret;
313
314 return len;
315 }
316
317 static const struct iio_chan_spec_ext_info max22007_ext_info[] = {
318 {
319 .name = "powerdown",
320 .read = max22007_read_dac_powerdown,
321 .write = max22007_write_dac_powerdown,
322 .shared = IIO_SEPARATE,
323 },
324 { }
325 };
326
max22007_parse_channel_cfg(struct max22007_state * st,u8 * num_channels)327 static int max22007_parse_channel_cfg(struct max22007_state *st, u8 *num_channels)
328 {
329 struct device *dev = &st->spi->dev;
330 int ret, num_chan;
331 int i = 0;
332 u32 reg;
333
334 num_chan = device_get_child_node_count(dev);
335 if (!num_chan)
336 return dev_err_probe(dev, -ENODEV, "no channels configured\n");
337
338 st->iio_chans = devm_kcalloc(dev, num_chan, sizeof(*st->iio_chans), GFP_KERNEL);
339 if (!st->iio_chans)
340 return -ENOMEM;
341
342 device_for_each_child_node_scoped(dev, child) {
343 u32 ch_func;
344 enum iio_chan_type chan_type;
345
346 ret = fwnode_property_read_u32(child, "reg", ®);
347 if (ret)
348 return dev_err_probe(dev, ret,
349 "failed to read reg property of %pfwP\n", child);
350
351 if (reg >= MAX22007_NUM_CHANNELS)
352 return dev_err_probe(dev, -EINVAL,
353 "reg out of range in %pfwP\n", child);
354
355 ret = fwnode_property_read_u32(child, "adi,ch-func", &ch_func);
356 if (ret)
357 return dev_err_probe(dev, ret,
358 "missing adi,ch-func property for %pfwP\n", child);
359
360 switch (ch_func) {
361 case CH_FUNC_VOLTAGE_OUTPUT:
362 chan_type = IIO_VOLTAGE;
363 break;
364 case CH_FUNC_CURRENT_OUTPUT:
365 chan_type = IIO_CURRENT;
366 break;
367 default:
368 return dev_err_probe(dev, -EINVAL,
369 "invalid adi,ch-func %u for %pfwP\n",
370 ch_func, child);
371 }
372
373 st->iio_chans[i++] = (struct iio_chan_spec) {
374 .output = 1,
375 .indexed = 1,
376 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
377 BIT(IIO_CHAN_INFO_SCALE),
378 .ext_info = max22007_ext_info,
379 .channel = reg,
380 .type = chan_type,
381 };
382
383 ret = regmap_update_bits(st->regmap, MAX22007_CHANNEL_MODE_REG,
384 MAX22007_CH_MODE_CH_MASK(reg),
385 MAX22007_CH_MODE_VAL(reg, ch_func - 1));
386 if (ret)
387 return ret;
388
389 /* Set DAC to transparent mode (immediate update) */
390 ret = regmap_update_bits(st->regmap, MAX22007_CONFIG_REG,
391 MAX22007_DAC_LATCH_MODE_MASK(reg),
392 MAX22007_DAC_LATCH_MODE_VAL(reg, 1));
393 if (ret)
394 return ret;
395 }
396
397 *num_channels = num_chan;
398
399 return 0;
400 }
401
max22007_probe(struct spi_device * spi)402 static int max22007_probe(struct spi_device *spi)
403 {
404 struct device *dev = &spi->dev;
405 struct gpio_desc *reset_gpio;
406 struct max22007_state *st;
407 struct iio_dev *indio_dev;
408 u8 num_channels;
409 int ret;
410
411 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
412 if (!indio_dev)
413 return -ENOMEM;
414
415 st = iio_priv(indio_dev);
416 st->spi = spi;
417
418 crc8_populate_lsb(max22007_crc8_table, MAX22007_CRC8_POLYNOMIAL);
419
420 st->regmap = devm_regmap_init(dev, &max22007_regmap_bus, st,
421 &max22007_regmap_config);
422 if (IS_ERR(st->regmap))
423 return dev_err_probe(dev, PTR_ERR(st->regmap),
424 "Failed to initialize regmap\n");
425
426 ret = devm_regulator_bulk_get_enable(dev, MAX22007_NUM_SUPPLIES,
427 max22007_supply_names);
428 if (ret)
429 return dev_err_probe(dev, ret, "Failed to get and enable regulators\n");
430
431 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
432 if (IS_ERR(reset_gpio))
433 return dev_err_probe(dev, PTR_ERR(reset_gpio),
434 "Failed to get reset GPIO\n");
435
436 if (reset_gpio) {
437 gpiod_set_value_cansleep(reset_gpio, 1);
438 usleep_range(1000, 5000);
439 gpiod_set_value_cansleep(reset_gpio, 0);
440 usleep_range(1000, 5000);
441 } else {
442 ret = regmap_write(st->regmap, MAX22007_SOFT_RESET_REG,
443 MAX22007_SOFT_RESET_BITS_MASK);
444 if (ret)
445 return ret;
446 }
447
448 ret = regmap_set_bits(st->regmap, MAX22007_CONFIG_REG,
449 MAX22007_CRC_EN_MASK);
450 if (ret)
451 return ret;
452
453 ret = max22007_parse_channel_cfg(st, &num_channels);
454 if (ret)
455 return ret;
456
457 indio_dev->info = &max22007_info;
458 indio_dev->modes = INDIO_DIRECT_MODE;
459 indio_dev->channels = st->iio_chans;
460 indio_dev->num_channels = num_channels;
461 indio_dev->name = "max22007";
462
463 return devm_iio_device_register(dev, indio_dev);
464 }
465
466 static const struct spi_device_id max22007_id[] = {
467 { .name = "max22007" },
468 { }
469 };
470 MODULE_DEVICE_TABLE(spi, max22007_id);
471
472 static const struct of_device_id max22007_of_match[] = {
473 { .compatible = "adi,max22007" },
474 { }
475 };
476 MODULE_DEVICE_TABLE(of, max22007_of_match);
477
478 static struct spi_driver max22007_driver = {
479 .driver = {
480 .name = "max22007",
481 .of_match_table = max22007_of_match,
482 },
483 .probe = max22007_probe,
484 .id_table = max22007_id,
485 };
486 module_spi_driver(max22007_driver);
487
488 MODULE_AUTHOR("Janani Sunil <janani.sunil@analog.com>");
489 MODULE_DESCRIPTION("Analog Devices MAX22007 DAC");
490 MODULE_LICENSE("GPL");
491