1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * omap-dmic.c -- OMAP ASoC DMIC DAI driver
4 *
5 * Copyright (C) 2010 - 2011 Texas Instruments
6 *
7 * Author: David Lambert <dlambert@ti.com>
8 * Misael Lopez Cruz <misael.lopez@ti.com>
9 * Liam Girdwood <lrg@ti.com>
10 * Peter Ujfalusi <peter.ujfalusi@ti.com>
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/slab.h>
20 #include <linux/pm_runtime.h>
21
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/initval.h>
26 #include <sound/soc.h>
27 #include <sound/dmaengine_pcm.h>
28
29 #include "omap-dmic.h"
30 #include "sdma-pcm.h"
31
32 struct omap_dmic {
33 struct device *dev;
34 void __iomem *io_base;
35 struct clk *fclk;
36 struct pm_qos_request pm_qos_req;
37 int latency;
38 int fclk_freq;
39 int out_freq;
40 int clk_div;
41 int sysclk;
42 int threshold;
43 u32 ch_enabled;
44 bool active;
45 struct mutex mutex;
46
47 struct snd_dmaengine_dai_dma_data dma_data;
48 };
49
omap_dmic_write(struct omap_dmic * dmic,u16 reg,u32 val)50 static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
51 {
52 writel_relaxed(val, dmic->io_base + reg);
53 }
54
omap_dmic_read(struct omap_dmic * dmic,u16 reg)55 static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
56 {
57 return readl_relaxed(dmic->io_base + reg);
58 }
59
omap_dmic_start(struct omap_dmic * dmic)60 static inline void omap_dmic_start(struct omap_dmic *dmic)
61 {
62 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
63
64 /* Configure DMA controller */
65 omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
66 OMAP_DMIC_DMA_ENABLE);
67
68 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
69 }
70
omap_dmic_stop(struct omap_dmic * dmic)71 static inline void omap_dmic_stop(struct omap_dmic *dmic)
72 {
73 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
74 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
75 ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
76
77 /* Disable DMA request generation */
78 omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
79 OMAP_DMIC_DMA_ENABLE);
80
81 }
82
dmic_is_enabled(struct omap_dmic * dmic)83 static inline int dmic_is_enabled(struct omap_dmic *dmic)
84 {
85 return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
86 OMAP_DMIC_UP_ENABLE_MASK;
87 }
88
omap_dmic_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)89 static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
90 struct snd_soc_dai *dai)
91 {
92 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
93
94 guard(mutex)(&dmic->mutex);
95
96 if (snd_soc_dai_active(dai))
97 return -EBUSY;
98
99 dmic->active = 1;
100 return 0;
101 }
102
omap_dmic_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)103 static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
104 struct snd_soc_dai *dai)
105 {
106 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
107
108 guard(mutex)(&dmic->mutex);
109
110 cpu_latency_qos_remove_request(&dmic->pm_qos_req);
111
112 if (!snd_soc_dai_active(dai))
113 dmic->active = 0;
114 }
115
omap_dmic_select_divider(struct omap_dmic * dmic,int sample_rate)116 static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
117 {
118 int divider = -EINVAL;
119
120 /*
121 * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
122 * configuration.
123 */
124 if (sample_rate == 192000) {
125 if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
126 divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
127 else
128 dev_err(dmic->dev,
129 "invalid clock configuration for 192KHz\n");
130
131 return divider;
132 }
133
134 switch (dmic->out_freq) {
135 case 1536000:
136 if (dmic->fclk_freq != 24576000)
137 goto div_err;
138 divider = 0x4; /* Divider: 16 */
139 break;
140 case 2400000:
141 switch (dmic->fclk_freq) {
142 case 12000000:
143 divider = 0x5; /* Divider: 5 */
144 break;
145 case 19200000:
146 divider = 0x0; /* Divider: 8 */
147 break;
148 case 24000000:
149 divider = 0x2; /* Divider: 10 */
150 break;
151 default:
152 goto div_err;
153 }
154 break;
155 case 3072000:
156 if (dmic->fclk_freq != 24576000)
157 goto div_err;
158 divider = 0x3; /* Divider: 8 */
159 break;
160 case 3840000:
161 if (dmic->fclk_freq != 19200000)
162 goto div_err;
163 divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
164 break;
165 default:
166 dev_err(dmic->dev, "invalid out frequency: %dHz\n",
167 dmic->out_freq);
168 break;
169 }
170
171 return divider;
172
173 div_err:
174 dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
175 dmic->out_freq, dmic->fclk_freq);
176 return -EINVAL;
177 }
178
omap_dmic_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)179 static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
180 struct snd_pcm_hw_params *params,
181 struct snd_soc_dai *dai)
182 {
183 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
184 struct snd_dmaengine_dai_dma_data *dma_data;
185 int channels;
186
187 dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
188 if (dmic->clk_div < 0) {
189 dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
190 dmic->out_freq, dmic->fclk_freq);
191 return -EINVAL;
192 }
193
194 dmic->ch_enabled = 0;
195 channels = params_channels(params);
196 switch (channels) {
197 case 6:
198 dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
199 fallthrough;
200 case 4:
201 dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
202 fallthrough;
203 case 2:
204 dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
205 break;
206 default:
207 dev_err(dmic->dev, "invalid number of legacy channels\n");
208 return -EINVAL;
209 }
210
211 /* packet size is threshold * channels */
212 dma_data = snd_soc_dai_get_dma_data(dai, substream);
213 dma_data->maxburst = dmic->threshold * channels;
214 dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
215 params_rate(params);
216
217 return 0;
218 }
219
omap_dmic_dai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)220 static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
221 struct snd_soc_dai *dai)
222 {
223 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
224 u32 ctrl;
225
226 if (cpu_latency_qos_request_active(&dmic->pm_qos_req))
227 cpu_latency_qos_update_request(&dmic->pm_qos_req,
228 dmic->latency);
229
230 /* Configure uplink threshold */
231 omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
232
233 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
234
235 /* Set dmic out format */
236 ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
237 ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
238 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
239
240 /* Configure dmic clock divider */
241 ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
242 ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
243
244 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
245
246 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
247 ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
248 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
249
250 return 0;
251 }
252
omap_dmic_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)253 static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
254 int cmd, struct snd_soc_dai *dai)
255 {
256 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
257
258 switch (cmd) {
259 case SNDRV_PCM_TRIGGER_START:
260 omap_dmic_start(dmic);
261 break;
262 case SNDRV_PCM_TRIGGER_STOP:
263 omap_dmic_stop(dmic);
264 break;
265 default:
266 break;
267 }
268
269 return 0;
270 }
271
omap_dmic_select_fclk(struct omap_dmic * dmic,int clk_id,unsigned int freq)272 static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
273 unsigned int freq)
274 {
275 struct clk *parent_clk, *mux;
276 char *parent_clk_name;
277 int ret = 0;
278
279 switch (freq) {
280 case 12000000:
281 case 19200000:
282 case 24000000:
283 case 24576000:
284 break;
285 default:
286 dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
287 dmic->fclk_freq = 0;
288 return -EINVAL;
289 }
290
291 if (dmic->sysclk == clk_id) {
292 dmic->fclk_freq = freq;
293 return 0;
294 }
295
296 /* re-parent not allowed if a stream is ongoing */
297 if (dmic->active && dmic_is_enabled(dmic)) {
298 dev_err(dmic->dev, "can't re-parent when DMIC active\n");
299 return -EBUSY;
300 }
301
302 switch (clk_id) {
303 case OMAP_DMIC_SYSCLK_PAD_CLKS:
304 parent_clk_name = "pad_clks_ck";
305 break;
306 case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
307 parent_clk_name = "slimbus_clk";
308 break;
309 case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
310 parent_clk_name = "dmic_sync_mux_ck";
311 break;
312 default:
313 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
314 return -EINVAL;
315 }
316
317 parent_clk = clk_get(dmic->dev, parent_clk_name);
318 if (IS_ERR(parent_clk)) {
319 dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
320 return -ENODEV;
321 }
322
323 mux = clk_get_parent(dmic->fclk);
324 if (!mux) {
325 dev_err(dmic->dev, "can't get fck mux parent\n");
326 clk_put(parent_clk);
327 return -ENODEV;
328 }
329
330 scoped_guard(mutex, &dmic->mutex) {
331 if (dmic->active) {
332 /* disable clock while reparenting */
333 pm_runtime_put_sync(dmic->dev);
334 ret = clk_set_parent(mux, parent_clk);
335 pm_runtime_get_sync(dmic->dev);
336 } else {
337 ret = clk_set_parent(mux, parent_clk);
338 }
339 }
340
341 if (ret < 0) {
342 dev_err(dmic->dev, "re-parent failed\n");
343 } else {
344 dmic->sysclk = clk_id;
345 dmic->fclk_freq = freq;
346 }
347
348 clk_put(mux);
349 clk_put(parent_clk);
350
351 return ret;
352 }
353
omap_dmic_select_outclk(struct omap_dmic * dmic,int clk_id,unsigned int freq)354 static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
355 unsigned int freq)
356 {
357 int ret = 0;
358
359 if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
360 dev_err(dmic->dev, "output clk_id (%d) not supported\n",
361 clk_id);
362 return -EINVAL;
363 }
364
365 switch (freq) {
366 case 1536000:
367 case 2400000:
368 case 3072000:
369 case 3840000:
370 dmic->out_freq = freq;
371 break;
372 default:
373 dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
374 dmic->out_freq = 0;
375 ret = -EINVAL;
376 }
377
378 return ret;
379 }
380
omap_dmic_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)381 static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
382 unsigned int freq, int dir)
383 {
384 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
385
386 if (dir == SND_SOC_CLOCK_IN)
387 return omap_dmic_select_fclk(dmic, clk_id, freq);
388 else if (dir == SND_SOC_CLOCK_OUT)
389 return omap_dmic_select_outclk(dmic, clk_id, freq);
390
391 dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
392 return -EINVAL;
393 }
394
omap_dmic_probe(struct snd_soc_dai * dai)395 static int omap_dmic_probe(struct snd_soc_dai *dai)
396 {
397 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
398
399 pm_runtime_enable(dmic->dev);
400
401 /* Disable lines while request is ongoing */
402 pm_runtime_get_sync(dmic->dev);
403 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
404 pm_runtime_put_sync(dmic->dev);
405
406 /* Configure DMIC threshold value */
407 dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
408
409 snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
410
411 return 0;
412 }
413
omap_dmic_remove(struct snd_soc_dai * dai)414 static int omap_dmic_remove(struct snd_soc_dai *dai)
415 {
416 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
417
418 pm_runtime_disable(dmic->dev);
419
420 return 0;
421 }
422
423 static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
424 .probe = omap_dmic_probe,
425 .remove = omap_dmic_remove,
426 .startup = omap_dmic_dai_startup,
427 .shutdown = omap_dmic_dai_shutdown,
428 .hw_params = omap_dmic_dai_hw_params,
429 .prepare = omap_dmic_dai_prepare,
430 .trigger = omap_dmic_dai_trigger,
431 .set_sysclk = omap_dmic_set_dai_sysclk,
432 };
433
434 static struct snd_soc_dai_driver omap_dmic_dai = {
435 .name = "omap-dmic",
436 .capture = {
437 .channels_min = 2,
438 .channels_max = 6,
439 .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
440 .formats = SNDRV_PCM_FMTBIT_S32_LE,
441 .sig_bits = 24,
442 },
443 .ops = &omap_dmic_dai_ops,
444 };
445
446 static const struct snd_soc_component_driver omap_dmic_component = {
447 .name = "omap-dmic",
448 .legacy_dai_naming = 1,
449 };
450
asoc_dmic_probe(struct platform_device * pdev)451 static int asoc_dmic_probe(struct platform_device *pdev)
452 {
453 struct omap_dmic *dmic;
454 struct resource *res;
455 int ret;
456
457 dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
458 if (!dmic)
459 return -ENOMEM;
460
461 platform_set_drvdata(pdev, dmic);
462 dmic->dev = &pdev->dev;
463 dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
464
465 mutex_init(&dmic->mutex);
466
467 dmic->fclk = devm_clk_get(dmic->dev, "fck");
468 if (IS_ERR(dmic->fclk))
469 return dev_err_probe(dmic->dev, PTR_ERR(dmic->fclk),
470 "can't get fck\n");
471
472 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
473 if (!res) {
474 dev_err(dmic->dev, "invalid dma memory resource\n");
475 return -ENODEV;
476 }
477 dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
478
479 dmic->dma_data.filter_data = "up_link";
480
481 dmic->io_base = devm_platform_ioremap_resource_byname(pdev, "mpu");
482 if (IS_ERR(dmic->io_base))
483 return PTR_ERR(dmic->io_base);
484
485 ret = devm_snd_soc_register_component(&pdev->dev,
486 &omap_dmic_component,
487 &omap_dmic_dai, 1);
488 if (ret)
489 return ret;
490
491 ret = sdma_pcm_platform_register(&pdev->dev, NULL, "up_link");
492 if (ret)
493 return ret;
494
495 return 0;
496 }
497
498 static const struct of_device_id omap_dmic_of_match[] = {
499 { .compatible = "ti,omap4-dmic", },
500 { }
501 };
502 MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
503
504 static struct platform_driver asoc_dmic_driver = {
505 .driver = {
506 .name = "omap-dmic",
507 .of_match_table = omap_dmic_of_match,
508 },
509 .probe = asoc_dmic_probe,
510 };
511
512 module_platform_driver(asoc_dmic_driver);
513
514 MODULE_ALIAS("platform:omap-dmic");
515 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
516 MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
517 MODULE_LICENSE("GPL");
518