1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface 4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 5 * 6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c" 7 * Copyright (C) 2008 Magnus Damm 8 * 9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c", 10 * Copyright (C) 2006, Sascha Hauer, Pengutronix 11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/err.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_graph.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/time.h> 30 #include <linux/videodev2.h> 31 32 #include <media/v4l2-async.h> 33 #include <media/v4l2-common.h> 34 #include <media/v4l2-ctrls.h> 35 #include <media/v4l2-dev.h> 36 #include <media/v4l2-device.h> 37 #include <media/v4l2-event.h> 38 #include <media/v4l2-fwnode.h> 39 #include <media/v4l2-image-sizes.h> 40 #include <media/v4l2-ioctl.h> 41 #include <media/v4l2-mediabus.h> 42 #include <media/videobuf2-dma-contig.h> 43 44 #include <media/drv-intf/renesas-ceu.h> 45 46 #define DRIVER_NAME "renesas-ceu" 47 48 /* CEU registers offsets and masks. */ 49 #define CEU_CAPSR 0x00 /* Capture start register */ 50 #define CEU_CAPCR 0x04 /* Capture control register */ 51 #define CEU_CAMCR 0x08 /* Capture interface control register */ 52 #define CEU_CAMOR 0x10 /* Capture interface offset register */ 53 #define CEU_CAPWR 0x14 /* Capture interface width register */ 54 #define CEU_CAIFR 0x18 /* Capture interface input format register */ 55 #define CEU_CRCNTR 0x28 /* CEU register control register */ 56 #define CEU_CRCMPR 0x2c /* CEU register forcible control register */ 57 #define CEU_CFLCR 0x30 /* Capture filter control register */ 58 #define CEU_CFSZR 0x34 /* Capture filter size clip register */ 59 #define CEU_CDWDR 0x38 /* Capture destination width register */ 60 #define CEU_CDAYR 0x3c /* Capture data address Y register */ 61 #define CEU_CDACR 0x40 /* Capture data address C register */ 62 #define CEU_CFWCR 0x5c /* Firewall operation control register */ 63 #define CEU_CDOCR 0x64 /* Capture data output control register */ 64 #define CEU_CEIER 0x70 /* Capture event interrupt enable register */ 65 #define CEU_CETCR 0x74 /* Capture event flag clear register */ 66 #define CEU_CSTSR 0x7c /* Capture status register */ 67 #define CEU_CSRTR 0x80 /* Capture software reset register */ 68 69 /* Data synchronous fetch mode. */ 70 #define CEU_CAMCR_JPEG BIT(4) 71 72 /* Input components ordering: CEU_CAMCR.DTARY field. */ 73 #define CEU_CAMCR_DTARY_8_UYVY (0x00 << 8) 74 #define CEU_CAMCR_DTARY_8_VYUY (0x01 << 8) 75 #define CEU_CAMCR_DTARY_8_YUYV (0x02 << 8) 76 #define CEU_CAMCR_DTARY_8_YVYU (0x03 << 8) 77 /* TODO: input components ordering for 16 bits input. */ 78 79 /* Bus transfer MTU. */ 80 #define CEU_CAPCR_BUS_WIDTH256 (0x3 << 20) 81 82 /* Bus width configuration. */ 83 #define CEU_CAMCR_DTIF_16BITS BIT(12) 84 85 /* No downsampling to planar YUV420 in image fetch mode. */ 86 #define CEU_CDOCR_NO_DOWSAMPLE BIT(4) 87 88 /* Swap all input data in 8-bit, 16-bits and 32-bits units (Figure 46.45). */ 89 #define CEU_CDOCR_SWAP_ENDIANNESS (7) 90 91 /* Capture reset and enable bits. */ 92 #define CEU_CAPSR_CPKIL BIT(16) 93 #define CEU_CAPSR_CE BIT(0) 94 95 /* CEU operating flag bit. */ 96 #define CEU_CAPCR_CTNCP BIT(16) 97 #define CEU_CSTRST_CPTON BIT(0) 98 99 /* Platform specific IRQ source flags. */ 100 #define CEU_CETCR_ALL_IRQS_RZ 0x397f313 101 #define CEU_CETCR_ALL_IRQS_SH4 0x3d7f313 102 103 /* Prohibited register access interrupt bit. */ 104 #define CEU_CETCR_IGRW BIT(4) 105 /* One-frame capture end interrupt. */ 106 #define CEU_CEIER_CPE BIT(0) 107 /* VBP error. */ 108 #define CEU_CEIER_VBP BIT(20) 109 #define CEU_CEIER_MASK (CEU_CEIER_CPE | CEU_CEIER_VBP) 110 111 #define CEU_MAX_WIDTH 2560 112 #define CEU_MAX_HEIGHT 1920 113 #define CEU_MAX_BPL 8188 114 #define CEU_W_MAX(w) ((w) < CEU_MAX_WIDTH ? (w) : CEU_MAX_WIDTH) 115 #define CEU_H_MAX(h) ((h) < CEU_MAX_HEIGHT ? (h) : CEU_MAX_HEIGHT) 116 117 /* 118 * ceu_bus_fmt - describe a 8-bits yuyv format the sensor can produce 119 * 120 * @mbus_code: bus format code 121 * @fmt_order: CEU_CAMCR.DTARY ordering of input components (Y, Cb, Cr) 122 * @fmt_order_swap: swapped CEU_CAMCR.DTARY ordering of input components 123 * (Y, Cr, Cb) 124 * @swapped: does Cr appear before Cb? 125 * @bps: number of bits sent over bus for each sample 126 * @bpp: number of bits per pixels unit 127 */ 128 struct ceu_mbus_fmt { 129 u32 mbus_code; 130 u32 fmt_order; 131 u32 fmt_order_swap; 132 bool swapped; 133 u8 bps; 134 u8 bpp; 135 }; 136 137 /* 138 * ceu_buffer - Link vb2 buffer to the list of available buffers. 139 */ 140 struct ceu_buffer { 141 struct vb2_v4l2_buffer vb; 142 struct list_head queue; 143 }; 144 145 static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf) 146 { 147 return container_of(vbuf, struct ceu_buffer, vb); 148 } 149 150 /* 151 * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice. 152 */ 153 struct ceu_subdev { 154 struct v4l2_async_connection asd; 155 struct v4l2_subdev *v4l2_sd; 156 157 /* per-subdevice mbus configuration options */ 158 unsigned int mbus_flags; 159 struct ceu_mbus_fmt mbus_fmt; 160 }; 161 162 static struct ceu_subdev *to_ceu_subdev(struct v4l2_async_connection *asd) 163 { 164 return container_of(asd, struct ceu_subdev, asd); 165 } 166 167 /* 168 * ceu_device - CEU device instance 169 */ 170 struct ceu_device { 171 struct device *dev; 172 struct video_device vdev; 173 struct v4l2_device v4l2_dev; 174 175 /* subdevices descriptors */ 176 struct ceu_subdev **subdevs; 177 /* the subdevice currently in use */ 178 struct ceu_subdev *sd; 179 unsigned int sd_index; 180 unsigned int num_sd; 181 182 /* platform specific mask with all IRQ sources flagged */ 183 u32 irq_mask; 184 185 /* currently configured field and pixel format */ 186 enum v4l2_field field; 187 struct v4l2_pix_format_mplane v4l2_pix; 188 189 /* async subdev notification helpers */ 190 struct v4l2_async_notifier notifier; 191 192 /* vb2 queue, capture buffer list and active buffer pointer */ 193 struct vb2_queue vb2_vq; 194 struct list_head capture; 195 struct vb2_v4l2_buffer *active; 196 unsigned int sequence; 197 198 /* mlock - lock access to interface reset and vb2 queue */ 199 struct mutex mlock; 200 201 /* lock - lock access to capture buffer queue and active buffer */ 202 spinlock_t lock; 203 204 /* base - CEU memory base address */ 205 void __iomem *base; 206 }; 207 208 static inline struct ceu_device *v4l2_to_ceu(struct v4l2_device *v4l2_dev) 209 { 210 return container_of(v4l2_dev, struct ceu_device, v4l2_dev); 211 } 212 213 /* --- CEU memory output formats --- */ 214 215 /* 216 * ceu_fmt - describe a memory output format supported by CEU interface. 217 * 218 * @fourcc: memory layout fourcc format code 219 * @bpp: number of bits for each pixel stored in memory 220 */ 221 struct ceu_fmt { 222 u32 fourcc; 223 u32 bpp; 224 }; 225 226 /* 227 * ceu_format_list - List of supported memory output formats 228 * 229 * If sensor provides any YUYV bus format, all the following planar memory 230 * formats are available thanks to CEU re-ordering and sub-sampling 231 * capabilities. 232 */ 233 static const struct ceu_fmt ceu_fmt_list[] = { 234 { 235 .fourcc = V4L2_PIX_FMT_NV16, 236 .bpp = 16, 237 }, 238 { 239 .fourcc = V4L2_PIX_FMT_NV61, 240 .bpp = 16, 241 }, 242 { 243 .fourcc = V4L2_PIX_FMT_NV12, 244 .bpp = 12, 245 }, 246 { 247 .fourcc = V4L2_PIX_FMT_NV21, 248 .bpp = 12, 249 }, 250 { 251 .fourcc = V4L2_PIX_FMT_YUYV, 252 .bpp = 16, 253 }, 254 { 255 .fourcc = V4L2_PIX_FMT_UYVY, 256 .bpp = 16, 257 }, 258 { 259 .fourcc = V4L2_PIX_FMT_YVYU, 260 .bpp = 16, 261 }, 262 { 263 .fourcc = V4L2_PIX_FMT_VYUY, 264 .bpp = 16, 265 }, 266 }; 267 268 static const struct ceu_fmt *get_ceu_fmt_from_fourcc(unsigned int fourcc) 269 { 270 const struct ceu_fmt *fmt = &ceu_fmt_list[0]; 271 unsigned int i; 272 273 for (i = 0; i < ARRAY_SIZE(ceu_fmt_list); i++, fmt++) 274 if (fmt->fourcc == fourcc) 275 return fmt; 276 277 return NULL; 278 } 279 280 static bool ceu_fmt_mplane(struct v4l2_pix_format_mplane *pix) 281 { 282 switch (pix->pixelformat) { 283 case V4L2_PIX_FMT_YUYV: 284 case V4L2_PIX_FMT_UYVY: 285 case V4L2_PIX_FMT_YVYU: 286 case V4L2_PIX_FMT_VYUY: 287 return false; 288 case V4L2_PIX_FMT_NV16: 289 case V4L2_PIX_FMT_NV61: 290 case V4L2_PIX_FMT_NV12: 291 case V4L2_PIX_FMT_NV21: 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 /* --- CEU HW operations --- */ 299 300 static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data) 301 { 302 iowrite32(data, priv->base + reg_offs); 303 } 304 305 static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs) 306 { 307 return ioread32(priv->base + reg_offs); 308 } 309 310 /* 311 * ceu_soft_reset() - Software reset the CEU interface. 312 * @ceu_device: CEU device. 313 * 314 * Returns 0 for success, -EIO for error. 315 */ 316 static int ceu_soft_reset(struct ceu_device *ceudev) 317 { 318 unsigned int i; 319 320 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL); 321 322 for (i = 0; i < 100; i++) { 323 if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON)) 324 break; 325 udelay(1); 326 } 327 328 if (i == 100) { 329 dev_err(ceudev->dev, "soft reset time out\n"); 330 return -EIO; 331 } 332 333 for (i = 0; i < 100; i++) { 334 if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL)) 335 return 0; 336 udelay(1); 337 } 338 339 /* If we get here, CEU has not reset properly. */ 340 return -EIO; 341 } 342 343 /* --- CEU Capture Operations --- */ 344 345 /* 346 * ceu_hw_config() - Configure CEU interface registers. 347 */ 348 static int ceu_hw_config(struct ceu_device *ceudev) 349 { 350 u32 camcr, cdocr, cfzsr, cdwdr, capwr; 351 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 352 struct ceu_subdev *ceu_sd = ceudev->sd; 353 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt; 354 unsigned int mbus_flags = ceu_sd->mbus_flags; 355 356 /* Start configuring CEU registers */ 357 ceu_write(ceudev, CEU_CAIFR, 0); 358 ceu_write(ceudev, CEU_CFWCR, 0); 359 ceu_write(ceudev, CEU_CRCNTR, 0); 360 ceu_write(ceudev, CEU_CRCMPR, 0); 361 362 /* Set the frame capture period for both image capture and data sync. */ 363 capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8; 364 365 /* 366 * Swap input data endianness by default. 367 * In data fetch mode bytes are received in chunks of 8 bytes. 368 * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first) 369 * The data is however by default written to memory in reverse order: 370 * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte) 371 * 372 * Use CEU_CDOCR[2:0] to swap data ordering. 373 */ 374 cdocr = CEU_CDOCR_SWAP_ENDIANNESS; 375 376 /* 377 * Configure CAMCR and CDOCR: 378 * match input components ordering with memory output format and 379 * handle downsampling to YUV420. 380 * 381 * If the memory output planar format is 'swapped' (Cr before Cb) and 382 * input format is not, use the swapped version of CAMCR.DTARY. 383 * 384 * If the memory output planar format is not 'swapped' (Cb before Cr) 385 * and input format is, use the swapped version of CAMCR.DTARY. 386 * 387 * CEU by default downsample to planar YUV420 (CDCOR[4] = 0). 388 * If output is planar YUV422 set CDOCR[4] = 1 389 * 390 * No downsample for data fetch sync mode. 391 */ 392 switch (pix->pixelformat) { 393 /* Data fetch sync mode */ 394 case V4L2_PIX_FMT_YUYV: 395 case V4L2_PIX_FMT_YVYU: 396 case V4L2_PIX_FMT_UYVY: 397 case V4L2_PIX_FMT_VYUY: 398 camcr = CEU_CAMCR_JPEG; 399 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 400 cfzsr = (pix->height << 16) | pix->width; 401 cdwdr = pix->plane_fmt[0].bytesperline; 402 break; 403 404 /* Non-swapped planar image capture mode. */ 405 case V4L2_PIX_FMT_NV16: 406 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 407 fallthrough; 408 case V4L2_PIX_FMT_NV12: 409 if (mbus_fmt->swapped) 410 camcr = mbus_fmt->fmt_order_swap; 411 else 412 camcr = mbus_fmt->fmt_order; 413 414 cfzsr = (pix->height << 16) | pix->width; 415 cdwdr = pix->width; 416 break; 417 418 /* Swapped planar image capture mode. */ 419 case V4L2_PIX_FMT_NV61: 420 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 421 fallthrough; 422 case V4L2_PIX_FMT_NV21: 423 if (mbus_fmt->swapped) 424 camcr = mbus_fmt->fmt_order; 425 else 426 camcr = mbus_fmt->fmt_order_swap; 427 428 cfzsr = (pix->height << 16) | pix->width; 429 cdwdr = pix->width; 430 break; 431 432 default: 433 return -EINVAL; 434 } 435 436 camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0; 437 camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0; 438 439 /* TODO: handle 16 bit bus width with DTIF bit in CAMCR */ 440 ceu_write(ceudev, CEU_CAMCR, camcr); 441 ceu_write(ceudev, CEU_CDOCR, cdocr); 442 ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256); 443 444 /* 445 * TODO: make CAMOR offsets configurable. 446 * CAMOR wants to know the number of blanks between a VS/HS signal 447 * and valid data. This value should actually come from the sensor... 448 */ 449 ceu_write(ceudev, CEU_CAMOR, 0); 450 451 /* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */ 452 ceu_write(ceudev, CEU_CAPWR, capwr); 453 ceu_write(ceudev, CEU_CFSZR, cfzsr); 454 ceu_write(ceudev, CEU_CDWDR, cdwdr); 455 456 return 0; 457 } 458 459 /* 460 * ceu_capture() - Trigger start of a capture sequence. 461 * 462 * Program the CEU DMA registers with addresses where to transfer image data. 463 */ 464 static int ceu_capture(struct ceu_device *ceudev) 465 { 466 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 467 dma_addr_t phys_addr_top; 468 469 phys_addr_top = 470 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 0); 471 ceu_write(ceudev, CEU_CDAYR, phys_addr_top); 472 473 /* Ignore CbCr plane for non multi-planar image formats. */ 474 if (ceu_fmt_mplane(pix)) { 475 phys_addr_top = 476 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 477 1); 478 ceu_write(ceudev, CEU_CDACR, phys_addr_top); 479 } 480 481 /* 482 * Trigger new capture start: once for each frame, as we work in 483 * one-frame capture mode. 484 */ 485 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CE); 486 487 return 0; 488 } 489 490 static irqreturn_t ceu_irq(int irq, void *data) 491 { 492 struct ceu_device *ceudev = data; 493 struct vb2_v4l2_buffer *vbuf; 494 struct ceu_buffer *buf; 495 u32 status; 496 497 /* Clean interrupt status. */ 498 status = ceu_read(ceudev, CEU_CETCR); 499 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask); 500 501 /* Unexpected interrupt. */ 502 if (!(status & CEU_CEIER_MASK)) 503 return IRQ_NONE; 504 505 spin_lock(&ceudev->lock); 506 507 /* Stale interrupt from a released buffer, ignore it. */ 508 vbuf = ceudev->active; 509 if (!vbuf) { 510 spin_unlock(&ceudev->lock); 511 return IRQ_HANDLED; 512 } 513 514 /* 515 * When a VBP interrupt occurs, no capture end interrupt will occur 516 * and the image of that frame is not captured correctly. 517 */ 518 if (status & CEU_CEIER_VBP) { 519 dev_err(ceudev->dev, "VBP interrupt: abort capture\n"); 520 goto error_irq_out; 521 } 522 523 /* Prepare to return the 'previous' buffer. */ 524 vbuf->vb2_buf.timestamp = ktime_get_ns(); 525 vbuf->sequence = ceudev->sequence++; 526 vbuf->field = ceudev->field; 527 528 /* Prepare a new 'active' buffer and trigger a new capture. */ 529 if (!list_empty(&ceudev->capture)) { 530 buf = list_first_entry(&ceudev->capture, struct ceu_buffer, 531 queue); 532 list_del(&buf->queue); 533 ceudev->active = &buf->vb; 534 535 ceu_capture(ceudev); 536 } 537 538 /* Return the 'previous' buffer. */ 539 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE); 540 541 spin_unlock(&ceudev->lock); 542 543 return IRQ_HANDLED; 544 545 error_irq_out: 546 /* Return the 'previous' buffer and all queued ones. */ 547 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_ERROR); 548 549 list_for_each_entry(buf, &ceudev->capture, queue) 550 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 551 552 spin_unlock(&ceudev->lock); 553 554 return IRQ_HANDLED; 555 } 556 557 /* --- CEU Videobuf2 operations --- */ 558 559 static void ceu_update_plane_sizes(struct v4l2_plane_pix_format *plane, 560 unsigned int bpl, unsigned int szimage) 561 { 562 memset(plane, 0, sizeof(*plane)); 563 564 plane->sizeimage = szimage; 565 if (plane->bytesperline < bpl || plane->bytesperline > CEU_MAX_BPL) 566 plane->bytesperline = bpl; 567 } 568 569 /* 570 * ceu_calc_plane_sizes() - Fill per-plane 'struct v4l2_plane_pix_format' 571 * information according to the currently configured 572 * pixel format. 573 * @ceu_device: CEU device. 574 * @ceu_fmt: Active image format. 575 * @pix: Pixel format information (store line width and image sizes) 576 */ 577 static void ceu_calc_plane_sizes(struct ceu_device *ceudev, 578 const struct ceu_fmt *ceu_fmt, 579 struct v4l2_pix_format_mplane *pix) 580 { 581 unsigned int bpl, szimage; 582 583 switch (pix->pixelformat) { 584 case V4L2_PIX_FMT_YUYV: 585 case V4L2_PIX_FMT_UYVY: 586 case V4L2_PIX_FMT_YVYU: 587 case V4L2_PIX_FMT_VYUY: 588 pix->num_planes = 1; 589 bpl = pix->width * ceu_fmt->bpp / 8; 590 szimage = pix->height * bpl; 591 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage); 592 break; 593 594 case V4L2_PIX_FMT_NV12: 595 case V4L2_PIX_FMT_NV21: 596 pix->num_planes = 2; 597 bpl = pix->width; 598 szimage = pix->height * pix->width; 599 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage); 600 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage / 2); 601 break; 602 603 case V4L2_PIX_FMT_NV16: 604 case V4L2_PIX_FMT_NV61: 605 default: 606 pix->num_planes = 2; 607 bpl = pix->width; 608 szimage = pix->height * pix->width; 609 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage); 610 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage); 611 break; 612 } 613 } 614 615 /* 616 * ceu_vb2_setup() - is called to check whether the driver can accept the 617 * requested number of buffers and to fill in plane sizes 618 * for the current frame format, if required. 619 */ 620 static int ceu_vb2_setup(struct vb2_queue *vq, unsigned int *count, 621 unsigned int *num_planes, unsigned int sizes[], 622 struct device *alloc_devs[]) 623 { 624 struct ceu_device *ceudev = vb2_get_drv_priv(vq); 625 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 626 unsigned int i; 627 628 /* num_planes is set: just check plane sizes. */ 629 if (*num_planes) { 630 for (i = 0; i < pix->num_planes; i++) 631 if (sizes[i] < pix->plane_fmt[i].sizeimage) 632 return -EINVAL; 633 634 return 0; 635 } 636 637 /* num_planes not set: called from REQBUFS, just set plane sizes. */ 638 *num_planes = pix->num_planes; 639 for (i = 0; i < pix->num_planes; i++) 640 sizes[i] = pix->plane_fmt[i].sizeimage; 641 642 return 0; 643 } 644 645 static void ceu_vb2_queue(struct vb2_buffer *vb) 646 { 647 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue); 648 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 649 struct ceu_buffer *buf = vb2_to_ceu(vbuf); 650 unsigned long irqflags; 651 652 spin_lock_irqsave(&ceudev->lock, irqflags); 653 list_add_tail(&buf->queue, &ceudev->capture); 654 spin_unlock_irqrestore(&ceudev->lock, irqflags); 655 } 656 657 static int ceu_vb2_prepare(struct vb2_buffer *vb) 658 { 659 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue); 660 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 661 unsigned int i; 662 663 for (i = 0; i < pix->num_planes; i++) { 664 if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) { 665 dev_err(ceudev->dev, 666 "Plane size too small (%lu < %u)\n", 667 vb2_plane_size(vb, i), 668 pix->plane_fmt[i].sizeimage); 669 return -EINVAL; 670 } 671 672 vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage); 673 } 674 675 return 0; 676 } 677 678 static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count) 679 { 680 struct ceu_device *ceudev = vb2_get_drv_priv(vq); 681 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 682 struct ceu_buffer *buf; 683 unsigned long irqflags; 684 int ret; 685 686 /* Program the CEU interface according to the CEU image format. */ 687 ret = ceu_hw_config(ceudev); 688 if (ret) 689 goto error_return_bufs; 690 691 ret = v4l2_subdev_call(v4l2_sd, video, s_stream, 1); 692 if (ret && ret != -ENOIOCTLCMD) { 693 dev_dbg(ceudev->dev, 694 "Subdevice failed to start streaming: %d\n", ret); 695 goto error_return_bufs; 696 } 697 698 spin_lock_irqsave(&ceudev->lock, irqflags); 699 ceudev->sequence = 0; 700 701 /* Grab the first available buffer and trigger the first capture. */ 702 buf = list_first_entry(&ceudev->capture, struct ceu_buffer, 703 queue); 704 705 list_del(&buf->queue); 706 ceudev->active = &buf->vb; 707 708 /* Clean and program interrupts for first capture. */ 709 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask); 710 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK); 711 712 ceu_capture(ceudev); 713 714 spin_unlock_irqrestore(&ceudev->lock, irqflags); 715 716 return 0; 717 718 error_return_bufs: 719 spin_lock_irqsave(&ceudev->lock, irqflags); 720 list_for_each_entry(buf, &ceudev->capture, queue) 721 vb2_buffer_done(&ceudev->active->vb2_buf, 722 VB2_BUF_STATE_QUEUED); 723 ceudev->active = NULL; 724 spin_unlock_irqrestore(&ceudev->lock, irqflags); 725 726 return ret; 727 } 728 729 static void ceu_stop_streaming(struct vb2_queue *vq) 730 { 731 struct ceu_device *ceudev = vb2_get_drv_priv(vq); 732 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 733 struct ceu_buffer *buf; 734 unsigned long irqflags; 735 736 /* Clean and disable interrupt sources. */ 737 ceu_write(ceudev, CEU_CETCR, 738 ceu_read(ceudev, CEU_CETCR) & ceudev->irq_mask); 739 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK); 740 741 v4l2_subdev_call(v4l2_sd, video, s_stream, 0); 742 743 spin_lock_irqsave(&ceudev->lock, irqflags); 744 if (ceudev->active) { 745 vb2_buffer_done(&ceudev->active->vb2_buf, 746 VB2_BUF_STATE_ERROR); 747 ceudev->active = NULL; 748 } 749 750 /* Release all queued buffers. */ 751 list_for_each_entry(buf, &ceudev->capture, queue) 752 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 753 INIT_LIST_HEAD(&ceudev->capture); 754 755 spin_unlock_irqrestore(&ceudev->lock, irqflags); 756 757 ceu_soft_reset(ceudev); 758 } 759 760 static const struct vb2_ops ceu_vb2_ops = { 761 .queue_setup = ceu_vb2_setup, 762 .buf_queue = ceu_vb2_queue, 763 .buf_prepare = ceu_vb2_prepare, 764 .start_streaming = ceu_start_streaming, 765 .stop_streaming = ceu_stop_streaming, 766 }; 767 768 /* --- CEU image formats handling --- */ 769 770 /* 771 * __ceu_try_fmt() - test format on CEU and sensor 772 * @ceudev: The CEU device. 773 * @v4l2_fmt: format to test. 774 * @sd_mbus_code: the media bus code accepted by the subdevice; output param. 775 * 776 * Returns 0 for success, < 0 for errors. 777 */ 778 static int __ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt, 779 u32 *sd_mbus_code) 780 { 781 struct ceu_subdev *ceu_sd = ceudev->sd; 782 struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp; 783 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 784 struct v4l2_subdev_pad_config pad_cfg; 785 struct v4l2_subdev_state pad_state = { 786 .pads = &pad_cfg, 787 }; 788 const struct ceu_fmt *ceu_fmt; 789 u32 mbus_code_old; 790 u32 mbus_code; 791 int ret; 792 793 /* 794 * Set format on sensor sub device: bus format used to produce memory 795 * format is selected depending on YUV component ordering or 796 * at initialization time. 797 */ 798 struct v4l2_subdev_format sd_format = { 799 .which = V4L2_SUBDEV_FORMAT_TRY, 800 }; 801 802 mbus_code_old = ceu_sd->mbus_fmt.mbus_code; 803 804 switch (pix->pixelformat) { 805 case V4L2_PIX_FMT_YUYV: 806 mbus_code = MEDIA_BUS_FMT_YUYV8_2X8; 807 break; 808 case V4L2_PIX_FMT_UYVY: 809 mbus_code = MEDIA_BUS_FMT_UYVY8_2X8; 810 break; 811 case V4L2_PIX_FMT_YVYU: 812 mbus_code = MEDIA_BUS_FMT_YVYU8_2X8; 813 break; 814 case V4L2_PIX_FMT_VYUY: 815 mbus_code = MEDIA_BUS_FMT_VYUY8_2X8; 816 break; 817 case V4L2_PIX_FMT_NV16: 818 case V4L2_PIX_FMT_NV61: 819 case V4L2_PIX_FMT_NV12: 820 case V4L2_PIX_FMT_NV21: 821 mbus_code = ceu_sd->mbus_fmt.mbus_code; 822 break; 823 824 default: 825 pix->pixelformat = V4L2_PIX_FMT_NV16; 826 mbus_code = ceu_sd->mbus_fmt.mbus_code; 827 break; 828 } 829 830 ceu_fmt = get_ceu_fmt_from_fourcc(pix->pixelformat); 831 832 /* CFSZR requires height and width to be 4-pixel aligned. */ 833 v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4, 834 &pix->height, 4, CEU_MAX_HEIGHT, 4, 0); 835 836 v4l2_fill_mbus_format_mplane(&sd_format.format, pix); 837 838 /* 839 * Try with the mbus_code matching YUYV components ordering first, 840 * if that one fails, fallback to default selected at initialization 841 * time. 842 */ 843 sd_format.format.code = mbus_code; 844 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, &pad_state, 845 &sd_format); 846 if (ret) { 847 if (ret == -EINVAL) { 848 /* fallback */ 849 sd_format.format.code = mbus_code_old; 850 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, 851 &pad_state, &sd_format); 852 } 853 854 if (ret) 855 return ret; 856 } 857 858 /* Apply size returned by sensor as the CEU can't scale. */ 859 v4l2_fill_pix_format_mplane(pix, &sd_format.format); 860 861 /* Calculate per-plane sizes based on image format. */ 862 ceu_calc_plane_sizes(ceudev, ceu_fmt, pix); 863 864 /* Report to caller the configured mbus format. */ 865 *sd_mbus_code = sd_format.format.code; 866 867 return 0; 868 } 869 870 /* 871 * ceu_try_fmt() - Wrapper for __ceu_try_fmt; discard configured mbus_fmt 872 */ 873 static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt) 874 { 875 u32 mbus_code; 876 877 return __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code); 878 } 879 880 /* 881 * ceu_set_fmt() - Apply the supplied format to both sensor and CEU 882 */ 883 static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt) 884 { 885 struct ceu_subdev *ceu_sd = ceudev->sd; 886 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 887 u32 mbus_code; 888 int ret; 889 890 /* 891 * Set format on sensor sub device: bus format used to produce memory 892 * format is selected at initialization time. 893 */ 894 struct v4l2_subdev_format format = { 895 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 896 }; 897 898 ret = __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code); 899 if (ret) 900 return ret; 901 902 format.format.code = mbus_code; 903 v4l2_fill_mbus_format_mplane(&format.format, &v4l2_fmt->fmt.pix_mp); 904 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, NULL, &format); 905 if (ret) 906 return ret; 907 908 ceudev->v4l2_pix = v4l2_fmt->fmt.pix_mp; 909 ceudev->field = V4L2_FIELD_NONE; 910 911 return 0; 912 } 913 914 /* 915 * ceu_set_default_fmt() - Apply default NV16 memory output format with VGA 916 * sizes. 917 */ 918 static int ceu_set_default_fmt(struct ceu_device *ceudev) 919 { 920 int ret; 921 922 struct v4l2_format v4l2_fmt = { 923 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 924 .fmt.pix_mp = { 925 .width = VGA_WIDTH, 926 .height = VGA_HEIGHT, 927 .field = V4L2_FIELD_NONE, 928 .pixelformat = V4L2_PIX_FMT_NV16, 929 .num_planes = 2, 930 .plane_fmt = { 931 [0] = { 932 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2, 933 .bytesperline = VGA_WIDTH * 2, 934 }, 935 [1] = { 936 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2, 937 .bytesperline = VGA_WIDTH * 2, 938 }, 939 }, 940 }, 941 }; 942 943 ret = ceu_try_fmt(ceudev, &v4l2_fmt); 944 if (ret) 945 return ret; 946 947 ceudev->v4l2_pix = v4l2_fmt.fmt.pix_mp; 948 ceudev->field = V4L2_FIELD_NONE; 949 950 return 0; 951 } 952 953 /* 954 * ceu_init_mbus_fmt() - Query sensor for supported formats and initialize 955 * CEU media bus format used to produce memory formats. 956 * 957 * Find out if sensor can produce a permutation of 8-bits YUYV bus format. 958 * From a single 8-bits YUYV bus format the CEU can produce several memory 959 * output formats: 960 * - NV[12|21|16|61] through image fetch mode; 961 * - YUYV422 if sensor provides YUYV422 962 * 963 * TODO: Other YUYV422 permutations through data fetch sync mode and DTARY 964 * TODO: Binary data (eg. JPEG) and raw formats through data fetch sync mode 965 */ 966 static int ceu_init_mbus_fmt(struct ceu_device *ceudev) 967 { 968 struct ceu_subdev *ceu_sd = ceudev->sd; 969 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt; 970 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 971 bool yuyv_bus_fmt = false; 972 973 struct v4l2_subdev_mbus_code_enum sd_mbus_fmt = { 974 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 975 .index = 0, 976 }; 977 978 /* Find out if sensor can produce any permutation of 8-bits YUYV422. */ 979 while (!yuyv_bus_fmt && 980 !v4l2_subdev_call(v4l2_sd, pad, enum_mbus_code, 981 NULL, &sd_mbus_fmt)) { 982 switch (sd_mbus_fmt.code) { 983 case MEDIA_BUS_FMT_YUYV8_2X8: 984 case MEDIA_BUS_FMT_YVYU8_2X8: 985 case MEDIA_BUS_FMT_UYVY8_2X8: 986 case MEDIA_BUS_FMT_VYUY8_2X8: 987 yuyv_bus_fmt = true; 988 break; 989 default: 990 /* 991 * Only support 8-bits YUYV bus formats at the moment; 992 * 993 * TODO: add support for binary formats (data sync 994 * fetch mode). 995 */ 996 break; 997 } 998 999 sd_mbus_fmt.index++; 1000 } 1001 1002 if (!yuyv_bus_fmt) 1003 return -ENXIO; 1004 1005 /* 1006 * Save the first encountered YUYV format as "mbus_fmt" and use it 1007 * to output all planar YUV422 and YUV420 (NV*) formats to memory as 1008 * well as for data synch fetch mode (YUYV - YVYU etc. ). 1009 */ 1010 mbus_fmt->mbus_code = sd_mbus_fmt.code; 1011 mbus_fmt->bps = 8; 1012 1013 /* Annotate the selected bus format components ordering. */ 1014 switch (sd_mbus_fmt.code) { 1015 case MEDIA_BUS_FMT_YUYV8_2X8: 1016 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YUYV; 1017 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YVYU; 1018 mbus_fmt->swapped = false; 1019 mbus_fmt->bpp = 16; 1020 break; 1021 1022 case MEDIA_BUS_FMT_YVYU8_2X8: 1023 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YVYU; 1024 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YUYV; 1025 mbus_fmt->swapped = true; 1026 mbus_fmt->bpp = 16; 1027 break; 1028 1029 case MEDIA_BUS_FMT_UYVY8_2X8: 1030 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_UYVY; 1031 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_VYUY; 1032 mbus_fmt->swapped = false; 1033 mbus_fmt->bpp = 16; 1034 break; 1035 1036 case MEDIA_BUS_FMT_VYUY8_2X8: 1037 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_VYUY; 1038 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_UYVY; 1039 mbus_fmt->swapped = true; 1040 mbus_fmt->bpp = 16; 1041 break; 1042 } 1043 1044 return 0; 1045 } 1046 1047 /* --- Runtime PM Handlers --- */ 1048 1049 /* 1050 * ceu_runtime_resume() - soft-reset the interface and turn sensor power on. 1051 */ 1052 static int ceu_runtime_resume(struct device *dev) 1053 { 1054 struct ceu_device *ceudev = dev_get_drvdata(dev); 1055 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 1056 1057 v4l2_subdev_call(v4l2_sd, core, s_power, 1); 1058 1059 ceu_soft_reset(ceudev); 1060 1061 return 0; 1062 } 1063 1064 /* 1065 * ceu_runtime_suspend() - disable capture and interrupts and soft-reset. 1066 * Turn sensor power off. 1067 */ 1068 static int ceu_runtime_suspend(struct device *dev) 1069 { 1070 struct ceu_device *ceudev = dev_get_drvdata(dev); 1071 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 1072 1073 v4l2_subdev_call(v4l2_sd, core, s_power, 0); 1074 1075 ceu_write(ceudev, CEU_CEIER, 0); 1076 ceu_soft_reset(ceudev); 1077 1078 return 0; 1079 } 1080 1081 /* --- File Operations --- */ 1082 1083 static int ceu_open(struct file *file) 1084 { 1085 struct ceu_device *ceudev = video_drvdata(file); 1086 int ret; 1087 1088 ret = v4l2_fh_open(file); 1089 if (ret) 1090 return ret; 1091 1092 mutex_lock(&ceudev->mlock); 1093 /* Causes soft-reset and sensor power on on first open */ 1094 ret = pm_runtime_resume_and_get(ceudev->dev); 1095 mutex_unlock(&ceudev->mlock); 1096 1097 return ret; 1098 } 1099 1100 static int ceu_release(struct file *file) 1101 { 1102 struct ceu_device *ceudev = video_drvdata(file); 1103 1104 vb2_fop_release(file); 1105 1106 mutex_lock(&ceudev->mlock); 1107 /* Causes soft-reset and sensor power down on last close */ 1108 pm_runtime_put(ceudev->dev); 1109 mutex_unlock(&ceudev->mlock); 1110 1111 return 0; 1112 } 1113 1114 static const struct v4l2_file_operations ceu_fops = { 1115 .owner = THIS_MODULE, 1116 .open = ceu_open, 1117 .release = ceu_release, 1118 .unlocked_ioctl = video_ioctl2, 1119 .mmap = vb2_fop_mmap, 1120 .poll = vb2_fop_poll, 1121 }; 1122 1123 /* --- Video Device IOCTLs --- */ 1124 1125 static int ceu_querycap(struct file *file, void *priv, 1126 struct v4l2_capability *cap) 1127 { 1128 struct ceu_device *ceudev = video_drvdata(file); 1129 1130 strscpy(cap->card, "Renesas CEU", sizeof(cap->card)); 1131 strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver)); 1132 snprintf(cap->bus_info, sizeof(cap->bus_info), 1133 "platform:renesas-ceu-%s", dev_name(ceudev->dev)); 1134 1135 return 0; 1136 } 1137 1138 static int ceu_enum_fmt_vid_cap(struct file *file, void *priv, 1139 struct v4l2_fmtdesc *f) 1140 { 1141 const struct ceu_fmt *fmt; 1142 1143 if (f->index >= ARRAY_SIZE(ceu_fmt_list)) 1144 return -EINVAL; 1145 1146 fmt = &ceu_fmt_list[f->index]; 1147 f->pixelformat = fmt->fourcc; 1148 1149 return 0; 1150 } 1151 1152 static int ceu_try_fmt_vid_cap(struct file *file, void *priv, 1153 struct v4l2_format *f) 1154 { 1155 struct ceu_device *ceudev = video_drvdata(file); 1156 1157 return ceu_try_fmt(ceudev, f); 1158 } 1159 1160 static int ceu_s_fmt_vid_cap(struct file *file, void *priv, 1161 struct v4l2_format *f) 1162 { 1163 struct ceu_device *ceudev = video_drvdata(file); 1164 1165 if (vb2_is_streaming(&ceudev->vb2_vq)) 1166 return -EBUSY; 1167 1168 return ceu_set_fmt(ceudev, f); 1169 } 1170 1171 static int ceu_g_fmt_vid_cap(struct file *file, void *priv, 1172 struct v4l2_format *f) 1173 { 1174 struct ceu_device *ceudev = video_drvdata(file); 1175 1176 f->fmt.pix_mp = ceudev->v4l2_pix; 1177 1178 return 0; 1179 } 1180 1181 static int ceu_enum_input(struct file *file, void *priv, 1182 struct v4l2_input *inp) 1183 { 1184 struct ceu_device *ceudev = video_drvdata(file); 1185 1186 if (inp->index >= ceudev->num_sd) 1187 return -EINVAL; 1188 1189 inp->type = V4L2_INPUT_TYPE_CAMERA; 1190 inp->std = 0; 1191 snprintf(inp->name, sizeof(inp->name), "Camera %u", inp->index); 1192 1193 return 0; 1194 } 1195 1196 static int ceu_g_input(struct file *file, void *priv, unsigned int *i) 1197 { 1198 struct ceu_device *ceudev = video_drvdata(file); 1199 1200 *i = ceudev->sd_index; 1201 1202 return 0; 1203 } 1204 1205 static int ceu_s_input(struct file *file, void *priv, unsigned int i) 1206 { 1207 struct ceu_device *ceudev = video_drvdata(file); 1208 struct ceu_subdev *ceu_sd_old; 1209 int ret; 1210 1211 if (i >= ceudev->num_sd) 1212 return -EINVAL; 1213 1214 if (vb2_is_streaming(&ceudev->vb2_vq)) 1215 return -EBUSY; 1216 1217 if (i == ceudev->sd_index) 1218 return 0; 1219 1220 ceu_sd_old = ceudev->sd; 1221 ceudev->sd = ceudev->subdevs[i]; 1222 1223 /* 1224 * Make sure we can generate output image formats and apply 1225 * default one. 1226 */ 1227 ret = ceu_init_mbus_fmt(ceudev); 1228 if (ret) { 1229 ceudev->sd = ceu_sd_old; 1230 return -EINVAL; 1231 } 1232 1233 ret = ceu_set_default_fmt(ceudev); 1234 if (ret) { 1235 ceudev->sd = ceu_sd_old; 1236 return -EINVAL; 1237 } 1238 1239 /* Now that we're sure we can use the sensor, power off the old one. */ 1240 v4l2_subdev_call(ceu_sd_old->v4l2_sd, core, s_power, 0); 1241 v4l2_subdev_call(ceudev->sd->v4l2_sd, core, s_power, 1); 1242 1243 ceudev->sd_index = i; 1244 1245 return 0; 1246 } 1247 1248 static int ceu_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1249 { 1250 struct ceu_device *ceudev = video_drvdata(file); 1251 1252 return v4l2_g_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a); 1253 } 1254 1255 static int ceu_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1256 { 1257 struct ceu_device *ceudev = video_drvdata(file); 1258 1259 return v4l2_s_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a); 1260 } 1261 1262 static int ceu_enum_framesizes(struct file *file, void *fh, 1263 struct v4l2_frmsizeenum *fsize) 1264 { 1265 struct ceu_device *ceudev = video_drvdata(file); 1266 struct ceu_subdev *ceu_sd = ceudev->sd; 1267 const struct ceu_fmt *ceu_fmt; 1268 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 1269 int ret; 1270 1271 struct v4l2_subdev_frame_size_enum fse = { 1272 .code = ceu_sd->mbus_fmt.mbus_code, 1273 .index = fsize->index, 1274 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1275 }; 1276 1277 /* Just check if user supplied pixel format is supported. */ 1278 ceu_fmt = get_ceu_fmt_from_fourcc(fsize->pixel_format); 1279 if (!ceu_fmt) 1280 return -EINVAL; 1281 1282 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size, 1283 NULL, &fse); 1284 if (ret) 1285 return ret; 1286 1287 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 1288 fsize->discrete.width = CEU_W_MAX(fse.max_width); 1289 fsize->discrete.height = CEU_H_MAX(fse.max_height); 1290 1291 return 0; 1292 } 1293 1294 static int ceu_enum_frameintervals(struct file *file, void *fh, 1295 struct v4l2_frmivalenum *fival) 1296 { 1297 struct ceu_device *ceudev = video_drvdata(file); 1298 struct ceu_subdev *ceu_sd = ceudev->sd; 1299 const struct ceu_fmt *ceu_fmt; 1300 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 1301 int ret; 1302 1303 struct v4l2_subdev_frame_interval_enum fie = { 1304 .code = ceu_sd->mbus_fmt.mbus_code, 1305 .index = fival->index, 1306 .width = fival->width, 1307 .height = fival->height, 1308 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1309 }; 1310 1311 /* Just check if user supplied pixel format is supported. */ 1312 ceu_fmt = get_ceu_fmt_from_fourcc(fival->pixel_format); 1313 if (!ceu_fmt) 1314 return -EINVAL; 1315 1316 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL, 1317 &fie); 1318 if (ret) 1319 return ret; 1320 1321 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; 1322 fival->discrete = fie.interval; 1323 1324 return 0; 1325 } 1326 1327 static const struct v4l2_ioctl_ops ceu_ioctl_ops = { 1328 .vidioc_querycap = ceu_querycap, 1329 1330 .vidioc_enum_fmt_vid_cap = ceu_enum_fmt_vid_cap, 1331 .vidioc_try_fmt_vid_cap_mplane = ceu_try_fmt_vid_cap, 1332 .vidioc_s_fmt_vid_cap_mplane = ceu_s_fmt_vid_cap, 1333 .vidioc_g_fmt_vid_cap_mplane = ceu_g_fmt_vid_cap, 1334 1335 .vidioc_enum_input = ceu_enum_input, 1336 .vidioc_g_input = ceu_g_input, 1337 .vidioc_s_input = ceu_s_input, 1338 1339 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1340 .vidioc_querybuf = vb2_ioctl_querybuf, 1341 .vidioc_qbuf = vb2_ioctl_qbuf, 1342 .vidioc_expbuf = vb2_ioctl_expbuf, 1343 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1344 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1345 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1346 .vidioc_streamon = vb2_ioctl_streamon, 1347 .vidioc_streamoff = vb2_ioctl_streamoff, 1348 1349 .vidioc_g_parm = ceu_g_parm, 1350 .vidioc_s_parm = ceu_s_parm, 1351 .vidioc_enum_framesizes = ceu_enum_framesizes, 1352 .vidioc_enum_frameintervals = ceu_enum_frameintervals, 1353 1354 .vidioc_log_status = v4l2_ctrl_log_status, 1355 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1356 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1357 }; 1358 1359 /* 1360 * ceu_vdev_release() - release CEU video device memory when last reference 1361 * to this driver is closed 1362 */ 1363 static void ceu_vdev_release(struct video_device *vdev) 1364 { 1365 struct ceu_device *ceudev = video_get_drvdata(vdev); 1366 1367 kfree(ceudev); 1368 } 1369 1370 static int ceu_notify_bound(struct v4l2_async_notifier *notifier, 1371 struct v4l2_subdev *v4l2_sd, 1372 struct v4l2_async_connection *asd) 1373 { 1374 struct v4l2_device *v4l2_dev = notifier->v4l2_dev; 1375 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev); 1376 struct ceu_subdev *ceu_sd = to_ceu_subdev(asd); 1377 1378 ceu_sd->v4l2_sd = v4l2_sd; 1379 ceudev->num_sd++; 1380 1381 return 0; 1382 } 1383 1384 static int ceu_notify_complete(struct v4l2_async_notifier *notifier) 1385 { 1386 struct v4l2_device *v4l2_dev = notifier->v4l2_dev; 1387 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev); 1388 struct video_device *vdev = &ceudev->vdev; 1389 struct vb2_queue *q = &ceudev->vb2_vq; 1390 struct v4l2_subdev *v4l2_sd; 1391 int ret; 1392 1393 /* Initialize vb2 queue. */ 1394 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1395 q->io_modes = VB2_MMAP | VB2_DMABUF; 1396 q->drv_priv = ceudev; 1397 q->ops = &ceu_vb2_ops; 1398 q->mem_ops = &vb2_dma_contig_memops; 1399 q->buf_struct_size = sizeof(struct ceu_buffer); 1400 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1401 q->min_queued_buffers = 2; 1402 q->lock = &ceudev->mlock; 1403 q->dev = ceudev->v4l2_dev.dev; 1404 1405 ret = vb2_queue_init(q); 1406 if (ret) 1407 return ret; 1408 1409 /* 1410 * Make sure at least one sensor is primary and use it to initialize 1411 * ceu formats. 1412 */ 1413 if (!ceudev->sd) { 1414 ceudev->sd = ceudev->subdevs[0]; 1415 ceudev->sd_index = 0; 1416 } 1417 1418 v4l2_sd = ceudev->sd->v4l2_sd; 1419 1420 ret = ceu_init_mbus_fmt(ceudev); 1421 if (ret) 1422 return ret; 1423 1424 ret = ceu_set_default_fmt(ceudev); 1425 if (ret) 1426 return ret; 1427 1428 /* Register the video device. */ 1429 strscpy(vdev->name, DRIVER_NAME, sizeof(vdev->name)); 1430 vdev->v4l2_dev = v4l2_dev; 1431 vdev->lock = &ceudev->mlock; 1432 vdev->queue = &ceudev->vb2_vq; 1433 vdev->ctrl_handler = v4l2_sd->ctrl_handler; 1434 vdev->fops = &ceu_fops; 1435 vdev->ioctl_ops = &ceu_ioctl_ops; 1436 vdev->release = ceu_vdev_release; 1437 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | 1438 V4L2_CAP_STREAMING; 1439 video_set_drvdata(vdev, ceudev); 1440 1441 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1442 if (ret < 0) { 1443 v4l2_err(vdev->v4l2_dev, 1444 "video_register_device failed: %d\n", ret); 1445 return ret; 1446 } 1447 1448 return 0; 1449 } 1450 1451 static const struct v4l2_async_notifier_operations ceu_notify_ops = { 1452 .bound = ceu_notify_bound, 1453 .complete = ceu_notify_complete, 1454 }; 1455 1456 /* 1457 * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in 1458 * ceu device. Both DT and platform data parsing use 1459 * this routine. 1460 * 1461 * Returns 0 for success, -ENOMEM for failure. 1462 */ 1463 static int ceu_init_async_subdevs(struct ceu_device *ceudev, unsigned int n_sd) 1464 { 1465 /* Reserve memory for 'n_sd' ceu_subdev descriptors. */ 1466 ceudev->subdevs = devm_kcalloc(ceudev->dev, n_sd, 1467 sizeof(*ceudev->subdevs), GFP_KERNEL); 1468 if (!ceudev->subdevs) 1469 return -ENOMEM; 1470 1471 ceudev->sd = NULL; 1472 ceudev->sd_index = 0; 1473 ceudev->num_sd = 0; 1474 1475 return 0; 1476 } 1477 1478 /* 1479 * ceu_parse_platform_data() - Initialize async_subdevices using platform 1480 * device provided data. 1481 */ 1482 static int ceu_parse_platform_data(struct ceu_device *ceudev, 1483 const struct ceu_platform_data *pdata) 1484 { 1485 const struct ceu_async_subdev *async_sd; 1486 struct ceu_subdev *ceu_sd; 1487 unsigned int i; 1488 int ret; 1489 1490 if (pdata->num_subdevs == 0) 1491 return -ENODEV; 1492 1493 ret = ceu_init_async_subdevs(ceudev, pdata->num_subdevs); 1494 if (ret) 1495 return ret; 1496 1497 for (i = 0; i < pdata->num_subdevs; i++) { 1498 1499 /* Setup the ceu subdevice and the async subdevice. */ 1500 async_sd = &pdata->subdevs[i]; 1501 ceu_sd = v4l2_async_nf_add_i2c(&ceudev->notifier, 1502 async_sd->i2c_adapter_id, 1503 async_sd->i2c_address, 1504 struct ceu_subdev); 1505 if (IS_ERR(ceu_sd)) { 1506 v4l2_async_nf_cleanup(&ceudev->notifier); 1507 return PTR_ERR(ceu_sd); 1508 } 1509 ceu_sd->mbus_flags = async_sd->flags; 1510 ceudev->subdevs[i] = ceu_sd; 1511 } 1512 1513 return pdata->num_subdevs; 1514 } 1515 1516 /* 1517 * ceu_parse_dt() - Initialize async_subdevs parsing device tree graph. 1518 */ 1519 static int ceu_parse_dt(struct ceu_device *ceudev) 1520 { 1521 struct device_node *of = ceudev->dev->of_node; 1522 struct device_node *ep; 1523 struct ceu_subdev *ceu_sd; 1524 unsigned int i; 1525 int num_ep; 1526 int ret; 1527 1528 num_ep = of_graph_get_endpoint_count(of); 1529 if (!num_ep) 1530 return -ENODEV; 1531 1532 ret = ceu_init_async_subdevs(ceudev, num_ep); 1533 if (ret) 1534 return ret; 1535 1536 for (i = 0; i < num_ep; i++) { 1537 struct v4l2_fwnode_endpoint fw_ep = { 1538 .bus_type = V4L2_MBUS_PARALLEL, 1539 .bus = { 1540 .parallel = { 1541 .flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH | 1542 V4L2_MBUS_VSYNC_ACTIVE_HIGH, 1543 .bus_width = 8, 1544 }, 1545 }, 1546 }; 1547 1548 ep = of_graph_get_endpoint_by_regs(of, 0, i); 1549 if (!ep) { 1550 dev_err(ceudev->dev, 1551 "No subdevice connected on endpoint %u.\n", i); 1552 ret = -ENODEV; 1553 goto error_cleanup; 1554 } 1555 1556 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep); 1557 if (ret) { 1558 dev_err(ceudev->dev, 1559 "Unable to parse endpoint #%u: %d.\n", i, ret); 1560 goto error_cleanup; 1561 } 1562 1563 /* Setup the ceu subdevice and the async subdevice. */ 1564 ceu_sd = v4l2_async_nf_add_fwnode_remote(&ceudev->notifier, 1565 of_fwnode_handle(ep), 1566 struct ceu_subdev); 1567 if (IS_ERR(ceu_sd)) { 1568 ret = PTR_ERR(ceu_sd); 1569 goto error_cleanup; 1570 } 1571 ceu_sd->mbus_flags = fw_ep.bus.parallel.flags; 1572 ceudev->subdevs[i] = ceu_sd; 1573 1574 of_node_put(ep); 1575 } 1576 1577 return num_ep; 1578 1579 error_cleanup: 1580 v4l2_async_nf_cleanup(&ceudev->notifier); 1581 of_node_put(ep); 1582 return ret; 1583 } 1584 1585 /* 1586 * struct ceu_data - Platform specific CEU data 1587 * @irq_mask: CETCR mask with all interrupt sources enabled. The mask differs 1588 * between SH4 and RZ platforms. 1589 */ 1590 struct ceu_data { 1591 u32 irq_mask; 1592 }; 1593 1594 static const struct ceu_data ceu_data_sh4 = { 1595 .irq_mask = CEU_CETCR_ALL_IRQS_SH4, 1596 }; 1597 1598 #if IS_ENABLED(CONFIG_OF) 1599 static const struct ceu_data ceu_data_rz = { 1600 .irq_mask = CEU_CETCR_ALL_IRQS_RZ, 1601 }; 1602 1603 static const struct of_device_id ceu_of_match[] = { 1604 { .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz }, 1605 { .compatible = "renesas,r8a7740-ceu", .data = &ceu_data_rz }, 1606 { } 1607 }; 1608 MODULE_DEVICE_TABLE(of, ceu_of_match); 1609 #endif 1610 1611 static int ceu_probe(struct platform_device *pdev) 1612 { 1613 struct device *dev = &pdev->dev; 1614 const struct ceu_data *ceu_data; 1615 struct ceu_device *ceudev; 1616 unsigned int irq; 1617 int num_subdevs; 1618 int ret; 1619 1620 ceudev = kzalloc_obj(*ceudev); 1621 if (!ceudev) 1622 return -ENOMEM; 1623 1624 platform_set_drvdata(pdev, ceudev); 1625 ceudev->dev = dev; 1626 1627 INIT_LIST_HEAD(&ceudev->capture); 1628 spin_lock_init(&ceudev->lock); 1629 mutex_init(&ceudev->mlock); 1630 1631 ceudev->base = devm_platform_ioremap_resource(pdev, 0); 1632 if (IS_ERR(ceudev->base)) { 1633 ret = PTR_ERR(ceudev->base); 1634 goto error_free_ceudev; 1635 } 1636 1637 ret = platform_get_irq(pdev, 0); 1638 if (ret < 0) 1639 goto error_free_ceudev; 1640 irq = ret; 1641 1642 ret = devm_request_irq(dev, irq, ceu_irq, 1643 0, dev_name(dev), ceudev); 1644 if (ret) { 1645 dev_err(&pdev->dev, "Unable to request CEU interrupt.\n"); 1646 goto error_free_ceudev; 1647 } 1648 1649 pm_runtime_enable(dev); 1650 1651 ret = v4l2_device_register(dev, &ceudev->v4l2_dev); 1652 if (ret) 1653 goto error_pm_disable; 1654 1655 v4l2_async_nf_init(&ceudev->notifier, &ceudev->v4l2_dev); 1656 1657 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 1658 ceu_data = of_device_get_match_data(dev); 1659 num_subdevs = ceu_parse_dt(ceudev); 1660 } else if (dev->platform_data) { 1661 /* Assume SH4 if booting with platform data. */ 1662 ceu_data = &ceu_data_sh4; 1663 num_subdevs = ceu_parse_platform_data(ceudev, 1664 dev->platform_data); 1665 } else { 1666 num_subdevs = -EINVAL; 1667 } 1668 1669 if (num_subdevs < 0) { 1670 ret = num_subdevs; 1671 goto error_v4l2_unregister; 1672 } 1673 ceudev->irq_mask = ceu_data->irq_mask; 1674 1675 ceudev->notifier.v4l2_dev = &ceudev->v4l2_dev; 1676 ceudev->notifier.ops = &ceu_notify_ops; 1677 ret = v4l2_async_nf_register(&ceudev->notifier); 1678 if (ret) 1679 goto error_cleanup; 1680 1681 dev_info(dev, "Renesas Capture Engine Unit %s\n", dev_name(dev)); 1682 1683 return 0; 1684 1685 error_cleanup: 1686 v4l2_async_nf_cleanup(&ceudev->notifier); 1687 error_v4l2_unregister: 1688 v4l2_device_unregister(&ceudev->v4l2_dev); 1689 error_pm_disable: 1690 pm_runtime_disable(dev); 1691 error_free_ceudev: 1692 kfree(ceudev); 1693 1694 return ret; 1695 } 1696 1697 static void ceu_remove(struct platform_device *pdev) 1698 { 1699 struct ceu_device *ceudev = platform_get_drvdata(pdev); 1700 1701 pm_runtime_disable(ceudev->dev); 1702 1703 v4l2_async_nf_unregister(&ceudev->notifier); 1704 1705 v4l2_async_nf_cleanup(&ceudev->notifier); 1706 1707 v4l2_device_unregister(&ceudev->v4l2_dev); 1708 1709 video_unregister_device(&ceudev->vdev); 1710 } 1711 1712 static const struct dev_pm_ops ceu_pm_ops = { 1713 RUNTIME_PM_OPS(ceu_runtime_suspend, ceu_runtime_resume, NULL) 1714 }; 1715 1716 static struct platform_driver ceu_driver = { 1717 .driver = { 1718 .name = DRIVER_NAME, 1719 .pm = pm_ptr(&ceu_pm_ops), 1720 .of_match_table = of_match_ptr(ceu_of_match), 1721 }, 1722 .probe = ceu_probe, 1723 .remove = ceu_remove, 1724 }; 1725 1726 module_platform_driver(ceu_driver); 1727 1728 MODULE_DESCRIPTION("Renesas CEU camera driver"); 1729 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org>"); 1730 MODULE_LICENSE("GPL v2"); 1731