1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved. 4 */ 5 6 #define pr_fmt(fmt) "GICv5: " fmt 7 8 #include <linux/acpi_iort.h> 9 #include <linux/cpuhotplug.h> 10 #include <linux/idr.h> 11 #include <linux/irqdomain.h> 12 #include <linux/slab.h> 13 #include <linux/wordpart.h> 14 15 #include <linux/irqchip.h> 16 #include <linux/irqchip/arm-gic-v5.h> 17 #include <linux/irqchip/arm-vgic-info.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/exception.h> 21 22 static u8 pri_bits __ro_after_init = 5; 23 24 #define GICV5_IRQ_PRI_MASK 0x1f 25 #define GICV5_IRQ_PRI_MI (GICV5_IRQ_PRI_MASK & GENMASK(4, 5 - pri_bits)) 26 27 #define PPI_NR 128 28 29 static bool gicv5_cpuif_has_gcie(void) 30 { 31 return this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF); 32 } 33 34 struct gicv5_chip_data gicv5_global_data __read_mostly; 35 36 static DEFINE_IDA(lpi_ida); 37 static u32 num_lpis __ro_after_init; 38 39 void __init gicv5_init_lpis(u32 lpis) 40 { 41 num_lpis = lpis; 42 } 43 44 void __init gicv5_deinit_lpis(void) 45 { 46 num_lpis = 0; 47 } 48 49 static int alloc_lpi(void) 50 { 51 if (!num_lpis) 52 return -ENOSPC; 53 54 return ida_alloc_max(&lpi_ida, num_lpis - 1, GFP_KERNEL); 55 } 56 57 static void release_lpi(u32 lpi) 58 { 59 ida_free(&lpi_ida, lpi); 60 } 61 62 static void gicv5_ppi_priority_init(void) 63 { 64 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR0_EL1); 65 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR1_EL1); 66 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR2_EL1); 67 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR3_EL1); 68 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR4_EL1); 69 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR5_EL1); 70 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR6_EL1); 71 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR7_EL1); 72 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR8_EL1); 73 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR9_EL1); 74 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR10_EL1); 75 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR11_EL1); 76 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR12_EL1); 77 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR13_EL1); 78 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR14_EL1); 79 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR15_EL1); 80 81 /* 82 * Context syncronization required to make sure system register writes 83 * effects are synchronised. 84 */ 85 isb(); 86 } 87 88 static void gicv5_hwirq_init(irq_hw_number_t hwirq, u8 priority, u8 hwirq_type) 89 { 90 u64 cdpri, cdaff; 91 u16 iaffid; 92 int ret; 93 94 if (hwirq_type == GICV5_HWIRQ_TYPE_LPI || hwirq_type == GICV5_HWIRQ_TYPE_SPI) { 95 cdpri = FIELD_PREP(GICV5_GIC_CDPRI_PRIORITY_MASK, priority) | 96 FIELD_PREP(GICV5_GIC_CDPRI_TYPE_MASK, hwirq_type) | 97 FIELD_PREP(GICV5_GIC_CDPRI_ID_MASK, hwirq); 98 gic_insn(cdpri, CDPRI); 99 100 ret = gicv5_irs_cpu_to_iaffid(smp_processor_id(), &iaffid); 101 102 if (WARN_ON_ONCE(ret)) 103 return; 104 105 cdaff = FIELD_PREP(GICV5_GIC_CDAFF_IAFFID_MASK, iaffid) | 106 FIELD_PREP(GICV5_GIC_CDAFF_TYPE_MASK, hwirq_type) | 107 FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, hwirq); 108 gic_insn(cdaff, CDAFF); 109 } 110 } 111 112 static void gicv5_ppi_irq_mask(struct irq_data *d) 113 { 114 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64); 115 116 if (d->hwirq < 64) 117 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER0_EL1, hwirq_id_bit, 0); 118 else 119 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER1_EL1, hwirq_id_bit, 0); 120 121 /* 122 * We must ensure that the disable takes effect immediately to 123 * guarantee that the lazy-disabled IRQ mechanism works. 124 * A context synchronization event is required to guarantee it. 125 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. 126 */ 127 isb(); 128 } 129 130 static void gicv5_iri_irq_mask(struct irq_data *d, u8 hwirq_type) 131 { 132 u64 cddis; 133 134 cddis = FIELD_PREP(GICV5_GIC_CDDIS_ID_MASK, d->hwirq) | 135 FIELD_PREP(GICV5_GIC_CDDIS_TYPE_MASK, hwirq_type); 136 137 gic_insn(cddis, CDDIS); 138 /* 139 * We must make sure that GIC CDDIS write effects are propagated 140 * immediately to make sure the disable takes effect to guarantee 141 * that the lazy-disabled IRQ mechanism works. 142 * Rule R_XCLJC states that the effects of a GIC system instruction 143 * complete in finite time. 144 * The GSB ensures completion of the GIC instruction and prevents 145 * loads, stores and GIC instructions from executing part of their 146 * functionality before the GSB SYS. 147 */ 148 gsb_sys(); 149 } 150 151 static void gicv5_spi_irq_mask(struct irq_data *d) 152 { 153 gicv5_iri_irq_mask(d, GICV5_HWIRQ_TYPE_SPI); 154 } 155 156 static void gicv5_lpi_irq_mask(struct irq_data *d) 157 { 158 gicv5_iri_irq_mask(d, GICV5_HWIRQ_TYPE_LPI); 159 } 160 161 static void gicv5_ppi_irq_unmask(struct irq_data *d) 162 { 163 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64); 164 165 if (d->hwirq < 64) 166 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER0_EL1, 0, hwirq_id_bit); 167 else 168 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER1_EL1, 0, hwirq_id_bit); 169 /* 170 * We must ensure that the enable takes effect in finite time - a 171 * context synchronization event is required to guarantee it, we 172 * can not take for granted that would happen (eg a core going straight 173 * into idle after enabling a PPI). 174 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. 175 */ 176 isb(); 177 } 178 179 static void gicv5_iri_irq_unmask(struct irq_data *d, u8 hwirq_type) 180 { 181 u64 cden; 182 183 cden = FIELD_PREP(GICV5_GIC_CDEN_ID_MASK, d->hwirq) | 184 FIELD_PREP(GICV5_GIC_CDEN_TYPE_MASK, hwirq_type); 185 /* 186 * Rule R_XCLJC states that the effects of a GIC system instruction 187 * complete in finite time and that's the only requirement when 188 * unmasking an SPI/LPI IRQ. 189 */ 190 gic_insn(cden, CDEN); 191 } 192 193 static void gicv5_spi_irq_unmask(struct irq_data *d) 194 { 195 gicv5_iri_irq_unmask(d, GICV5_HWIRQ_TYPE_SPI); 196 } 197 198 static void gicv5_lpi_irq_unmask(struct irq_data *d) 199 { 200 gicv5_iri_irq_unmask(d, GICV5_HWIRQ_TYPE_LPI); 201 } 202 203 static void gicv5_hwirq_eoi(u32 hwirq_id, u8 hwirq_type) 204 { 205 u64 cddi; 206 207 cddi = FIELD_PREP(GICV5_GIC_CDDI_ID_MASK, hwirq_id) | 208 FIELD_PREP(GICV5_GIC_CDDI_TYPE_MASK, hwirq_type); 209 210 gic_insn(cddi, CDDI); 211 } 212 213 static void gicv5_ppi_irq_eoi(struct irq_data *d) 214 { 215 /* Skip deactivate for forwarded PPI interrupts */ 216 if (irqd_is_forwarded_to_vcpu(d)) 217 return; 218 219 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_PPI); 220 } 221 222 static void gicv5_spi_irq_eoi(struct irq_data *d) 223 { 224 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_SPI); 225 } 226 227 static void gicv5_lpi_irq_eoi(struct irq_data *d) 228 { 229 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_LPI); 230 } 231 232 static int gicv5_iri_irq_set_affinity(struct irq_data *d, 233 const struct cpumask *mask_val, 234 bool force, u8 hwirq_type) 235 { 236 int ret, cpuid; 237 u16 iaffid; 238 u64 cdaff; 239 240 if (force) 241 cpuid = cpumask_first(mask_val); 242 else 243 cpuid = cpumask_any_and(mask_val, cpu_online_mask); 244 245 ret = gicv5_irs_cpu_to_iaffid(cpuid, &iaffid); 246 if (ret) 247 return ret; 248 249 cdaff = FIELD_PREP(GICV5_GIC_CDAFF_IAFFID_MASK, iaffid) | 250 FIELD_PREP(GICV5_GIC_CDAFF_TYPE_MASK, hwirq_type) | 251 FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, d->hwirq); 252 gic_insn(cdaff, CDAFF); 253 254 irq_data_update_effective_affinity(d, cpumask_of(cpuid)); 255 256 return IRQ_SET_MASK_OK_DONE; 257 } 258 259 static int gicv5_spi_irq_set_affinity(struct irq_data *d, 260 const struct cpumask *mask_val, 261 bool force) 262 { 263 return gicv5_iri_irq_set_affinity(d, mask_val, force, 264 GICV5_HWIRQ_TYPE_SPI); 265 } 266 267 static int gicv5_lpi_irq_set_affinity(struct irq_data *d, 268 const struct cpumask *mask_val, 269 bool force) 270 { 271 return gicv5_iri_irq_set_affinity(d, mask_val, force, 272 GICV5_HWIRQ_TYPE_LPI); 273 } 274 275 enum ppi_reg { 276 PPI_PENDING, 277 PPI_ACTIVE, 278 PPI_HM 279 }; 280 281 static __always_inline u64 read_ppi_sysreg_s(unsigned int irq, 282 const enum ppi_reg which) 283 { 284 switch (which) { 285 case PPI_PENDING: 286 return irq < 64 ? read_sysreg_s(SYS_ICC_PPI_SPENDR0_EL1) : 287 read_sysreg_s(SYS_ICC_PPI_SPENDR1_EL1); 288 case PPI_ACTIVE: 289 return irq < 64 ? read_sysreg_s(SYS_ICC_PPI_SACTIVER0_EL1) : 290 read_sysreg_s(SYS_ICC_PPI_SACTIVER1_EL1); 291 case PPI_HM: 292 return irq < 64 ? read_sysreg_s(SYS_ICC_PPI_HMR0_EL1) : 293 read_sysreg_s(SYS_ICC_PPI_HMR1_EL1); 294 default: 295 BUILD_BUG_ON(1); 296 } 297 } 298 299 static __always_inline void write_ppi_sysreg_s(unsigned int irq, bool set, 300 const enum ppi_reg which) 301 { 302 u64 bit = BIT_ULL(irq % 64); 303 304 switch (which) { 305 case PPI_PENDING: 306 if (set) { 307 if (irq < 64) 308 write_sysreg_s(bit, SYS_ICC_PPI_SPENDR0_EL1); 309 else 310 write_sysreg_s(bit, SYS_ICC_PPI_SPENDR1_EL1); 311 } else { 312 if (irq < 64) 313 write_sysreg_s(bit, SYS_ICC_PPI_CPENDR0_EL1); 314 else 315 write_sysreg_s(bit, SYS_ICC_PPI_CPENDR1_EL1); 316 } 317 return; 318 case PPI_ACTIVE: 319 if (set) { 320 if (irq < 64) 321 write_sysreg_s(bit, SYS_ICC_PPI_SACTIVER0_EL1); 322 else 323 write_sysreg_s(bit, SYS_ICC_PPI_SACTIVER1_EL1); 324 } else { 325 if (irq < 64) 326 write_sysreg_s(bit, SYS_ICC_PPI_CACTIVER0_EL1); 327 else 328 write_sysreg_s(bit, SYS_ICC_PPI_CACTIVER1_EL1); 329 } 330 return; 331 default: 332 BUILD_BUG_ON(1); 333 } 334 } 335 336 static int gicv5_ppi_irq_get_irqchip_state(struct irq_data *d, 337 enum irqchip_irq_state which, 338 bool *state) 339 { 340 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64); 341 342 switch (which) { 343 case IRQCHIP_STATE_PENDING: 344 *state = !!(read_ppi_sysreg_s(d->hwirq, PPI_PENDING) & hwirq_id_bit); 345 return 0; 346 case IRQCHIP_STATE_ACTIVE: 347 *state = !!(read_ppi_sysreg_s(d->hwirq, PPI_ACTIVE) & hwirq_id_bit); 348 return 0; 349 default: 350 pr_debug("Unexpected PPI irqchip state\n"); 351 return -EINVAL; 352 } 353 } 354 355 static int gicv5_iri_irq_get_irqchip_state(struct irq_data *d, 356 enum irqchip_irq_state which, 357 bool *state, u8 hwirq_type) 358 { 359 u64 icsr, cdrcfg; 360 361 cdrcfg = d->hwirq | FIELD_PREP(GICV5_GIC_CDRCFG_TYPE_MASK, hwirq_type); 362 363 gic_insn(cdrcfg, CDRCFG); 364 isb(); 365 icsr = read_sysreg_s(SYS_ICC_ICSR_EL1); 366 367 if (FIELD_GET(ICC_ICSR_EL1_F, icsr)) { 368 pr_err("ICSR_EL1 is invalid\n"); 369 return -EINVAL; 370 } 371 372 switch (which) { 373 case IRQCHIP_STATE_PENDING: 374 *state = !!(FIELD_GET(ICC_ICSR_EL1_Pending, icsr)); 375 return 0; 376 377 case IRQCHIP_STATE_ACTIVE: 378 *state = !!(FIELD_GET(ICC_ICSR_EL1_Active, icsr)); 379 return 0; 380 381 default: 382 pr_debug("Unexpected irqchip_irq_state\n"); 383 return -EINVAL; 384 } 385 } 386 387 static int gicv5_spi_irq_get_irqchip_state(struct irq_data *d, 388 enum irqchip_irq_state which, 389 bool *state) 390 { 391 return gicv5_iri_irq_get_irqchip_state(d, which, state, 392 GICV5_HWIRQ_TYPE_SPI); 393 } 394 395 static int gicv5_lpi_irq_get_irqchip_state(struct irq_data *d, 396 enum irqchip_irq_state which, 397 bool *state) 398 { 399 return gicv5_iri_irq_get_irqchip_state(d, which, state, 400 GICV5_HWIRQ_TYPE_LPI); 401 } 402 403 static int gicv5_ppi_irq_set_irqchip_state(struct irq_data *d, 404 enum irqchip_irq_state which, 405 bool state) 406 { 407 switch (which) { 408 case IRQCHIP_STATE_PENDING: 409 write_ppi_sysreg_s(d->hwirq, state, PPI_PENDING); 410 return 0; 411 case IRQCHIP_STATE_ACTIVE: 412 write_ppi_sysreg_s(d->hwirq, state, PPI_ACTIVE); 413 return 0; 414 default: 415 pr_debug("Unexpected PPI irqchip state\n"); 416 return -EINVAL; 417 } 418 } 419 420 static void gicv5_iri_irq_write_pending_state(struct irq_data *d, bool state, 421 u8 hwirq_type) 422 { 423 u64 cdpend; 424 425 cdpend = FIELD_PREP(GICV5_GIC_CDPEND_TYPE_MASK, hwirq_type) | 426 FIELD_PREP(GICV5_GIC_CDPEND_ID_MASK, d->hwirq) | 427 FIELD_PREP(GICV5_GIC_CDPEND_PENDING_MASK, state); 428 429 gic_insn(cdpend, CDPEND); 430 } 431 432 static void gicv5_spi_irq_write_pending_state(struct irq_data *d, bool state) 433 { 434 gicv5_iri_irq_write_pending_state(d, state, GICV5_HWIRQ_TYPE_SPI); 435 } 436 437 static void gicv5_lpi_irq_write_pending_state(struct irq_data *d, bool state) 438 { 439 gicv5_iri_irq_write_pending_state(d, state, GICV5_HWIRQ_TYPE_LPI); 440 } 441 442 static int gicv5_spi_irq_set_irqchip_state(struct irq_data *d, 443 enum irqchip_irq_state which, 444 bool state) 445 { 446 switch (which) { 447 case IRQCHIP_STATE_PENDING: 448 gicv5_spi_irq_write_pending_state(d, state); 449 break; 450 default: 451 pr_debug("Unexpected irqchip_irq_state\n"); 452 return -EINVAL; 453 } 454 455 return 0; 456 } 457 458 static int gicv5_lpi_irq_set_irqchip_state(struct irq_data *d, 459 enum irqchip_irq_state which, 460 bool state) 461 { 462 switch (which) { 463 case IRQCHIP_STATE_PENDING: 464 gicv5_lpi_irq_write_pending_state(d, state); 465 break; 466 467 default: 468 pr_debug("Unexpected irqchip_irq_state\n"); 469 return -EINVAL; 470 } 471 472 return 0; 473 } 474 475 static int gicv5_spi_irq_retrigger(struct irq_data *data) 476 { 477 return !gicv5_spi_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, 478 true); 479 } 480 481 static int gicv5_lpi_irq_retrigger(struct irq_data *data) 482 { 483 return !gicv5_lpi_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, 484 true); 485 } 486 487 static void gicv5_ipi_send_single(struct irq_data *d, unsigned int cpu) 488 { 489 /* Mark the LPI pending */ 490 irq_chip_retrigger_hierarchy(d); 491 } 492 493 static bool gicv5_ppi_irq_is_level(irq_hw_number_t hwirq) 494 { 495 u64 bit = BIT_ULL(hwirq % 64); 496 497 return !!(read_ppi_sysreg_s(hwirq, PPI_HM) & bit); 498 } 499 500 static int gicv5_ppi_irq_set_type(struct irq_data *d, unsigned int type) 501 { 502 /* 503 * GICv5's PPIs do not have a configurable trigger or handling 504 * mode. Check that the attempt to set a type matches what the 505 * hardware reports in the HMR, and error on a mismatch. 506 */ 507 508 if (type & IRQ_TYPE_EDGE_BOTH && gicv5_ppi_irq_is_level(d->hwirq)) 509 return -EINVAL; 510 511 if (type & IRQ_TYPE_LEVEL_MASK && !gicv5_ppi_irq_is_level(d->hwirq)) 512 return -EINVAL; 513 514 return 0; 515 } 516 517 static int gicv5_ppi_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 518 { 519 if (vcpu) 520 irqd_set_forwarded_to_vcpu(d); 521 else 522 irqd_clr_forwarded_to_vcpu(d); 523 524 return 0; 525 } 526 527 static const struct irq_chip gicv5_ppi_irq_chip = { 528 .name = "GICv5-PPI", 529 .irq_mask = gicv5_ppi_irq_mask, 530 .irq_unmask = gicv5_ppi_irq_unmask, 531 .irq_eoi = gicv5_ppi_irq_eoi, 532 .irq_set_type = gicv5_ppi_irq_set_type, 533 .irq_get_irqchip_state = gicv5_ppi_irq_get_irqchip_state, 534 .irq_set_irqchip_state = gicv5_ppi_irq_set_irqchip_state, 535 .irq_set_vcpu_affinity = gicv5_ppi_irq_set_vcpu_affinity, 536 .flags = IRQCHIP_SKIP_SET_WAKE | 537 IRQCHIP_MASK_ON_SUSPEND, 538 }; 539 540 static const struct irq_chip gicv5_spi_irq_chip = { 541 .name = "GICv5-SPI", 542 .irq_mask = gicv5_spi_irq_mask, 543 .irq_unmask = gicv5_spi_irq_unmask, 544 .irq_eoi = gicv5_spi_irq_eoi, 545 .irq_set_type = gicv5_spi_irq_set_type, 546 .irq_set_affinity = gicv5_spi_irq_set_affinity, 547 .irq_retrigger = gicv5_spi_irq_retrigger, 548 .irq_get_irqchip_state = gicv5_spi_irq_get_irqchip_state, 549 .irq_set_irqchip_state = gicv5_spi_irq_set_irqchip_state, 550 .flags = IRQCHIP_SET_TYPE_MASKED | 551 IRQCHIP_SKIP_SET_WAKE | 552 IRQCHIP_MASK_ON_SUSPEND, 553 }; 554 555 static const struct irq_chip gicv5_lpi_irq_chip = { 556 .name = "GICv5-LPI", 557 .irq_mask = gicv5_lpi_irq_mask, 558 .irq_unmask = gicv5_lpi_irq_unmask, 559 .irq_eoi = gicv5_lpi_irq_eoi, 560 .irq_set_affinity = gicv5_lpi_irq_set_affinity, 561 .irq_retrigger = gicv5_lpi_irq_retrigger, 562 .irq_get_irqchip_state = gicv5_lpi_irq_get_irqchip_state, 563 .irq_set_irqchip_state = gicv5_lpi_irq_set_irqchip_state, 564 .flags = IRQCHIP_SKIP_SET_WAKE | 565 IRQCHIP_MASK_ON_SUSPEND, 566 }; 567 568 static const struct irq_chip gicv5_ipi_irq_chip = { 569 .name = "GICv5-IPI", 570 .irq_mask = irq_chip_mask_parent, 571 .irq_unmask = irq_chip_unmask_parent, 572 .irq_eoi = irq_chip_eoi_parent, 573 .irq_set_affinity = irq_chip_set_affinity_parent, 574 .irq_get_irqchip_state = irq_chip_get_parent_state, 575 .irq_set_irqchip_state = irq_chip_set_parent_state, 576 .ipi_send_single = gicv5_ipi_send_single, 577 .flags = IRQCHIP_SKIP_SET_WAKE | 578 IRQCHIP_MASK_ON_SUSPEND, 579 }; 580 581 static __always_inline int gicv5_irq_domain_translate(struct irq_domain *d, 582 struct irq_fwspec *fwspec, 583 irq_hw_number_t *hwirq, 584 unsigned int *type, 585 const u8 hwirq_type) 586 { 587 unsigned int hwirq_trigger; 588 u8 fwspec_irq_type; 589 590 if (is_of_node(fwspec->fwnode)) { 591 592 if (fwspec->param_count < 3) 593 return -EINVAL; 594 595 fwspec_irq_type = fwspec->param[0]; 596 597 if (fwspec->param[0] != hwirq_type) 598 return -EINVAL; 599 600 *hwirq = fwspec->param[1]; 601 hwirq_trigger = fwspec->param[2]; 602 } 603 604 if (is_fwnode_irqchip(fwspec->fwnode)) { 605 606 if (fwspec->param_count != 2) 607 return -EINVAL; 608 609 fwspec_irq_type = FIELD_GET(GICV5_HWIRQ_TYPE, fwspec->param[0]); 610 611 if (fwspec_irq_type != hwirq_type) 612 return -EINVAL; 613 614 *hwirq = FIELD_GET(GICV5_HWIRQ_ID, fwspec->param[0]); 615 hwirq_trigger = fwspec->param[1]; 616 } 617 618 switch (hwirq_type) { 619 case GICV5_HWIRQ_TYPE_PPI: 620 /* 621 * Handling mode is hardcoded for PPIs, set the type using 622 * HW reported value. 623 */ 624 *type = gicv5_ppi_irq_is_level(*hwirq) ? IRQ_TYPE_LEVEL_LOW : 625 IRQ_TYPE_EDGE_RISING; 626 break; 627 case GICV5_HWIRQ_TYPE_SPI: 628 *type = hwirq_trigger & IRQ_TYPE_SENSE_MASK; 629 break; 630 default: 631 BUILD_BUG_ON(1); 632 } 633 634 return 0; 635 } 636 637 static int gicv5_irq_ppi_domain_translate(struct irq_domain *d, 638 struct irq_fwspec *fwspec, 639 irq_hw_number_t *hwirq, 640 unsigned int *type) 641 { 642 return gicv5_irq_domain_translate(d, fwspec, hwirq, type, 643 GICV5_HWIRQ_TYPE_PPI); 644 } 645 646 static int gicv5_irq_ppi_domain_alloc(struct irq_domain *domain, unsigned int virq, 647 unsigned int nr_irqs, void *arg) 648 { 649 unsigned int type = IRQ_TYPE_NONE; 650 struct irq_fwspec *fwspec = arg; 651 irq_hw_number_t hwirq; 652 int ret; 653 654 if (WARN_ON_ONCE(nr_irqs != 1)) 655 return -EINVAL; 656 657 ret = gicv5_irq_ppi_domain_translate(domain, fwspec, &hwirq, &type); 658 if (ret) 659 return ret; 660 661 if (type & IRQ_TYPE_LEVEL_MASK) 662 irq_set_status_flags(virq, IRQ_LEVEL); 663 664 irq_set_percpu_devid(virq); 665 irq_domain_set_info(domain, virq, hwirq, &gicv5_ppi_irq_chip, NULL, 666 handle_percpu_devid_irq, NULL, NULL); 667 668 return 0; 669 } 670 671 static void gicv5_irq_domain_free(struct irq_domain *domain, unsigned int virq, 672 unsigned int nr_irqs) 673 { 674 struct irq_data *d; 675 676 if (WARN_ON_ONCE(nr_irqs != 1)) 677 return; 678 679 d = irq_domain_get_irq_data(domain, virq); 680 681 irq_set_handler(virq, NULL); 682 irq_domain_reset_irq_data(d); 683 } 684 685 static int gicv5_irq_ppi_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, 686 enum irq_domain_bus_token bus_token) 687 { 688 u32 hwirq_type; 689 690 if (fwspec->fwnode != d->fwnode) 691 return 0; 692 693 if (is_of_node(fwspec->fwnode)) 694 hwirq_type = fwspec->param[0]; 695 696 if (is_fwnode_irqchip(fwspec->fwnode)) 697 hwirq_type = FIELD_GET(GICV5_HWIRQ_TYPE, fwspec->param[0]); 698 699 if (hwirq_type != GICV5_HWIRQ_TYPE_PPI) 700 return 0; 701 702 return (d == gicv5_global_data.ppi_domain); 703 } 704 705 static const struct irq_domain_ops gicv5_irq_ppi_domain_ops = { 706 .translate = gicv5_irq_ppi_domain_translate, 707 .alloc = gicv5_irq_ppi_domain_alloc, 708 .free = gicv5_irq_domain_free, 709 .select = gicv5_irq_ppi_domain_select 710 }; 711 712 static int gicv5_irq_spi_domain_translate(struct irq_domain *d, 713 struct irq_fwspec *fwspec, 714 irq_hw_number_t *hwirq, 715 unsigned int *type) 716 { 717 return gicv5_irq_domain_translate(d, fwspec, hwirq, type, 718 GICV5_HWIRQ_TYPE_SPI); 719 } 720 721 static int gicv5_irq_spi_domain_alloc(struct irq_domain *domain, unsigned int virq, 722 unsigned int nr_irqs, void *arg) 723 { 724 struct gicv5_irs_chip_data *chip_data; 725 unsigned int type = IRQ_TYPE_NONE; 726 struct irq_fwspec *fwspec = arg; 727 struct irq_data *irqd; 728 irq_hw_number_t hwirq; 729 int ret; 730 731 if (WARN_ON_ONCE(nr_irqs != 1)) 732 return -EINVAL; 733 734 ret = gicv5_irq_spi_domain_translate(domain, fwspec, &hwirq, &type); 735 if (ret) 736 return ret; 737 738 irqd = irq_desc_get_irq_data(irq_to_desc(virq)); 739 chip_data = gicv5_irs_lookup_by_spi_id(hwirq); 740 741 irq_domain_set_info(domain, virq, hwirq, &gicv5_spi_irq_chip, chip_data, 742 handle_fasteoi_irq, NULL, NULL); 743 irq_set_probe(virq); 744 irqd_set_single_target(irqd); 745 746 gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_SPI); 747 748 return 0; 749 } 750 751 static int gicv5_irq_spi_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, 752 enum irq_domain_bus_token bus_token) 753 { 754 u32 hwirq_type; 755 756 if (fwspec->fwnode != d->fwnode) 757 return 0; 758 759 if (is_of_node(fwspec->fwnode)) 760 hwirq_type = fwspec->param[0]; 761 762 if (is_fwnode_irqchip(fwspec->fwnode)) 763 hwirq_type = FIELD_GET(GICV5_HWIRQ_TYPE, fwspec->param[0]); 764 765 if (hwirq_type != GICV5_HWIRQ_TYPE_SPI) 766 return 0; 767 768 return (d == gicv5_global_data.spi_domain); 769 } 770 771 static const struct irq_domain_ops gicv5_irq_spi_domain_ops = { 772 .translate = gicv5_irq_spi_domain_translate, 773 .alloc = gicv5_irq_spi_domain_alloc, 774 .free = gicv5_irq_domain_free, 775 .select = gicv5_irq_spi_domain_select 776 }; 777 778 static void gicv5_lpi_config_reset(struct irq_data *d) 779 { 780 u64 cdhm; 781 782 /* 783 * Reset LPIs handling mode to edge by default and clear pending 784 * state to make sure we start the LPI with a clean state from 785 * previous incarnations. 786 */ 787 cdhm = FIELD_PREP(GICV5_GIC_CDHM_HM_MASK, 0) | 788 FIELD_PREP(GICV5_GIC_CDHM_TYPE_MASK, GICV5_HWIRQ_TYPE_LPI) | 789 FIELD_PREP(GICV5_GIC_CDHM_ID_MASK, d->hwirq); 790 gic_insn(cdhm, CDHM); 791 792 gicv5_lpi_irq_write_pending_state(d, false); 793 } 794 795 static void gicv5_irq_lpi_domain_free(struct irq_domain *domain, unsigned int virq, 796 unsigned int nr_irqs) 797 { 798 struct irq_data *d; 799 800 for (unsigned int i = 0; i < nr_irqs; i++, virq++) { 801 d = irq_domain_get_irq_data(domain, virq); 802 803 release_lpi(d->hwirq); 804 805 irq_set_handler(virq, NULL); 806 irq_domain_reset_irq_data(d); 807 } 808 } 809 810 static int gicv5_irq_lpi_domain_alloc(struct irq_domain *domain, unsigned int virq, 811 unsigned int nr_irqs, void *arg) 812 { 813 irq_hw_number_t hwirq; 814 struct irq_data *irqd; 815 unsigned int i; 816 int ret; 817 818 for (i = 0; i < nr_irqs; i++) { 819 ret = alloc_lpi(); 820 if (ret < 0) 821 goto out_free_lpis; 822 hwirq = ret; 823 824 ret = gicv5_irs_iste_alloc(hwirq); 825 if (ret < 0) { 826 /* Undo partial state first, then clean up the rest */ 827 release_lpi(hwirq); 828 goto out_free_lpis; 829 } 830 831 irqd = irq_domain_get_irq_data(domain, virq + i); 832 833 irq_domain_set_info(domain, virq + i, hwirq, &gicv5_lpi_irq_chip, 834 NULL, handle_fasteoi_irq, NULL, NULL); 835 irqd_set_single_target(irqd); 836 837 gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_LPI); 838 gicv5_lpi_config_reset(irqd); 839 } 840 841 return 0; 842 843 out_free_lpis: 844 if (i) 845 gicv5_irq_lpi_domain_free(domain, virq, i); 846 847 return ret; 848 } 849 850 static const struct irq_domain_ops gicv5_irq_lpi_domain_ops = { 851 .alloc = gicv5_irq_lpi_domain_alloc, 852 .free = gicv5_irq_lpi_domain_free, 853 }; 854 855 void __init gicv5_init_lpi_domain(void) 856 { 857 struct irq_domain *d; 858 859 d = irq_domain_create_tree(NULL, &gicv5_irq_lpi_domain_ops, NULL); 860 gicv5_global_data.lpi_domain = d; 861 } 862 863 void __init gicv5_free_lpi_domain(void) 864 { 865 irq_domain_remove(gicv5_global_data.lpi_domain); 866 gicv5_global_data.lpi_domain = NULL; 867 } 868 869 static int gicv5_irq_ipi_domain_alloc(struct irq_domain *domain, unsigned int virq, 870 unsigned int nr_irqs, void *arg) 871 { 872 struct irq_data *irqd; 873 int ret; 874 875 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 876 if (ret) 877 return ret; 878 879 for (unsigned int i = 0; i < nr_irqs; i++, virq++) { 880 irqd = irq_domain_get_irq_data(domain, virq); 881 882 irq_domain_set_hwirq_and_chip(domain, virq, i, 883 &gicv5_ipi_irq_chip, NULL); 884 885 irqd_set_single_target(irqd); 886 887 irq_set_handler(virq, handle_percpu_irq); 888 } 889 890 return 0; 891 } 892 893 static void gicv5_irq_ipi_domain_free(struct irq_domain *domain, unsigned int virq, 894 unsigned int nr_irqs) 895 { 896 struct irq_data *d; 897 unsigned int i; 898 899 for (i = 0; i < nr_irqs; i++) { 900 d = irq_domain_get_irq_data(domain, virq + i); 901 902 if (!d) 903 return; 904 905 irq_set_handler(virq + i, NULL); 906 irq_domain_reset_irq_data(d); 907 } 908 909 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 910 } 911 912 static const struct irq_domain_ops gicv5_irq_ipi_domain_ops = { 913 .alloc = gicv5_irq_ipi_domain_alloc, 914 .free = gicv5_irq_ipi_domain_free, 915 }; 916 917 static void handle_irq_per_domain(u32 hwirq) 918 { 919 u8 hwirq_type = FIELD_GET(GICV5_HWIRQ_TYPE, hwirq); 920 u32 hwirq_id = FIELD_GET(GICV5_HWIRQ_ID, hwirq); 921 struct irq_domain *domain; 922 923 switch (hwirq_type) { 924 case GICV5_HWIRQ_TYPE_PPI: 925 domain = gicv5_global_data.ppi_domain; 926 break; 927 case GICV5_HWIRQ_TYPE_SPI: 928 domain = gicv5_global_data.spi_domain; 929 break; 930 case GICV5_HWIRQ_TYPE_LPI: 931 domain = gicv5_global_data.lpi_domain; 932 break; 933 default: 934 pr_err_once("Unknown IRQ type, bail out\n"); 935 return; 936 } 937 938 if (generic_handle_domain_irq(domain, hwirq_id)) { 939 pr_err_once("Could not handle, hwirq = 0x%x", hwirq_id); 940 gicv5_hwirq_eoi(hwirq_id, hwirq_type); 941 } 942 } 943 944 static void __exception_irq_entry gicv5_handle_irq(struct pt_regs *regs) 945 { 946 bool valid; 947 u32 hwirq; 948 u64 ia; 949 950 ia = gicr_insn(CDIA); 951 valid = GICV5_GICR_CDIA_VALID(ia); 952 953 if (!valid) 954 return; 955 956 /* 957 * Ensure that the CDIA instruction effects (ie IRQ activation) are 958 * completed before handling the interrupt. 959 */ 960 gsb_ack(); 961 962 /* 963 * Ensure instruction ordering between an acknowledgment and subsequent 964 * instructions in the IRQ handler using an ISB. 965 */ 966 isb(); 967 968 /* 969 * Ensure that we can receive the next interrupts in the event that we 970 * have a long running handler or directly enter a guest by doing the 971 * priority drop immediately. 972 */ 973 gic_insn(0, CDEOI); 974 975 hwirq = FIELD_GET(GICV5_HWIRQ_INTID, ia); 976 977 handle_irq_per_domain(hwirq); 978 } 979 980 static void gicv5_cpu_disable_interrupts(void) 981 { 982 u64 cr0; 983 984 cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0); 985 write_sysreg_s(cr0, SYS_ICC_CR0_EL1); 986 } 987 988 static void gicv5_cpu_enable_interrupts(void) 989 { 990 u64 cr0, pcr; 991 992 write_sysreg_s(0, SYS_ICC_PPI_ENABLER0_EL1); 993 write_sysreg_s(0, SYS_ICC_PPI_ENABLER1_EL1); 994 995 gicv5_ppi_priority_init(); 996 997 pcr = FIELD_PREP(ICC_PCR_EL1_PRIORITY, GICV5_IRQ_PRI_MI); 998 write_sysreg_s(pcr, SYS_ICC_PCR_EL1); 999 1000 cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 1); 1001 write_sysreg_s(cr0, SYS_ICC_CR0_EL1); 1002 } 1003 1004 static int base_ipi_virq; 1005 1006 static int gicv5_starting_cpu(unsigned int cpu) 1007 { 1008 if (WARN(!gicv5_cpuif_has_gcie(), 1009 "GICv5 system components present but CPU does not have FEAT_GCIE")) 1010 return -ENODEV; 1011 1012 gicv5_cpu_enable_interrupts(); 1013 1014 return gicv5_irs_register_cpu(cpu); 1015 } 1016 1017 static void __init gicv5_smp_init(void) 1018 { 1019 unsigned int num_ipis = GICV5_IPIS_PER_CPU * nr_cpu_ids; 1020 1021 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 1022 "irqchip/arm/gicv5:starting", 1023 gicv5_starting_cpu, NULL); 1024 1025 base_ipi_virq = irq_domain_alloc_irqs(gicv5_global_data.ipi_domain, 1026 num_ipis, NUMA_NO_NODE, NULL); 1027 if (WARN(base_ipi_virq <= 0, "IPI IRQ allocation was not successful")) 1028 return; 1029 1030 set_smp_ipi_range_percpu(base_ipi_virq, GICV5_IPIS_PER_CPU, nr_cpu_ids); 1031 } 1032 1033 static void __init gicv5_free_domains(void) 1034 { 1035 if (gicv5_global_data.ppi_domain) 1036 irq_domain_remove(gicv5_global_data.ppi_domain); 1037 if (gicv5_global_data.spi_domain) 1038 irq_domain_remove(gicv5_global_data.spi_domain); 1039 if (gicv5_global_data.ipi_domain) 1040 irq_domain_remove(gicv5_global_data.ipi_domain); 1041 1042 gicv5_global_data.ppi_domain = NULL; 1043 gicv5_global_data.spi_domain = NULL; 1044 gicv5_global_data.ipi_domain = NULL; 1045 } 1046 1047 static int __init gicv5_init_domains(struct fwnode_handle *handle) 1048 { 1049 u32 spi_count = gicv5_global_data.global_spi_count; 1050 struct irq_domain *d; 1051 1052 d = irq_domain_create_linear(handle, PPI_NR, &gicv5_irq_ppi_domain_ops, NULL); 1053 if (!d) 1054 return -ENOMEM; 1055 1056 irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED); 1057 gicv5_global_data.ppi_domain = d; 1058 1059 if (spi_count) { 1060 d = irq_domain_create_linear(handle, spi_count, 1061 &gicv5_irq_spi_domain_ops, NULL); 1062 1063 if (!d) { 1064 gicv5_free_domains(); 1065 return -ENOMEM; 1066 } 1067 1068 gicv5_global_data.spi_domain = d; 1069 irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED); 1070 } 1071 1072 if (!WARN(!gicv5_global_data.lpi_domain, 1073 "LPI domain uninitialized, can't set up IPIs")) { 1074 d = irq_domain_create_hierarchy(gicv5_global_data.lpi_domain, 1075 0, GICV5_IPIS_PER_CPU * nr_cpu_ids, 1076 NULL, &gicv5_irq_ipi_domain_ops, 1077 NULL); 1078 1079 if (!d) { 1080 gicv5_free_domains(); 1081 return -ENOMEM; 1082 } 1083 gicv5_global_data.ipi_domain = d; 1084 } 1085 gicv5_global_data.fwnode = handle; 1086 1087 return 0; 1088 } 1089 1090 static void gicv5_set_cpuif_pribits(void) 1091 { 1092 u64 icc_idr0 = read_sysreg_s(SYS_ICC_IDR0_EL1); 1093 1094 switch (FIELD_GET(ICC_IDR0_EL1_PRI_BITS, icc_idr0)) { 1095 case ICC_IDR0_EL1_PRI_BITS_4BITS: 1096 gicv5_global_data.cpuif_pri_bits = 4; 1097 break; 1098 case ICC_IDR0_EL1_PRI_BITS_5BITS: 1099 gicv5_global_data.cpuif_pri_bits = 5; 1100 break; 1101 default: 1102 pr_err("Unexpected ICC_IDR0_EL1_PRI_BITS value, default to 4"); 1103 gicv5_global_data.cpuif_pri_bits = 4; 1104 break; 1105 } 1106 } 1107 1108 static void gicv5_set_cpuif_idbits(void) 1109 { 1110 u32 icc_idr0 = read_sysreg_s(SYS_ICC_IDR0_EL1); 1111 1112 switch (FIELD_GET(ICC_IDR0_EL1_ID_BITS, icc_idr0)) { 1113 case ICC_IDR0_EL1_ID_BITS_16BITS: 1114 gicv5_global_data.cpuif_id_bits = 16; 1115 break; 1116 case ICC_IDR0_EL1_ID_BITS_24BITS: 1117 gicv5_global_data.cpuif_id_bits = 24; 1118 break; 1119 default: 1120 pr_err("Unexpected ICC_IDR0_EL1_ID_BITS value, default to 16"); 1121 gicv5_global_data.cpuif_id_bits = 16; 1122 break; 1123 } 1124 } 1125 1126 #ifdef CONFIG_KVM 1127 static struct gic_kvm_info gic_v5_kvm_info __initdata; 1128 1129 static void __init gic_of_setup_kvm_info(struct device_node *node) 1130 { 1131 /* 1132 * If we don't have native GICv5 virtualisation support, then 1133 * we also don't have FEAT_GCIE_LEGACY - the architecture 1134 * forbids this combination. 1135 */ 1136 if (!gicv5_global_data.virt_capable) { 1137 pr_info("GIC implementation is not virtualization capable\n"); 1138 return; 1139 } 1140 1141 gic_v5_kvm_info.type = GIC_V5; 1142 1143 /* GIC Virtual CPU interface maintenance interrupt */ 1144 gic_v5_kvm_info.no_maint_irq_mask = false; 1145 gic_v5_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1146 if (!gic_v5_kvm_info.maint_irq) { 1147 pr_warn("cannot find GICv5 virtual CPU interface maintenance interrupt\n"); 1148 return; 1149 } 1150 1151 vgic_set_kvm_info(&gic_v5_kvm_info); 1152 } 1153 #else 1154 static inline void __init gic_of_setup_kvm_info(struct device_node *node) 1155 { 1156 } 1157 #endif // CONFIG_KVM 1158 1159 static int __init gicv5_init_common(struct fwnode_handle *parent_domain) 1160 { 1161 int ret = gicv5_init_domains(parent_domain); 1162 if (ret) 1163 return ret; 1164 1165 gicv5_set_cpuif_pribits(); 1166 gicv5_set_cpuif_idbits(); 1167 1168 pri_bits = min_not_zero(gicv5_global_data.cpuif_pri_bits, 1169 gicv5_global_data.irs_pri_bits); 1170 1171 ret = gicv5_starting_cpu(smp_processor_id()); 1172 if (ret) 1173 goto out_dom; 1174 1175 ret = set_handle_irq(gicv5_handle_irq); 1176 if (ret) 1177 goto out_int; 1178 1179 ret = gicv5_irs_enable(); 1180 if (ret) 1181 goto out_int; 1182 1183 gicv5_smp_init(); 1184 1185 gicv5_irs_its_probe(); 1186 return 0; 1187 1188 out_int: 1189 gicv5_cpu_disable_interrupts(); 1190 out_dom: 1191 gicv5_free_domains(); 1192 return ret; 1193 } 1194 1195 static int __init gicv5_of_init(struct device_node *node, struct device_node *parent) 1196 { 1197 int ret = gicv5_irs_of_probe(node); 1198 if (ret) 1199 return ret; 1200 1201 ret = gicv5_init_common(of_fwnode_handle(node)); 1202 if (ret) 1203 goto out_irs; 1204 1205 gic_of_setup_kvm_info(node); 1206 1207 return 0; 1208 out_irs: 1209 gicv5_irs_remove(); 1210 1211 return ret; 1212 } 1213 IRQCHIP_DECLARE(gic_v5, "arm,gic-v5", gicv5_of_init); 1214 1215 #ifdef CONFIG_ACPI 1216 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1217 struct acpi_probe_entry *ape) 1218 { 1219 struct acpi_madt_gicv5_irs *irs = (struct acpi_madt_gicv5_irs *)header; 1220 1221 return (irs->version == ape->driver_data); 1222 } 1223 1224 static struct fwnode_handle *gsi_domain_handle; 1225 1226 static struct fwnode_handle *gic_v5_get_gsi_domain_id(u32 gsi) 1227 { 1228 if (FIELD_GET(GICV5_GSI_IC_TYPE, gsi) == GICV5_GSI_IWB_TYPE) 1229 return iort_iwb_handle(FIELD_GET(GICV5_GSI_IWB_FRAME_ID, gsi)); 1230 1231 return gsi_domain_handle; 1232 } 1233 1234 static int __init gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end) 1235 { 1236 struct acpi_madt_gicv5_irs *irs = (struct acpi_madt_gicv5_irs *)header; 1237 int ret; 1238 1239 if (gsi_domain_handle) 1240 return 0; 1241 1242 gsi_domain_handle = irq_domain_alloc_fwnode(&irs->config_base_address); 1243 if (!gsi_domain_handle) 1244 return -ENOMEM; 1245 1246 ret = gicv5_irs_acpi_probe(); 1247 if (ret) 1248 goto out_fwnode; 1249 1250 ret = gicv5_init_common(gsi_domain_handle); 1251 if (ret) 1252 goto out_irs; 1253 1254 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC_V5, gic_v5_get_gsi_domain_id); 1255 1256 return 0; 1257 1258 out_irs: 1259 gicv5_irs_remove(); 1260 out_fwnode: 1261 irq_domain_free_fwnode(gsi_domain_handle); 1262 return ret; 1263 } 1264 IRQCHIP_ACPI_DECLARE(gic_v5, ACPI_MADT_TYPE_GICV5_IRS, 1265 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V5, 1266 gic_acpi_init); 1267 #endif 1268