1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, 2020, Linaro Ltd.
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/suspend.h>
21 #include <linux/thermal.h>
22 #include "../thermal_hwmon.h"
23 #include "tsens.h"
24
25 /**
26 * struct tsens_irq_data - IRQ status and temperature violations
27 * @up_viol: upper threshold violated
28 * @up_thresh: upper threshold temperature value
29 * @up_irq_mask: mask register for upper threshold irqs
30 * @up_irq_clear: clear register for upper threshold irqs
31 * @low_viol: lower threshold violated
32 * @low_thresh: lower threshold temperature value
33 * @low_irq_mask: mask register for lower threshold irqs
34 * @low_irq_clear: clear register for lower threshold irqs
35 * @crit_viol: critical threshold violated
36 * @crit_thresh: critical threshold temperature value
37 * @crit_irq_mask: mask register for critical threshold irqs
38 * @crit_irq_clear: clear register for critical threshold irqs
39 *
40 * Structure containing data about temperature threshold settings and
41 * irq status if they were violated.
42 */
43 struct tsens_irq_data {
44 u32 up_viol;
45 int up_thresh;
46 u32 up_irq_mask;
47 u32 up_irq_clear;
48 u32 low_viol;
49 int low_thresh;
50 u32 low_irq_mask;
51 u32 low_irq_clear;
52 u32 crit_viol;
53 u32 crit_thresh;
54 u32 crit_irq_mask;
55 u32 crit_irq_clear;
56 };
57
qfprom_read(struct device * dev,const char * cname)58 char *qfprom_read(struct device *dev, const char *cname)
59 {
60 struct nvmem_cell *cell;
61 ssize_t data;
62 char *ret;
63
64 cell = nvmem_cell_get(dev, cname);
65 if (IS_ERR(cell))
66 return ERR_CAST(cell);
67
68 ret = nvmem_cell_read(cell, &data);
69 nvmem_cell_put(cell);
70
71 return ret;
72 }
73
tsens_read_calibration(struct tsens_priv * priv,int shift,u32 * p1,u32 * p2,bool backup)74 int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup)
75 {
76 u32 mode;
77 u32 base1, base2;
78 char name[] = "sXX_pY_backup"; /* s10_p1_backup */
79 int i, ret;
80
81 if (priv->num_sensors > MAX_SENSORS)
82 return -EINVAL;
83
84 ret = snprintf(name, sizeof(name), "mode%s", backup ? "_backup" : "");
85 if (ret < 0)
86 return ret;
87
88 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode);
89 if (ret == -ENOENT)
90 dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n");
91 if (ret < 0)
92 return ret;
93
94 dev_dbg(priv->dev, "calibration mode is %d\n", mode);
95
96 ret = snprintf(name, sizeof(name), "base1%s", backup ? "_backup" : "");
97 if (ret < 0)
98 return ret;
99
100 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1);
101 if (ret < 0)
102 return ret;
103
104 ret = snprintf(name, sizeof(name), "base2%s", backup ? "_backup" : "");
105 if (ret < 0)
106 return ret;
107
108 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base2);
109 if (ret < 0)
110 return ret;
111
112 for (i = 0; i < priv->num_sensors; i++) {
113 ret = snprintf(name, sizeof(name), "s%d_p1%s", priv->sensor[i].hw_id,
114 backup ? "_backup" : "");
115 if (ret < 0)
116 return ret;
117
118 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p1[i]);
119 if (ret)
120 return ret;
121
122 ret = snprintf(name, sizeof(name), "s%d_p2%s", priv->sensor[i].hw_id,
123 backup ? "_backup" : "");
124 if (ret < 0)
125 return ret;
126
127 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p2[i]);
128 if (ret)
129 return ret;
130 }
131
132 switch (mode) {
133 case ONE_PT_CALIB:
134 for (i = 0; i < priv->num_sensors; i++)
135 p1[i] = p1[i] + (base1 << shift);
136 break;
137 case TWO_PT_CALIB:
138 case TWO_PT_CALIB_NO_OFFSET:
139 for (i = 0; i < priv->num_sensors; i++)
140 p2[i] = (p2[i] + base2) << shift;
141 fallthrough;
142 case ONE_PT_CALIB2:
143 case ONE_PT_CALIB2_NO_OFFSET:
144 for (i = 0; i < priv->num_sensors; i++)
145 p1[i] = (p1[i] + base1) << shift;
146 break;
147 default:
148 dev_dbg(priv->dev, "calibrationless mode\n");
149 for (i = 0; i < priv->num_sensors; i++) {
150 p1[i] = 500;
151 p2[i] = 780;
152 }
153 }
154
155 /* Apply calibration offset workaround except for _NO_OFFSET modes */
156 switch (mode) {
157 case TWO_PT_CALIB:
158 for (i = 0; i < priv->num_sensors; i++)
159 p2[i] += priv->sensor[i].p2_calib_offset;
160 fallthrough;
161 case ONE_PT_CALIB2:
162 for (i = 0; i < priv->num_sensors; i++)
163 p1[i] += priv->sensor[i].p1_calib_offset;
164 break;
165 }
166
167 return mode;
168 }
169
tsens_calibrate_nvmem(struct tsens_priv * priv,int shift)170 int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift)
171 {
172 u32 p1[MAX_SENSORS], p2[MAX_SENSORS];
173 int mode;
174
175 mode = tsens_read_calibration(priv, shift, p1, p2, false);
176 if (mode < 0)
177 return mode;
178
179 compute_intercept_slope(priv, p1, p2, mode);
180
181 return 0;
182 }
183
tsens_calibrate_common(struct tsens_priv * priv)184 int tsens_calibrate_common(struct tsens_priv *priv)
185 {
186 return tsens_calibrate_nvmem(priv, 2);
187 }
188
tsens_read_cell(const struct tsens_single_value * cell,u8 len,u32 * data0,u32 * data1)189 static u32 tsens_read_cell(const struct tsens_single_value *cell, u8 len, u32 *data0, u32 *data1)
190 {
191 u32 val;
192 u32 *data = cell->blob ? data1 : data0;
193
194 if (cell->shift + len <= 32) {
195 val = data[cell->idx] >> cell->shift;
196 } else {
197 u8 part = 32 - cell->shift;
198
199 val = data[cell->idx] >> cell->shift;
200 val |= data[cell->idx + 1] << part;
201 }
202
203 return val & ((1 << len) - 1);
204 }
205
tsens_read_calibration_legacy(struct tsens_priv * priv,const struct tsens_legacy_calibration_format * format,u32 * p1,u32 * p2,u32 * cdata0,u32 * cdata1)206 int tsens_read_calibration_legacy(struct tsens_priv *priv,
207 const struct tsens_legacy_calibration_format *format,
208 u32 *p1, u32 *p2,
209 u32 *cdata0, u32 *cdata1)
210 {
211 u32 mode, invalid;
212 u32 base1, base2;
213 int i;
214
215 mode = tsens_read_cell(&format->mode, 2, cdata0, cdata1);
216 invalid = tsens_read_cell(&format->invalid, 1, cdata0, cdata1);
217 if (invalid)
218 mode = NO_PT_CALIB;
219 dev_dbg(priv->dev, "calibration mode is %d\n", mode);
220
221 base1 = tsens_read_cell(&format->base[0], format->base_len, cdata0, cdata1);
222 base2 = tsens_read_cell(&format->base[1], format->base_len, cdata0, cdata1);
223
224 for (i = 0; i < priv->num_sensors; i++) {
225 p1[i] = tsens_read_cell(&format->sp[i][0], format->sp_len, cdata0, cdata1);
226 p2[i] = tsens_read_cell(&format->sp[i][1], format->sp_len, cdata0, cdata1);
227 }
228
229 switch (mode) {
230 case ONE_PT_CALIB:
231 for (i = 0; i < priv->num_sensors; i++)
232 p1[i] = p1[i] + (base1 << format->base_shift);
233 break;
234 case TWO_PT_CALIB:
235 for (i = 0; i < priv->num_sensors; i++)
236 p2[i] = (p2[i] + base2) << format->base_shift;
237 fallthrough;
238 case ONE_PT_CALIB2:
239 for (i = 0; i < priv->num_sensors; i++)
240 p1[i] = (p1[i] + base1) << format->base_shift;
241 break;
242 default:
243 dev_dbg(priv->dev, "calibrationless mode\n");
244 for (i = 0; i < priv->num_sensors; i++) {
245 p1[i] = 500;
246 p2[i] = 780;
247 }
248 }
249
250 return mode;
251 }
252
253 /*
254 * Use this function on devices where slope and offset calculations
255 * depend on calibration data read from qfprom. On others the slope
256 * and offset values are derived from tz->tzp->slope and tz->tzp->offset
257 * resp.
258 */
compute_intercept_slope(struct tsens_priv * priv,u32 * p1,u32 * p2,u32 mode)259 void compute_intercept_slope(struct tsens_priv *priv, u32 *p1,
260 u32 *p2, u32 mode)
261 {
262 int i;
263 int num, den;
264
265 for (i = 0; i < priv->num_sensors; i++) {
266 dev_dbg(priv->dev,
267 "%s: sensor%d - data_point1:%#x data_point2:%#x\n",
268 __func__, i, p1[i], p2 ? p2[i] : 0);
269
270 if (!priv->sensor[i].slope)
271 priv->sensor[i].slope = SLOPE_DEFAULT;
272 if (mode == TWO_PT_CALIB || mode == TWO_PT_CALIB_NO_OFFSET) {
273 /*
274 * slope (m) = adc_code2 - adc_code1 (y2 - y1)/
275 * temp_120_degc - temp_30_degc (x2 - x1)
276 */
277 num = p2[i] - p1[i];
278 num *= SLOPE_FACTOR;
279 den = CAL_DEGC_PT2 - CAL_DEGC_PT1;
280 priv->sensor[i].slope = num / den;
281 }
282
283 priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) -
284 (CAL_DEGC_PT1 *
285 priv->sensor[i].slope);
286 dev_dbg(priv->dev, "%s: offset:%d\n", __func__,
287 priv->sensor[i].offset);
288 }
289 }
290
degc_to_code(int degc,const struct tsens_sensor * s)291 static inline u32 degc_to_code(int degc, const struct tsens_sensor *s)
292 {
293 u64 code = div_u64(((u64)degc * s->slope + s->offset), SLOPE_FACTOR);
294
295 pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc);
296 return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE);
297 }
298
code_to_degc(u32 adc_code,const struct tsens_sensor * s)299 static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s)
300 {
301 int degc, num, den;
302
303 num = (adc_code * SLOPE_FACTOR) - s->offset;
304 den = s->slope;
305
306 if (num > 0)
307 degc = num + (den / 2);
308 else if (num < 0)
309 degc = num - (den / 2);
310 else
311 degc = num;
312
313 degc /= den;
314
315 return degc;
316 }
317
318 /**
319 * tsens_read_temp - Retrieve temperature readings from the hardware.
320 * @s: Pointer to sensor struct
321 * @field: Index into regmap_field array pointing to temperature data
322 * @temp: temperature in deciCelsius to be read from hardware
323 *
324 * This function handles temperature returned in ADC code or deciCelsius
325 * depending on IP version.
326 *
327 * Return: 0 on success, a negative errno will be returned in error cases
328 */
tsens_read_temp(const struct tsens_sensor * s,int field,int * temp)329 static int tsens_read_temp(const struct tsens_sensor *s, int field, int *temp)
330 {
331 struct tsens_priv *priv = s->priv;
332 int temp_val[MAX_READ_RETRY] = {0};
333 u32 status;
334 int ret;
335 u32 last_temp_mask = GENMASK(priv->fields[LAST_TEMP_0].msb,
336 priv->fields[LAST_TEMP_0].lsb);
337 u32 valid_bit = priv->rf[VALID_0] ? BIT(priv->fields[VALID_0].lsb) : 0;
338
339 for (int i = 0; i < MAX_READ_RETRY; i++) {
340 ret = regmap_read(priv->tm_map, priv->fields[field].reg, &status);
341 if (ret)
342 return ret;
343
344 /* VER_0 doesn't have a VALID bit */
345 if (!valid_bit) {
346 *temp = status & last_temp_mask;
347 return 0;
348 }
349
350 temp_val[i] = status & last_temp_mask;
351
352 if (status & valid_bit) {
353 *temp = temp_val[i];
354 return 0;
355 }
356 }
357
358 /*
359 * As per the HW guidelines, if none of the attempts observe a
360 * valid sample, a stable fallback value must be returned. If the
361 * first and second samples match, the second value is returned;
362 * otherwise, if the second and third samples match, the third
363 * value is returned.
364 */
365 if (temp_val[0] == temp_val[1])
366 *temp = temp_val[1];
367 else if (temp_val[1] == temp_val[2])
368 *temp = temp_val[2];
369 else
370 return -EAGAIN;
371
372 return 0;
373 }
374
375 /**
376 * tsens_hw_to_mC - Return sign-extended temperature in mCelsius.
377 * @s: Pointer to sensor struct
378 * @temp: temperature in milliCelsius to be read from hardware
379 *
380 * This function handles temperature returned in ADC code or deciCelsius
381 * depending on IP version.
382 *
383 * Return: Temperature in milliCelsius on success, a negative errno will
384 * be returned in error cases
385 */
tsens_hw_to_mC(const struct tsens_sensor * s,int temp)386 static int tsens_hw_to_mC(const struct tsens_sensor *s, int temp)
387 {
388 struct tsens_priv *priv = s->priv;
389 u32 resolution;
390
391 resolution = priv->fields[LAST_TEMP_0].msb -
392 priv->fields[LAST_TEMP_0].lsb;
393
394 /* Convert temperature from ADC code to milliCelsius */
395 if (priv->feat->adc)
396 return code_to_degc(temp, s) * 1000;
397
398 /* deciCelsius -> milliCelsius along with sign extension */
399 return sign_extend32(temp, resolution) * 100;
400 }
401
402 /**
403 * tsens_mC_to_hw - Convert temperature to hardware register value
404 * @s: Pointer to sensor struct
405 * @temp: temperature in milliCelsius to be programmed to hardware
406 *
407 * This function outputs the value to be written to hardware in ADC code
408 * or deciCelsius depending on IP version.
409 *
410 * Return: ADC code or temperature in deciCelsius.
411 */
tsens_mC_to_hw(const struct tsens_sensor * s,int temp)412 static int tsens_mC_to_hw(const struct tsens_sensor *s, int temp)
413 {
414 struct tsens_priv *priv = s->priv;
415
416 /* milliC to adc code */
417 if (priv->feat->adc)
418 return degc_to_code(temp / 1000, s);
419
420 /* milliC to deciC */
421 return temp / 100;
422 }
423
tsens_version(struct tsens_priv * priv)424 static inline enum tsens_ver tsens_version(struct tsens_priv *priv)
425 {
426 return priv->feat->ver_major;
427 }
428
tsens_set_interrupt_v1(struct tsens_priv * priv,u32 hw_id,enum tsens_irq_type irq_type,bool enable)429 static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id,
430 enum tsens_irq_type irq_type, bool enable)
431 {
432 u32 index = 0;
433
434 switch (irq_type) {
435 case UPPER:
436 index = UP_INT_CLEAR_0 + hw_id;
437 break;
438 case LOWER:
439 index = LOW_INT_CLEAR_0 + hw_id;
440 break;
441 case CRITICAL:
442 /* No critical interrupts before v2 */
443 return;
444 }
445 regmap_field_write(priv->rf[index], enable ? 0 : 1);
446 }
447
tsens_set_interrupt_v2(struct tsens_priv * priv,u32 hw_id,enum tsens_irq_type irq_type,bool enable)448 static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id,
449 enum tsens_irq_type irq_type, bool enable)
450 {
451 u32 index_mask = 0, index_clear = 0;
452
453 /*
454 * To enable the interrupt flag for a sensor:
455 * - clear the mask bit
456 * To disable the interrupt flag for a sensor:
457 * - Mask further interrupts for this sensor
458 * - Write 1 followed by 0 to clear the interrupt
459 */
460 switch (irq_type) {
461 case UPPER:
462 index_mask = UP_INT_MASK_0 + hw_id;
463 index_clear = UP_INT_CLEAR_0 + hw_id;
464 break;
465 case LOWER:
466 index_mask = LOW_INT_MASK_0 + hw_id;
467 index_clear = LOW_INT_CLEAR_0 + hw_id;
468 break;
469 case CRITICAL:
470 index_mask = CRIT_INT_MASK_0 + hw_id;
471 index_clear = CRIT_INT_CLEAR_0 + hw_id;
472 break;
473 }
474
475 if (enable) {
476 regmap_field_write(priv->rf[index_mask], 0);
477 } else {
478 regmap_field_write(priv->rf[index_mask], 1);
479 regmap_field_write(priv->rf[index_clear], 1);
480 regmap_field_write(priv->rf[index_clear], 0);
481 }
482 }
483
484 /**
485 * tsens_set_interrupt - Set state of an interrupt
486 * @priv: Pointer to tsens controller private data
487 * @hw_id: Hardware ID aka. sensor number
488 * @irq_type: irq_type from enum tsens_irq_type
489 * @enable: false = disable, true = enable
490 *
491 * Call IP-specific function to set state of an interrupt
492 *
493 * Return: void
494 */
tsens_set_interrupt(struct tsens_priv * priv,u32 hw_id,enum tsens_irq_type irq_type,bool enable)495 static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id,
496 enum tsens_irq_type irq_type, bool enable)
497 {
498 dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__,
499 irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW",
500 enable ? "en" : "dis");
501 if (tsens_version(priv) >= VER_2_X)
502 tsens_set_interrupt_v2(priv, hw_id, irq_type, enable);
503 else
504 tsens_set_interrupt_v1(priv, hw_id, irq_type, enable);
505 }
506
507 /**
508 * tsens_threshold_violated - Check if a sensor temperature violated a preset threshold
509 * @priv: Pointer to tsens controller private data
510 * @hw_id: Hardware ID aka. sensor number
511 * @d: Pointer to irq state data
512 *
513 * Return: 0 if threshold was not violated, 1 if it was violated and negative
514 * errno in case of errors
515 */
tsens_threshold_violated(struct tsens_priv * priv,u32 hw_id,struct tsens_irq_data * d)516 static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id,
517 struct tsens_irq_data *d)
518 {
519 int ret;
520
521 ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol);
522 if (ret)
523 return ret;
524 ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol);
525 if (ret)
526 return ret;
527
528 if (priv->feat->crit_int) {
529 ret = regmap_field_read(priv->rf[CRITICAL_STATUS_0 + hw_id],
530 &d->crit_viol);
531 if (ret)
532 return ret;
533 }
534
535 if (d->up_viol || d->low_viol || d->crit_viol)
536 return 1;
537
538 return 0;
539 }
540
tsens_read_irq_state(struct tsens_priv * priv,u32 hw_id,const struct tsens_sensor * s,struct tsens_irq_data * d)541 static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id,
542 const struct tsens_sensor *s,
543 struct tsens_irq_data *d)
544 {
545 int ret;
546
547 ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear);
548 if (ret)
549 return ret;
550 ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear);
551 if (ret)
552 return ret;
553 if (tsens_version(priv) >= VER_2_X) {
554 ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask);
555 if (ret)
556 return ret;
557 ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask);
558 if (ret)
559 return ret;
560 ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id],
561 &d->crit_irq_clear);
562 if (ret)
563 return ret;
564 ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id],
565 &d->crit_irq_mask);
566 if (ret)
567 return ret;
568 ret = regmap_field_read(priv->rf[CRIT_THRESH_0 + hw_id], &d->crit_thresh);
569 if (ret)
570 return ret;
571 d->crit_thresh = tsens_hw_to_mC(s, d->crit_thresh);
572 } else {
573 /* No mask register on older TSENS */
574 d->up_irq_mask = 0;
575 d->low_irq_mask = 0;
576 d->crit_irq_clear = 0;
577 d->crit_irq_mask = 0;
578 d->crit_thresh = 0;
579 }
580
581 ret = regmap_field_read(priv->rf[UP_THRESH_0 + hw_id], &d->up_thresh);
582 if (ret)
583 return ret;
584
585 d->up_thresh = tsens_hw_to_mC(s, d->up_thresh);
586 ret = regmap_field_read(priv->rf[LOW_THRESH_0 + hw_id], &d->low_thresh);
587 if (ret)
588 return ret;
589
590 d->low_thresh = tsens_hw_to_mC(s, d->low_thresh);
591
592 dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u|%u) | clr(%u|%u|%u) | mask(%u|%u|%u)\n",
593 hw_id, __func__,
594 (d->up_viol || d->low_viol || d->crit_viol) ? "(V)" : "",
595 d->low_viol, d->up_viol, d->crit_viol,
596 d->low_irq_clear, d->up_irq_clear, d->crit_irq_clear,
597 d->low_irq_mask, d->up_irq_mask, d->crit_irq_mask);
598 dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d:%d)\n", hw_id, __func__,
599 (d->up_viol || d->low_viol || d->crit_viol) ? "(V)" : "",
600 d->low_thresh, d->up_thresh, d->crit_thresh);
601
602 return 0;
603 }
604
masked_irq(u32 hw_id,u32 mask,enum tsens_ver ver)605 static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver)
606 {
607 if (ver >= VER_2_X)
608 return mask & (1 << hw_id);
609
610 /* v1, v0.1 don't have a irq mask register */
611 return 0;
612 }
613
614 /**
615 * tsens_critical_irq_thread() - Threaded handler for critical interrupts
616 * @irq: irq number
617 * @data: tsens controller private data
618 *
619 * Check FSM watchdog bark status and clear if needed.
620 * Check all sensors to find ones that violated their critical threshold limits.
621 * Clear and then re-enable the interrupt.
622 *
623 * The level-triggered interrupt might deassert if the temperature returned to
624 * within the threshold limits by the time the handler got scheduled. We
625 * consider the irq to have been handled in that case.
626 *
627 * Return: IRQ_HANDLED
628 */
tsens_critical_irq_thread(int irq,void * data)629 static irqreturn_t tsens_critical_irq_thread(int irq, void *data)
630 {
631 struct tsens_priv *priv = data;
632 struct tsens_irq_data d;
633 int temp, ret, i;
634 u32 wdog_status, wdog_count;
635
636 if (priv->feat->has_watchdog) {
637 ret = regmap_field_read(priv->rf[WDOG_BARK_STATUS],
638 &wdog_status);
639 if (ret)
640 return ret;
641
642 if (wdog_status) {
643 /* Clear WDOG interrupt */
644 regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 1);
645 regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 0);
646 ret = regmap_field_read(priv->rf[WDOG_BARK_COUNT],
647 &wdog_count);
648 if (ret)
649 return ret;
650 if (wdog_count)
651 dev_dbg(priv->dev, "%s: watchdog count: %d\n",
652 __func__, wdog_count);
653
654 /* Fall through to handle critical interrupts if any */
655 }
656 }
657
658 for (i = 0; i < priv->num_sensors; i++) {
659 const struct tsens_sensor *s = &priv->sensor[i];
660 u32 hw_id = s->hw_id;
661
662 if (!s->tzd)
663 continue;
664 if (!tsens_threshold_violated(priv, hw_id, &d))
665 continue;
666 ret = get_temp_tsens_valid(s, &temp);
667 if (ret) {
668 dev_err(priv->dev, "[%u] %s: error reading sensor\n",
669 hw_id, __func__);
670 continue;
671 }
672
673 tsens_read_irq_state(priv, hw_id, s, &d);
674 if (d.crit_viol &&
675 !masked_irq(hw_id, d.crit_irq_mask, tsens_version(priv))) {
676 /* Mask critical interrupts, unused on Linux */
677 tsens_set_interrupt(priv, hw_id, CRITICAL, false);
678 }
679 }
680
681 return IRQ_HANDLED;
682 }
683
684 /**
685 * tsens_irq_thread - Threaded interrupt handler for uplow interrupts
686 * @irq: irq number
687 * @data: tsens controller private data
688 *
689 * Check all sensors to find ones that violated their threshold limits. If the
690 * temperature is still outside the limits, call thermal_zone_device_update() to
691 * update the thresholds, else re-enable the interrupts.
692 *
693 * The level-triggered interrupt might deassert if the temperature returned to
694 * within the threshold limits by the time the handler got scheduled. We
695 * consider the irq to have been handled in that case.
696 *
697 * Return: IRQ_HANDLED
698 */
tsens_irq_thread(int irq,void * data)699 static irqreturn_t tsens_irq_thread(int irq, void *data)
700 {
701 struct tsens_priv *priv = data;
702 struct tsens_irq_data d;
703 int i;
704
705 for (i = 0; i < priv->num_sensors; i++) {
706 const struct tsens_sensor *s = &priv->sensor[i];
707 u32 hw_id = s->hw_id;
708
709 if (!s->tzd)
710 continue;
711 if (!tsens_threshold_violated(priv, hw_id, &d))
712 continue;
713
714 thermal_zone_device_update(s->tzd, THERMAL_EVENT_UNSPECIFIED);
715
716 if (tsens_version(priv) < VER_0_1) {
717 /* Constraint: There is only 1 interrupt control register for all
718 * 11 temperature sensor. So monitoring more than 1 sensor based
719 * on interrupts will yield inconsistent result. To overcome this
720 * issue we will monitor only sensor 0 which is the master sensor.
721 */
722 break;
723 }
724 }
725
726 return IRQ_HANDLED;
727 }
728
729 /**
730 * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
731 * @irq: irq number
732 * @data: tsens controller private data
733 *
734 * Handle the combined interrupt as if it were 2 separate interrupts, so call the
735 * critical handler first and then the up/low one.
736 *
737 * Return: IRQ_HANDLED
738 */
tsens_combined_irq_thread(int irq,void * data)739 static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
740 {
741 irqreturn_t ret;
742
743 ret = tsens_critical_irq_thread(irq, data);
744 if (ret != IRQ_HANDLED)
745 return ret;
746
747 return tsens_irq_thread(irq, data);
748 }
749
tsens_set_trips(struct thermal_zone_device * tz,int low,int high)750 static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
751 {
752 struct tsens_sensor *s = thermal_zone_device_priv(tz);
753 struct tsens_priv *priv = s->priv;
754 struct device *dev = priv->dev;
755 struct tsens_irq_data d;
756 unsigned long flags;
757 int high_val, low_val, cl_high, cl_low;
758 u32 hw_id = s->hw_id;
759
760 if (tsens_version(priv) < VER_0_1) {
761 /* Pre v0.1 IP had a single register for each type of interrupt
762 * and thresholds
763 */
764 hw_id = 0;
765 }
766
767 dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
768 hw_id, __func__, low, high);
769
770 cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
771 cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
772
773 high_val = tsens_mC_to_hw(s, cl_high);
774 low_val = tsens_mC_to_hw(s, cl_low);
775
776 spin_lock_irqsave(&priv->ul_lock, flags);
777
778 tsens_read_irq_state(priv, hw_id, s, &d);
779
780 /* Write the new thresholds and clear the status */
781 regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val);
782 regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val);
783 tsens_set_interrupt(priv, hw_id, LOWER, true);
784 tsens_set_interrupt(priv, hw_id, UPPER, true);
785
786 spin_unlock_irqrestore(&priv->ul_lock, flags);
787
788 dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n",
789 hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high);
790
791 return 0;
792 }
793
tsens_enable_irq(struct tsens_priv * priv)794 static int tsens_enable_irq(struct tsens_priv *priv)
795 {
796 int ret;
797 int val = tsens_version(priv) >= VER_2_X ? 7 : 1;
798
799 ret = regmap_field_write(priv->rf[INT_EN], val);
800 if (ret < 0)
801 dev_err(priv->dev, "%s: failed to enable interrupts\n",
802 __func__);
803
804 return ret;
805 }
806
tsens_disable_irq(struct tsens_priv * priv)807 static void tsens_disable_irq(struct tsens_priv *priv)
808 {
809 regmap_field_write(priv->rf[INT_EN], 0);
810 }
811
get_temp_tsens_valid(const struct tsens_sensor * s,int * temp)812 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp)
813 {
814 int hw_id = s->hw_id;
815 u32 temp_idx = LAST_TEMP_0 + hw_id;
816 int ret;
817
818 ret = tsens_read_temp(s, temp_idx, temp);
819 if (!ret)
820 *temp = tsens_hw_to_mC(s, *temp);
821
822 return ret;
823 }
824
get_temp_common(const struct tsens_sensor * s,int * temp)825 int get_temp_common(const struct tsens_sensor *s, int *temp)
826 {
827 struct tsens_priv *priv = s->priv;
828 int hw_id = s->hw_id;
829 int last_temp = 0, ret, trdy;
830 unsigned long timeout;
831
832 timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
833 do {
834 if (tsens_version(priv) == VER_0) {
835 ret = regmap_field_read(priv->rf[TRDY], &trdy);
836 if (ret)
837 return ret;
838 if (!trdy)
839 continue;
840 }
841
842 ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
843 if (ret)
844 return ret;
845
846 *temp = code_to_degc(last_temp, s) * 1000;
847
848 return 0;
849 } while (time_before(jiffies, timeout));
850
851 return -ETIMEDOUT;
852 }
853
854 #ifdef CONFIG_DEBUG_FS
dbg_sensors_show(struct seq_file * s,void * data)855 static int dbg_sensors_show(struct seq_file *s, void *data)
856 {
857 struct platform_device *pdev = s->private;
858 struct tsens_priv *priv = platform_get_drvdata(pdev);
859 int i;
860
861 seq_printf(s, "max: %2d\nnum: %2d\n\n",
862 priv->feat->max_sensors, priv->num_sensors);
863
864 seq_puts(s, " id slope offset\n--------------------------\n");
865 for (i = 0; i < priv->num_sensors; i++) {
866 seq_printf(s, "%8d %8d %8d\n", priv->sensor[i].hw_id,
867 priv->sensor[i].slope, priv->sensor[i].offset);
868 }
869
870 return 0;
871 }
872
dbg_version_show(struct seq_file * s,void * data)873 static int dbg_version_show(struct seq_file *s, void *data)
874 {
875 struct platform_device *pdev = s->private;
876 struct tsens_priv *priv = platform_get_drvdata(pdev);
877 u32 maj_ver, min_ver, step_ver;
878 int ret;
879
880 if (tsens_version(priv) > VER_0_1) {
881 ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver);
882 if (ret)
883 return ret;
884 ret = regmap_field_read(priv->rf[VER_MINOR], &min_ver);
885 if (ret)
886 return ret;
887 ret = regmap_field_read(priv->rf[VER_STEP], &step_ver);
888 if (ret)
889 return ret;
890 seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
891 } else {
892 seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
893 }
894
895 return 0;
896 }
897
898 DEFINE_SHOW_ATTRIBUTE(dbg_version);
899 DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
900
tsens_debug_init(struct platform_device * pdev)901 static void tsens_debug_init(struct platform_device *pdev)
902 {
903 struct tsens_priv *priv = platform_get_drvdata(pdev);
904
905 priv->debug_root = debugfs_lookup("tsens", NULL);
906 if (!priv->debug_root)
907 priv->debug_root = debugfs_create_dir("tsens", NULL);
908
909 /* A directory for each instance of the TSENS IP */
910 priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
911 debugfs_create_file("version", 0444, priv->debug, pdev, &dbg_version_fops);
912 debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
913 }
914 #else
tsens_debug_init(struct platform_device * pdev)915 static inline void tsens_debug_init(struct platform_device *pdev) {}
916 #endif
917
918 static const struct regmap_config tsens_config = {
919 .name = "tm",
920 .reg_bits = 32,
921 .val_bits = 32,
922 .reg_stride = 4,
923 };
924
925 static const struct regmap_config tsens_srot_config = {
926 .name = "srot",
927 .reg_bits = 32,
928 .val_bits = 32,
929 .reg_stride = 4,
930 };
931
init_common(struct tsens_priv * priv)932 int __init init_common(struct tsens_priv *priv)
933 {
934 void __iomem *tm_base, *srot_base;
935 struct device *dev = priv->dev;
936 u32 ver_minor;
937 struct resource *res;
938 u32 enabled;
939 int ret, i, j;
940 struct platform_device *op = of_find_device_by_node(priv->dev->of_node);
941
942 if (!op)
943 return -EINVAL;
944
945 if (op->num_resources > 1) {
946 /* DT with separate SROT and TM address space */
947 priv->tm_offset = 0;
948 res = platform_get_resource(op, IORESOURCE_MEM, 1);
949 srot_base = devm_ioremap_resource(dev, res);
950 if (IS_ERR(srot_base)) {
951 ret = PTR_ERR(srot_base);
952 goto err_put_device;
953 }
954
955 priv->srot_map = devm_regmap_init_mmio(dev, srot_base,
956 &tsens_srot_config);
957 if (IS_ERR(priv->srot_map)) {
958 ret = PTR_ERR(priv->srot_map);
959 goto err_put_device;
960 }
961 } else {
962 /* old DTs where SROT and TM were in a contiguous 2K block */
963 priv->tm_offset = 0x1000;
964 }
965
966 if (tsens_version(priv) >= VER_0_1) {
967 res = platform_get_resource(op, IORESOURCE_MEM, 0);
968 tm_base = devm_ioremap_resource(dev, res);
969 if (IS_ERR(tm_base)) {
970 ret = PTR_ERR(tm_base);
971 goto err_put_device;
972 }
973
974 priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
975 } else { /* VER_0 share the same gcc regs using a syscon */
976 struct device *parent = priv->dev->parent;
977
978 if (parent)
979 priv->tm_map = syscon_node_to_regmap(parent->of_node);
980 }
981
982 if (IS_ERR_OR_NULL(priv->tm_map)) {
983 if (!priv->tm_map)
984 ret = -ENODEV;
985 else
986 ret = PTR_ERR(priv->tm_map);
987 goto err_put_device;
988 }
989
990 /* VER_0 have only tm_map */
991 if (!priv->srot_map)
992 priv->srot_map = priv->tm_map;
993
994 if (tsens_version(priv) > VER_0_1) {
995 for (i = VER_MAJOR; i <= VER_STEP; i++) {
996 priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,
997 priv->fields[i]);
998 if (IS_ERR(priv->rf[i])) {
999 ret = PTR_ERR(priv->rf[i]);
1000 goto err_put_device;
1001 }
1002 }
1003 ret = regmap_field_read(priv->rf[VER_MINOR], &ver_minor);
1004 if (ret)
1005 goto err_put_device;
1006 }
1007
1008 priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map,
1009 priv->fields[TSENS_EN]);
1010 if (IS_ERR(priv->rf[TSENS_EN])) {
1011 ret = PTR_ERR(priv->rf[TSENS_EN]);
1012 goto err_put_device;
1013 }
1014 /* in VER_0 TSENS need to be explicitly enabled */
1015 if (tsens_version(priv) == VER_0)
1016 regmap_field_write(priv->rf[TSENS_EN], 1);
1017
1018 ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
1019 if (ret)
1020 goto err_put_device;
1021 if (!enabled) {
1022 switch (tsens_version(priv)) {
1023 case VER_1_X_NO_RPM:
1024 case VER_2_X_NO_RPM:
1025 break;
1026 default:
1027 dev_err(dev, "%s: device not enabled\n", __func__);
1028 ret = -ENODEV;
1029 goto err_put_device;
1030 }
1031 }
1032
1033 priv->rf[SENSOR_EN] = devm_regmap_field_alloc(dev, priv->srot_map,
1034 priv->fields[SENSOR_EN]);
1035 if (IS_ERR(priv->rf[SENSOR_EN])) {
1036 ret = PTR_ERR(priv->rf[SENSOR_EN]);
1037 goto err_put_device;
1038 }
1039 priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map,
1040 priv->fields[INT_EN]);
1041 if (IS_ERR(priv->rf[INT_EN])) {
1042 ret = PTR_ERR(priv->rf[INT_EN]);
1043 goto err_put_device;
1044 }
1045
1046 priv->rf[TSENS_SW_RST] =
1047 devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]);
1048 if (IS_ERR(priv->rf[TSENS_SW_RST])) {
1049 ret = PTR_ERR(priv->rf[TSENS_SW_RST]);
1050 goto err_put_device;
1051 }
1052
1053 priv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]);
1054 if (IS_ERR(priv->rf[TRDY])) {
1055 ret = PTR_ERR(priv->rf[TRDY]);
1056 goto err_put_device;
1057 }
1058
1059 /* This loop might need changes if enum regfield_ids is reordered */
1060 for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {
1061 for (i = 0; i < priv->feat->max_sensors; i++) {
1062 int idx = j + i;
1063
1064 priv->rf[idx] = devm_regmap_field_alloc(dev,
1065 priv->tm_map,
1066 priv->fields[idx]);
1067 if (IS_ERR(priv->rf[idx])) {
1068 ret = PTR_ERR(priv->rf[idx]);
1069 goto err_put_device;
1070 }
1071 }
1072 }
1073
1074 if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) {
1075 /* Loop might need changes if enum regfield_ids is reordered */
1076 for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) {
1077 for (i = 0; i < priv->feat->max_sensors; i++) {
1078 int idx = j + i;
1079
1080 priv->rf[idx] =
1081 devm_regmap_field_alloc(dev,
1082 priv->tm_map,
1083 priv->fields[idx]);
1084 if (IS_ERR(priv->rf[idx])) {
1085 ret = PTR_ERR(priv->rf[idx]);
1086 goto err_put_device;
1087 }
1088 }
1089 }
1090 }
1091
1092 if (tsens_version(priv) >= VER_2_X && ver_minor > 2) {
1093 /* Watchdog is present only on v2.3+ */
1094 priv->feat->has_watchdog = 1;
1095 for (i = WDOG_BARK_STATUS; i <= CC_MON_MASK; i++) {
1096 priv->rf[i] = devm_regmap_field_alloc(dev, priv->tm_map,
1097 priv->fields[i]);
1098 if (IS_ERR(priv->rf[i])) {
1099 ret = PTR_ERR(priv->rf[i]);
1100 goto err_put_device;
1101 }
1102 }
1103 /*
1104 * Watchdog is already enabled, unmask the bark.
1105 * Disable cycle completion monitoring
1106 */
1107 regmap_field_write(priv->rf[WDOG_BARK_MASK], 0);
1108 regmap_field_write(priv->rf[CC_MON_MASK], 1);
1109 }
1110
1111 spin_lock_init(&priv->ul_lock);
1112
1113 /* VER_0 interrupt doesn't need to be enabled */
1114 if (tsens_version(priv) >= VER_0_1)
1115 tsens_enable_irq(priv);
1116
1117 err_put_device:
1118 put_device(&op->dev);
1119 return ret;
1120 }
1121
tsens_get_temp(struct thermal_zone_device * tz,int * temp)1122 static int tsens_get_temp(struct thermal_zone_device *tz, int *temp)
1123 {
1124 struct tsens_sensor *s = thermal_zone_device_priv(tz);
1125 struct tsens_priv *priv = s->priv;
1126
1127 return priv->ops->get_temp(s, temp);
1128 }
1129
tsens_suspend(struct device * dev)1130 static int __maybe_unused tsens_suspend(struct device *dev)
1131 {
1132 int ret = 0;
1133 struct tsens_priv *priv = dev_get_drvdata(dev);
1134
1135 if (priv->ops && priv->ops->suspend) {
1136 ret = priv->ops->suspend(priv);
1137 if (ret)
1138 return ret;
1139 }
1140
1141 return tsens_suspend_common(priv);
1142 }
1143
tsens_resume(struct device * dev)1144 static int __maybe_unused tsens_resume(struct device *dev)
1145 {
1146 int ret = 0;
1147 struct tsens_priv *priv = dev_get_drvdata(dev);
1148
1149 if (priv->ops && priv->ops->resume) {
1150 ret = priv->ops->resume(priv);
1151 if (ret)
1152 return ret;
1153 }
1154
1155 return tsens_resume_common(priv);
1156 }
1157
1158 static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
1159
1160 static const struct of_device_id tsens_table[] = {
1161 {
1162 .compatible = "qcom,ipq5018-tsens",
1163 .data = &data_ipq5018,
1164 }, {
1165 .compatible = "qcom,ipq5332-tsens",
1166 .data = &data_ipq5332,
1167 }, {
1168 .compatible = "qcom,ipq5424-tsens",
1169 .data = &data_ipq5424,
1170 }, {
1171 .compatible = "qcom,ipq8064-tsens",
1172 .data = &data_8960,
1173 }, {
1174 .compatible = "qcom,ipq8074-tsens",
1175 .data = &data_ipq8074,
1176 }, {
1177 .compatible = "qcom,mdm9607-tsens",
1178 .data = &data_9607,
1179 }, {
1180 .compatible = "qcom,msm8226-tsens",
1181 .data = &data_8226,
1182 }, {
1183 .compatible = "qcom,msm8909-tsens",
1184 .data = &data_8909,
1185 }, {
1186 .compatible = "qcom,msm8916-tsens",
1187 .data = &data_8916,
1188 }, {
1189 .compatible = "qcom,msm8937-tsens",
1190 .data = &data_8937,
1191 }, {
1192 .compatible = "qcom,msm8939-tsens",
1193 .data = &data_8939,
1194 }, {
1195 .compatible = "qcom,msm8956-tsens",
1196 .data = &data_8956,
1197 }, {
1198 .compatible = "qcom,msm8960-tsens",
1199 .data = &data_8960,
1200 }, {
1201 .compatible = "qcom,msm8974-tsens",
1202 .data = &data_8974,
1203 }, {
1204 .compatible = "qcom,msm8976-tsens",
1205 .data = &data_8976,
1206 }, {
1207 .compatible = "qcom,msm8996-tsens",
1208 .data = &data_8996,
1209 }, {
1210 .compatible = "qcom,tsens-v1",
1211 .data = &data_tsens_v1,
1212 }, {
1213 .compatible = "qcom,tsens-v2",
1214 .data = &data_tsens_v2,
1215 }, {
1216 .compatible = "qcom,sa8775p-tsens",
1217 .data = &data_automotive_v2,
1218 }, {
1219 .compatible = "qcom,sa8255p-tsens",
1220 .data = &data_automotive_v2,
1221 },
1222 {}
1223 };
1224 MODULE_DEVICE_TABLE(of, tsens_table);
1225
1226 static const struct thermal_zone_device_ops tsens_of_ops = {
1227 .get_temp = tsens_get_temp,
1228 .set_trips = tsens_set_trips,
1229 };
1230
tsens_register_irq(struct tsens_priv * priv,char * irqname,irq_handler_t thread_fn,int * irq_num)1231 static int tsens_register_irq(struct tsens_priv *priv, char *irqname,
1232 irq_handler_t thread_fn, int *irq_num)
1233 {
1234 struct platform_device *pdev;
1235 int ret, irq;
1236
1237 pdev = of_find_device_by_node(priv->dev->of_node);
1238 if (!pdev)
1239 return -ENODEV;
1240
1241 irq = platform_get_irq_byname(pdev, irqname);
1242 if (irq < 0) {
1243 ret = irq;
1244 /* For old DTs with no IRQ defined */
1245 if (irq == -ENXIO)
1246 ret = 0;
1247 } else {
1248 /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */
1249 if (tsens_version(priv) == VER_0)
1250 ret = devm_request_threaded_irq(&pdev->dev, irq,
1251 thread_fn, NULL,
1252 IRQF_TRIGGER_RISING,
1253 dev_name(&pdev->dev),
1254 priv);
1255 else
1256 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1257 thread_fn, IRQF_ONESHOT,
1258 dev_name(&pdev->dev),
1259 priv);
1260
1261 if (!ret)
1262 *irq_num = irq;
1263 }
1264
1265 put_device(&pdev->dev);
1266 return ret;
1267 }
1268
1269 #ifdef CONFIG_SUSPEND
tsens_reinit(struct tsens_priv * priv)1270 static int tsens_reinit(struct tsens_priv *priv)
1271 {
1272 if (tsens_version(priv) >= VER_2_X) {
1273 /*
1274 * Re-enable the watchdog, unmask the bark.
1275 * Disable cycle completion monitoring
1276 */
1277 if (priv->feat->has_watchdog) {
1278 regmap_field_write(priv->rf[WDOG_BARK_MASK], 0);
1279 regmap_field_write(priv->rf[CC_MON_MASK], 1);
1280 }
1281
1282 /* Re-enable interrupts */
1283 tsens_enable_irq(priv);
1284 }
1285
1286 return 0;
1287 }
1288
tsens_suspend_common(struct tsens_priv * priv)1289 int tsens_suspend_common(struct tsens_priv *priv)
1290 {
1291 if (!device_may_wakeup(priv->dev))
1292 return 0;
1293
1294 if (priv->feat->combo_int)
1295 enable_irq_wake(priv->combined_irq);
1296 else {
1297 enable_irq_wake(priv->uplow_irq);
1298 if (priv->feat->crit_int)
1299 enable_irq_wake(priv->crit_irq);
1300 }
1301
1302 return 0;
1303 }
1304
tsens_resume_common(struct tsens_priv * priv)1305 int tsens_resume_common(struct tsens_priv *priv)
1306 {
1307 if (pm_suspend_target_state == PM_SUSPEND_MEM)
1308 tsens_reinit(priv);
1309
1310 if (!device_may_wakeup(priv->dev))
1311 return 0;
1312
1313 if (priv->feat->combo_int)
1314 disable_irq_wake(priv->combined_irq);
1315 else {
1316 disable_irq_wake(priv->uplow_irq);
1317 if (priv->feat->crit_int)
1318 disable_irq_wake(priv->crit_irq);
1319 }
1320
1321 return 0;
1322 }
1323
1324 #endif /* !CONFIG_SUSPEND */
1325
tsens_register(struct tsens_priv * priv)1326 static int tsens_register(struct tsens_priv *priv)
1327 {
1328 int i, ret;
1329 struct thermal_zone_device *tzd;
1330
1331 for (i = 0; i < priv->num_sensors; i++) {
1332 priv->sensor[i].priv = priv;
1333 tzd = devm_thermal_of_zone_register(priv->dev, priv->sensor[i].hw_id,
1334 &priv->sensor[i],
1335 &tsens_of_ops);
1336 if (IS_ERR(tzd))
1337 continue;
1338 priv->sensor[i].tzd = tzd;
1339 if (priv->ops->enable)
1340 priv->ops->enable(priv, i);
1341
1342 devm_thermal_add_hwmon_sysfs(priv->dev, tzd);
1343 }
1344
1345 /* VER_0 require to set MIN and MAX THRESH
1346 * These 2 regs are set using the:
1347 * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C
1348 * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C
1349 */
1350 if (tsens_version(priv) < VER_0_1) {
1351 regmap_field_write(priv->rf[CRIT_THRESH_0],
1352 tsens_mC_to_hw(priv->sensor, 120000));
1353
1354 regmap_field_write(priv->rf[CRIT_THRESH_1],
1355 tsens_mC_to_hw(priv->sensor, 0));
1356 }
1357
1358 if (priv->feat->combo_int) {
1359 ret = tsens_register_irq(priv, "combined",
1360 tsens_combined_irq_thread, &priv->combined_irq);
1361 } else {
1362 ret = tsens_register_irq(priv, "uplow", tsens_irq_thread,
1363 &priv->uplow_irq);
1364 if (ret < 0)
1365 return ret;
1366
1367 if (priv->feat->crit_int) {
1368 ret = tsens_register_irq(priv, "critical",
1369 tsens_critical_irq_thread,
1370 &priv->crit_irq);
1371 }
1372 }
1373
1374 return ret;
1375 }
1376
tsens_probe(struct platform_device * pdev)1377 static int tsens_probe(struct platform_device *pdev)
1378 {
1379 int ret, i;
1380 struct device *dev;
1381 struct device_node *np;
1382 struct tsens_priv *priv;
1383 const struct tsens_plat_data *data;
1384 const struct of_device_id *id;
1385 u32 num_sensors;
1386
1387 if (pdev->dev.of_node)
1388 dev = &pdev->dev;
1389 else
1390 dev = pdev->dev.parent;
1391
1392 np = dev->of_node;
1393
1394 id = of_match_node(tsens_table, np);
1395 if (id)
1396 data = id->data;
1397 else
1398 data = &data_8960;
1399
1400 num_sensors = data->num_sensors;
1401
1402 if (np)
1403 of_property_read_u32(np, "#qcom,sensors", &num_sensors);
1404
1405 if (num_sensors <= 0) {
1406 dev_err(dev, "%s: invalid number of sensors\n", __func__);
1407 return -EINVAL;
1408 }
1409
1410 priv = devm_kzalloc(dev,
1411 struct_size(priv, sensor, num_sensors),
1412 GFP_KERNEL);
1413 if (!priv)
1414 return -ENOMEM;
1415
1416 priv->dev = dev;
1417 priv->num_sensors = num_sensors;
1418 priv->ops = data->ops;
1419 for (i = 0; i < priv->num_sensors; i++) {
1420 if (data->hw_ids)
1421 priv->sensor[i].hw_id = data->hw_ids[i];
1422 else
1423 priv->sensor[i].hw_id = i;
1424 }
1425 priv->feat = data->feat;
1426 priv->fields = data->fields;
1427
1428 platform_set_drvdata(pdev, priv);
1429
1430 device_init_wakeup(dev, !data->no_irq_wake);
1431
1432 if (!priv->ops || !priv->ops->init || !priv->ops->get_temp)
1433 return -EINVAL;
1434
1435 ret = priv->ops->init(priv);
1436 if (ret < 0) {
1437 dev_err(dev, "%s: init failed\n", __func__);
1438 return ret;
1439 }
1440
1441 if (priv->ops->calibrate) {
1442 ret = priv->ops->calibrate(priv);
1443 if (ret < 0)
1444 return dev_err_probe(dev, ret, "%s: calibration failed\n",
1445 __func__);
1446 }
1447
1448 ret = tsens_register(priv);
1449 if (!ret)
1450 tsens_debug_init(pdev);
1451
1452 return ret;
1453 }
1454
tsens_remove(struct platform_device * pdev)1455 static void tsens_remove(struct platform_device *pdev)
1456 {
1457 struct tsens_priv *priv = platform_get_drvdata(pdev);
1458
1459 debugfs_remove_recursive(priv->debug_root);
1460 tsens_disable_irq(priv);
1461 if (priv->ops->disable)
1462 priv->ops->disable(priv);
1463 }
1464
1465 static struct platform_driver tsens_driver = {
1466 .probe = tsens_probe,
1467 .remove = tsens_remove,
1468 .driver = {
1469 .name = "qcom-tsens",
1470 .pm = &tsens_pm_ops,
1471 .of_match_table = tsens_table,
1472 },
1473 };
1474 module_platform_driver(tsens_driver);
1475
1476 MODULE_LICENSE("GPL v2");
1477 MODULE_DESCRIPTION("QCOM Temperature Sensor driver");
1478 MODULE_ALIAS("platform:qcom-tsens");
1479