1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2023 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "debug.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 11 static const struct rtw89_ccx_regs rtw89_ccx_regs_be = { 12 .setting_addr = R_CCX, 13 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1, 14 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 15 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 16 .en_mask = B_CCX_EN_MSK, 17 .ifs_cnt_addr = R_IFS_COUNTER, 18 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 19 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 20 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 21 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 22 .ifs_t1_addr = R_IFS_T1, 23 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 24 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 25 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 26 .ifs_t2_addr = R_IFS_T2, 27 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 28 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 29 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 30 .ifs_t3_addr = R_IFS_T3, 31 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 32 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 33 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 34 .ifs_t4_addr = R_IFS_T4, 35 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 36 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 37 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 38 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_V1, 39 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 40 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 41 .ifs_clm_cca_addr = R_IFS_CLM_CCA_V1, 42 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 43 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 44 .ifs_clm_fa_addr = R_IFS_CLM_FA_V1, 45 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 46 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 47 .ifs_his_addr = R_IFS_HIS_V1, 48 .ifs_his_addr2 = R_IFS_HIS_V1, 49 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 50 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 51 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 52 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 53 .ifs_avg_l_addr = R_IFS_AVG_L_V1, 54 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 55 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 56 .ifs_avg_h_addr = R_IFS_AVG_H_V1, 57 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 58 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 59 .ifs_cca_l_addr = R_IFS_CCA_L_V1, 60 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 61 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 62 .ifs_cca_h_addr = R_IFS_CCA_H_V1, 63 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 64 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 65 .ifs_total_addr = R_IFSCNT_V1, 66 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 67 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 68 .nhm = R_NHM_BE, 69 .nhm_ready = B_NHM_READY_BE_MSK, 70 .nhm_config = R_NHM_CFG, 71 .nhm_period_mask = B_NHM_PERIOD_MSK, 72 .nhm_unit_mask = B_NHM_COUNTER_MSK, 73 .nhm_include_cca_mask = B_NHM_INCLUDE_CCA_MSK, 74 .nhm_en_mask = B_NHM_EN_MSK, 75 .nhm_method = R_NHM_TH9, 76 .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK, 77 .edcca_clm_rdy = R_CLM_EDCCA_RDY_V1, 78 .edcca_clm_rdy_mask = B_CLM_EDCCA_RDY, 79 .edcca_clm_cnt = R_CLM_EDCCA_RESULT_V1, 80 .edcca_clm_cnt_mask = B_CLM_EDCCA_RESULT, 81 }; 82 83 static const struct rtw89_ccx_regs rtw89_ccx_regs_be_v1 = { 84 .setting_addr = R_CCX_BE4, 85 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1, 86 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 87 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 88 .en_mask = B_CCX_EN_MSK, 89 .ifs_cnt_addr = R_IFS_COUNTER_BE4, 90 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 91 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 92 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 93 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 94 .ifs_t1_addr = R_IFS_T1_BE4, 95 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 96 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 97 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 98 .ifs_t2_addr = R_IFS_T2_BE4, 99 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 100 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 101 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 102 .ifs_t3_addr = R_IFS_T3_BE4, 103 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 104 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 105 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 106 .ifs_t4_addr = R_IFS_T4_BE4, 107 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 108 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 109 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 110 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_BE4, 111 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 112 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 113 .ifs_clm_cca_addr = R_IFS_CLM_CCA_BE4, 114 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 115 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 116 .ifs_clm_fa_addr = R_IFS_CLM_FA_BE4, 117 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 118 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 119 .ifs_his_addr = R_IFS_T1_HIS_BE4, 120 .ifs_his_addr2 = R_IFS_T3_HIS_BE4, /* for 3/4 */ 121 .ifs_t4_his_mask = B_IFS_T4_HIS_BE4, 122 .ifs_t3_his_mask = B_IFS_T3_HIS_BE4, 123 .ifs_t2_his_mask = B_IFS_T2_HIS_BE4, 124 .ifs_t1_his_mask = B_IFS_T1_HIS_BE4, 125 .ifs_avg_l_addr = R_IFS_T1_AVG_BE4, 126 .ifs_t2_avg_mask = B_IFS_T2_AVG_BE4, 127 .ifs_t1_avg_mask = B_IFS_T1_AVG_BE4, 128 .ifs_avg_h_addr = R_IFS_T3_AVG_BE4, 129 .ifs_t4_avg_mask = B_IFS_T4_AVG_BE4, 130 .ifs_t3_avg_mask = B_IFS_T3_AVG_BE4, 131 .ifs_cca_l_addr = R_IFS_T1_CLM_BE4, 132 .ifs_t2_cca_mask = B_IFS_T2_CLM_BE4, 133 .ifs_t1_cca_mask = B_IFS_T1_CLM_BE4, 134 .ifs_cca_h_addr = R_IFS_T3_CLM_BE4, 135 .ifs_t4_cca_mask = B_IFS_T4_CLM_BE4, 136 .ifs_t3_cca_mask = B_IFS_T3_CLM_BE4, 137 .ifs_total_addr = R_IFS_TOTAL_BE4, 138 .ifs_cnt_done_mask = B_IFS_CNT_DONE_BE4, 139 .ifs_total_mask = B_IFS_TOTAL_BE4, 140 .edcca_clm_rdy = R_CLM_EDCCA_RDY_BE4, 141 .edcca_clm_rdy_mask = B_CLM_EDCCA_RDY, 142 .edcca_clm_cnt = R_CLM_EDCCA_RESULT_BE4, 143 .edcca_clm_cnt_mask = B_CLM_EDCCA_RESULT, 144 }; 145 146 static const u32 rtw89_tx_info_reg_be[] = { 147 R_TX_INFO_0_0_COMB_V1, 148 R_TX_INFO_0_1_COMB_V1, 149 R_TX_INFO_1_0_COMB_V1, 150 R_TX_INFO_1_1_COMB_V1, 151 R_TX_INFO_2_0_COMB_V1, 152 R_TX_INFO_2_1_COMB_V1 153 }; 154 155 static const u32 rtw89_tx_common_ctrl_reg_be[] = { 156 R_TX_COMMON_CTRL_0_0_COMB_V1, 157 R_TX_COMMON_CTRL_0_1_COMB_V1 158 }; 159 160 static const struct rtw89_reg_def rtw89_txpwr_be[] = { 161 {.addr = R_PATH0_TXPWR_V1, .mask = B_PATH0_TXPWR}, 162 {.addr = R_PATH1_TXPWR_V1, .mask = B_PATH1_TXPWR} 163 }; 164 165 static const struct rtw89_physts_regs rtw89_physts_regs_be = { 166 .setting_addr = R_PLCP_HISTOGRAM, 167 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 168 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 169 .mac_phy_intf_sel = {R_INTF_R_INTF_RPT_SEL, B_INTF_R_INTF_RPT_SEL}, 170 .txpwr = rtw89_txpwr_be, 171 .tx_info = RTW89_REGS_DEF(rtw89_tx_info_reg_be), 172 .tx_common_ctrl = RTW89_REGS_DEF(rtw89_tx_common_ctrl_reg_be), 173 }; 174 175 static const u32 rtw89_tx_info_reg_be_v1[] = { 176 R_TX_INFO_0_0_COMB_BE4, 177 R_TX_INFO_0_1_COMB_BE4, 178 R_TX_INFO_1_0_COMB_BE4, 179 R_TX_INFO_1_1_COMB_BE4, 180 R_TX_INFO_2_0_COMB_BE4, 181 R_TX_INFO_2_1_COMB_BE4 182 }; 183 184 static const u32 rtw89_tx_common_ctrl_reg_be_v1[] = { 185 R_TX_COMMON_CTRL_0_0_COMB_BE4, 186 R_TX_COMMON_CTRL_0_1_COMB_BE4 187 }; 188 189 static const struct rtw89_reg_def rtw89_txpwr_be_v1[] = { 190 {.addr = R_PATH0_TXPWR_BE4, .mask = B_PATH0_TXPWR}, 191 {.addr = R_PATH1_TXPWR_BE4, .mask = B_PATH1_TXPWR} 192 }; 193 194 static const struct rtw89_physts_regs rtw89_physts_regs_be_v1 = { 195 .setting_addr = R_PLCP_HISTOGRAM_BE_V1, 196 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 197 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 198 .mac_phy_intf_sel = {R_INTF_R_INTF_RPT_SEL_BE4, B_INTF_R_INTF_RPT_SEL}, 199 .txpwr = rtw89_txpwr_be_v1, 200 .tx_info = RTW89_REGS_DEF(rtw89_tx_info_reg_be_v1), 201 .tx_common_ctrl = RTW89_REGS_DEF(rtw89_tx_common_ctrl_reg_be_v1), 202 }; 203 204 static const struct rtw89_cfo_regs rtw89_cfo_regs_be = { 205 .comp = R_DCFO_WEIGHT_BE, 206 .weighting_mask = B_DCFO_WEIGHT_MSK_BE, 207 .comp_seg0 = R_DCFO_OPT_BE, 208 .valid_0_mask = B_DCFO_OPT_EN_BE, 209 }; 210 211 static const struct rtw89_cfo_regs rtw89_cfo_regs_be_v1 = { 212 .comp = R_DCFO_WEIGHT_BE_V1, 213 .weighting_mask = B_DCFO_WEIGHT_MSK_BE, 214 .comp_seg0 = R_DCFO_OPT_BE_V1, 215 .valid_0_mask = B_DCFO_OPT_EN_BE, 216 }; 217 218 static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be = { 219 .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE, 220 .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE, 221 }; 222 223 static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be_v1 = { 224 .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE_V1, 225 .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE_V1, 226 }; 227 228 static const struct rtw89_nctl_regs rtw89_nctl_regs_be = { 229 .cfg = R_NCTL_CFG, 230 .rw = R_NCTL_RW, 231 }; 232 233 static const struct rtw89_nctl_regs rtw89_nctl_regs_be_v1 = { 234 .cfg = R_NCTL_CFG_BE4, 235 .rw = R_NCTL_RW_BE4, 236 }; 237 238 static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr) 239 { 240 u32 phy_page = addr >> 8; 241 u32 ofst = 0; 242 243 if ((phy_page >= 0x4 && phy_page <= 0xF) || 244 (phy_page >= 0x20 && phy_page <= 0x2B) || 245 (phy_page >= 0x40 && phy_page <= 0x4f) || 246 (phy_page >= 0x60 && phy_page <= 0x6f) || 247 (phy_page >= 0xE4 && phy_page <= 0xE5) || 248 (phy_page >= 0xE8 && phy_page <= 0xED)) 249 ofst = 0x1000; 250 else 251 ofst = 0x0; 252 253 return ofst; 254 } 255 256 static u32 rtw89_phy0_phy1_offset_be_v1(struct rtw89_dev *rtwdev, u32 addr) 257 { 258 u32 phy_page = addr >> 8; 259 u32 ofst = 0; 260 261 if ((phy_page >= 0x204 && phy_page <= 0x20F) || 262 (phy_page >= 0x220 && phy_page <= 0x22F) || 263 (phy_page >= 0x240 && phy_page <= 0x24f) || 264 (phy_page >= 0x260 && phy_page <= 0x26f) || 265 (phy_page >= 0x2C0 && phy_page <= 0x2C9) || 266 (phy_page >= 0x2E0 && phy_page <= 0x2E8) || 267 phy_page == 0x2EE) 268 ofst = 0x1000; 269 else 270 ofst = 0x0; 271 272 return ofst; 273 } 274 275 union rtw89_phy_bb_gain_arg_be { 276 u32 addr; 277 struct { 278 u8 type; 279 #define BB_GAIN_TYPE_SUB0_BE GENMASK(3, 0) 280 #define BB_GAIN_TYPE_SUB1_BE GENMASK(7, 4) 281 u8 path_bw; 282 #define BB_GAIN_PATH_BE GENMASK(3, 0) 283 #define BB_GAIN_BW_BE GENMASK(7, 4) 284 u8 gain_band; 285 u8 cfg_type; 286 } __packed; 287 } __packed; 288 289 static void 290 rtw89_phy_cfg_bb_gain_error_be(struct rtw89_dev *rtwdev, 291 union rtw89_phy_bb_gain_arg_be arg, u32 data) 292 { 293 struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be; 294 u8 bw_type = u8_get_bits(arg.path_bw, BB_GAIN_BW_BE); 295 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE); 296 u8 gband = arg.gain_band; 297 u8 type = arg.type; 298 int i; 299 300 switch (type) { 301 case 0: 302 for (i = 0; i < 4; i++, data >>= 8) 303 gain->lna_gain[gband][bw_type][path][i] = data & 0xff; 304 break; 305 case 1: 306 for (i = 4; i < 7; i++, data >>= 8) 307 gain->lna_gain[gband][bw_type][path][i] = data & 0xff; 308 break; 309 case 2: 310 for (i = 0; i < 2; i++, data >>= 8) 311 gain->tia_gain[gband][bw_type][path][i] = data & 0xff; 312 break; 313 default: 314 rtw89_warn(rtwdev, 315 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 316 arg.addr, data, type); 317 break; 318 } 319 } 320 321 static void 322 rtw89_phy_cfg_bb_rpl_ofst_be(struct rtw89_dev *rtwdev, 323 union rtw89_phy_bb_gain_arg_be arg, u32 data) 324 { 325 struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be; 326 u8 type_sub0 = u8_get_bits(arg.type, BB_GAIN_TYPE_SUB0_BE); 327 u8 type_sub1 = u8_get_bits(arg.type, BB_GAIN_TYPE_SUB1_BE); 328 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE); 329 u8 gband = arg.gain_band; 330 u8 ofst = 0; 331 int i; 332 333 switch (type_sub1) { 334 case RTW89_CMAC_BW_20M: 335 gain->rpl_ofst_20[gband][path][0] = (s8)data; 336 break; 337 case RTW89_CMAC_BW_40M: 338 for (i = 0; i < RTW89_BW20_SC_40M; i++, data >>= 8) 339 gain->rpl_ofst_40[gband][path][i] = data & 0xff; 340 break; 341 case RTW89_CMAC_BW_80M: 342 for (i = 0; i < RTW89_BW20_SC_80M; i++, data >>= 8) 343 gain->rpl_ofst_80[gband][path][i] = data & 0xff; 344 break; 345 case RTW89_CMAC_BW_160M: 346 if (type_sub0 == 0) 347 ofst = 0; 348 else 349 ofst = RTW89_BW20_SC_80M; 350 351 for (i = 0; i < RTW89_BW20_SC_80M; i++, data >>= 8) 352 gain->rpl_ofst_160[gband][path][i + ofst] = data & 0xff; 353 break; 354 default: 355 rtw89_warn(rtwdev, 356 "bb rpl ofst {0x%x:0x%x} with unknown type_sub1: %d\n", 357 arg.addr, data, type_sub1); 358 break; 359 } 360 } 361 362 static void 363 rtw89_phy_cfg_bb_gain_op1db_be(struct rtw89_dev *rtwdev, 364 union rtw89_phy_bb_gain_arg_be arg, u32 data) 365 { 366 struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be; 367 u8 bw_type = u8_get_bits(arg.path_bw, BB_GAIN_BW_BE); 368 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE); 369 u8 gband = arg.gain_band; 370 u8 type = arg.type; 371 int i; 372 373 switch (type) { 374 case 0: 375 for (i = 0; i < 4; i++, data >>= 8) 376 gain->lna_op1db[gband][bw_type][path][i] = data & 0xff; 377 break; 378 case 1: 379 for (i = 4; i < 7; i++, data >>= 8) 380 gain->lna_op1db[gband][bw_type][path][i] = data & 0xff; 381 break; 382 case 2: 383 for (i = 0; i < 4; i++, data >>= 8) 384 gain->tia_lna_op1db[gband][bw_type][path][i] = data & 0xff; 385 break; 386 case 3: 387 for (i = 4; i < 8; i++, data >>= 8) 388 gain->tia_lna_op1db[gband][bw_type][path][i] = data & 0xff; 389 break; 390 default: 391 rtw89_warn(rtwdev, 392 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 393 arg.addr, data, type); 394 break; 395 } 396 } 397 398 static void rtw89_phy_config_bb_gain_be(struct rtw89_dev *rtwdev, 399 const struct rtw89_reg2_def *reg, 400 enum rtw89_rf_path rf_path, 401 void *extra_data) 402 { 403 const struct rtw89_chip_info *chip = rtwdev->chip; 404 union rtw89_phy_bb_gain_arg_be arg = { .addr = reg->addr }; 405 struct rtw89_efuse *efuse = &rtwdev->efuse; 406 u8 bw_type = u8_get_bits(arg.path_bw, BB_GAIN_BW_BE); 407 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE); 408 409 if (bw_type >= RTW89_BB_BW_NR_BE) 410 return; 411 412 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR_BE) 413 return; 414 415 if (path >= chip->rf_path_num) 416 return; 417 418 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 419 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 420 return; 421 } 422 423 switch (arg.cfg_type) { 424 case 0: 425 rtw89_phy_cfg_bb_gain_error_be(rtwdev, arg, reg->data); 426 break; 427 case 1: 428 rtw89_phy_cfg_bb_rpl_ofst_be(rtwdev, arg, reg->data); 429 break; 430 case 2: 431 /* ignore BB gain bypass */ 432 break; 433 case 3: 434 rtw89_phy_cfg_bb_gain_op1db_be(rtwdev, arg, reg->data); 435 break; 436 case 15: 437 rtw89_phy_write32_idx(rtwdev, reg->addr & 0xFFFFF, MASKDWORD, 438 reg->data, RTW89_PHY_0); 439 break; 440 case 4: 441 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 442 if (efuse->rfe_type < 50) 443 break; 444 fallthrough; 445 default: 446 rtw89_warn(rtwdev, 447 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 448 arg.addr, reg->data, arg.cfg_type); 449 break; 450 } 451 } 452 453 static void rtw89_phy_preinit_rf_nctl_check_be(struct rtw89_dev *rtwdev) 454 { 455 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 456 const struct rtw89_nctl_regs *nctl = phy->nctl; 457 int poll; 458 u32 val; 459 460 rtw89_phy_write32(rtwdev, nctl->cfg, B_NCTL_CHK_EN); 461 462 for (poll = 0; poll < 10000; poll++) { 463 rtw89_phy_write32(rtwdev, nctl->rw, B_NCTL_CHECK); 464 465 fsleep(10); 466 467 val = rtw89_phy_read32(rtwdev, nctl->rw); 468 if (val == B_NCTL_CHECK) 469 return; 470 } 471 472 rtw89_warn(rtwdev, "NCTL INIT check 0x%x[2]TIMEOUT!\n", nctl->rw); 473 } 474 475 static void rtw89_phy_preinit_rf_nctl_be(struct rtw89_dev *rtwdev) 476 { 477 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C0, B_GOTX_IQKDPK, 0x3); 478 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C1, B_GOTX_IQKDPK, 0x3); 479 rtw89_phy_write32_mask(rtwdev, R_IQKDPK_HC, B_IQKDPK_HC, 0x1); 480 rtw89_phy_write32_mask(rtwdev, R_CLK_GCK, B_CLK_GCK, 0x00fffff); 481 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_CLKEN, 0x3); 482 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST, B_IQK_DPK_RST, 0x1); 483 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST, B_IQK_DPK_PRST, 0x1); 484 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1, B_IQK_DPK_PRST, 0x1); 485 rtw89_phy_write32_mask(rtwdev, R_TXRFC, B_TXRFC_RST, 0x1); 486 487 if (rtwdev->dbcc_en) { 488 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_C1, B_IQK_DPK_RST, 0x1); 489 rtw89_phy_write32_mask(rtwdev, R_TXRFC_C1, B_TXRFC_RST, 0x1); 490 } 491 492 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_RX_CFIR_PATH_EN, 0x1); 493 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_RX_CFIR_PATH, 0x3); 494 495 rtw89_phy_preinit_rf_nctl_check_be(rtwdev); 496 } 497 498 static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev) 499 { 500 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C0_BE4, B_GOTX_IQKDPK, 0x3); 501 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C1_BE4, B_GOTX_IQKDPK, 0x3); 502 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK_BE4, B_IOQ_IQK_DPK_RST, 0x1); 503 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_BE4, B_IQK_DPK_RST, 0x1); 504 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_BE4, B_IQK_DPK_PRST, 0x1); 505 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1_BE4, B_IQK_DPK_PRST, 0x1); 506 507 rtw89_phy_preinit_rf_nctl_check_be(rtwdev); 508 } 509 510 static u32 rtw89_phy_bb_wrap_flush_addr(struct rtw89_dev *rtwdev, u32 addr) 511 { 512 struct rtw89_hal *hal = &rtwdev->hal; 513 514 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 515 return 0; 516 517 if (rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7025) { 518 if (addr >= R_BE_PWR_MACID_PATH_BASE_V1 && 519 addr <= R_BE_PWR_MACID_PATH_BASE_V1 + 0xFF) 520 return addr + 0x800; 521 522 if (addr >= R_BE_PWR_MACID_LMT_BASE_V1 && 523 addr <= R_BE_PWR_MACID_LMT_BASE_V1 + 0xFF) 524 return addr - 0x800; 525 } 526 527 return 0; 528 } 529 530 static 531 void rtw89_write_bb_wrap_flush(struct rtw89_dev *rtwdev, u32 addr, u32 data) 532 { 533 /* To write registers of pwr_macid_lmt and pwr_macid_path with flush */ 534 u32 flush_addr; 535 u32 val32; 536 537 flush_addr = rtw89_phy_bb_wrap_flush_addr(rtwdev, addr); 538 if (flush_addr) { 539 val32 = rtw89_read32(rtwdev, flush_addr); 540 rtw89_write32(rtwdev, flush_addr, val32); 541 } 542 543 rtw89_write32(rtwdev, addr, data); 544 } 545 546 static 547 void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) 548 { 549 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 550 const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; 551 u32 max_macid = rtwdev->chip->support_macid_num; 552 u32 macid_idx, cr, base_macid_lmt; 553 554 base_macid_lmt = bb_wrap->pwr_macid_lmt; 555 556 for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) { 557 cr = base_macid_lmt + macid_idx; 558 rtw89_write_bb_wrap_flush(rtwdev, cr, 0); 559 } 560 } 561 562 static 563 void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev) 564 { 565 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 566 const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; 567 u32 max_macid = rtwdev->chip->support_macid_num; 568 u32 cr = bb_wrap->pwr_macid_path; 569 int i; 570 571 for (i = 0; i < max_macid; i++, cr += 4) 572 rtw89_write_bb_wrap_flush(rtwdev, cr, 0); 573 } 574 575 static void rtw89_phy_bb_wrap_tpu_set_all(struct rtw89_dev *rtwdev, 576 enum rtw89_mac_idx mac_idx) 577 { 578 u32 addr, t; 579 580 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM_SS, mac_idx); 581 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_BY_RATE_DBW_ON, 0x3); 582 583 for (addr = R_BE_PWR_BY_RATE; addr <= R_BE_PWR_BY_RATE_END; addr += 4) { 584 t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 585 rtw89_write32(rtwdev, t, 0); 586 } 587 for (addr = R_BE_PWR_RULMT_START; addr <= R_BE_PWR_RULMT_END; addr += 4) { 588 t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 589 rtw89_write32(rtwdev, t, 0); 590 } 591 for (addr = R_BE_PWR_RATE_OFST_CTRL; addr <= R_BE_PWR_RATE_OFST_END; addr += 4) { 592 t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 593 rtw89_write32(rtwdev, t, 0); 594 } 595 596 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_REF_CTRL, mac_idx); 597 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMT_DB, 0); 598 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_LMTBF, mac_idx); 599 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMTBF_DB, 0); 600 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RATE_CTRL, mac_idx); 601 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_BYRATE_DB, 0); 602 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_RULMT, mac_idx); 603 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_RULMT_DB, 0); 604 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_SW, mac_idx); 605 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_SW_DB, 0); 606 } 607 608 static 609 void rtw89_phy_bb_wrap_listen_path_en_init(struct rtw89_dev *rtwdev) 610 { 611 u32 addr; 612 int ret; 613 614 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 615 if (ret) 616 return; 617 618 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_LISTEN_PATH, RTW89_MAC_1); 619 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_LISTEN_PATH_EN, 0x2); 620 } 621 622 static void rtw89_phy_bb_wrap_force_cr_init(struct rtw89_dev *rtwdev, 623 enum rtw89_mac_idx mac_idx) 624 { 625 u32 addr; 626 627 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FORCE_LMT, mac_idx); 628 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_LMT_ON, 0); 629 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RATE_CTRL, mac_idx); 630 rtw89_write32_mask(rtwdev, addr, B_BE_FORCE_PWR_BY_RATE_EN, 0); 631 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_RULMT, mac_idx); 632 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ENON, 0); 633 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ON, 0); 634 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FORCE_MACID, mac_idx); 635 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_MACID_ALL, 0); 636 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_COEX_CTRL, mac_idx); 637 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_COEX_ON, 0); 638 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, mac_idx); 639 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RATE_ON, 0); 640 } 641 642 static void rtw89_phy_bb_wrap_ftm_init(struct rtw89_dev *rtwdev, 643 enum rtw89_mac_idx mac_idx) 644 { 645 u32 addr; 646 647 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM, mac_idx); 648 rtw89_write32(rtwdev, addr, 0xE4E431); 649 650 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM_SS, mac_idx); 651 rtw89_write32_mask(rtwdev, addr, 0x7, 0); 652 } 653 654 static u32 rtw89_phy_bb_wrap_be_bandedge_decision(struct rtw89_dev *rtwdev, 655 const struct rtw89_chan *chan) 656 { 657 u8 pri_ch = chan->primary_channel; 658 u32 val = 0; 659 660 switch (chan->band_type) { 661 default: 662 case RTW89_BAND_2G: 663 if (pri_ch == 1 || pri_ch == 13) 664 val = BIT(1) | BIT(0); 665 else if (pri_ch == 5 || pri_ch == 9) 666 val = BIT(1); 667 break; 668 case RTW89_BAND_5G: 669 if (pri_ch == 36 || pri_ch == 64 || pri_ch == 100) 670 val = BIT(3) | BIT(2) | BIT(1) | BIT(0); 671 else if (pri_ch == 40 || pri_ch == 60 || pri_ch == 104) 672 val = BIT(3) | BIT(2) | BIT(1); 673 else if ((pri_ch > 40 && pri_ch < 60) || pri_ch == 108 || pri_ch == 112) 674 val = BIT(3) | BIT(2); 675 else if (pri_ch > 112 && pri_ch < 132) 676 val = BIT(3); 677 break; 678 case RTW89_BAND_6G: 679 break; 680 } 681 682 return val; 683 } 684 685 static void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev, 686 const struct rtw89_chan *chan, 687 enum rtw89_mac_idx mac_idx) 688 { 689 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 690 const u32 *val; 691 u32 reg; 692 693 if (!d || !d->common) 694 return; 695 696 val = d->common->bands[chan->rfsi_band].rfsi_ct_opt; 697 698 reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_0_BE4, mac_idx); 699 rtw89_write32(rtwdev, reg, val[0]); 700 701 reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_8_BE4, mac_idx); 702 rtw89_write32(rtwdev, reg, val[1]); 703 } 704 705 void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev, 706 const struct rtw89_chan *chan, 707 enum rtw89_phy_idx phy_idx) 708 { 709 bool cfr_manual_en = false; 710 u32 reg; 711 u32 val; 712 713 val = rtw89_phy_bb_wrap_be_bandedge_decision(rtwdev, chan); 714 715 if (chan->band_type == RTW89_BAND_2G && 716 ((chan->primary_channel == 13 && chan->band_width == RTW89_CHANNEL_WIDTH_20) || 717 (chan->primary_channel == 11 && chan->band_width == RTW89_CHANNEL_WIDTH_40))) 718 cfr_manual_en = true; 719 720 rtw89_phy_write32_idx(rtwdev, R_TX_CFR_MANUAL_EN_BE4, B_TX_CFR_MANUAL_EN_BE4_M, 721 cfr_manual_en, phy_idx); 722 723 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); 724 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW20_BE4, val & BIT(0)); 725 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); 726 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW40_BE4, (val & BIT(1)) >> 1); 727 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); 728 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW80_BE4, (val & BIT(2)) >> 2); 729 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWY_BE4, phy_idx); 730 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW160_BE4, (val & BIT(3)) >> 3); 731 } 732 EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_bandedge_ch); 733 734 static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev *rtwdev, 735 const struct rtw89_chan *chan, 736 enum rtw89_mac_idx mac_idx) 737 { 738 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 739 u8 th0, th1, th2; 740 741 if (!d || !d->common) 742 return; 743 744 th0 = d->common->bands[chan->rfsi_band].qam_th[0]; 745 th1 = d->common->bands[chan->rfsi_band].qam_th[1]; 746 th2 = d->common->bands[chan->rfsi_band].qam_th[2]; 747 748 /* TH0 */ 749 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_0_BE4, th0, mac_idx); 750 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_3_BE4, th0, mac_idx); 751 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_1_BE4, th0, mac_idx); 752 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_4_BE4, th0, mac_idx); 753 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_7_BE4, th0, mac_idx); 754 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_0_BE4, th0, mac_idx); 755 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_3_BE4, th0, mac_idx); 756 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_6_BE4, th0, mac_idx); 757 /* TH1 */ 758 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_1_BE4, th1, mac_idx); 759 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_4_BE4, th1, mac_idx); 760 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_2_BE4, th1, mac_idx); 761 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_5_BE4, th1, mac_idx); 762 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_8_BE4, th1, mac_idx); 763 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_1_BE4, th1, mac_idx); 764 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_4_BE4, th1, mac_idx); 765 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_7_BE4, th1, mac_idx); 766 /* TH2 */ 767 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_2_BE4, th2, mac_idx); 768 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_0_BE4, th2, mac_idx); 769 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_3_BE4, th2, mac_idx); 770 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_6_BE4, th2, mac_idx); 771 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_9_BE4, th2, mac_idx); 772 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_2_BE4, th2, mac_idx); 773 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_5_BE4, th2, mac_idx); 774 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_8_BE4, th2, mac_idx); 775 } 776 777 static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen2_init(struct rtw89_dev *rtwdev, 778 enum rtw89_mac_idx mac_idx) 779 { 780 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 781 const struct rtw89_bb_wrap_common_data_gen2 *common_gen2; 782 u8 th0, th2, th3, th4, th5; 783 784 if (!d || !d->common_gen2) 785 return; 786 787 common_gen2 = d->common_gen2; 788 th0 = common_gen2->qam_th.mdpd_160m; 789 /* th1 (MDPD 320M) has no RTL8922D wrapper register */ 790 th2 = common_gen2->qam_th.oob_dpd_20m; 791 th3 = common_gen2->qam_th.oob_dpd_40m; 792 th4 = common_gen2->qam_th.oob_dpd_80m; 793 th5 = common_gen2->qam_th.cim3k; 794 795 /* DPD 160M */ 796 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_0_BE4, th0, mac_idx); 797 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_1_BE4, th0, mac_idx); 798 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_2_BE4, th0, mac_idx); 799 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_3_BE4, th0, mac_idx); 800 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_4_BE4, th0, mac_idx); 801 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_5_BE4, th0, mac_idx); 802 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_6_BE4, th0, mac_idx); 803 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_7_BE4, th0, mac_idx); 804 /* DPD 20M */ 805 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_0_BE4, th2, mac_idx); 806 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_1_BE4, th2, mac_idx); 807 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_2_BE4, th2, mac_idx); 808 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_3_BE4, th2, mac_idx); 809 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_4_BE4, th2, mac_idx); 810 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_5_BE4, th2, mac_idx); 811 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_6_BE4, th2, mac_idx); 812 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH1_7_BE4, th2, mac_idx); 813 /* DPD 40M */ 814 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_0_BE4, th3, mac_idx); 815 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_1_BE4, th3, mac_idx); 816 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_2_BE4, th3, mac_idx); 817 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_3_BE4, th3, mac_idx); 818 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_4_BE4, th3, mac_idx); 819 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_5_BE4, th3, mac_idx); 820 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_6_BE4, th3, mac_idx); 821 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_7_BE4, th3, mac_idx); 822 /* DPD 80M */ 823 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW80_TH1_0_BE4, th4, mac_idx); 824 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_1_BE4, th4, mac_idx); 825 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_2_BE4, th4, mac_idx); 826 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_3_BE4, th4, mac_idx); 827 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_4_BE4, th4, mac_idx); 828 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_5_BE4, th4, mac_idx); 829 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_6_BE4, th4, mac_idx); 830 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_7_BE4, th4, mac_idx); 831 /* CIM3K */ 832 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH2_BE4, th5, mac_idx); 833 } 834 835 static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(struct rtw89_dev *rtwdev, 836 const struct rtw89_chan *chan, 837 enum rtw89_mac_idx mac_idx) 838 { 839 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 840 const struct rtw89_bb_wrap_common_data_gen3 *common_gen3; 841 const u8 *ths; 842 843 if (!d || !d->common_gen3) 844 return; 845 846 common_gen3 = d->common_gen3; 847 ths = common_gen3->bands[chan->rfsi_band].qam_th; 848 849 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_0_BE4, ths[0], mac_idx); 850 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_1_BE4, ths[0], mac_idx); 851 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_2_BE4, ths[0], mac_idx); 852 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_3_BE4, ths[0], mac_idx); 853 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_4_BE4, ths[0], mac_idx); 854 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_5_BE4, ths[0], mac_idx); 855 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_6_BE4, ths[0], mac_idx); 856 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_7_BE4, ths[0], mac_idx); 857 858 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_0_BE4, ths[1], mac_idx); 859 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_1_BE4, ths[1], mac_idx); 860 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_2_BE4, ths[1], mac_idx); 861 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_3_BE4, ths[1], mac_idx); 862 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_4_BE4, ths[1], mac_idx); 863 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_5_BE4, ths[1], mac_idx); 864 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_6_BE4, ths[1], mac_idx); 865 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_7_BE4, ths[1], mac_idx); 866 867 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_0_BE4, ths[2], mac_idx); 868 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_1_BE4, ths[2], mac_idx); 869 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_2_BE4, ths[2], mac_idx); 870 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_3_BE4, ths[2], mac_idx); 871 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_4_BE4, ths[2], mac_idx); 872 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_5_BE4, ths[2], mac_idx); 873 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_6_BE4, ths[2], mac_idx); 874 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_7_BE4, ths[2], mac_idx); 875 876 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_0_BE4, ths[3], mac_idx); 877 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_1_BE4, ths[3], mac_idx); 878 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_2_BE4, ths[3], mac_idx); 879 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_3_BE4, ths[3], mac_idx); 880 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_4_BE4, ths[3], mac_idx); 881 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_5_BE4, ths[3], mac_idx); 882 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_6_BE4, ths[3], mac_idx); 883 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_7_BE4, ths[3], mac_idx); 884 885 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_0_BE4, ths[4], mac_idx); 886 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_1_BE4, ths[4], mac_idx); 887 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_2_BE4, ths[4], mac_idx); 888 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_3_BE4, ths[4], mac_idx); 889 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_4_BE4, ths[4], mac_idx); 890 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_5_BE4, ths[4], mac_idx); 891 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_6_BE4, ths[4], mac_idx); 892 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_7_BE4, ths[4], mac_idx); 893 894 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_0_BE4, ths[5], mac_idx); 895 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_1_BE4, ths[5], mac_idx); 896 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_2_BE4, ths[5], mac_idx); 897 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_3_BE4, ths[5], mac_idx); 898 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_4_BE4, ths[5], mac_idx); 899 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_5_BE4, ths[5], mac_idx); 900 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_6_BE4, ths[5], mac_idx); 901 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_7_BE4, ths[5], mac_idx); 902 } 903 904 static void rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev *rtwdev, 905 const struct rtw89_chan *chan, 906 enum rtw89_mac_idx mac_idx) 907 { 908 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 909 u8 pb_tb = 0; 910 911 if (d && d->common) 912 pb_tb = d->common->bands[chan->rfsi_band].pb_tb; 913 914 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_ER_BE4, 0x0, mac_idx); 915 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SUBF_BE4, 0x0, mac_idx); 916 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_FTM_BE4, 0x0, mac_idx); 917 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SENS_BE4, 0x0, mac_idx); 918 919 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DEF_BE, 0x0, mac_idx); 920 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_PB_BE4, pb_tb, mac_idx); 921 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_WO_BE4, 0x0, mac_idx); 922 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_BF_BE4, 0x0, mac_idx); 923 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_MUMIMO_BE4, 0x0, mac_idx); 924 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_FTM_BE4, 0x0, mac_idx); 925 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_SENS_BE4, 0x0, mac_idx); 926 } 927 928 static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(struct rtw89_dev *rtwdev, 929 const struct rtw89_chan *chan, 930 enum rtw89_mac_idx mac_idx) 931 { 932 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 933 const u16 *th; 934 935 if (!d) 936 return; 937 938 th = d->bands[chan->rfsi_band].qam_comp_th0; 939 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, th[0], mac_idx); 940 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, th[1], mac_idx); 941 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, th[2], mac_idx); 942 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, th[3], mac_idx); 943 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, th[4], mac_idx); 944 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, th[5], mac_idx); 945 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, th[6], mac_idx); 946 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, th[7], mac_idx); 947 948 th = d->bands[chan->rfsi_band].qam_comp_th1; 949 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_L, th[0], mac_idx); 950 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_M, th[1], mac_idx); 951 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_H, th[2], mac_idx); 952 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_L, th[3], mac_idx); 953 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_M, th[4], mac_idx); 954 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_H, th[5], mac_idx); 955 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_L, th[6], mac_idx); 956 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_M, th[7], mac_idx); 957 958 th = d->bands[chan->rfsi_band].qam_comp_th2; 959 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2L, th[0], mac_idx); 960 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2M, th[1], mac_idx); 961 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2H, th[2], mac_idx); 962 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2L, th[3], mac_idx); 963 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2M, th[4], mac_idx); 964 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2H, th[5], mac_idx); 965 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2L, th[6], mac_idx); 966 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2M, th[7], mac_idx); 967 968 th = d->bands[chan->rfsi_band].qam_comp_ow; 969 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, th[0], mac_idx); 970 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, th[1], mac_idx); 971 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, th[2], mac_idx); 972 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, th[3], mac_idx); 973 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, th[4], mac_idx); 974 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, th[5], mac_idx); 975 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, th[6], mac_idx); 976 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, th[7], mac_idx); 977 } 978 979 static void rtw89_phy_trig_spect_tx_shape_disabled(struct rtw89_dev *rtwdev, 980 const struct rtw89_chan *chan, 981 enum rtw89_mac_idx mac_idx) 982 { 983 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 984 u8 band = chan->band_type; 985 u8 tx_shape_idx; 986 987 /* 988 * Only needed by chips with d->bands[].{qam_comp_th0, qam_comp_ow} as 989 * what rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val() does. 990 */ 991 if (!d) 992 return; 993 994 tx_shape_idx = rtw89_get_tx_shape_idx(rtwdev, band, RTW89_RS_OFDM); 995 if (tx_shape_idx) 996 return; 997 998 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, mac_idx); 999 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, mac_idx); 1000 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, mac_idx); 1001 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, mac_idx); 1002 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, mac_idx); 1003 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, mac_idx); 1004 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, mac_idx); 1005 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, mac_idx); 1006 1007 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, B_OW_VAL_TRIANGULAR_L, 0, mac_idx); 1008 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, B_OW_VAL_TRIANGULAR_H, 0, mac_idx); 1009 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, B_OW_VAL_TRIANGULAR_L, 0, mac_idx); 1010 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, B_OW_VAL_TRIANGULAR_H, 0, mac_idx); 1011 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, B_OW_VAL_TRIANGULAR_L, 0, mac_idx); 1012 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, B_OW_VAL_TRIANGULAR_H, 0, mac_idx); 1013 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, B_OW_VAL_TRIANGULAR_L, 0, mac_idx); 1014 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, B_OW_VAL_TRIANGULAR_H, 0, mac_idx); 1015 } 1016 1017 static void rtw89_phy_bb_set_oob_dpd_qam_comp_val(struct rtw89_dev *rtwdev, 1018 const struct rtw89_chan *chan, 1019 enum rtw89_mac_idx mac_idx) 1020 { 1021 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 1022 u8 th; 1023 1024 if (!d) 1025 return; 1026 1027 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[0]; 1028 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK0_BE4, th, mac_idx); 1029 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK1_BE4, th, mac_idx); 1030 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK2_BE4, th, mac_idx); 1031 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK3_BE4, th, mac_idx); 1032 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK4_BE4, th, mac_idx); 1033 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK5_BE4, th, mac_idx); 1034 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK6_BE4, th, mac_idx); 1035 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK7_BE4, th, mac_idx); 1036 1037 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[1]; 1038 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK0_BE4, th, mac_idx); 1039 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK1_BE4, th, mac_idx); 1040 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK2_BE4, th, mac_idx); 1041 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK3_BE4, th, mac_idx); 1042 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK4_BE4, th, mac_idx); 1043 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK5_BE4, th, mac_idx); 1044 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK6_BE4, th, mac_idx); 1045 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK7_BE4, th, mac_idx); 1046 1047 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[2]; 1048 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH0_BE4, th, mac_idx); 1049 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH1_BE4, th, mac_idx); 1050 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH2_BE4, th, mac_idx); 1051 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH3_BE4, th, mac_idx); 1052 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH4_BE4, th, mac_idx); 1053 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH5_BE4, th, mac_idx); 1054 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH6_BE4, th, mac_idx); 1055 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH7_BE4, th, mac_idx); 1056 1057 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[3]; 1058 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH0_BE4, th, mac_idx); 1059 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH1_BE4, th, mac_idx); 1060 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH2_BE4, th, mac_idx); 1061 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH3_BE4, th, mac_idx); 1062 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH4_BE4, th, mac_idx); 1063 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH5_BE4, th, mac_idx); 1064 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH6_BE4, th, mac_idx); 1065 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH7_BE4, th, mac_idx); 1066 1067 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[4]; 1068 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH0_BE4, th, mac_idx); 1069 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH1_BE4, th, mac_idx); 1070 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH2_BE4, th, mac_idx); 1071 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH3_BE4, th, mac_idx); 1072 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH4_BE4, th, mac_idx); 1073 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH5_BE4, th, mac_idx); 1074 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH6_BE4, th, mac_idx); 1075 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH7_BE4, th, mac_idx); 1076 1077 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[5]; 1078 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW0_BE4, th, mac_idx); 1079 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW1_BE4, th, mac_idx); 1080 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW2_BE4, th, mac_idx); 1081 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW3_BE4, th, mac_idx); 1082 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW4_BE4, th, mac_idx); 1083 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW5_BE4, th, mac_idx); 1084 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW6_BE4, th, mac_idx); 1085 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW7_BE4, th, mac_idx); 1086 1087 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[6]; 1088 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW0_BE4, th, mac_idx); 1089 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW1_BE4, th, mac_idx); 1090 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW2_BE4, th, mac_idx); 1091 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW3_BE4, th, mac_idx); 1092 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW4_BE4, th, mac_idx); 1093 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW5_BE4, th, mac_idx); 1094 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW6_BE4, th, mac_idx); 1095 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW7_BE4, th, mac_idx); 1096 1097 th = d->bands[chan->rfsi_band].oob_dpd_by_cbw[7]; 1098 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW0_BE4, th, mac_idx); 1099 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW1_BE4, th, mac_idx); 1100 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW2_BE4, th, mac_idx); 1101 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW3_BE4, th, mac_idx); 1102 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW4_BE4, th, mac_idx); 1103 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW5_BE4, th, mac_idx); 1104 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW6_BE4, th, mac_idx); 1105 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW7_BE4, th, mac_idx); 1106 } 1107 1108 static void rtw89_phy_bb_set_mdpd_qam_comp_val(struct rtw89_dev *rtwdev, 1109 enum rtw89_mac_idx mac_idx) 1110 { 1111 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 1112 u8 th; 1113 1114 if (!d) 1115 return; 1116 1117 th = d->mdpd_by_dbw[0]; 1118 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH0_BE4, th, mac_idx); 1119 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH1_BE4, th, mac_idx); 1120 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH2_BE4, th, mac_idx); 1121 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH3_BE4, th, mac_idx); 1122 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH4_BE4, th, mac_idx); 1123 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH5_BE4, th, mac_idx); 1124 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH6_BE4, th, mac_idx); 1125 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH7_BE4, th, mac_idx); 1126 1127 th = d->mdpd_by_dbw[2]; 1128 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW0_BE4, th, mac_idx); 1129 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW1_BE4, th, mac_idx); 1130 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW2_BE4, th, mac_idx); 1131 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW3_BE4, th, mac_idx); 1132 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW4_BE4, th, mac_idx); 1133 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW5_BE4, th, mac_idx); 1134 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW6_BE4, th, mac_idx); 1135 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW7_BE4, th, mac_idx); 1136 } 1137 1138 static void rtw89_phy_bb_set_cim3k_val(struct rtw89_dev *rtwdev, 1139 const struct rtw89_chan *chan, 1140 enum rtw89_mac_idx mac_idx) 1141 { 1142 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 1143 const struct rtw89_bb_wrap_data_cim3k *p; 1144 1145 if (!d || !d->common) 1146 return; 1147 1148 p = &d->common->bands[chan->rfsi_band].cim3k; 1149 1150 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, p->th, mac_idx); 1151 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, p->ow, mac_idx); 1152 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4, 1153 p->non_bandedge, mac_idx); 1154 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4, 1155 p->bandedge, mac_idx); 1156 1157 if (rtwdev->chip->chip_id != RTL8922D) 1158 return; 1159 1160 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_EN, 1, mac_idx); 1161 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_VAL, 0, mac_idx); 1162 1163 if (rtwdev->hal.cid == RTL8922D_CID7025) 1164 return; 1165 1166 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_RU26_FORCE_EN, 1, mac_idx); 1167 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_RU26_FORCE_VAL, 0, mac_idx); 1168 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_RU52_FORCE_EN, 1, mac_idx); 1169 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_RU52_FORCE_VAL, 1, mac_idx); 1170 } 1171 1172 static void rtw89_phy_bb_set_cck_cfir_filter_val_gen3(struct rtw89_dev *rtwdev, 1173 enum rtw89_mac_idx mac_idx) 1174 { 1175 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data; 1176 const struct rtw89_bb_wrap_common_data_gen3 *common_gen3; 1177 u8 cck0, cck1; 1178 1179 if (!d || !d->common_gen3) 1180 return; 1181 1182 common_gen3 = d->common_gen3; 1183 cck0 = common_gen3->cck_val[0]; 1184 cck1 = common_gen3->cck_val[1]; 1185 1186 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR0_BE4, cck0, mac_idx); 1187 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR1_BE4, cck0, mac_idx); 1188 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR2_BE4, cck0, mac_idx); 1189 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR3_BE4, cck0, mac_idx); 1190 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR4_BE4, cck0, mac_idx); 1191 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR5_BE4, cck0, mac_idx); 1192 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR6_BE4, cck0, mac_idx); 1193 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR7_BE4, cck0, mac_idx); 1194 1195 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR0_BE4, cck1, mac_idx); 1196 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR1_BE4, cck1, mac_idx); 1197 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR2_BE4, cck1, mac_idx); 1198 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR3_BE4, cck1, mac_idx); 1199 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR4_BE4, cck1, mac_idx); 1200 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR5_BE4, cck1, mac_idx); 1201 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR6_BE4, cck1, mac_idx); 1202 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR7_BE4, cck1, mac_idx); 1203 } 1204 1205 static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev, 1206 enum rtw89_mac_idx mac_idx) 1207 { 1208 enum rtw89_phy_idx phy_idx = mac_idx != RTW89_MAC_0 ? RTW89_PHY_1 : RTW89_PHY_0; 1209 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1210 struct rtw89_entity_conf conf; 1211 const struct rtw89_chan *chan; 1212 1213 if (chip_id != RTL8922D) 1214 return; 1215 1216 rtw89_entity_get_conf(rtwdev, &conf); 1217 chan = conf.chans[phy_idx]; 1218 1219 rtw89_phy_bb_wrap_tx_rfsi_ctrl_init_by_chan(rtwdev, chan, mac_idx); 1220 } 1221 1222 void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init_by_chan(struct rtw89_dev *rtwdev, 1223 const struct rtw89_chan *chan, 1224 u8 mac_idx) 1225 { 1226 rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(rtwdev, chan, mac_idx); 1227 rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen2_init(rtwdev, mac_idx); 1228 rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(rtwdev, chan, mac_idx); 1229 rtw89_phy_bb_wrap_tx_rfsi_scenario_def(rtwdev, chan, mac_idx); 1230 rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(rtwdev, chan, mac_idx); 1231 rtw89_phy_trig_spect_tx_shape_disabled(rtwdev, chan, mac_idx); 1232 rtw89_phy_bb_set_oob_dpd_qam_comp_val(rtwdev, chan, mac_idx); 1233 rtw89_phy_bb_set_mdpd_qam_comp_val(rtwdev, mac_idx); 1234 rtw89_phy_bb_set_cim3k_val(rtwdev, chan, mac_idx); 1235 rtw89_phy_bb_set_cck_cfir_filter_val_gen3(rtwdev, mac_idx); 1236 rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, chan, mac_idx); 1237 } 1238 EXPORT_SYMBOL(rtw89_phy_bb_wrap_tx_rfsi_ctrl_init_by_chan); 1239 1240 static void rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev *rtwdev) 1241 { 1242 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1243 u8 mac_idx; 1244 u32 addr; 1245 1246 if (chip_id != RTL8922A) 1247 return; 1248 1249 for (mac_idx = 0; mac_idx < RTW89_MAC_NUM; mac_idx++) { 1250 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RSSI_TARGET_LMT, mac_idx); 1251 rtw89_write32(rtwdev, addr, 0x0201FE00); 1252 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_TH, mac_idx); 1253 rtw89_write32(rtwdev, addr, 0x00FFEC7E); 1254 } 1255 } 1256 1257 static void __rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev, 1258 enum rtw89_mac_idx mac_idx) 1259 { 1260 rtw89_phy_bb_wrap_tx_path_by_macid_init(rtwdev); 1261 rtw89_phy_bb_wrap_pwr_by_macid_init(rtwdev); 1262 rtw89_phy_bb_wrap_tpu_set_all(rtwdev, mac_idx); 1263 rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(rtwdev, mac_idx); 1264 rtw89_phy_bb_wrap_force_cr_init(rtwdev, mac_idx); 1265 rtw89_phy_bb_wrap_ftm_init(rtwdev, mac_idx); 1266 rtw89_phy_bb_wrap_listen_path_en_init(rtwdev); 1267 rtw89_phy_bb_wrap_ul_pwr(rtwdev); 1268 } 1269 1270 static void rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev) 1271 { 1272 __rtw89_phy_bb_wrap_init_be(rtwdev, RTW89_MAC_0); 1273 if (rtwdev->dbcc_en) 1274 __rtw89_phy_bb_wrap_init_be(rtwdev, RTW89_MAC_1); 1275 } 1276 1277 static void rtw89_phy_ch_info_init_be(struct rtw89_dev *rtwdev) 1278 { 1279 rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG, B_CHINFO_SEG_LEN, 0x0); 1280 rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG, B_CHINFO_SEG, 0xf); 1281 rtw89_phy_write32_mask(rtwdev, R_CHINFO_DATA, B_CHINFO_DATA_BITMAP, 0x1); 1282 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ELM_SRC, B_CHINFO_ELM_BITMAP, 0x40303); 1283 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ELM_SRC, B_CHINFO_SRC, 0x0); 1284 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_TYPE_SCAL, B_CHINFO_TYPE, 0x3); 1285 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_TYPE_SCAL, B_CHINFO_SCAL, 0x0); 1286 } 1287 1288 static void rtw89_phy_ch_info_init_be_v1(struct rtw89_dev *rtwdev) 1289 { 1290 rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG_BE4, B_CHINFO_SEG_LEN_BE4, 0); 1291 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_OPT_BE4, B_CHINFO_OPT_BE4, 0x3); 1292 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_NX_BE4, B_CHINFO_NX_BE4, 0x669); 1293 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ALG_BE4, B_CHINFO_ALG_BE4, 0); 1294 } 1295 1296 static int rtw89_phy_btc_bttrx_en_be(struct rtw89_dev *rtwdev, u8 bt_en_int, 1297 bool enable) 1298 { 1299 if (RTW89_CHK_FW_FEATURE(NO_DRV_BT_TXRX_EN, &rtwdev->fw)) 1300 return 0; 1301 1302 rtw89_io_pack(rtwdev); 1303 1304 rtw89_write_rf(rtwdev, RF_PATH_A, RR_BTG_CONTROL, 1305 RR_BTG_CONTROL_EN << bt_en_int, enable); 1306 rtw89_write_rf(rtwdev, RF_PATH_B, RR_BTG_CONTROL, 1307 RR_BTG_CONTROL_EN << bt_en_int, enable); 1308 1309 return rtw89_io_unpack(rtwdev); 1310 } 1311 1312 struct rtw89_byr_spec_ent_be { 1313 struct rtw89_rate_desc init; 1314 u8 num_of_idx; 1315 bool no_over_bw40; 1316 bool no_multi_nss; 1317 }; 1318 1319 static const struct rtw89_byr_spec_ent_be rtw89_byr_spec_be[] = { 1320 { 1321 .init = { .rs = RTW89_RS_CCK }, 1322 .num_of_idx = RTW89_RATE_CCK_NUM, 1323 .no_over_bw40 = true, 1324 .no_multi_nss = true, 1325 }, 1326 { 1327 .init = { .rs = RTW89_RS_OFDM }, 1328 .num_of_idx = RTW89_RATE_OFDM_NUM, 1329 .no_multi_nss = true, 1330 }, 1331 { 1332 .init = { .rs = RTW89_RS_MCS, .idx = 14, .ofdma = RTW89_NON_OFDMA }, 1333 .num_of_idx = 2, 1334 .no_multi_nss = true, 1335 }, 1336 { 1337 .init = { .rs = RTW89_RS_MCS, .idx = 14, .ofdma = RTW89_OFDMA }, 1338 .num_of_idx = 2, 1339 .no_multi_nss = true, 1340 }, 1341 { 1342 .init = { .rs = RTW89_RS_MCS, .ofdma = RTW89_NON_OFDMA }, 1343 .num_of_idx = 14, 1344 }, 1345 { 1346 .init = { .rs = RTW89_RS_HEDCM, .ofdma = RTW89_NON_OFDMA }, 1347 .num_of_idx = RTW89_RATE_HEDCM_NUM, 1348 }, 1349 { 1350 .init = { .rs = RTW89_RS_MCS, .ofdma = RTW89_OFDMA }, 1351 .num_of_idx = 14, 1352 }, 1353 { 1354 .init = { .rs = RTW89_RS_HEDCM, .ofdma = RTW89_OFDMA }, 1355 .num_of_idx = RTW89_RATE_HEDCM_NUM, 1356 }, 1357 }; 1358 1359 static 1360 void __phy_set_txpwr_byrate_be(struct rtw89_dev *rtwdev, u8 band, u8 bw, 1361 u8 nss, u32 *addr, enum rtw89_phy_idx phy_idx) 1362 { 1363 const struct rtw89_byr_spec_ent_be *ent; 1364 struct rtw89_rate_desc desc; 1365 int pos = 0; 1366 int i, j; 1367 u32 val; 1368 s8 v[4]; 1369 1370 for (i = 0; i < ARRAY_SIZE(rtw89_byr_spec_be); i++) { 1371 ent = &rtw89_byr_spec_be[i]; 1372 1373 if (bw > RTW89_CHANNEL_WIDTH_40 && ent->no_over_bw40) 1374 continue; 1375 if (nss > RTW89_NSS_1 && ent->no_multi_nss) 1376 continue; 1377 1378 desc = ent->init; 1379 desc.nss = nss; 1380 for (j = 0; j < ent->num_of_idx; j++, desc.idx++) { 1381 v[pos] = rtw89_phy_read_txpwr_byrate(rtwdev, band, bw, 1382 &desc); 1383 pos = (pos + 1) % 4; 1384 if (pos) 1385 continue; 1386 1387 val = u32_encode_bits(v[0], GENMASK(7, 0)) | 1388 u32_encode_bits(v[1], GENMASK(15, 8)) | 1389 u32_encode_bits(v[2], GENMASK(23, 16)) | 1390 u32_encode_bits(v[3], GENMASK(31, 24)); 1391 1392 rtw89_mac_txpwr_write32(rtwdev, phy_idx, *addr, val); 1393 *addr += 4; 1394 } 1395 } 1396 } 1397 1398 static void rtw89_phy_set_txpwr_byrate_be(struct rtw89_dev *rtwdev, 1399 const struct rtw89_chan *chan, 1400 enum rtw89_phy_idx phy_idx) 1401 { 1402 u32 addr = R_BE_PWR_BY_RATE; 1403 u8 band = chan->band_type; 1404 u8 bw, nss; 1405 1406 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1407 "[TXPWR] set txpwr byrate on band %d\n", band); 1408 1409 for (bw = 0; bw <= RTW89_CHANNEL_WIDTH_320; bw++) 1410 for (nss = 0; nss <= RTW89_NSS_2; nss++) 1411 __phy_set_txpwr_byrate_be(rtwdev, band, bw, nss, 1412 &addr, phy_idx); 1413 } 1414 1415 static void rtw89_phy_set_txpwr_offset_be(struct rtw89_dev *rtwdev, 1416 const struct rtw89_chan *chan, 1417 enum rtw89_phy_idx phy_idx) 1418 { 1419 struct rtw89_rate_desc desc = { 1420 .nss = RTW89_NSS_1, 1421 .rs = RTW89_RS_OFFSET, 1422 }; 1423 u8 band = chan->band_type; 1424 s8 v[RTW89_RATE_OFFSET_NUM_BE] = {}; 1425 u32 val; 1426 1427 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1428 "[TXPWR] set txpwr offset on band %d\n", band); 1429 1430 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_BE; desc.idx++) 1431 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 1432 1433 val = u32_encode_bits(v[RTW89_RATE_OFFSET_CCK], GENMASK(3, 0)) | 1434 u32_encode_bits(v[RTW89_RATE_OFFSET_OFDM], GENMASK(7, 4)) | 1435 u32_encode_bits(v[RTW89_RATE_OFFSET_HT], GENMASK(11, 8)) | 1436 u32_encode_bits(v[RTW89_RATE_OFFSET_VHT], GENMASK(15, 12)) | 1437 u32_encode_bits(v[RTW89_RATE_OFFSET_HE], GENMASK(19, 16)) | 1438 u32_encode_bits(v[RTW89_RATE_OFFSET_EHT], GENMASK(23, 20)) | 1439 u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_HE], GENMASK(27, 24)) | 1440 u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_EHT], GENMASK(31, 28)); 1441 1442 rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_BE_PWR_RATE_OFST_CTRL, val); 1443 } 1444 1445 static void 1446 fill_limit_nonbf_bf(struct rtw89_dev *rtwdev, s8 (*ptr)[RTW89_BF_NUM], 1447 u8 band, u8 bw, u8 ntx, u8 rs, u8 ch) 1448 { 1449 int bf; 1450 1451 for (bf = 0; bf < RTW89_BF_NUM; bf++) 1452 (*ptr)[bf] = rtw89_phy_read_txpwr_limit(rtwdev, band, bw, ntx, 1453 rs, bf, ch); 1454 } 1455 1456 static void 1457 fill_limit_nonbf_bf_min(struct rtw89_dev *rtwdev, s8 (*ptr)[RTW89_BF_NUM], 1458 u8 band, u8 bw, u8 ntx, u8 rs, u8 ch1, u8 ch2) 1459 { 1460 s8 v1[RTW89_BF_NUM]; 1461 s8 v2[RTW89_BF_NUM]; 1462 int bf; 1463 1464 fill_limit_nonbf_bf(rtwdev, &v1, band, bw, ntx, rs, ch1); 1465 fill_limit_nonbf_bf(rtwdev, &v2, band, bw, ntx, rs, ch2); 1466 1467 for (bf = 0; bf < RTW89_BF_NUM; bf++) 1468 (*ptr)[bf] = min(v1[bf], v2[bf]); 1469 } 1470 1471 static void phy_fill_limit_20m_be(struct rtw89_dev *rtwdev, 1472 struct rtw89_txpwr_limit_be *lmt, 1473 u8 band, u8 ntx, u8 ch) 1474 { 1475 fill_limit_nonbf_bf(rtwdev, &lmt->cck_20m, band, 1476 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_CCK, ch); 1477 fill_limit_nonbf_bf(rtwdev, &lmt->cck_40m, band, 1478 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_CCK, ch); 1479 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band, 1480 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, ch); 1481 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band, 1482 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch); 1483 } 1484 1485 static void phy_fill_limit_40m_be(struct rtw89_dev *rtwdev, 1486 struct rtw89_txpwr_limit_be *lmt, 1487 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1488 { 1489 fill_limit_nonbf_bf(rtwdev, &lmt->cck_20m, band, 1490 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_CCK, ch - 2); 1491 fill_limit_nonbf_bf(rtwdev, &lmt->cck_40m, band, 1492 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_CCK, ch); 1493 1494 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band, 1495 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch); 1496 1497 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band, 1498 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2); 1499 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band, 1500 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2); 1501 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band, 1502 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch); 1503 } 1504 1505 static void phy_fill_limit_80m_be(struct rtw89_dev *rtwdev, 1506 struct rtw89_txpwr_limit_be *lmt, 1507 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1508 { 1509 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band, 1510 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch); 1511 1512 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band, 1513 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 6); 1514 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band, 1515 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2); 1516 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[2], band, 1517 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2); 1518 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[3], band, 1519 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 6); 1520 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band, 1521 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 4); 1522 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[1], band, 1523 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 4); 1524 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[0], band, 1525 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch); 1526 1527 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_0p5, band, 1528 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, 1529 ch - 4, ch + 4); 1530 } 1531 1532 static void phy_fill_limit_160m_be(struct rtw89_dev *rtwdev, 1533 struct rtw89_txpwr_limit_be *lmt, 1534 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1535 { 1536 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band, 1537 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch); 1538 1539 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band, 1540 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 14); 1541 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band, 1542 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 10); 1543 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[2], band, 1544 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 6); 1545 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[3], band, 1546 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2); 1547 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[4], band, 1548 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2); 1549 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[5], band, 1550 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 6); 1551 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[6], band, 1552 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 10); 1553 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[7], band, 1554 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 14); 1555 1556 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band, 1557 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 12); 1558 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[1], band, 1559 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 4); 1560 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[2], band, 1561 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 4); 1562 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[3], band, 1563 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 12); 1564 1565 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[0], band, 1566 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch - 8); 1567 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[1], band, 1568 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch + 8); 1569 1570 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_160m[0], band, 1571 RTW89_CHANNEL_WIDTH_160, ntx, RTW89_RS_MCS, ch); 1572 1573 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_0p5, band, 1574 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, 1575 ch - 12, ch - 4); 1576 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_2p5, band, 1577 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, 1578 ch + 4, ch + 12); 1579 } 1580 1581 static void phy_fill_limit_320m_be(struct rtw89_dev *rtwdev, 1582 struct rtw89_txpwr_limit_be *lmt, 1583 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1584 { 1585 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band, 1586 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch); 1587 1588 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band, 1589 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 30); 1590 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band, 1591 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 26); 1592 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[2], band, 1593 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 22); 1594 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[3], band, 1595 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 18); 1596 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[4], band, 1597 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 14); 1598 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[5], band, 1599 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 10); 1600 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[6], band, 1601 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 6); 1602 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[7], band, 1603 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2); 1604 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[8], band, 1605 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2); 1606 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[9], band, 1607 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 6); 1608 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[10], band, 1609 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 10); 1610 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[11], band, 1611 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 14); 1612 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[12], band, 1613 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 18); 1614 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[13], band, 1615 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 22); 1616 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[14], band, 1617 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 26); 1618 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[15], band, 1619 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 30); 1620 1621 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band, 1622 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 28); 1623 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[1], band, 1624 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 20); 1625 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[2], band, 1626 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 12); 1627 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[3], band, 1628 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 4); 1629 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[4], band, 1630 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 4); 1631 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[5], band, 1632 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 12); 1633 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[6], band, 1634 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 20); 1635 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[7], band, 1636 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 28); 1637 1638 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[0], band, 1639 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch - 24); 1640 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[1], band, 1641 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch - 8); 1642 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[2], band, 1643 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch + 8); 1644 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[3], band, 1645 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch + 24); 1646 1647 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_160m[0], band, 1648 RTW89_CHANNEL_WIDTH_160, ntx, RTW89_RS_MCS, ch - 16); 1649 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_160m[1], band, 1650 RTW89_CHANNEL_WIDTH_160, ntx, RTW89_RS_MCS, ch + 16); 1651 1652 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_320m, band, 1653 RTW89_CHANNEL_WIDTH_320, ntx, RTW89_RS_MCS, ch); 1654 1655 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_0p5, band, 1656 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, 1657 ch - 28, ch - 20); 1658 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_2p5, band, 1659 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, 1660 ch - 12, ch - 4); 1661 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_4p5, band, 1662 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, 1663 ch + 4, ch + 12); 1664 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_6p5, band, 1665 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, 1666 ch + 20, ch + 28); 1667 } 1668 1669 static void rtw89_phy_fill_limit_be(struct rtw89_dev *rtwdev, 1670 const struct rtw89_chan *chan, 1671 struct rtw89_txpwr_limit_be *lmt, 1672 u8 ntx) 1673 { 1674 u8 band = chan->band_type; 1675 u8 pri_ch = chan->primary_channel; 1676 u8 ch = chan->channel; 1677 u8 bw = chan->band_width; 1678 1679 memset(lmt, 0, sizeof(*lmt)); 1680 1681 switch (bw) { 1682 case RTW89_CHANNEL_WIDTH_20: 1683 phy_fill_limit_20m_be(rtwdev, lmt, band, ntx, ch); 1684 break; 1685 case RTW89_CHANNEL_WIDTH_40: 1686 phy_fill_limit_40m_be(rtwdev, lmt, band, ntx, ch, pri_ch); 1687 break; 1688 case RTW89_CHANNEL_WIDTH_80: 1689 phy_fill_limit_80m_be(rtwdev, lmt, band, ntx, ch, pri_ch); 1690 break; 1691 case RTW89_CHANNEL_WIDTH_160: 1692 phy_fill_limit_160m_be(rtwdev, lmt, band, ntx, ch, pri_ch); 1693 break; 1694 case RTW89_CHANNEL_WIDTH_320: 1695 phy_fill_limit_320m_be(rtwdev, lmt, band, ntx, ch, pri_ch); 1696 break; 1697 } 1698 } 1699 1700 static void rtw89_phy_set_txpwr_limit_be(struct rtw89_dev *rtwdev, 1701 const struct rtw89_chan *chan, 1702 enum rtw89_phy_idx phy_idx) 1703 { 1704 struct rtw89_txpwr_limit_be lmt; 1705 const s8 *ptr; 1706 u32 addr, val; 1707 u8 i, j; 1708 1709 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_be) != 1710 RTW89_TXPWR_LMT_PAGE_SIZE_BE); 1711 1712 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1713 "[TXPWR] set txpwr limit on band %d bw %d\n", 1714 chan->band_type, chan->band_width); 1715 1716 addr = R_BE_PWR_LMT; 1717 for (i = 0; i <= RTW89_NSS_2; i++) { 1718 rtw89_phy_fill_limit_be(rtwdev, chan, &lmt, i); 1719 1720 ptr = (s8 *)&lmt; 1721 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_BE; 1722 j += 4, addr += 4, ptr += 4) { 1723 val = u32_encode_bits(ptr[0], GENMASK(7, 0)) | 1724 u32_encode_bits(ptr[1], GENMASK(15, 8)) | 1725 u32_encode_bits(ptr[2], GENMASK(23, 16)) | 1726 u32_encode_bits(ptr[3], GENMASK(31, 24)); 1727 1728 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1729 } 1730 } 1731 } 1732 1733 static void fill_limit_ru_each(struct rtw89_dev *rtwdev, u8 index, 1734 struct rtw89_txpwr_limit_ru_be *lmt_ru, 1735 u8 band, u8 ntx, u8 ch) 1736 { 1737 lmt_ru->ru26[index] = 1738 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU26, ntx, ch); 1739 lmt_ru->ru52[index] = 1740 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU52, ntx, ch); 1741 lmt_ru->ru106[index] = 1742 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU106, ntx, ch); 1743 lmt_ru->ru52_26[index] = 1744 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU52_26, ntx, ch); 1745 lmt_ru->ru106_26[index] = 1746 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU106_26, ntx, ch); 1747 } 1748 1749 static void phy_fill_limit_ru_20m_be(struct rtw89_dev *rtwdev, 1750 struct rtw89_txpwr_limit_ru_be *lmt_ru, 1751 u8 band, u8 ntx, u8 ch) 1752 { 1753 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch); 1754 } 1755 1756 static void phy_fill_limit_ru_40m_be(struct rtw89_dev *rtwdev, 1757 struct rtw89_txpwr_limit_ru_be *lmt_ru, 1758 u8 band, u8 ntx, u8 ch) 1759 { 1760 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 2); 1761 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch + 2); 1762 } 1763 1764 static void phy_fill_limit_ru_80m_be(struct rtw89_dev *rtwdev, 1765 struct rtw89_txpwr_limit_ru_be *lmt_ru, 1766 u8 band, u8 ntx, u8 ch) 1767 { 1768 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 6); 1769 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch - 2); 1770 fill_limit_ru_each(rtwdev, 2, lmt_ru, band, ntx, ch + 2); 1771 fill_limit_ru_each(rtwdev, 3, lmt_ru, band, ntx, ch + 6); 1772 } 1773 1774 static void phy_fill_limit_ru_160m_be(struct rtw89_dev *rtwdev, 1775 struct rtw89_txpwr_limit_ru_be *lmt_ru, 1776 u8 band, u8 ntx, u8 ch) 1777 { 1778 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 14); 1779 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch - 10); 1780 fill_limit_ru_each(rtwdev, 2, lmt_ru, band, ntx, ch - 6); 1781 fill_limit_ru_each(rtwdev, 3, lmt_ru, band, ntx, ch - 2); 1782 fill_limit_ru_each(rtwdev, 4, lmt_ru, band, ntx, ch + 2); 1783 fill_limit_ru_each(rtwdev, 5, lmt_ru, band, ntx, ch + 6); 1784 fill_limit_ru_each(rtwdev, 6, lmt_ru, band, ntx, ch + 10); 1785 fill_limit_ru_each(rtwdev, 7, lmt_ru, band, ntx, ch + 14); 1786 } 1787 1788 static void phy_fill_limit_ru_320m_be(struct rtw89_dev *rtwdev, 1789 struct rtw89_txpwr_limit_ru_be *lmt_ru, 1790 u8 band, u8 ntx, u8 ch) 1791 { 1792 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 30); 1793 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch - 26); 1794 fill_limit_ru_each(rtwdev, 2, lmt_ru, band, ntx, ch - 22); 1795 fill_limit_ru_each(rtwdev, 3, lmt_ru, band, ntx, ch - 18); 1796 fill_limit_ru_each(rtwdev, 4, lmt_ru, band, ntx, ch - 14); 1797 fill_limit_ru_each(rtwdev, 5, lmt_ru, band, ntx, ch - 10); 1798 fill_limit_ru_each(rtwdev, 6, lmt_ru, band, ntx, ch - 6); 1799 fill_limit_ru_each(rtwdev, 7, lmt_ru, band, ntx, ch - 2); 1800 fill_limit_ru_each(rtwdev, 8, lmt_ru, band, ntx, ch + 2); 1801 fill_limit_ru_each(rtwdev, 9, lmt_ru, band, ntx, ch + 6); 1802 fill_limit_ru_each(rtwdev, 10, lmt_ru, band, ntx, ch + 10); 1803 fill_limit_ru_each(rtwdev, 11, lmt_ru, band, ntx, ch + 14); 1804 fill_limit_ru_each(rtwdev, 12, lmt_ru, band, ntx, ch + 18); 1805 fill_limit_ru_each(rtwdev, 13, lmt_ru, band, ntx, ch + 22); 1806 fill_limit_ru_each(rtwdev, 14, lmt_ru, band, ntx, ch + 26); 1807 fill_limit_ru_each(rtwdev, 15, lmt_ru, band, ntx, ch + 30); 1808 } 1809 1810 static void rtw89_phy_fill_limit_ru_be(struct rtw89_dev *rtwdev, 1811 const struct rtw89_chan *chan, 1812 struct rtw89_txpwr_limit_ru_be *lmt_ru, 1813 u8 ntx) 1814 { 1815 u8 band = chan->band_type; 1816 u8 ch = chan->channel; 1817 u8 bw = chan->band_width; 1818 1819 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1820 1821 switch (bw) { 1822 case RTW89_CHANNEL_WIDTH_20: 1823 phy_fill_limit_ru_20m_be(rtwdev, lmt_ru, band, ntx, ch); 1824 break; 1825 case RTW89_CHANNEL_WIDTH_40: 1826 phy_fill_limit_ru_40m_be(rtwdev, lmt_ru, band, ntx, ch); 1827 break; 1828 case RTW89_CHANNEL_WIDTH_80: 1829 phy_fill_limit_ru_80m_be(rtwdev, lmt_ru, band, ntx, ch); 1830 break; 1831 case RTW89_CHANNEL_WIDTH_160: 1832 phy_fill_limit_ru_160m_be(rtwdev, lmt_ru, band, ntx, ch); 1833 break; 1834 case RTW89_CHANNEL_WIDTH_320: 1835 phy_fill_limit_ru_320m_be(rtwdev, lmt_ru, band, ntx, ch); 1836 break; 1837 } 1838 } 1839 1840 static 1841 void rtw89_phy_fill_limit_ru484_242_be(struct rtw89_dev *rtwdev, 1842 s8 (*lmt)[RTW89_RU484_242_SEC_NUM_BE], 1843 u8 ntx, u8 band, u8 ch, u8 bw) 1844 { 1845 switch (bw) { 1846 case RTW89_CHANNEL_WIDTH_80: 1847 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1848 RTW89_RU484_242, 1849 ntx, ch); 1850 break; 1851 case RTW89_CHANNEL_WIDTH_160: 1852 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1853 RTW89_RU484_242, 1854 ntx, ch - 8); 1855 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1856 RTW89_RU484_242, 1857 ntx, ch + 8); 1858 break; 1859 case RTW89_CHANNEL_WIDTH_320: 1860 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1861 RTW89_RU484_242, 1862 ntx, ch - 24); 1863 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1864 RTW89_RU484_242, 1865 ntx, ch - 8); 1866 (*lmt)[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1867 RTW89_RU484_242, 1868 ntx, ch + 8); 1869 (*lmt)[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1870 RTW89_RU484_242, 1871 ntx, ch + 24); 1872 break; 1873 } 1874 } 1875 1876 static 1877 void rtw89_phy_fill_limit_ru996_484_be(struct rtw89_dev *rtwdev, 1878 s8 (*lmt)[RTW89_RU996_484_SEC_NUM_BE], 1879 u8 ntx, u8 band, u8 ch, u8 bw) 1880 { 1881 switch (bw) { 1882 case RTW89_CHANNEL_WIDTH_160: 1883 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1884 RTW89_RU996_484, 1885 ntx, ch); 1886 break; 1887 case RTW89_CHANNEL_WIDTH_320: 1888 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1889 RTW89_RU996_484, 1890 ntx, ch - 16); 1891 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1892 RTW89_RU996_484, 1893 ntx, ch + 16); 1894 break; 1895 } 1896 } 1897 1898 static 1899 void rtw89_phy_fill_limit_ru996_484_242_be(struct rtw89_dev *rtwdev, 1900 s8 (*lmt)[RTW89_RU996_484_242_SEC_NUM_BE], 1901 u8 ntx, u8 band, u8 ch, u8 bw) 1902 { 1903 switch (bw) { 1904 case RTW89_CHANNEL_WIDTH_160: 1905 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1906 RTW89_RU996_484_242, 1907 ntx, ch); 1908 break; 1909 case RTW89_CHANNEL_WIDTH_320: 1910 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1911 RTW89_RU996_484_242, 1912 ntx, ch - 16); 1913 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1914 RTW89_RU996_484_242, 1915 ntx, ch + 16); 1916 break; 1917 } 1918 } 1919 1920 static 1921 void rtw89_phy_fill_limit_large_mru_be(struct rtw89_dev *rtwdev, 1922 const struct rtw89_chan *chan, 1923 struct rtw89_txpwr_limit_large_mru_be *lmt, 1924 bool has_bf) 1925 { 1926 u8 band = chan->band_type; 1927 u8 ch = chan->channel; 1928 u8 bw = chan->band_width; 1929 int i; 1930 1931 memset(lmt, 0, sizeof(*lmt)); 1932 1933 if (has_bf) 1934 return; 1935 1936 for (i = 0; i <= RTW89_NSS_2; i++) { 1937 rtw89_phy_fill_limit_ru484_242_be(rtwdev, &lmt->ru484_242[i], 1938 i, band, ch, bw); 1939 rtw89_phy_fill_limit_ru996_484_be(rtwdev, &lmt->ru996_484[i], 1940 i, band, ch, bw); 1941 rtw89_phy_fill_limit_ru996_484_242_be(rtwdev, &lmt->ru996_484_242[i], 1942 i, band, ch, bw); 1943 } 1944 } 1945 1946 static 1947 void rtw89_phy_conf_limit_large_mru_be(struct rtw89_dev *rtwdev, 1948 const struct rtw89_chan *chan, 1949 enum rtw89_phy_idx phy_idx, 1950 bool has_bf) 1951 { 1952 struct rtw89_txpwr_limit_large_mru_be lmt_lmru; 1953 u32 addr, val; 1954 1955 rtw89_phy_fill_limit_large_mru_be(rtwdev, chan, &lmt_lmru, has_bf); 1956 1957 addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU484_242_0 : 1958 R_BE_TXAGC_MAX_1TX_RU484_242_0; 1959 1960 val = u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][0], GENMASK(7, 0)) | 1961 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][1], GENMASK(15, 8)) | 1962 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][2], GENMASK(23, 16)) | 1963 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][3], GENMASK(31, 24)); 1964 1965 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1966 1967 val = u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][0], GENMASK(7, 0)) | 1968 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][1], GENMASK(15, 8)) | 1969 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][2], GENMASK(23, 16)) | 1970 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][3], GENMASK(31, 24)); 1971 1972 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr + 4, val); 1973 1974 addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU996_484_0 : 1975 R_BE_TXAGC_MAX_1TX_RU996_484_0; 1976 1977 val = u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_1][0], GENMASK(7, 0)) | 1978 u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_1][1], GENMASK(15, 8)) | 1979 u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_2][0], GENMASK(23, 16)) | 1980 u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_2][1], GENMASK(31, 24)); 1981 1982 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1983 1984 addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU996_484_242_0 : 1985 R_BE_TXAGC_MAX_1TX_RU996_484_242_0; 1986 1987 val = u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_1][0], GENMASK(7, 0)) | 1988 u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_1][1], GENMASK(15, 8)) | 1989 u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_2][0], GENMASK(23, 16)) | 1990 u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_2][1], GENMASK(31, 24)); 1991 1992 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1993 } 1994 1995 static void rtw89_phy_set_txpwr_limit_ru_be(struct rtw89_dev *rtwdev, 1996 const struct rtw89_chan *chan, 1997 enum rtw89_phy_idx phy_idx) 1998 { 1999 const struct rtw89_chip_info *chip = rtwdev->chip; 2000 struct rtw89_txpwr_limit_ru_be lmt_ru; 2001 struct rtw89_hal *hal = &rtwdev->hal; 2002 const s8 *ptr; 2003 u32 addr, val; 2004 u8 i, j; 2005 2006 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_be) != 2007 RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE); 2008 2009 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2010 "[TXPWR] set txpwr limit ru on band %d bw %d\n", 2011 chan->band_type, chan->band_width); 2012 2013 addr = R_BE_PWR_RU_LMT; 2014 for (i = 0; i <= RTW89_NSS_2; i++) { 2015 rtw89_phy_fill_limit_ru_be(rtwdev, chan, &lmt_ru, i); 2016 2017 ptr = (s8 *)&lmt_ru; 2018 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE; 2019 j += 4, addr += 4, ptr += 4) { 2020 val = u32_encode_bits(ptr[0], GENMASK(7, 0)) | 2021 u32_encode_bits(ptr[1], GENMASK(15, 8)) | 2022 u32_encode_bits(ptr[2], GENMASK(23, 16)) | 2023 u32_encode_bits(ptr[3], GENMASK(31, 24)); 2024 2025 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2026 } 2027 } 2028 2029 if (!(chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)) 2030 return; 2031 2032 rtw89_phy_conf_limit_large_mru_be(rtwdev, chan, phy_idx, false); 2033 rtw89_phy_conf_limit_large_mru_be(rtwdev, chan, phy_idx, true); 2034 } 2035 2036 const struct rtw89_phy_gen_def rtw89_phy_gen_be = { 2037 .cr_base = 0x20000, 2038 .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START, 2039 .physt_bmp_eht = R_PHY_STS_BITMAP_EHT, 2040 .physt_ie_len = {32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 2041 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN, 2042 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32}, 2043 .physt_gen = 1, 2044 .ccx = &rtw89_ccx_regs_be, 2045 .physts = &rtw89_physts_regs_be, 2046 .cfo = &rtw89_cfo_regs_be, 2047 .bb_wrap = &rtw89_bb_wrap_regs_be, 2048 .nctl = &rtw89_nctl_regs_be, 2049 .phy0_phy1_offset = rtw89_phy0_phy1_offset_be, 2050 .config_bb_gain = rtw89_phy_config_bb_gain_be, 2051 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be, 2052 .bb_wrap_init = rtw89_phy_bb_wrap_init_be, 2053 .ch_info_init = rtw89_phy_ch_info_init_be, 2054 .btc_bttrx_en = rtw89_phy_btc_bttrx_en_be, 2055 2056 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be, 2057 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_be, 2058 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_be, 2059 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be, 2060 }; 2061 EXPORT_SYMBOL(rtw89_phy_gen_be); 2062 2063 const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = { 2064 .cr_base = 0x0, 2065 .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START_BE4, 2066 .physt_bmp_eht = R_PHY_STS_BITMAP_EHT_BE4, 2067 .physt_ie_len = {32, 40, 24, 24, 16, 16, 16, 16, VAR_LEN, VAR_LEN, VAR_LEN, 168, 2068 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 32, 56, 2069 96, VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32}, 2070 .physt_gen = 2, 2071 .ccx = &rtw89_ccx_regs_be_v1, 2072 .physts = &rtw89_physts_regs_be_v1, 2073 .cfo = &rtw89_cfo_regs_be_v1, 2074 .bb_wrap = &rtw89_bb_wrap_regs_be_v1, 2075 .nctl = &rtw89_nctl_regs_be_v1, 2076 .phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1, 2077 .config_bb_gain = rtw89_phy_config_bb_gain_be, 2078 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1, 2079 .bb_wrap_init = rtw89_phy_bb_wrap_init_be, 2080 .ch_info_init = rtw89_phy_ch_info_init_be_v1, 2081 .btc_bttrx_en = rtw89_phy_btc_bttrx_en_be, 2082 2083 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be, 2084 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_be, 2085 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_be, 2086 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be, 2087 }; 2088 EXPORT_SYMBOL(rtw89_phy_gen_be_v1); 2089