1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2023 Realtek Corporation
3 */
4
5 #include "chan.h"
6 #include "debug.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10
11 static const struct rtw89_ccx_regs rtw89_ccx_regs_be = {
12 .setting_addr = R_CCX,
13 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1,
14 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
15 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
16 .en_mask = B_CCX_EN_MSK,
17 .ifs_cnt_addr = R_IFS_COUNTER,
18 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
19 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
20 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
21 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
22 .ifs_t1_addr = R_IFS_T1,
23 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
24 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
25 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
26 .ifs_t2_addr = R_IFS_T2,
27 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
28 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
29 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
30 .ifs_t3_addr = R_IFS_T3,
31 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
32 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
33 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
34 .ifs_t4_addr = R_IFS_T4,
35 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
36 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
37 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
38 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_V1,
39 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
40 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
41 .ifs_clm_cca_addr = R_IFS_CLM_CCA_V1,
42 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
43 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
44 .ifs_clm_fa_addr = R_IFS_CLM_FA_V1,
45 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
46 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
47 .ifs_his_addr = R_IFS_HIS_V1,
48 .ifs_his_addr2 = R_IFS_HIS_V1,
49 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
50 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
51 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
52 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
53 .ifs_avg_l_addr = R_IFS_AVG_L_V1,
54 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
55 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
56 .ifs_avg_h_addr = R_IFS_AVG_H_V1,
57 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
58 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
59 .ifs_cca_l_addr = R_IFS_CCA_L_V1,
60 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
61 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
62 .ifs_cca_h_addr = R_IFS_CCA_H_V1,
63 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
64 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
65 .ifs_total_addr = R_IFSCNT_V1,
66 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
67 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
68 .nhm = R_NHM_BE,
69 .nhm_ready = B_NHM_READY_BE_MSK,
70 .nhm_config = R_NHM_CFG,
71 .nhm_period_mask = B_NHM_PERIOD_MSK,
72 .nhm_unit_mask = B_NHM_COUNTER_MSK,
73 .nhm_include_cca_mask = B_NHM_INCLUDE_CCA_MSK,
74 .nhm_en_mask = B_NHM_EN_MSK,
75 .nhm_method = R_NHM_TH9,
76 .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK,
77 .edcca_clm_rdy = R_CLM_EDCCA_RDY_V1,
78 .edcca_clm_rdy_mask = B_CLM_EDCCA_RDY,
79 .edcca_clm_cnt = R_CLM_EDCCA_RESULT_V1,
80 .edcca_clm_cnt_mask = B_CLM_EDCCA_RESULT,
81 };
82
83 static const struct rtw89_ccx_regs rtw89_ccx_regs_be_v1 = {
84 .setting_addr = R_CCX_BE4,
85 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1,
86 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
87 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
88 .en_mask = B_CCX_EN_MSK,
89 .ifs_cnt_addr = R_IFS_COUNTER_BE4,
90 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
91 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
92 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
93 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
94 .ifs_t1_addr = R_IFS_T1_BE4,
95 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
96 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
97 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
98 .ifs_t2_addr = R_IFS_T2_BE4,
99 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
100 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
101 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
102 .ifs_t3_addr = R_IFS_T3_BE4,
103 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
104 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
105 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
106 .ifs_t4_addr = R_IFS_T4_BE4,
107 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
108 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
109 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
110 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_BE4,
111 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
112 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
113 .ifs_clm_cca_addr = R_IFS_CLM_CCA_BE4,
114 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
115 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
116 .ifs_clm_fa_addr = R_IFS_CLM_FA_BE4,
117 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
118 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
119 .ifs_his_addr = R_IFS_T1_HIS_BE4,
120 .ifs_his_addr2 = R_IFS_T3_HIS_BE4, /* for 3/4 */
121 .ifs_t4_his_mask = B_IFS_T4_HIS_BE4,
122 .ifs_t3_his_mask = B_IFS_T3_HIS_BE4,
123 .ifs_t2_his_mask = B_IFS_T2_HIS_BE4,
124 .ifs_t1_his_mask = B_IFS_T1_HIS_BE4,
125 .ifs_avg_l_addr = R_IFS_T1_AVG_BE4,
126 .ifs_t2_avg_mask = B_IFS_T2_AVG_BE4,
127 .ifs_t1_avg_mask = B_IFS_T1_AVG_BE4,
128 .ifs_avg_h_addr = R_IFS_T3_AVG_BE4,
129 .ifs_t4_avg_mask = B_IFS_T4_AVG_BE4,
130 .ifs_t3_avg_mask = B_IFS_T3_AVG_BE4,
131 .ifs_cca_l_addr = R_IFS_T1_CLM_BE4,
132 .ifs_t2_cca_mask = B_IFS_T2_CLM_BE4,
133 .ifs_t1_cca_mask = B_IFS_T1_CLM_BE4,
134 .ifs_cca_h_addr = R_IFS_T3_CLM_BE4,
135 .ifs_t4_cca_mask = B_IFS_T4_CLM_BE4,
136 .ifs_t3_cca_mask = B_IFS_T3_CLM_BE4,
137 .ifs_total_addr = R_IFS_TOTAL_BE4,
138 .ifs_cnt_done_mask = B_IFS_CNT_DONE_BE4,
139 .ifs_total_mask = B_IFS_TOTAL_BE4,
140 .edcca_clm_rdy = R_CLM_EDCCA_RDY_BE4,
141 .edcca_clm_rdy_mask = B_CLM_EDCCA_RDY,
142 .edcca_clm_cnt = R_CLM_EDCCA_RESULT_BE4,
143 .edcca_clm_cnt_mask = B_CLM_EDCCA_RESULT,
144 };
145
146 static const u32 rtw89_tx_info_reg_be[] = {
147 R_TX_INFO_0_0_COMB_V1,
148 R_TX_INFO_0_1_COMB_V1,
149 R_TX_INFO_1_0_COMB_V1,
150 R_TX_INFO_1_1_COMB_V1,
151 R_TX_INFO_2_0_COMB_V1,
152 R_TX_INFO_2_1_COMB_V1
153 };
154
155 static const u32 rtw89_tx_common_ctrl_reg_be[] = {
156 R_TX_COMMON_CTRL_0_0_COMB_V1,
157 R_TX_COMMON_CTRL_0_1_COMB_V1
158 };
159
160 static const struct rtw89_reg_def rtw89_txpwr_be[] = {
161 {.addr = R_PATH0_TXPWR_V1, .mask = B_PATH0_TXPWR},
162 {.addr = R_PATH1_TXPWR_V1, .mask = B_PATH1_TXPWR}
163 };
164
165 static const struct rtw89_physts_regs rtw89_physts_regs_be = {
166 .setting_addr = R_PLCP_HISTOGRAM,
167 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
168 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
169 .mac_phy_intf_sel = {R_INTF_R_INTF_RPT_SEL, B_INTF_R_INTF_RPT_SEL},
170 .txpwr = rtw89_txpwr_be,
171 .tx_info = RTW89_REGS_DEF(rtw89_tx_info_reg_be),
172 .tx_common_ctrl = RTW89_REGS_DEF(rtw89_tx_common_ctrl_reg_be),
173 };
174
175 static const u32 rtw89_tx_info_reg_be_v1[] = {
176 R_TX_INFO_0_0_COMB_BE4,
177 R_TX_INFO_0_1_COMB_BE4,
178 R_TX_INFO_1_0_COMB_BE4,
179 R_TX_INFO_1_1_COMB_BE4,
180 R_TX_INFO_2_0_COMB_BE4,
181 R_TX_INFO_2_1_COMB_BE4
182 };
183
184 static const u32 rtw89_tx_common_ctrl_reg_be_v1[] = {
185 R_TX_COMMON_CTRL_0_0_COMB_BE4,
186 R_TX_COMMON_CTRL_0_1_COMB_BE4
187 };
188
189 static const struct rtw89_reg_def rtw89_txpwr_be_v1[] = {
190 {.addr = R_PATH0_TXPWR_BE4, .mask = B_PATH0_TXPWR},
191 {.addr = R_PATH1_TXPWR_BE4, .mask = B_PATH1_TXPWR}
192 };
193
194 static const struct rtw89_physts_regs rtw89_physts_regs_be_v1 = {
195 .setting_addr = R_PLCP_HISTOGRAM_BE_V1,
196 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
197 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
198 .mac_phy_intf_sel = {R_INTF_R_INTF_RPT_SEL_BE4, B_INTF_R_INTF_RPT_SEL},
199 .txpwr = rtw89_txpwr_be_v1,
200 .tx_info = RTW89_REGS_DEF(rtw89_tx_info_reg_be_v1),
201 .tx_common_ctrl = RTW89_REGS_DEF(rtw89_tx_common_ctrl_reg_be_v1),
202 };
203
204 static const struct rtw89_cfo_regs rtw89_cfo_regs_be = {
205 .comp = R_DCFO_WEIGHT_BE,
206 .weighting_mask = B_DCFO_WEIGHT_MSK_BE,
207 .comp_seg0 = R_DCFO_OPT_BE,
208 .valid_0_mask = B_DCFO_OPT_EN_BE,
209 };
210
211 static const struct rtw89_cfo_regs rtw89_cfo_regs_be_v1 = {
212 .comp = R_DCFO_WEIGHT_BE_V1,
213 .weighting_mask = B_DCFO_WEIGHT_MSK_BE,
214 .comp_seg0 = R_DCFO_OPT_BE_V1,
215 .valid_0_mask = B_DCFO_OPT_EN_BE,
216 };
217
218 static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be = {
219 .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE,
220 .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE,
221 };
222
223 static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be_v1 = {
224 .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE_V1,
225 .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE_V1,
226 };
227
228 static const struct rtw89_nctl_regs rtw89_nctl_regs_be = {
229 .cfg = R_NCTL_CFG,
230 .rw = R_NCTL_RW,
231 };
232
233 static const struct rtw89_nctl_regs rtw89_nctl_regs_be_v1 = {
234 .cfg = R_NCTL_CFG_BE4,
235 .rw = R_NCTL_RW_BE4,
236 };
237
rtw89_phy0_phy1_offset_be(struct rtw89_dev * rtwdev,u32 addr)238 static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr)
239 {
240 u32 phy_page = addr >> 8;
241 u32 ofst = 0;
242
243 if ((phy_page >= 0x4 && phy_page <= 0xF) ||
244 (phy_page >= 0x20 && phy_page <= 0x2B) ||
245 (phy_page >= 0x40 && phy_page <= 0x4f) ||
246 (phy_page >= 0x60 && phy_page <= 0x6f) ||
247 (phy_page >= 0xE4 && phy_page <= 0xE5) ||
248 (phy_page >= 0xE8 && phy_page <= 0xED))
249 ofst = 0x1000;
250 else
251 ofst = 0x0;
252
253 return ofst;
254 }
255
rtw89_phy0_phy1_offset_be_v1(struct rtw89_dev * rtwdev,u32 addr)256 static u32 rtw89_phy0_phy1_offset_be_v1(struct rtw89_dev *rtwdev, u32 addr)
257 {
258 u32 phy_page = addr >> 8;
259 u32 ofst = 0;
260
261 if ((phy_page >= 0x204 && phy_page <= 0x20F) ||
262 (phy_page >= 0x220 && phy_page <= 0x22F) ||
263 (phy_page >= 0x240 && phy_page <= 0x24f) ||
264 (phy_page >= 0x260 && phy_page <= 0x26f) ||
265 (phy_page >= 0x2C0 && phy_page <= 0x2C9) ||
266 (phy_page >= 0x2E0 && phy_page <= 0x2E8) ||
267 phy_page == 0x2EE)
268 ofst = 0x1000;
269 else
270 ofst = 0x0;
271
272 return ofst;
273 }
274
275 union rtw89_phy_bb_gain_arg_be {
276 u32 addr;
277 struct {
278 u8 type;
279 #define BB_GAIN_TYPE_SUB0_BE GENMASK(3, 0)
280 #define BB_GAIN_TYPE_SUB1_BE GENMASK(7, 4)
281 u8 path_bw;
282 #define BB_GAIN_PATH_BE GENMASK(3, 0)
283 #define BB_GAIN_BW_BE GENMASK(7, 4)
284 u8 gain_band;
285 u8 cfg_type;
286 } __packed;
287 } __packed;
288
289 static void
rtw89_phy_cfg_bb_gain_error_be(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg_be arg,u32 data)290 rtw89_phy_cfg_bb_gain_error_be(struct rtw89_dev *rtwdev,
291 union rtw89_phy_bb_gain_arg_be arg, u32 data)
292 {
293 struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
294 u8 bw_type = u8_get_bits(arg.path_bw, BB_GAIN_BW_BE);
295 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE);
296 u8 gband = arg.gain_band;
297 u8 type = arg.type;
298 int i;
299
300 switch (type) {
301 case 0:
302 for (i = 0; i < 4; i++, data >>= 8)
303 gain->lna_gain[gband][bw_type][path][i] = data & 0xff;
304 break;
305 case 1:
306 for (i = 4; i < 7; i++, data >>= 8)
307 gain->lna_gain[gband][bw_type][path][i] = data & 0xff;
308 break;
309 case 2:
310 for (i = 0; i < 2; i++, data >>= 8)
311 gain->tia_gain[gband][bw_type][path][i] = data & 0xff;
312 break;
313 default:
314 rtw89_warn(rtwdev,
315 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
316 arg.addr, data, type);
317 break;
318 }
319 }
320
321 static void
rtw89_phy_cfg_bb_rpl_ofst_be(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg_be arg,u32 data)322 rtw89_phy_cfg_bb_rpl_ofst_be(struct rtw89_dev *rtwdev,
323 union rtw89_phy_bb_gain_arg_be arg, u32 data)
324 {
325 struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
326 u8 type_sub0 = u8_get_bits(arg.type, BB_GAIN_TYPE_SUB0_BE);
327 u8 type_sub1 = u8_get_bits(arg.type, BB_GAIN_TYPE_SUB1_BE);
328 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE);
329 u8 gband = arg.gain_band;
330 u8 ofst = 0;
331 int i;
332
333 switch (type_sub1) {
334 case RTW89_CMAC_BW_20M:
335 gain->rpl_ofst_20[gband][path][0] = (s8)data;
336 break;
337 case RTW89_CMAC_BW_40M:
338 for (i = 0; i < RTW89_BW20_SC_40M; i++, data >>= 8)
339 gain->rpl_ofst_40[gband][path][i] = data & 0xff;
340 break;
341 case RTW89_CMAC_BW_80M:
342 for (i = 0; i < RTW89_BW20_SC_80M; i++, data >>= 8)
343 gain->rpl_ofst_80[gband][path][i] = data & 0xff;
344 break;
345 case RTW89_CMAC_BW_160M:
346 if (type_sub0 == 0)
347 ofst = 0;
348 else
349 ofst = RTW89_BW20_SC_80M;
350
351 for (i = 0; i < RTW89_BW20_SC_80M; i++, data >>= 8)
352 gain->rpl_ofst_160[gband][path][i + ofst] = data & 0xff;
353 break;
354 default:
355 rtw89_warn(rtwdev,
356 "bb rpl ofst {0x%x:0x%x} with unknown type_sub1: %d\n",
357 arg.addr, data, type_sub1);
358 break;
359 }
360 }
361
362 static void
rtw89_phy_cfg_bb_gain_op1db_be(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg_be arg,u32 data)363 rtw89_phy_cfg_bb_gain_op1db_be(struct rtw89_dev *rtwdev,
364 union rtw89_phy_bb_gain_arg_be arg, u32 data)
365 {
366 struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
367 u8 bw_type = u8_get_bits(arg.path_bw, BB_GAIN_BW_BE);
368 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE);
369 u8 gband = arg.gain_band;
370 u8 type = arg.type;
371 int i;
372
373 switch (type) {
374 case 0:
375 for (i = 0; i < 4; i++, data >>= 8)
376 gain->lna_op1db[gband][bw_type][path][i] = data & 0xff;
377 break;
378 case 1:
379 for (i = 4; i < 7; i++, data >>= 8)
380 gain->lna_op1db[gband][bw_type][path][i] = data & 0xff;
381 break;
382 case 2:
383 for (i = 0; i < 4; i++, data >>= 8)
384 gain->tia_lna_op1db[gband][bw_type][path][i] = data & 0xff;
385 break;
386 case 3:
387 for (i = 4; i < 8; i++, data >>= 8)
388 gain->tia_lna_op1db[gband][bw_type][path][i] = data & 0xff;
389 break;
390 default:
391 rtw89_warn(rtwdev,
392 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
393 arg.addr, data, type);
394 break;
395 }
396 }
397
rtw89_phy_config_bb_gain_be(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)398 static void rtw89_phy_config_bb_gain_be(struct rtw89_dev *rtwdev,
399 const struct rtw89_reg2_def *reg,
400 enum rtw89_rf_path rf_path,
401 void *extra_data)
402 {
403 const struct rtw89_chip_info *chip = rtwdev->chip;
404 union rtw89_phy_bb_gain_arg_be arg = { .addr = reg->addr };
405 struct rtw89_efuse *efuse = &rtwdev->efuse;
406 u8 bw_type = u8_get_bits(arg.path_bw, BB_GAIN_BW_BE);
407 u8 path = u8_get_bits(arg.path_bw, BB_GAIN_PATH_BE);
408
409 if (bw_type >= RTW89_BB_BW_NR_BE)
410 return;
411
412 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR_BE)
413 return;
414
415 if (path >= chip->rf_path_num)
416 return;
417
418 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
419 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
420 return;
421 }
422
423 switch (arg.cfg_type) {
424 case 0:
425 rtw89_phy_cfg_bb_gain_error_be(rtwdev, arg, reg->data);
426 break;
427 case 1:
428 rtw89_phy_cfg_bb_rpl_ofst_be(rtwdev, arg, reg->data);
429 break;
430 case 2:
431 /* ignore BB gain bypass */
432 break;
433 case 3:
434 rtw89_phy_cfg_bb_gain_op1db_be(rtwdev, arg, reg->data);
435 break;
436 case 15:
437 rtw89_phy_write32_idx(rtwdev, reg->addr & 0xFFFFF, MASKHWORD,
438 reg->data, RTW89_PHY_0);
439 break;
440 case 4:
441 /* This cfg_type is only used by rfe_type >= 50 with eFEM */
442 if (efuse->rfe_type < 50)
443 break;
444 fallthrough;
445 default:
446 rtw89_warn(rtwdev,
447 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
448 arg.addr, reg->data, arg.cfg_type);
449 break;
450 }
451 }
452
rtw89_phy_preinit_rf_nctl_check_be(struct rtw89_dev * rtwdev)453 static void rtw89_phy_preinit_rf_nctl_check_be(struct rtw89_dev *rtwdev)
454 {
455 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
456 const struct rtw89_nctl_regs *nctl = phy->nctl;
457 int poll;
458 u32 val;
459
460 rtw89_phy_write32(rtwdev, nctl->cfg, B_NCTL_CHK_EN);
461
462 for (poll = 0; poll < 10000; poll++) {
463 rtw89_phy_write32(rtwdev, nctl->rw, B_NCTL_CHECK);
464
465 fsleep(10);
466
467 val = rtw89_phy_read32(rtwdev, nctl->rw);
468 if (val == B_NCTL_CHECK)
469 return;
470 }
471
472 rtw89_warn(rtwdev, "NCTL INIT check 0x%x[2]TIMEOUT!\n", nctl->rw);
473 }
474
rtw89_phy_preinit_rf_nctl_be(struct rtw89_dev * rtwdev)475 static void rtw89_phy_preinit_rf_nctl_be(struct rtw89_dev *rtwdev)
476 {
477 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C0, B_GOTX_IQKDPK, 0x3);
478 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C1, B_GOTX_IQKDPK, 0x3);
479 rtw89_phy_write32_mask(rtwdev, R_IQKDPK_HC, B_IQKDPK_HC, 0x1);
480 rtw89_phy_write32_mask(rtwdev, R_CLK_GCK, B_CLK_GCK, 0x00fffff);
481 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_CLKEN, 0x3);
482 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST, B_IQK_DPK_RST, 0x1);
483 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST, B_IQK_DPK_PRST, 0x1);
484 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1, B_IQK_DPK_PRST, 0x1);
485 rtw89_phy_write32_mask(rtwdev, R_TXRFC, B_TXRFC_RST, 0x1);
486
487 if (rtwdev->dbcc_en) {
488 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_C1, B_IQK_DPK_RST, 0x1);
489 rtw89_phy_write32_mask(rtwdev, R_TXRFC_C1, B_TXRFC_RST, 0x1);
490 }
491
492 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_RX_CFIR_PATH_EN, 0x1);
493 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_RX_CFIR_PATH, 0x3);
494
495 rtw89_phy_preinit_rf_nctl_check_be(rtwdev);
496 }
497
rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev * rtwdev)498 static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev)
499 {
500 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C0_BE4, B_GOTX_IQKDPK, 0x3);
501 rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C1_BE4, B_GOTX_IQKDPK, 0x3);
502 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK_BE4, B_IOQ_IQK_DPK_RST, 0x1);
503 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_BE4, B_IQK_DPK_RST, 0x1);
504 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_BE4, B_IQK_DPK_PRST, 0x1);
505 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1_BE4, B_IQK_DPK_PRST, 0x1);
506
507 rtw89_phy_preinit_rf_nctl_check_be(rtwdev);
508 }
509
rtw89_phy_bb_wrap_flush_addr(struct rtw89_dev * rtwdev,u32 addr)510 static u32 rtw89_phy_bb_wrap_flush_addr(struct rtw89_dev *rtwdev, u32 addr)
511 {
512 struct rtw89_hal *hal = &rtwdev->hal;
513
514 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
515 return 0;
516
517 if (rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7025) {
518 if (addr >= R_BE_PWR_MACID_PATH_BASE_V1 &&
519 addr <= R_BE_PWR_MACID_PATH_BASE_V1 + 0xFF)
520 return addr + 0x800;
521
522 if (addr >= R_BE_PWR_MACID_LMT_BASE_V1 &&
523 addr <= R_BE_PWR_MACID_LMT_BASE_V1 + 0xFF)
524 return addr - 0x800;
525 }
526
527 return 0;
528 }
529
530 static
rtw89_write_bb_wrap_flush(struct rtw89_dev * rtwdev,u32 addr,u32 data)531 void rtw89_write_bb_wrap_flush(struct rtw89_dev *rtwdev, u32 addr, u32 data)
532 {
533 /* To write registers of pwr_macid_lmt and pwr_macid_path with flush */
534 u32 flush_addr;
535 u32 val32;
536
537 flush_addr = rtw89_phy_bb_wrap_flush_addr(rtwdev, addr);
538 if (flush_addr) {
539 val32 = rtw89_read32(rtwdev, flush_addr);
540 rtw89_write32(rtwdev, flush_addr, val32);
541 }
542
543 rtw89_write32(rtwdev, addr, data);
544 }
545
546 static
rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev * rtwdev)547 void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev)
548 {
549 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
550 const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap;
551 u32 max_macid = rtwdev->chip->support_macid_num;
552 u32 macid_idx, cr, base_macid_lmt;
553
554 base_macid_lmt = bb_wrap->pwr_macid_lmt;
555
556 for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) {
557 cr = base_macid_lmt + macid_idx;
558 rtw89_write_bb_wrap_flush(rtwdev, cr, 0);
559 }
560 }
561
562 static
rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev * rtwdev)563 void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev)
564 {
565 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
566 const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap;
567 u32 max_macid = rtwdev->chip->support_macid_num;
568 u32 cr = bb_wrap->pwr_macid_path;
569 int i;
570
571 for (i = 0; i < max_macid; i++, cr += 4)
572 rtw89_write_bb_wrap_flush(rtwdev, cr, 0);
573 }
574
rtw89_phy_bb_wrap_tpu_set_all(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)575 static void rtw89_phy_bb_wrap_tpu_set_all(struct rtw89_dev *rtwdev,
576 enum rtw89_mac_idx mac_idx)
577 {
578 u32 addr, t;
579
580 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM_SS, mac_idx);
581 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_BY_RATE_DBW_ON, 0x3);
582
583 for (addr = R_BE_PWR_BY_RATE; addr <= R_BE_PWR_BY_RATE_END; addr += 4) {
584 t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx);
585 rtw89_write32(rtwdev, t, 0);
586 }
587 for (addr = R_BE_PWR_RULMT_START; addr <= R_BE_PWR_RULMT_END; addr += 4) {
588 t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx);
589 rtw89_write32(rtwdev, t, 0);
590 }
591 for (addr = R_BE_PWR_RATE_OFST_CTRL; addr <= R_BE_PWR_RATE_OFST_END; addr += 4) {
592 t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx);
593 rtw89_write32(rtwdev, t, 0);
594 }
595
596 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_REF_CTRL, mac_idx);
597 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMT_DB, 0);
598 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_LMTBF, mac_idx);
599 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMTBF_DB, 0);
600 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RATE_CTRL, mac_idx);
601 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_BYRATE_DB, 0);
602 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_RULMT, mac_idx);
603 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_RULMT_DB, 0);
604 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_SW, mac_idx);
605 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_SW_DB, 0);
606 }
607
608 static
rtw89_phy_bb_wrap_listen_path_en_init(struct rtw89_dev * rtwdev)609 void rtw89_phy_bb_wrap_listen_path_en_init(struct rtw89_dev *rtwdev)
610 {
611 u32 addr;
612 int ret;
613
614 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
615 if (ret)
616 return;
617
618 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_LISTEN_PATH, RTW89_MAC_1);
619 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_LISTEN_PATH_EN, 0x2);
620 }
621
rtw89_phy_bb_wrap_force_cr_init(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)622 static void rtw89_phy_bb_wrap_force_cr_init(struct rtw89_dev *rtwdev,
623 enum rtw89_mac_idx mac_idx)
624 {
625 u32 addr;
626
627 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FORCE_LMT, mac_idx);
628 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_LMT_ON, 0);
629 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RATE_CTRL, mac_idx);
630 rtw89_write32_mask(rtwdev, addr, B_BE_FORCE_PWR_BY_RATE_EN, 0);
631 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_RULMT, mac_idx);
632 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ENON, 0);
633 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ON, 0);
634 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FORCE_MACID, mac_idx);
635 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_MACID_ALL, 0);
636 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_COEX_CTRL, mac_idx);
637 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_COEX_ON, 0);
638 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, mac_idx);
639 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RATE_ON, 0);
640 }
641
rtw89_phy_bb_wrap_ftm_init(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)642 static void rtw89_phy_bb_wrap_ftm_init(struct rtw89_dev *rtwdev,
643 enum rtw89_mac_idx mac_idx)
644 {
645 u32 addr;
646
647 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM, mac_idx);
648 rtw89_write32(rtwdev, addr, 0xE4E431);
649
650 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM_SS, mac_idx);
651 rtw89_write32_mask(rtwdev, addr, 0x7, 0);
652 }
653
rtw89_phy_bb_wrap_be_bandedge_decision(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)654 static u32 rtw89_phy_bb_wrap_be_bandedge_decision(struct rtw89_dev *rtwdev,
655 const struct rtw89_chan *chan)
656 {
657 u8 pri_ch = chan->primary_channel;
658 u32 val = 0;
659
660 switch (chan->band_type) {
661 default:
662 case RTW89_BAND_2G:
663 if (pri_ch == 1 || pri_ch == 13)
664 val = BIT(1) | BIT(0);
665 else if (pri_ch == 5 || pri_ch == 9)
666 val = BIT(1);
667 break;
668 case RTW89_BAND_5G:
669 if (pri_ch == 36 || pri_ch == 64 || pri_ch == 100)
670 val = BIT(3) | BIT(2) | BIT(1) | BIT(0);
671 else if (pri_ch == 40 || pri_ch == 60 || pri_ch == 104)
672 val = BIT(3) | BIT(2) | BIT(1);
673 else if ((pri_ch > 40 && pri_ch < 60) || pri_ch == 108 || pri_ch == 112)
674 val = BIT(3) | BIT(2);
675 else if (pri_ch > 112 && pri_ch < 132)
676 val = BIT(3);
677 break;
678 case RTW89_BAND_6G:
679 break;
680 }
681
682 return val;
683 }
684
rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev * rtwdev,enum rtw89_rfsi_ctrl_band rfsi_band,enum rtw89_phy_idx phy_idx)685 void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev,
686 enum rtw89_rfsi_ctrl_band rfsi_band,
687 enum rtw89_phy_idx phy_idx)
688 {
689 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
690 const u32 *val;
691 u32 reg;
692
693 if (!d || !d->common)
694 return;
695
696 val = d->common->bands[rfsi_band].rfsi_ct_opt;
697
698 reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_0_BE4, phy_idx);
699 rtw89_write32(rtwdev, reg, val[0]);
700
701 reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_8_BE4, phy_idx);
702 rtw89_write32(rtwdev, reg, val[1]);
703 }
704 EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_ct_opt);
705
rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)706 void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev,
707 const struct rtw89_chan *chan,
708 enum rtw89_phy_idx phy_idx)
709 {
710 bool cfr_manual_en = false;
711 u32 reg;
712 u32 val;
713
714 val = rtw89_phy_bb_wrap_be_bandedge_decision(rtwdev, chan);
715
716 if (chan->band_type == RTW89_BAND_2G &&
717 ((chan->primary_channel == 13 && chan->band_width == RTW89_CHANNEL_WIDTH_20) ||
718 (chan->primary_channel == 11 && chan->band_width == RTW89_CHANNEL_WIDTH_40)))
719 cfr_manual_en = true;
720
721 rtw89_phy_write32_idx(rtwdev, R_TX_CFR_MANUAL_EN_BE4, B_TX_CFR_MANUAL_EN_BE4_M,
722 cfr_manual_en, phy_idx);
723
724 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx);
725 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW20_BE4, val & BIT(0));
726 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx);
727 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW40_BE4, (val & BIT(1)) >> 1);
728 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx);
729 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW80_BE4, (val & BIT(2)) >> 2);
730 reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWY_BE4, phy_idx);
731 rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW160_BE4, (val & BIT(3)) >> 3);
732 }
733 EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_bandedge_ch);
734
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)735 static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev *rtwdev,
736 enum rtw89_mac_idx mac_idx)
737 {
738 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
739 u8 th0, th1, th2;
740
741 if (!d || !d->common)
742 return;
743
744 th0 = d->common->qam_th[0];
745 th1 = d->common->qam_th[1];
746 th2 = d->common->qam_th[2];
747
748 /* TH0 */
749 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_0_BE4, th0, mac_idx);
750 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_3_BE4, th0, mac_idx);
751 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_1_BE4, th0, mac_idx);
752 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_4_BE4, th0, mac_idx);
753 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_7_BE4, th0, mac_idx);
754 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_0_BE4, th0, mac_idx);
755 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_3_BE4, th0, mac_idx);
756 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_6_BE4, th0, mac_idx);
757 /* TH1 */
758 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_1_BE4, th1, mac_idx);
759 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_4_BE4, th1, mac_idx);
760 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_2_BE4, th1, mac_idx);
761 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_5_BE4, th1, mac_idx);
762 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_8_BE4, th1, mac_idx);
763 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_1_BE4, th1, mac_idx);
764 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_4_BE4, th1, mac_idx);
765 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_7_BE4, th1, mac_idx);
766 /* TH2 */
767 rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_2_BE4, th2, mac_idx);
768 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_0_BE4, th2, mac_idx);
769 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_3_BE4, th2, mac_idx);
770 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_6_BE4, th2, mac_idx);
771 rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_9_BE4, th2, mac_idx);
772 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_2_BE4, th2, mac_idx);
773 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_5_BE4, th2, mac_idx);
774 rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_8_BE4, th2, mac_idx);
775 /* DPD 160M */
776 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_0_BE4, th0, mac_idx);
777 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_1_BE4, th0, mac_idx);
778 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_2_BE4, th0, mac_idx);
779 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_3_BE4, th0, mac_idx);
780 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_4_BE4, th0, mac_idx);
781 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_5_BE4, th0, mac_idx);
782 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_6_BE4, th0, mac_idx);
783 rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_7_BE4, th0, mac_idx);
784 /* DPD 20M */
785 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_0_BE4, 0x2, mac_idx);
786 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_1_BE4, 0x2, mac_idx);
787 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_2_BE4, 0x2, mac_idx);
788 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_3_BE4, 0x2, mac_idx);
789 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_4_BE4, 0x2, mac_idx);
790 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_5_BE4, 0x2, mac_idx);
791 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_6_BE4, 0x2, mac_idx);
792 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH1_7_BE4, 0x2, mac_idx);
793 /* DPD 40M */
794 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_0_BE4, 0x2, mac_idx);
795 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_1_BE4, 0x2, mac_idx);
796 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_2_BE4, 0x2, mac_idx);
797 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_3_BE4, 0x2, mac_idx);
798 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_4_BE4, 0x2, mac_idx);
799 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_3_BE4, 0x2, mac_idx);
800 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_4_BE4, 0x2, mac_idx);
801 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_5_BE4, 0x2, mac_idx);
802 /* DPD 80M */
803 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW80_TH1_0_BE4, 0x2, mac_idx);
804 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_1_BE4, 0x2, mac_idx);
805 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_2_BE4, 0x2, mac_idx);
806 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_3_BE4, 0x2, mac_idx);
807 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_4_BE4, 0x2, mac_idx);
808 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_5_BE4, 0x2, mac_idx);
809 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_6_BE4, 0x2, mac_idx);
810 rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_7_BE4, 0x2, mac_idx);
811 /* CIM3K */
812 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH2_BE4, 0x2, mac_idx);
813 }
814
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx)815 static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(struct rtw89_dev *rtwdev,
816 const struct rtw89_chan *chan,
817 enum rtw89_mac_idx mac_idx)
818 {
819 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
820 const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
821 const u8 *ths;
822
823 if (!d || !d->common_gen3)
824 return;
825
826 common_gen3 = d->common_gen3;
827 ths = common_gen3->bands[chan->rfsi_band].qam_th;
828
829 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_0_BE4, ths[0], mac_idx);
830 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_1_BE4, ths[0], mac_idx);
831 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_2_BE4, ths[0], mac_idx);
832 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_3_BE4, ths[0], mac_idx);
833 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_4_BE4, ths[0], mac_idx);
834 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_5_BE4, ths[0], mac_idx);
835 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_6_BE4, ths[0], mac_idx);
836 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_7_BE4, ths[0], mac_idx);
837
838 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_0_BE4, ths[1], mac_idx);
839 rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_1_BE4, ths[1], mac_idx);
840 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_2_BE4, ths[1], mac_idx);
841 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_3_BE4, ths[1], mac_idx);
842 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_4_BE4, ths[1], mac_idx);
843 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_5_BE4, ths[1], mac_idx);
844 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_6_BE4, ths[1], mac_idx);
845 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_7_BE4, ths[1], mac_idx);
846
847 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_0_BE4, ths[2], mac_idx);
848 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_1_BE4, ths[2], mac_idx);
849 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_2_BE4, ths[2], mac_idx);
850 rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_3_BE4, ths[2], mac_idx);
851 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_4_BE4, ths[2], mac_idx);
852 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_5_BE4, ths[2], mac_idx);
853 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_6_BE4, ths[2], mac_idx);
854 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_7_BE4, ths[2], mac_idx);
855
856 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_0_BE4, ths[3], mac_idx);
857 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_1_BE4, ths[3], mac_idx);
858 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_2_BE4, ths[3], mac_idx);
859 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_3_BE4, ths[3], mac_idx);
860 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_4_BE4, ths[3], mac_idx);
861 rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_5_BE4, ths[3], mac_idx);
862 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_6_BE4, ths[3], mac_idx);
863 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_7_BE4, ths[3], mac_idx);
864
865 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_0_BE4, ths[4], mac_idx);
866 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_1_BE4, ths[4], mac_idx);
867 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_2_BE4, ths[4], mac_idx);
868 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_3_BE4, ths[4], mac_idx);
869 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_4_BE4, ths[4], mac_idx);
870 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_5_BE4, ths[4], mac_idx);
871 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_6_BE4, ths[4], mac_idx);
872 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_7_BE4, ths[4], mac_idx);
873
874 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_0_BE4, ths[5], mac_idx);
875 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_1_BE4, ths[5], mac_idx);
876 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_2_BE4, ths[5], mac_idx);
877 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_3_BE4, ths[5], mac_idx);
878 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_4_BE4, ths[5], mac_idx);
879 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_5_BE4, ths[5], mac_idx);
880 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_6_BE4, ths[5], mac_idx);
881 rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_7_BE4, ths[5], mac_idx);
882 }
883
rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)884 static void rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev *rtwdev,
885 enum rtw89_mac_idx mac_idx)
886 {
887 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
888 u8 pb_tb = 0;
889
890 if (d && d->common)
891 pb_tb = d->common->bands[0].pb_tb;
892
893 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_ER_BE4, 0x0, mac_idx);
894 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SUBF_BE4, 0x0, mac_idx);
895 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_FTM_BE4, 0x0, mac_idx);
896 rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SENS_BE4, 0x0, mac_idx);
897
898 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DEF_BE, 0x0, mac_idx);
899 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_PB_BE4, pb_tb, mac_idx);
900 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_WO_BE4, 0x0, mac_idx);
901 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_BF_BE4, 0x0, mac_idx);
902 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_MUMIMO_BE4, 0x0, mac_idx);
903 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_FTM_BE4, 0x0, mac_idx);
904 rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_SENS_BE4, 0x0, mac_idx);
905 }
906
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)907 static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(struct rtw89_dev *rtwdev,
908 enum rtw89_mac_idx mac_idx)
909 {
910 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
911 const u16 *th;
912
913 if (!d || !d->common)
914 return;
915
916 th = d->bands[0].qam_comp_th0;
917 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, th[0], mac_idx);
918 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, th[1], mac_idx);
919 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, th[2], mac_idx);
920 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, th[3], mac_idx);
921 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, th[4], mac_idx);
922 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, th[5], mac_idx);
923 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, th[6], mac_idx);
924 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, th[7], mac_idx);
925
926 th = d->bands[0].qam_comp_th1;
927 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_L, th[0], mac_idx);
928 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_M, th[1], mac_idx);
929 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_H, th[2], mac_idx);
930 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_L, th[3], mac_idx);
931 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_M, th[4], mac_idx);
932 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_H, th[5], mac_idx);
933 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_L, th[6], mac_idx);
934 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_M, th[7], mac_idx);
935
936 th = d->bands[0].qam_comp_th2;
937 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2L, th[0], mac_idx);
938 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2M, th[1], mac_idx);
939 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2H, th[2], mac_idx);
940 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2L, th[3], mac_idx);
941 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2M, th[4], mac_idx);
942 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2H, th[5], mac_idx);
943 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2L, th[6], mac_idx);
944 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2M, th[7], mac_idx);
945
946 th = d->bands[0].qam_comp_ow;
947 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, th[0], mac_idx);
948 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, th[1], mac_idx);
949 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, th[2], mac_idx);
950 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, th[3], mac_idx);
951 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, th[4], mac_idx);
952 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, th[5], mac_idx);
953 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, th[6], mac_idx);
954 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, th[7], mac_idx);
955 }
956
rtw89_phy_bb_set_oob_dpd_qam_comp_val(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)957 static void rtw89_phy_bb_set_oob_dpd_qam_comp_val(struct rtw89_dev *rtwdev,
958 enum rtw89_mac_idx mac_idx)
959 {
960 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
961 u8 th;
962
963 if (!d)
964 return;
965
966 th = d->bands[0].oob_dpd_by_cbw[0];
967 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK0_BE4, th, mac_idx);
968 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK1_BE4, th, mac_idx);
969 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK2_BE4, th, mac_idx);
970 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK3_BE4, th, mac_idx);
971 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK4_BE4, th, mac_idx);
972 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK5_BE4, th, mac_idx);
973 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK6_BE4, th, mac_idx);
974 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK7_BE4, th, mac_idx);
975
976 th = d->bands[0].oob_dpd_by_cbw[1];
977 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK0_BE4, th, mac_idx);
978 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK1_BE4, th, mac_idx);
979 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK2_BE4, th, mac_idx);
980 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK3_BE4, th, mac_idx);
981 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK4_BE4, th, mac_idx);
982 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK5_BE4, th, mac_idx);
983 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK6_BE4, th, mac_idx);
984 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK7_BE4, th, mac_idx);
985
986 th = d->bands[0].oob_dpd_by_cbw[2];
987 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH0_BE4, th, mac_idx);
988 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH1_BE4, th, mac_idx);
989 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH2_BE4, th, mac_idx);
990 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH3_BE4, th, mac_idx);
991 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH4_BE4, th, mac_idx);
992 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH5_BE4, th, mac_idx);
993 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH6_BE4, th, mac_idx);
994 rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH7_BE4, th, mac_idx);
995
996 th = d->bands[0].oob_dpd_by_cbw[3];
997 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH0_BE4, th, mac_idx);
998 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH1_BE4, th, mac_idx);
999 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH2_BE4, th, mac_idx);
1000 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH3_BE4, th, mac_idx);
1001 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH4_BE4, th, mac_idx);
1002 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH5_BE4, th, mac_idx);
1003 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH6_BE4, th, mac_idx);
1004 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH7_BE4, th, mac_idx);
1005
1006 th = d->bands[0].oob_dpd_by_cbw[4];
1007 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH0_BE4, th, mac_idx);
1008 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH1_BE4, th, mac_idx);
1009 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH2_BE4, th, mac_idx);
1010 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH3_BE4, th, mac_idx);
1011 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH4_BE4, th, mac_idx);
1012 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH5_BE4, th, mac_idx);
1013 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH6_BE4, th, mac_idx);
1014 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH7_BE4, th, mac_idx);
1015
1016 th = d->bands[0].oob_dpd_by_cbw[5];
1017 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW0_BE4, th, mac_idx);
1018 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW1_BE4, th, mac_idx);
1019 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW2_BE4, th, mac_idx);
1020 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW3_BE4, th, mac_idx);
1021 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW4_BE4, th, mac_idx);
1022 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW5_BE4, th, mac_idx);
1023 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW6_BE4, th, mac_idx);
1024 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW7_BE4, th, mac_idx);
1025
1026 th = d->bands[0].oob_dpd_by_cbw[6];
1027 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW0_BE4, th, mac_idx);
1028 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW1_BE4, th, mac_idx);
1029 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW2_BE4, th, mac_idx);
1030 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW3_BE4, th, mac_idx);
1031 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW4_BE4, th, mac_idx);
1032 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW5_BE4, th, mac_idx);
1033 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW6_BE4, th, mac_idx);
1034 rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW7_BE4, th, mac_idx);
1035
1036 th = d->bands[0].oob_dpd_by_cbw[7];
1037 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW0_BE4, th, mac_idx);
1038 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW1_BE4, th, mac_idx);
1039 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW2_BE4, th, mac_idx);
1040 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW3_BE4, th, mac_idx);
1041 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW4_BE4, th, mac_idx);
1042 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW5_BE4, th, mac_idx);
1043 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW6_BE4, th, mac_idx);
1044 rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW7_BE4, th, mac_idx);
1045 }
1046
rtw89_phy_bb_set_mdpd_qam_comp_val(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)1047 static void rtw89_phy_bb_set_mdpd_qam_comp_val(struct rtw89_dev *rtwdev,
1048 enum rtw89_mac_idx mac_idx)
1049 {
1050 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
1051 u8 th;
1052
1053 if (!d)
1054 return;
1055
1056 th = d->mdpd_by_dbw[0];
1057 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH0_BE4, th, mac_idx);
1058 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH1_BE4, th, mac_idx);
1059 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH2_BE4, th, mac_idx);
1060 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH3_BE4, th, mac_idx);
1061 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH4_BE4, th, mac_idx);
1062 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH5_BE4, th, mac_idx);
1063 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH6_BE4, th, mac_idx);
1064 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH7_BE4, th, mac_idx);
1065
1066 th = d->mdpd_by_dbw[2];
1067 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW0_BE4, th, mac_idx);
1068 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW1_BE4, th, mac_idx);
1069 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW2_BE4, th, mac_idx);
1070 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW3_BE4, th, mac_idx);
1071 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW4_BE4, th, mac_idx);
1072 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW5_BE4, th, mac_idx);
1073 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW6_BE4, th, mac_idx);
1074 rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW7_BE4, th, mac_idx);
1075 }
1076
rtw89_phy_bb_set_cim3k_val(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)1077 static void rtw89_phy_bb_set_cim3k_val(struct rtw89_dev *rtwdev,
1078 enum rtw89_mac_idx mac_idx)
1079 {
1080 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
1081 const struct rtw89_bb_wrap_data_cim3k *p;
1082
1083 if (!d || !d->common)
1084 return;
1085
1086 p = &d->common->bands[0].cim3k;
1087
1088 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, p->th, mac_idx);
1089 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, p->ow, mac_idx);
1090 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4,
1091 p->non_bandedge, mac_idx);
1092 rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4,
1093 p->bandedge, mac_idx);
1094
1095 if (rtwdev->chip->chip_id != RTL8922D)
1096 return;
1097
1098 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_EN, 1, mac_idx);
1099 rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_VAL, 0, mac_idx);
1100 }
1101
rtw89_phy_bb_set_cck_cfir_filter_val_gen3(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)1102 static void rtw89_phy_bb_set_cck_cfir_filter_val_gen3(struct rtw89_dev *rtwdev,
1103 enum rtw89_mac_idx mac_idx)
1104 {
1105 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
1106 const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
1107 u8 cck0, cck1;
1108
1109 if (!d || !d->common_gen3)
1110 return;
1111
1112 common_gen3 = d->common_gen3;
1113 cck0 = common_gen3->cck_val[0];
1114 cck1 = common_gen3->cck_val[1];
1115
1116 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR0_BE4, cck0, mac_idx);
1117 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR1_BE4, cck0, mac_idx);
1118 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR2_BE4, cck0, mac_idx);
1119 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR3_BE4, cck0, mac_idx);
1120 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR4_BE4, cck0, mac_idx);
1121 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR5_BE4, cck0, mac_idx);
1122 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR6_BE4, cck0, mac_idx);
1123 rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR7_BE4, cck0, mac_idx);
1124
1125 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR0_BE4, cck1, mac_idx);
1126 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR1_BE4, cck1, mac_idx);
1127 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR2_BE4, cck1, mac_idx);
1128 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR3_BE4, cck1, mac_idx);
1129 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR4_BE4, cck1, mac_idx);
1130 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR5_BE4, cck1, mac_idx);
1131 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR6_BE4, cck1, mac_idx);
1132 rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR7_BE4, cck1, mac_idx);
1133 }
1134
rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)1135 static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev,
1136 enum rtw89_mac_idx mac_idx)
1137 {
1138 enum rtw89_phy_idx phy_idx = mac_idx != RTW89_MAC_0 ? RTW89_PHY_1 : RTW89_PHY_0;
1139 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1140 struct rtw89_entity_conf conf;
1141 const struct rtw89_chan *chan;
1142
1143 if (chip_id != RTL8922D)
1144 return;
1145
1146 rtw89_entity_get_conf(rtwdev, &conf);
1147 chan = conf.chans[phy_idx];
1148
1149 rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(rtwdev, mac_idx);
1150 rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(rtwdev, chan, mac_idx);
1151 rtw89_phy_bb_wrap_tx_rfsi_scenario_def(rtwdev, mac_idx);
1152 rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(rtwdev, mac_idx);
1153 rtw89_phy_bb_set_oob_dpd_qam_comp_val(rtwdev, mac_idx);
1154 rtw89_phy_bb_set_mdpd_qam_comp_val(rtwdev, mac_idx);
1155 rtw89_phy_bb_set_cim3k_val(rtwdev, mac_idx);
1156 rtw89_phy_bb_set_cck_cfir_filter_val_gen3(rtwdev, mac_idx);
1157 rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, 0, phy_idx);
1158 rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx);
1159 }
1160
rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev * rtwdev)1161 static void rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev *rtwdev)
1162 {
1163 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1164 u8 mac_idx;
1165 u32 addr;
1166
1167 if (chip_id != RTL8922A)
1168 return;
1169
1170 for (mac_idx = 0; mac_idx < RTW89_MAC_NUM; mac_idx++) {
1171 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RSSI_TARGET_LMT, mac_idx);
1172 rtw89_write32(rtwdev, addr, 0x0201FE00);
1173 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_TH, mac_idx);
1174 rtw89_write32(rtwdev, addr, 0x00FFEC7E);
1175 }
1176 }
1177
__rtw89_phy_bb_wrap_init_be(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx)1178 static void __rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev,
1179 enum rtw89_mac_idx mac_idx)
1180 {
1181 rtw89_phy_bb_wrap_tx_path_by_macid_init(rtwdev);
1182 rtw89_phy_bb_wrap_pwr_by_macid_init(rtwdev);
1183 rtw89_phy_bb_wrap_tpu_set_all(rtwdev, mac_idx);
1184 rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(rtwdev, mac_idx);
1185 rtw89_phy_bb_wrap_force_cr_init(rtwdev, mac_idx);
1186 rtw89_phy_bb_wrap_ftm_init(rtwdev, mac_idx);
1187 rtw89_phy_bb_wrap_listen_path_en_init(rtwdev);
1188 rtw89_phy_bb_wrap_ul_pwr(rtwdev);
1189 }
1190
rtw89_phy_bb_wrap_init_be(struct rtw89_dev * rtwdev)1191 static void rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev)
1192 {
1193 __rtw89_phy_bb_wrap_init_be(rtwdev, RTW89_MAC_0);
1194 if (rtwdev->dbcc_en)
1195 __rtw89_phy_bb_wrap_init_be(rtwdev, RTW89_MAC_1);
1196 }
1197
rtw89_phy_ch_info_init_be(struct rtw89_dev * rtwdev)1198 static void rtw89_phy_ch_info_init_be(struct rtw89_dev *rtwdev)
1199 {
1200 rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG, B_CHINFO_SEG_LEN, 0x0);
1201 rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG, B_CHINFO_SEG, 0xf);
1202 rtw89_phy_write32_mask(rtwdev, R_CHINFO_DATA, B_CHINFO_DATA_BITMAP, 0x1);
1203 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ELM_SRC, B_CHINFO_ELM_BITMAP, 0x40303);
1204 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ELM_SRC, B_CHINFO_SRC, 0x0);
1205 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_TYPE_SCAL, B_CHINFO_TYPE, 0x3);
1206 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_TYPE_SCAL, B_CHINFO_SCAL, 0x0);
1207 }
1208
rtw89_phy_ch_info_init_be_v1(struct rtw89_dev * rtwdev)1209 static void rtw89_phy_ch_info_init_be_v1(struct rtw89_dev *rtwdev)
1210 {
1211 rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG_BE4, B_CHINFO_SEG_LEN_BE4, 0);
1212 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_OPT_BE4, B_CHINFO_OPT_BE4, 0x3);
1213 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_NX_BE4, B_CHINFO_NX_BE4, 0x669);
1214 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ALG_BE4, B_CHINFO_ALG_BE4, 0);
1215 }
1216
1217 struct rtw89_byr_spec_ent_be {
1218 struct rtw89_rate_desc init;
1219 u8 num_of_idx;
1220 bool no_over_bw40;
1221 bool no_multi_nss;
1222 };
1223
1224 static const struct rtw89_byr_spec_ent_be rtw89_byr_spec_be[] = {
1225 {
1226 .init = { .rs = RTW89_RS_CCK },
1227 .num_of_idx = RTW89_RATE_CCK_NUM,
1228 .no_over_bw40 = true,
1229 .no_multi_nss = true,
1230 },
1231 {
1232 .init = { .rs = RTW89_RS_OFDM },
1233 .num_of_idx = RTW89_RATE_OFDM_NUM,
1234 .no_multi_nss = true,
1235 },
1236 {
1237 .init = { .rs = RTW89_RS_MCS, .idx = 14, .ofdma = RTW89_NON_OFDMA },
1238 .num_of_idx = 2,
1239 .no_multi_nss = true,
1240 },
1241 {
1242 .init = { .rs = RTW89_RS_MCS, .idx = 14, .ofdma = RTW89_OFDMA },
1243 .num_of_idx = 2,
1244 .no_multi_nss = true,
1245 },
1246 {
1247 .init = { .rs = RTW89_RS_MCS, .ofdma = RTW89_NON_OFDMA },
1248 .num_of_idx = 14,
1249 },
1250 {
1251 .init = { .rs = RTW89_RS_HEDCM, .ofdma = RTW89_NON_OFDMA },
1252 .num_of_idx = RTW89_RATE_HEDCM_NUM,
1253 },
1254 {
1255 .init = { .rs = RTW89_RS_MCS, .ofdma = RTW89_OFDMA },
1256 .num_of_idx = 14,
1257 },
1258 {
1259 .init = { .rs = RTW89_RS_HEDCM, .ofdma = RTW89_OFDMA },
1260 .num_of_idx = RTW89_RATE_HEDCM_NUM,
1261 },
1262 };
1263
1264 static
__phy_set_txpwr_byrate_be(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 nss,u32 * addr,enum rtw89_phy_idx phy_idx)1265 void __phy_set_txpwr_byrate_be(struct rtw89_dev *rtwdev, u8 band, u8 bw,
1266 u8 nss, u32 *addr, enum rtw89_phy_idx phy_idx)
1267 {
1268 const struct rtw89_byr_spec_ent_be *ent;
1269 struct rtw89_rate_desc desc;
1270 int pos = 0;
1271 int i, j;
1272 u32 val;
1273 s8 v[4];
1274
1275 for (i = 0; i < ARRAY_SIZE(rtw89_byr_spec_be); i++) {
1276 ent = &rtw89_byr_spec_be[i];
1277
1278 if (bw > RTW89_CHANNEL_WIDTH_40 && ent->no_over_bw40)
1279 continue;
1280 if (nss > RTW89_NSS_1 && ent->no_multi_nss)
1281 continue;
1282
1283 desc = ent->init;
1284 desc.nss = nss;
1285 for (j = 0; j < ent->num_of_idx; j++, desc.idx++) {
1286 v[pos] = rtw89_phy_read_txpwr_byrate(rtwdev, band, bw,
1287 &desc);
1288 pos = (pos + 1) % 4;
1289 if (pos)
1290 continue;
1291
1292 val = u32_encode_bits(v[0], GENMASK(7, 0)) |
1293 u32_encode_bits(v[1], GENMASK(15, 8)) |
1294 u32_encode_bits(v[2], GENMASK(23, 16)) |
1295 u32_encode_bits(v[3], GENMASK(31, 24));
1296
1297 rtw89_mac_txpwr_write32(rtwdev, phy_idx, *addr, val);
1298 *addr += 4;
1299 }
1300 }
1301 }
1302
rtw89_phy_set_txpwr_byrate_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1303 static void rtw89_phy_set_txpwr_byrate_be(struct rtw89_dev *rtwdev,
1304 const struct rtw89_chan *chan,
1305 enum rtw89_phy_idx phy_idx)
1306 {
1307 u32 addr = R_BE_PWR_BY_RATE;
1308 u8 band = chan->band_type;
1309 u8 bw, nss;
1310
1311 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1312 "[TXPWR] set txpwr byrate on band %d\n", band);
1313
1314 for (bw = 0; bw <= RTW89_CHANNEL_WIDTH_320; bw++)
1315 for (nss = 0; nss <= RTW89_NSS_2; nss++)
1316 __phy_set_txpwr_byrate_be(rtwdev, band, bw, nss,
1317 &addr, phy_idx);
1318 }
1319
rtw89_phy_set_txpwr_offset_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1320 static void rtw89_phy_set_txpwr_offset_be(struct rtw89_dev *rtwdev,
1321 const struct rtw89_chan *chan,
1322 enum rtw89_phy_idx phy_idx)
1323 {
1324 struct rtw89_rate_desc desc = {
1325 .nss = RTW89_NSS_1,
1326 .rs = RTW89_RS_OFFSET,
1327 };
1328 u8 band = chan->band_type;
1329 s8 v[RTW89_RATE_OFFSET_NUM_BE] = {};
1330 u32 val;
1331
1332 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1333 "[TXPWR] set txpwr offset on band %d\n", band);
1334
1335 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_BE; desc.idx++)
1336 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
1337
1338 val = u32_encode_bits(v[RTW89_RATE_OFFSET_CCK], GENMASK(3, 0)) |
1339 u32_encode_bits(v[RTW89_RATE_OFFSET_OFDM], GENMASK(7, 4)) |
1340 u32_encode_bits(v[RTW89_RATE_OFFSET_HT], GENMASK(11, 8)) |
1341 u32_encode_bits(v[RTW89_RATE_OFFSET_VHT], GENMASK(15, 12)) |
1342 u32_encode_bits(v[RTW89_RATE_OFFSET_HE], GENMASK(19, 16)) |
1343 u32_encode_bits(v[RTW89_RATE_OFFSET_EHT], GENMASK(23, 20)) |
1344 u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_HE], GENMASK(27, 24)) |
1345 u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_EHT], GENMASK(31, 28));
1346
1347 rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_BE_PWR_RATE_OFST_CTRL, val);
1348 }
1349
1350 static void
fill_limit_nonbf_bf(struct rtw89_dev * rtwdev,s8 (* ptr)[RTW89_BF_NUM],u8 band,u8 bw,u8 ntx,u8 rs,u8 ch)1351 fill_limit_nonbf_bf(struct rtw89_dev *rtwdev, s8 (*ptr)[RTW89_BF_NUM],
1352 u8 band, u8 bw, u8 ntx, u8 rs, u8 ch)
1353 {
1354 int bf;
1355
1356 for (bf = 0; bf < RTW89_BF_NUM; bf++)
1357 (*ptr)[bf] = rtw89_phy_read_txpwr_limit(rtwdev, band, bw, ntx,
1358 rs, bf, ch);
1359 }
1360
1361 static void
fill_limit_nonbf_bf_min(struct rtw89_dev * rtwdev,s8 (* ptr)[RTW89_BF_NUM],u8 band,u8 bw,u8 ntx,u8 rs,u8 ch1,u8 ch2)1362 fill_limit_nonbf_bf_min(struct rtw89_dev *rtwdev, s8 (*ptr)[RTW89_BF_NUM],
1363 u8 band, u8 bw, u8 ntx, u8 rs, u8 ch1, u8 ch2)
1364 {
1365 s8 v1[RTW89_BF_NUM];
1366 s8 v2[RTW89_BF_NUM];
1367 int bf;
1368
1369 fill_limit_nonbf_bf(rtwdev, &v1, band, bw, ntx, rs, ch1);
1370 fill_limit_nonbf_bf(rtwdev, &v2, band, bw, ntx, rs, ch2);
1371
1372 for (bf = 0; bf < RTW89_BF_NUM; bf++)
1373 (*ptr)[bf] = min(v1[bf], v2[bf]);
1374 }
1375
phy_fill_limit_20m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_be * lmt,u8 band,u8 ntx,u8 ch)1376 static void phy_fill_limit_20m_be(struct rtw89_dev *rtwdev,
1377 struct rtw89_txpwr_limit_be *lmt,
1378 u8 band, u8 ntx, u8 ch)
1379 {
1380 fill_limit_nonbf_bf(rtwdev, &lmt->cck_20m, band,
1381 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_CCK, ch);
1382 fill_limit_nonbf_bf(rtwdev, &lmt->cck_40m, band,
1383 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_CCK, ch);
1384 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band,
1385 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, ch);
1386 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band,
1387 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch);
1388 }
1389
phy_fill_limit_40m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_be * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)1390 static void phy_fill_limit_40m_be(struct rtw89_dev *rtwdev,
1391 struct rtw89_txpwr_limit_be *lmt,
1392 u8 band, u8 ntx, u8 ch, u8 pri_ch)
1393 {
1394 fill_limit_nonbf_bf(rtwdev, &lmt->cck_20m, band,
1395 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_CCK, ch - 2);
1396 fill_limit_nonbf_bf(rtwdev, &lmt->cck_40m, band,
1397 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_CCK, ch);
1398
1399 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band,
1400 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch);
1401
1402 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band,
1403 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2);
1404 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band,
1405 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2);
1406 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band,
1407 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch);
1408 }
1409
phy_fill_limit_80m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_be * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)1410 static void phy_fill_limit_80m_be(struct rtw89_dev *rtwdev,
1411 struct rtw89_txpwr_limit_be *lmt,
1412 u8 band, u8 ntx, u8 ch, u8 pri_ch)
1413 {
1414 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band,
1415 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch);
1416
1417 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band,
1418 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 6);
1419 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band,
1420 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2);
1421 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[2], band,
1422 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2);
1423 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[3], band,
1424 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 6);
1425 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band,
1426 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 4);
1427 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[1], band,
1428 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 4);
1429 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[0], band,
1430 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch);
1431
1432 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_0p5, band,
1433 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS,
1434 ch - 4, ch + 4);
1435 }
1436
phy_fill_limit_160m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_be * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)1437 static void phy_fill_limit_160m_be(struct rtw89_dev *rtwdev,
1438 struct rtw89_txpwr_limit_be *lmt,
1439 u8 band, u8 ntx, u8 ch, u8 pri_ch)
1440 {
1441 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band,
1442 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch);
1443
1444 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band,
1445 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 14);
1446 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band,
1447 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 10);
1448 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[2], band,
1449 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 6);
1450 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[3], band,
1451 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2);
1452 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[4], band,
1453 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2);
1454 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[5], band,
1455 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 6);
1456 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[6], band,
1457 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 10);
1458 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[7], band,
1459 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 14);
1460
1461 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band,
1462 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 12);
1463 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[1], band,
1464 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 4);
1465 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[2], band,
1466 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 4);
1467 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[3], band,
1468 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 12);
1469
1470 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[0], band,
1471 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch - 8);
1472 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[1], band,
1473 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch + 8);
1474
1475 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_160m[0], band,
1476 RTW89_CHANNEL_WIDTH_160, ntx, RTW89_RS_MCS, ch);
1477
1478 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_0p5, band,
1479 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS,
1480 ch - 12, ch - 4);
1481 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_2p5, band,
1482 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS,
1483 ch + 4, ch + 12);
1484 }
1485
phy_fill_limit_320m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_be * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)1486 static void phy_fill_limit_320m_be(struct rtw89_dev *rtwdev,
1487 struct rtw89_txpwr_limit_be *lmt,
1488 u8 band, u8 ntx, u8 ch, u8 pri_ch)
1489 {
1490 fill_limit_nonbf_bf(rtwdev, &lmt->ofdm, band,
1491 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, pri_ch);
1492
1493 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[0], band,
1494 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 30);
1495 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[1], band,
1496 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 26);
1497 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[2], band,
1498 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 22);
1499 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[3], band,
1500 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 18);
1501 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[4], band,
1502 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 14);
1503 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[5], band,
1504 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 10);
1505 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[6], band,
1506 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 6);
1507 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[7], band,
1508 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch - 2);
1509 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[8], band,
1510 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 2);
1511 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[9], band,
1512 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 6);
1513 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[10], band,
1514 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 10);
1515 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[11], band,
1516 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 14);
1517 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[12], band,
1518 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 18);
1519 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[13], band,
1520 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 22);
1521 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[14], band,
1522 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 26);
1523 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_20m[15], band,
1524 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch + 30);
1525
1526 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[0], band,
1527 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 28);
1528 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[1], band,
1529 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 20);
1530 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[2], band,
1531 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 12);
1532 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[3], band,
1533 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch - 4);
1534 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[4], band,
1535 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 4);
1536 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[5], band,
1537 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 12);
1538 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[6], band,
1539 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 20);
1540 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_40m[7], band,
1541 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS, ch + 28);
1542
1543 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[0], band,
1544 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch - 24);
1545 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[1], band,
1546 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch - 8);
1547 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[2], band,
1548 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch + 8);
1549 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_80m[3], band,
1550 RTW89_CHANNEL_WIDTH_80, ntx, RTW89_RS_MCS, ch + 24);
1551
1552 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_160m[0], band,
1553 RTW89_CHANNEL_WIDTH_160, ntx, RTW89_RS_MCS, ch - 16);
1554 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_160m[1], band,
1555 RTW89_CHANNEL_WIDTH_160, ntx, RTW89_RS_MCS, ch + 16);
1556
1557 fill_limit_nonbf_bf(rtwdev, &lmt->mcs_320m, band,
1558 RTW89_CHANNEL_WIDTH_320, ntx, RTW89_RS_MCS, ch);
1559
1560 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_0p5, band,
1561 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS,
1562 ch - 28, ch - 20);
1563 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_2p5, band,
1564 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS,
1565 ch - 12, ch - 4);
1566 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_4p5, band,
1567 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS,
1568 ch + 4, ch + 12);
1569 fill_limit_nonbf_bf_min(rtwdev, &lmt->mcs_40m_6p5, band,
1570 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_MCS,
1571 ch + 20, ch + 28);
1572 }
1573
rtw89_phy_fill_limit_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_be * lmt,u8 ntx)1574 static void rtw89_phy_fill_limit_be(struct rtw89_dev *rtwdev,
1575 const struct rtw89_chan *chan,
1576 struct rtw89_txpwr_limit_be *lmt,
1577 u8 ntx)
1578 {
1579 u8 band = chan->band_type;
1580 u8 pri_ch = chan->primary_channel;
1581 u8 ch = chan->channel;
1582 u8 bw = chan->band_width;
1583
1584 memset(lmt, 0, sizeof(*lmt));
1585
1586 switch (bw) {
1587 case RTW89_CHANNEL_WIDTH_20:
1588 phy_fill_limit_20m_be(rtwdev, lmt, band, ntx, ch);
1589 break;
1590 case RTW89_CHANNEL_WIDTH_40:
1591 phy_fill_limit_40m_be(rtwdev, lmt, band, ntx, ch, pri_ch);
1592 break;
1593 case RTW89_CHANNEL_WIDTH_80:
1594 phy_fill_limit_80m_be(rtwdev, lmt, band, ntx, ch, pri_ch);
1595 break;
1596 case RTW89_CHANNEL_WIDTH_160:
1597 phy_fill_limit_160m_be(rtwdev, lmt, band, ntx, ch, pri_ch);
1598 break;
1599 case RTW89_CHANNEL_WIDTH_320:
1600 phy_fill_limit_320m_be(rtwdev, lmt, band, ntx, ch, pri_ch);
1601 break;
1602 }
1603 }
1604
rtw89_phy_set_txpwr_limit_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1605 static void rtw89_phy_set_txpwr_limit_be(struct rtw89_dev *rtwdev,
1606 const struct rtw89_chan *chan,
1607 enum rtw89_phy_idx phy_idx)
1608 {
1609 struct rtw89_txpwr_limit_be lmt;
1610 const s8 *ptr;
1611 u32 addr, val;
1612 u8 i, j;
1613
1614 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_be) !=
1615 RTW89_TXPWR_LMT_PAGE_SIZE_BE);
1616
1617 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1618 "[TXPWR] set txpwr limit on band %d bw %d\n",
1619 chan->band_type, chan->band_width);
1620
1621 addr = R_BE_PWR_LMT;
1622 for (i = 0; i <= RTW89_NSS_2; i++) {
1623 rtw89_phy_fill_limit_be(rtwdev, chan, &lmt, i);
1624
1625 ptr = (s8 *)&lmt;
1626 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_BE;
1627 j += 4, addr += 4, ptr += 4) {
1628 val = u32_encode_bits(ptr[0], GENMASK(7, 0)) |
1629 u32_encode_bits(ptr[1], GENMASK(15, 8)) |
1630 u32_encode_bits(ptr[2], GENMASK(23, 16)) |
1631 u32_encode_bits(ptr[3], GENMASK(31, 24));
1632
1633 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1634 }
1635 }
1636 }
1637
fill_limit_ru_each(struct rtw89_dev * rtwdev,u8 index,struct rtw89_txpwr_limit_ru_be * lmt_ru,u8 band,u8 ntx,u8 ch)1638 static void fill_limit_ru_each(struct rtw89_dev *rtwdev, u8 index,
1639 struct rtw89_txpwr_limit_ru_be *lmt_ru,
1640 u8 band, u8 ntx, u8 ch)
1641 {
1642 lmt_ru->ru26[index] =
1643 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU26, ntx, ch);
1644 lmt_ru->ru52[index] =
1645 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU52, ntx, ch);
1646 lmt_ru->ru106[index] =
1647 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU106, ntx, ch);
1648 lmt_ru->ru52_26[index] =
1649 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU52_26, ntx, ch);
1650 lmt_ru->ru106_26[index] =
1651 rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU106_26, ntx, ch);
1652 }
1653
phy_fill_limit_ru_20m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_be * lmt_ru,u8 band,u8 ntx,u8 ch)1654 static void phy_fill_limit_ru_20m_be(struct rtw89_dev *rtwdev,
1655 struct rtw89_txpwr_limit_ru_be *lmt_ru,
1656 u8 band, u8 ntx, u8 ch)
1657 {
1658 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch);
1659 }
1660
phy_fill_limit_ru_40m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_be * lmt_ru,u8 band,u8 ntx,u8 ch)1661 static void phy_fill_limit_ru_40m_be(struct rtw89_dev *rtwdev,
1662 struct rtw89_txpwr_limit_ru_be *lmt_ru,
1663 u8 band, u8 ntx, u8 ch)
1664 {
1665 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 2);
1666 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch + 2);
1667 }
1668
phy_fill_limit_ru_80m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_be * lmt_ru,u8 band,u8 ntx,u8 ch)1669 static void phy_fill_limit_ru_80m_be(struct rtw89_dev *rtwdev,
1670 struct rtw89_txpwr_limit_ru_be *lmt_ru,
1671 u8 band, u8 ntx, u8 ch)
1672 {
1673 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 6);
1674 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch - 2);
1675 fill_limit_ru_each(rtwdev, 2, lmt_ru, band, ntx, ch + 2);
1676 fill_limit_ru_each(rtwdev, 3, lmt_ru, band, ntx, ch + 6);
1677 }
1678
phy_fill_limit_ru_160m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_be * lmt_ru,u8 band,u8 ntx,u8 ch)1679 static void phy_fill_limit_ru_160m_be(struct rtw89_dev *rtwdev,
1680 struct rtw89_txpwr_limit_ru_be *lmt_ru,
1681 u8 band, u8 ntx, u8 ch)
1682 {
1683 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 14);
1684 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch - 10);
1685 fill_limit_ru_each(rtwdev, 2, lmt_ru, band, ntx, ch - 6);
1686 fill_limit_ru_each(rtwdev, 3, lmt_ru, band, ntx, ch - 2);
1687 fill_limit_ru_each(rtwdev, 4, lmt_ru, band, ntx, ch + 2);
1688 fill_limit_ru_each(rtwdev, 5, lmt_ru, band, ntx, ch + 6);
1689 fill_limit_ru_each(rtwdev, 6, lmt_ru, band, ntx, ch + 10);
1690 fill_limit_ru_each(rtwdev, 7, lmt_ru, band, ntx, ch + 14);
1691 }
1692
phy_fill_limit_ru_320m_be(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_be * lmt_ru,u8 band,u8 ntx,u8 ch)1693 static void phy_fill_limit_ru_320m_be(struct rtw89_dev *rtwdev,
1694 struct rtw89_txpwr_limit_ru_be *lmt_ru,
1695 u8 band, u8 ntx, u8 ch)
1696 {
1697 fill_limit_ru_each(rtwdev, 0, lmt_ru, band, ntx, ch - 30);
1698 fill_limit_ru_each(rtwdev, 1, lmt_ru, band, ntx, ch - 26);
1699 fill_limit_ru_each(rtwdev, 2, lmt_ru, band, ntx, ch - 22);
1700 fill_limit_ru_each(rtwdev, 3, lmt_ru, band, ntx, ch - 18);
1701 fill_limit_ru_each(rtwdev, 4, lmt_ru, band, ntx, ch - 14);
1702 fill_limit_ru_each(rtwdev, 5, lmt_ru, band, ntx, ch - 10);
1703 fill_limit_ru_each(rtwdev, 6, lmt_ru, band, ntx, ch - 6);
1704 fill_limit_ru_each(rtwdev, 7, lmt_ru, band, ntx, ch - 2);
1705 fill_limit_ru_each(rtwdev, 8, lmt_ru, band, ntx, ch + 2);
1706 fill_limit_ru_each(rtwdev, 9, lmt_ru, band, ntx, ch + 6);
1707 fill_limit_ru_each(rtwdev, 10, lmt_ru, band, ntx, ch + 10);
1708 fill_limit_ru_each(rtwdev, 11, lmt_ru, band, ntx, ch + 14);
1709 fill_limit_ru_each(rtwdev, 12, lmt_ru, band, ntx, ch + 18);
1710 fill_limit_ru_each(rtwdev, 13, lmt_ru, band, ntx, ch + 22);
1711 fill_limit_ru_each(rtwdev, 14, lmt_ru, band, ntx, ch + 26);
1712 fill_limit_ru_each(rtwdev, 15, lmt_ru, band, ntx, ch + 30);
1713 }
1714
rtw89_phy_fill_limit_ru_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru_be * lmt_ru,u8 ntx)1715 static void rtw89_phy_fill_limit_ru_be(struct rtw89_dev *rtwdev,
1716 const struct rtw89_chan *chan,
1717 struct rtw89_txpwr_limit_ru_be *lmt_ru,
1718 u8 ntx)
1719 {
1720 u8 band = chan->band_type;
1721 u8 ch = chan->channel;
1722 u8 bw = chan->band_width;
1723
1724 memset(lmt_ru, 0, sizeof(*lmt_ru));
1725
1726 switch (bw) {
1727 case RTW89_CHANNEL_WIDTH_20:
1728 phy_fill_limit_ru_20m_be(rtwdev, lmt_ru, band, ntx, ch);
1729 break;
1730 case RTW89_CHANNEL_WIDTH_40:
1731 phy_fill_limit_ru_40m_be(rtwdev, lmt_ru, band, ntx, ch);
1732 break;
1733 case RTW89_CHANNEL_WIDTH_80:
1734 phy_fill_limit_ru_80m_be(rtwdev, lmt_ru, band, ntx, ch);
1735 break;
1736 case RTW89_CHANNEL_WIDTH_160:
1737 phy_fill_limit_ru_160m_be(rtwdev, lmt_ru, band, ntx, ch);
1738 break;
1739 case RTW89_CHANNEL_WIDTH_320:
1740 phy_fill_limit_ru_320m_be(rtwdev, lmt_ru, band, ntx, ch);
1741 break;
1742 }
1743 }
1744
1745 static
rtw89_phy_fill_limit_ru484_242_be(struct rtw89_dev * rtwdev,s8 (* lmt)[RTW89_RU484_242_SEC_NUM_BE],u8 ntx,u8 band,u8 ch,u8 bw)1746 void rtw89_phy_fill_limit_ru484_242_be(struct rtw89_dev *rtwdev,
1747 s8 (*lmt)[RTW89_RU484_242_SEC_NUM_BE],
1748 u8 ntx, u8 band, u8 ch, u8 bw)
1749 {
1750 switch (bw) {
1751 case RTW89_CHANNEL_WIDTH_80:
1752 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1753 RTW89_RU484_242,
1754 ntx, ch);
1755 break;
1756 case RTW89_CHANNEL_WIDTH_160:
1757 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1758 RTW89_RU484_242,
1759 ntx, ch - 8);
1760 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1761 RTW89_RU484_242,
1762 ntx, ch + 8);
1763 break;
1764 case RTW89_CHANNEL_WIDTH_320:
1765 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1766 RTW89_RU484_242,
1767 ntx, ch - 24);
1768 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1769 RTW89_RU484_242,
1770 ntx, ch - 8);
1771 (*lmt)[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1772 RTW89_RU484_242,
1773 ntx, ch + 8);
1774 (*lmt)[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1775 RTW89_RU484_242,
1776 ntx, ch + 24);
1777 break;
1778 }
1779 }
1780
1781 static
rtw89_phy_fill_limit_ru996_484_be(struct rtw89_dev * rtwdev,s8 (* lmt)[RTW89_RU996_484_SEC_NUM_BE],u8 ntx,u8 band,u8 ch,u8 bw)1782 void rtw89_phy_fill_limit_ru996_484_be(struct rtw89_dev *rtwdev,
1783 s8 (*lmt)[RTW89_RU996_484_SEC_NUM_BE],
1784 u8 ntx, u8 band, u8 ch, u8 bw)
1785 {
1786 switch (bw) {
1787 case RTW89_CHANNEL_WIDTH_160:
1788 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1789 RTW89_RU996_484,
1790 ntx, ch);
1791 break;
1792 case RTW89_CHANNEL_WIDTH_320:
1793 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1794 RTW89_RU996_484,
1795 ntx, ch - 16);
1796 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1797 RTW89_RU996_484,
1798 ntx, ch + 16);
1799 break;
1800 }
1801 }
1802
1803 static
rtw89_phy_fill_limit_ru996_484_242_be(struct rtw89_dev * rtwdev,s8 (* lmt)[RTW89_RU996_484_242_SEC_NUM_BE],u8 ntx,u8 band,u8 ch,u8 bw)1804 void rtw89_phy_fill_limit_ru996_484_242_be(struct rtw89_dev *rtwdev,
1805 s8 (*lmt)[RTW89_RU996_484_242_SEC_NUM_BE],
1806 u8 ntx, u8 band, u8 ch, u8 bw)
1807 {
1808 switch (bw) {
1809 case RTW89_CHANNEL_WIDTH_160:
1810 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1811 RTW89_RU996_484_242,
1812 ntx, ch);
1813 break;
1814 case RTW89_CHANNEL_WIDTH_320:
1815 (*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1816 RTW89_RU996_484_242,
1817 ntx, ch - 16);
1818 (*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1819 RTW89_RU996_484_242,
1820 ntx, ch + 16);
1821 break;
1822 }
1823 }
1824
1825 static
rtw89_phy_fill_limit_large_mru_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_large_mru_be * lmt,bool has_bf)1826 void rtw89_phy_fill_limit_large_mru_be(struct rtw89_dev *rtwdev,
1827 const struct rtw89_chan *chan,
1828 struct rtw89_txpwr_limit_large_mru_be *lmt,
1829 bool has_bf)
1830 {
1831 u8 band = chan->band_type;
1832 u8 ch = chan->channel;
1833 u8 bw = chan->band_width;
1834 int i;
1835
1836 memset(lmt, 0, sizeof(*lmt));
1837
1838 if (has_bf)
1839 return;
1840
1841 for (i = 0; i <= RTW89_NSS_2; i++) {
1842 rtw89_phy_fill_limit_ru484_242_be(rtwdev, &lmt->ru484_242[i],
1843 i, band, ch, bw);
1844 rtw89_phy_fill_limit_ru996_484_be(rtwdev, &lmt->ru996_484[i],
1845 i, band, ch, bw);
1846 rtw89_phy_fill_limit_ru996_484_242_be(rtwdev, &lmt->ru996_484_242[i],
1847 i, band, ch, bw);
1848 }
1849 }
1850
1851 static
rtw89_phy_conf_limit_large_mru_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx,bool has_bf)1852 void rtw89_phy_conf_limit_large_mru_be(struct rtw89_dev *rtwdev,
1853 const struct rtw89_chan *chan,
1854 enum rtw89_phy_idx phy_idx,
1855 bool has_bf)
1856 {
1857 struct rtw89_txpwr_limit_large_mru_be lmt_lmru;
1858 u32 addr, val;
1859
1860 rtw89_phy_fill_limit_large_mru_be(rtwdev, chan, &lmt_lmru, has_bf);
1861
1862 addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU484_242_0 :
1863 R_BE_TXAGC_MAX_1TX_RU484_242_0;
1864
1865 val = u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][0], GENMASK(7, 0)) |
1866 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][1], GENMASK(15, 8)) |
1867 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][2], GENMASK(23, 16)) |
1868 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][3], GENMASK(31, 24));
1869
1870 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1871
1872 val = u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][0], GENMASK(7, 0)) |
1873 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][1], GENMASK(15, 8)) |
1874 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][2], GENMASK(23, 16)) |
1875 u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][3], GENMASK(31, 24));
1876
1877 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr + 4, val);
1878
1879 addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU996_484_0 :
1880 R_BE_TXAGC_MAX_1TX_RU996_484_0;
1881
1882 val = u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_1][0], GENMASK(7, 0)) |
1883 u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_1][1], GENMASK(15, 8)) |
1884 u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_2][0], GENMASK(23, 16)) |
1885 u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_2][1], GENMASK(31, 24));
1886
1887 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1888
1889 addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU996_484_242_0 :
1890 R_BE_TXAGC_MAX_1TX_RU996_484_242_0;
1891
1892 val = u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_1][0], GENMASK(7, 0)) |
1893 u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_1][1], GENMASK(15, 8)) |
1894 u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_2][0], GENMASK(23, 16)) |
1895 u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_2][1], GENMASK(31, 24));
1896
1897 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1898 }
1899
rtw89_phy_set_txpwr_limit_ru_be(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1900 static void rtw89_phy_set_txpwr_limit_ru_be(struct rtw89_dev *rtwdev,
1901 const struct rtw89_chan *chan,
1902 enum rtw89_phy_idx phy_idx)
1903 {
1904 const struct rtw89_chip_info *chip = rtwdev->chip;
1905 struct rtw89_txpwr_limit_ru_be lmt_ru;
1906 struct rtw89_hal *hal = &rtwdev->hal;
1907 const s8 *ptr;
1908 u32 addr, val;
1909 u8 i, j;
1910
1911 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_be) !=
1912 RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE);
1913
1914 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1915 "[TXPWR] set txpwr limit ru on band %d bw %d\n",
1916 chan->band_type, chan->band_width);
1917
1918 addr = R_BE_PWR_RU_LMT;
1919 for (i = 0; i <= RTW89_NSS_2; i++) {
1920 rtw89_phy_fill_limit_ru_be(rtwdev, chan, &lmt_ru, i);
1921
1922 ptr = (s8 *)&lmt_ru;
1923 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE;
1924 j += 4, addr += 4, ptr += 4) {
1925 val = u32_encode_bits(ptr[0], GENMASK(7, 0)) |
1926 u32_encode_bits(ptr[1], GENMASK(15, 8)) |
1927 u32_encode_bits(ptr[2], GENMASK(23, 16)) |
1928 u32_encode_bits(ptr[3], GENMASK(31, 24));
1929
1930 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1931 }
1932 }
1933
1934 if (!(chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
1935 return;
1936
1937 rtw89_phy_conf_limit_large_mru_be(rtwdev, chan, phy_idx, false);
1938 rtw89_phy_conf_limit_large_mru_be(rtwdev, chan, phy_idx, true);
1939 }
1940
1941 const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
1942 .cr_base = 0x20000,
1943 .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START,
1944 .physt_bmp_eht = R_PHY_STS_BITMAP_EHT,
1945 .physt_ie_len = {32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1946 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN,
1947 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32},
1948 .physt_gen = 1,
1949 .ccx = &rtw89_ccx_regs_be,
1950 .physts = &rtw89_physts_regs_be,
1951 .cfo = &rtw89_cfo_regs_be,
1952 .bb_wrap = &rtw89_bb_wrap_regs_be,
1953 .nctl = &rtw89_nctl_regs_be,
1954 .phy0_phy1_offset = rtw89_phy0_phy1_offset_be,
1955 .config_bb_gain = rtw89_phy_config_bb_gain_be,
1956 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be,
1957 .bb_wrap_init = rtw89_phy_bb_wrap_init_be,
1958 .ch_info_init = rtw89_phy_ch_info_init_be,
1959
1960 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be,
1961 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_be,
1962 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_be,
1963 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be,
1964 };
1965 EXPORT_SYMBOL(rtw89_phy_gen_be);
1966
1967 const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = {
1968 .cr_base = 0x0,
1969 .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START_BE4,
1970 .physt_bmp_eht = R_PHY_STS_BITMAP_EHT_BE4,
1971 .physt_ie_len = {32, 40, 24, 24, 16, 16, 16, 16, VAR_LEN, VAR_LEN, VAR_LEN, 168,
1972 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 32, 56,
1973 96, VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32},
1974 .physt_gen = 2,
1975 .ccx = &rtw89_ccx_regs_be_v1,
1976 .physts = &rtw89_physts_regs_be_v1,
1977 .cfo = &rtw89_cfo_regs_be_v1,
1978 .bb_wrap = &rtw89_bb_wrap_regs_be_v1,
1979 .nctl = &rtw89_nctl_regs_be_v1,
1980 .phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1,
1981 .config_bb_gain = rtw89_phy_config_bb_gain_be,
1982 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1,
1983 .bb_wrap_init = rtw89_phy_bb_wrap_init_be,
1984 .ch_info_init = rtw89_phy_ch_info_init_be_v1,
1985
1986 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be,
1987 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_be,
1988 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_be,
1989 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be,
1990 };
1991 EXPORT_SYMBOL(rtw89_phy_gen_be_v1);
1992