1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 11#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 12#include <dt-bindings/clock/qcom,rpmcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,qcm2290.h> 18#include <dt-bindings/interconnect/qcom,rpm-icc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/sound/qcom,q6asm.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32764>; 41 #clock-cells = <0>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 capacity-dmips-mhz = <1024>; 55 dynamic-power-coefficient = <100>; 56 enable-method = "psci"; 57 next-level-cache = <&l2_0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 power-domains = <&cpu_pd0>; 60 power-domain-names = "psci"; 61 l2_0: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 }; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 clocks = <&cpufreq_hw 0>; 73 capacity-dmips-mhz = <1024>; 74 dynamic-power-coefficient = <100>; 75 enable-method = "psci"; 76 next-level-cache = <&l2_0>; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 power-domains = <&cpu_pd1>; 79 power-domain-names = "psci"; 80 }; 81 82 cpu2: cpu@2 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x2>; 86 clocks = <&cpufreq_hw 0>; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 enable-method = "psci"; 90 next-level-cache = <&l2_0>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 power-domains = <&cpu_pd2>; 93 power-domain-names = "psci"; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 clocks = <&cpufreq_hw 0>; 101 capacity-dmips-mhz = <1024>; 102 dynamic-power-coefficient = <100>; 103 enable-method = "psci"; 104 next-level-cache = <&l2_0>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 power-domains = <&cpu_pd3>; 107 power-domain-names = "psci"; 108 }; 109 110 cpu-map { 111 cluster0 { 112 core0 { 113 cpu = <&cpu0>; 114 }; 115 116 core1 { 117 cpu = <&cpu1>; 118 }; 119 120 core2 { 121 cpu = <&cpu2>; 122 }; 123 124 core3 { 125 cpu = <&cpu3>; 126 }; 127 }; 128 }; 129 130 domain-idle-states { 131 cluster_sleep: cluster-sleep-0 { 132 compatible = "domain-idle-state"; 133 arm,psci-suspend-param = <0x41000043>; 134 entry-latency-us = <800>; 135 exit-latency-us = <2118>; 136 min-residency-us = <7376>; 137 }; 138 }; 139 140 idle-states { 141 entry-method = "psci"; 142 143 cpu_sleep: cpu-sleep-0 { 144 compatible = "arm,idle-state"; 145 idle-state-name = "power-collapse"; 146 arm,psci-suspend-param = <0x40000003>; 147 entry-latency-us = <290>; 148 exit-latency-us = <376>; 149 min-residency-us = <1182>; 150 local-timer-stop; 151 }; 152 }; 153 }; 154 155 firmware { 156 scm: scm { 157 compatible = "qcom,scm-qcm2290", "qcom,scm"; 158 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 159 clock-names = "core"; 160 qcom,dload-mode = <&tcsr_regs 0x13000>; 161 #reset-cells = <1>; 162 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 163 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 164 }; 165 }; 166 167 memory@40000000 { 168 device_type = "memory"; 169 /* We expect the bootloader to fill in the size */ 170 reg = <0 0x40000000 0 0>; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a53-pmu"; 175 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 182 cpu_pd0: power-domain-cpu0 { 183 #power-domain-cells = <0>; 184 power-domains = <&cluster_pd>; 185 domain-idle-states = <&cpu_sleep>; 186 }; 187 188 cpu_pd1: power-domain-cpu1 { 189 #power-domain-cells = <0>; 190 power-domains = <&cluster_pd>; 191 domain-idle-states = <&cpu_sleep>; 192 }; 193 194 cpu_pd2: power-domain-cpu2 { 195 #power-domain-cells = <0>; 196 power-domains = <&cluster_pd>; 197 domain-idle-states = <&cpu_sleep>; 198 }; 199 200 cpu_pd3: power-domain-cpu3 { 201 #power-domain-cells = <0>; 202 power-domains = <&cluster_pd>; 203 domain-idle-states = <&cpu_sleep>; 204 }; 205 206 cluster_pd: power-domain-cpu-cluster { 207 #power-domain-cells = <0>; 208 power-domains = <&mpm>; 209 domain-idle-states = <&cluster_sleep>; 210 }; 211 }; 212 213 rpm: remoteproc { 214 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 215 216 glink-edge { 217 compatible = "qcom,glink-rpm"; 218 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 219 qcom,rpm-msg-ram = <&rpm_msg_ram>; 220 mboxes = <&apcs_glb 0>; 221 222 rpm_requests: rpm-requests { 223 compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm"; 224 qcom,glink-channels = "rpm_requests"; 225 226 rpmcc: clock-controller { 227 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 228 clocks = <&xo_board>; 229 clock-names = "xo"; 230 #clock-cells = <1>; 231 }; 232 233 rpmpd: power-controller { 234 compatible = "qcom,qcm2290-rpmpd"; 235 #power-domain-cells = <1>; 236 operating-points-v2 = <&rpmpd_opp_table>; 237 238 rpmpd_opp_table: opp-table { 239 compatible = "operating-points-v2"; 240 241 rpmpd_opp_min_svs: opp1 { 242 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 243 }; 244 245 rpmpd_opp_low_svs: opp2 { 246 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 247 }; 248 249 rpmpd_opp_svs: opp3 { 250 opp-level = <RPM_SMD_LEVEL_SVS>; 251 }; 252 253 rpmpd_opp_svs_plus: opp4 { 254 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 255 }; 256 257 rpmpd_opp_nom: opp5 { 258 opp-level = <RPM_SMD_LEVEL_NOM>; 259 }; 260 261 rpmpd_opp_nom_plus: opp6 { 262 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 263 }; 264 265 rpmpd_opp_turbo: opp7 { 266 opp-level = <RPM_SMD_LEVEL_TURBO>; 267 }; 268 269 rpmpd_opp_turbo_plus: opp8 { 270 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 271 }; 272 }; 273 }; 274 }; 275 }; 276 277 mpm: interrupt-controller { 278 compatible = "qcom,mpm"; 279 qcom,rpm-msg-ram = <&apss_mpm>; 280 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 281 mboxes = <&apcs_glb 1>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 #power-domain-cells = <0>; 285 interrupt-parent = <&intc>; 286 qcom,mpm-pin-count = <96>; 287 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 288 <5 296>, /* Soundwire master_irq */ 289 <12 422>, /* DWC3 ss_phy_irq */ 290 <24 79>, /* Soundwire wake_irq */ 291 <86 183>, /* MPM wake, SPMI */ 292 <90 260>; /* QUSB2_PHY DP+DM */ 293 }; 294 }; 295 296 reserved_memory: reserved-memory { 297 #address-cells = <2>; 298 #size-cells = <2>; 299 ranges; 300 301 hyp_mem: hyp@45700000 { 302 reg = <0x0 0x45700000 0x0 0x600000>; 303 no-map; 304 }; 305 306 xbl_aop_mem: xbl-aop@45e00000 { 307 reg = <0x0 0x45e00000 0x0 0x140000>; 308 no-map; 309 }; 310 311 sec_apps_mem: sec-apps@45fff000 { 312 reg = <0x0 0x45fff000 0x0 0x1000>; 313 no-map; 314 }; 315 316 smem_mem: smem@46000000 { 317 compatible = "qcom,smem"; 318 reg = <0x0 0x46000000 0x0 0x200000>; 319 no-map; 320 321 hwlocks = <&tcsr_mutex 3>; 322 qcom,rpm-msg-ram = <&rpm_msg_ram>; 323 }; 324 325 pil_modem_mem: modem@4ab00000 { 326 reg = <0x0 0x4ab00000 0x0 0x6900000>; 327 no-map; 328 }; 329 330 pil_video_mem: video@51400000 { 331 reg = <0x0 0x51400000 0x0 0x500000>; 332 no-map; 333 }; 334 335 wlan_msa_mem: wlan-msa@51900000 { 336 reg = <0x0 0x51900000 0x0 0x100000>; 337 no-map; 338 }; 339 340 pil_adsp_mem: adsp@51a00000 { 341 reg = <0x0 0x51a00000 0x0 0x1c00000>; 342 no-map; 343 }; 344 345 pil_ipa_fw_mem: ipa-fw@53600000 { 346 reg = <0x0 0x53600000 0x0 0x10000>; 347 no-map; 348 }; 349 350 pil_ipa_gsi_mem: ipa-gsi@53610000 { 351 reg = <0x0 0x53610000 0x0 0x5000>; 352 no-map; 353 }; 354 355 pil_gpu_mem: zap@53615000 { 356 compatible = "shared-dma-pool"; 357 reg = <0x0 0x53615000 0x0 0x2000>; 358 no-map; 359 }; 360 361 cont_splash_memory: framebuffer@5c000000 { 362 reg = <0x0 0x5c000000 0x0 0x00f00000>; 363 no-map; 364 }; 365 366 dfps_data_memory: dpfs-data@5cf00000 { 367 reg = <0x0 0x5cf00000 0x0 0x0100000>; 368 no-map; 369 }; 370 371 removed_mem: reserved@60000000 { 372 reg = <0x0 0x60000000 0x0 0x3900000>; 373 no-map; 374 }; 375 376 rmtfs_mem: memory@89b01000 { 377 compatible = "qcom,rmtfs-mem"; 378 reg = <0x0 0x89b01000 0x0 0x200000>; 379 no-map; 380 381 qcom,client-id = <1>; 382 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 383 }; 384 }; 385 386 smp2p-adsp { 387 compatible = "qcom,smp2p"; 388 qcom,smem = <443>, <429>; 389 390 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 391 392 mboxes = <&apcs_glb 10>; 393 394 qcom,local-pid = <0>; 395 qcom,remote-pid = <2>; 396 397 adsp_smp2p_out: master-kernel { 398 qcom,entry-name = "master-kernel"; 399 #qcom,smem-state-cells = <1>; 400 }; 401 402 adsp_smp2p_in: slave-kernel { 403 qcom,entry-name = "slave-kernel"; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 }; 408 409 smp2p-mpss { 410 compatible = "qcom,smp2p"; 411 qcom,smem = <435>, <428>; 412 413 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 414 415 mboxes = <&apcs_glb 14>; 416 417 qcom,local-pid = <0>; 418 qcom,remote-pid = <1>; 419 420 modem_smp2p_out: master-kernel { 421 qcom,entry-name = "master-kernel"; 422 #qcom,smem-state-cells = <1>; 423 }; 424 425 modem_smp2p_in: slave-kernel { 426 qcom,entry-name = "slave-kernel"; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 431 wlan_smp2p_in: wlan-wpss-to-ap { 432 qcom,entry-name = "wlan"; 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 437 ipa_smp2p_out: ipa-ap-to-modem { 438 qcom,entry-name = "ipa"; 439 #qcom,smem-state-cells = <1>; 440 }; 441 442 ipa_smp2p_in: ipa-modem-to-ap { 443 qcom,entry-name = "ipa"; 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 }; 447 448 }; 449 450 soc: soc@0 { 451 compatible = "simple-bus"; 452 #address-cells = <2>; 453 #size-cells = <2>; 454 ranges = <0 0 0 0 0x10 0>; 455 dma-ranges = <0 0 0 0 0x10 0>; 456 457 tcsr_mutex: hwlock@340000 { 458 compatible = "qcom,tcsr-mutex"; 459 reg = <0x0 0x00340000 0x0 0x20000>; 460 #hwlock-cells = <1>; 461 }; 462 463 tcsr_regs: syscon@3c0000 { 464 compatible = "qcom,qcm2290-tcsr", "syscon"; 465 reg = <0x0 0x003c0000 0x0 0x40000>; 466 }; 467 468 tlmm: pinctrl@500000 { 469 compatible = "qcom,qcm2290-tlmm"; 470 reg = <0x0 0x00500000 0x0 0x300000>; 471 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 472 gpio-controller; 473 gpio-ranges = <&tlmm 0 0 127>; 474 wakeup-parent = <&mpm>; 475 #gpio-cells = <2>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 479 qup_i2c0_default: qup-i2c0-default-state { 480 pins = "gpio0", "gpio1"; 481 function = "qup0"; 482 drive-strength = <2>; 483 bias-pull-up; 484 }; 485 486 qup_i2c1_default: qup-i2c1-default-state { 487 pins = "gpio4", "gpio5"; 488 function = "qup1"; 489 drive-strength = <2>; 490 bias-pull-up; 491 }; 492 493 qup_i2c2_default: qup-i2c2-default-state { 494 pins = "gpio6", "gpio7"; 495 function = "qup2"; 496 drive-strength = <2>; 497 bias-pull-up; 498 }; 499 500 qup_i2c3_default: qup-i2c3-default-state { 501 pins = "gpio8", "gpio9"; 502 function = "qup3"; 503 drive-strength = <2>; 504 bias-pull-up; 505 }; 506 507 qup_i2c4_default: qup-i2c4-default-state { 508 pins = "gpio12", "gpio13"; 509 function = "qup4"; 510 drive-strength = <2>; 511 bias-pull-up; 512 }; 513 514 qup_i2c5_default: qup-i2c5-default-state { 515 pins = "gpio14", "gpio15"; 516 function = "qup5"; 517 drive-strength = <2>; 518 bias-pull-up; 519 }; 520 521 qup_spi0_default: qup-spi0-default-state { 522 pins = "gpio0", "gpio1","gpio2", "gpio3"; 523 function = "qup0"; 524 drive-strength = <2>; 525 bias-pull-up; 526 }; 527 528 qup_spi1_default: qup-spi1-default-state { 529 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 530 function = "qup1"; 531 drive-strength = <2>; 532 bias-pull-up; 533 }; 534 535 qup_spi2_default: qup-spi2-default-state { 536 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 537 function = "qup2"; 538 drive-strength = <2>; 539 bias-pull-up; 540 }; 541 542 qup_spi3_default: qup-spi3-default-state { 543 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 544 function = "qup3"; 545 drive-strength = <2>; 546 bias-pull-up; 547 }; 548 549 qup_spi4_default: qup-spi4-default-state { 550 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 551 function = "qup4"; 552 drive-strength = <2>; 553 bias-pull-up; 554 }; 555 556 qup_spi5_default: qup-spi5-default-state { 557 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 558 function = "qup5"; 559 drive-strength = <2>; 560 bias-pull-up; 561 }; 562 563 qup_uart0_default: qup-uart0-default-state { 564 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 565 function = "qup0"; 566 drive-strength = <2>; 567 bias-disable; 568 }; 569 570 qup_uart1_default: qup-uart1-default-state { 571 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 572 function = "qup1"; 573 drive-strength = <2>; 574 bias-disable; 575 }; 576 577 qup_uart2_default: qup-uart2-default-state { 578 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 579 function = "qup2"; 580 drive-strength = <2>; 581 bias-disable; 582 }; 583 584 qup_uart3_default: qup-uart3-default-state { 585 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 586 function = "qup3"; 587 drive-strength = <2>; 588 bias-disable; 589 }; 590 591 qup_uart4_default: qup-uart4-default-state { 592 pins = "gpio12", "gpio13"; 593 function = "qup4"; 594 drive-strength = <2>; 595 bias-disable; 596 }; 597 598 qup_uart5_default: qup-uart5-default-state { 599 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 600 function = "qup5"; 601 drive-strength = <2>; 602 bias-disable; 603 }; 604 605 cci0_default: cci0-default-state { 606 pins = "gpio22", "gpio23"; 607 function = "cci_i2c"; 608 drive-strength = <2>; 609 bias-disable; 610 }; 611 612 cci1_default: cci1-default-state { 613 pins = "gpio29", "gpio30"; 614 function = "cci_i2c"; 615 drive-strength = <2>; 616 bias-disable; 617 }; 618 619 mclk0_default: mclk0-default-state { 620 pins = "gpio20"; 621 function = "cam_mclk"; 622 drive-strength = <16>; 623 bias-disable; 624 }; 625 626 mclk1_default: mclk1-default-state { 627 pins = "gpio21"; 628 function = "cam_mclk"; 629 drive-strength = <16>; 630 bias-disable; 631 }; 632 633 mclk2_default: mclk2-default-state { 634 pins = "gpio27"; 635 function = "cam_mclk"; 636 drive-strength = <16>; 637 bias-disable; 638 }; 639 640 mclk3_default: mclk3-default-state { 641 pins = "gpio28"; 642 function = "cam_mclk"; 643 drive-strength = <16>; 644 bias-disable; 645 }; 646 647 sdc1_state_on: sdc1-on-state { 648 clk-pins { 649 pins = "sdc1_clk"; 650 drive-strength = <16>; 651 bias-disable; 652 }; 653 654 cmd-pins { 655 pins = "sdc1_cmd"; 656 drive-strength = <10>; 657 bias-pull-up; 658 }; 659 660 data-pins { 661 pins = "sdc1_data"; 662 drive-strength = <10>; 663 bias-pull-up; 664 }; 665 666 rclk-pins { 667 pins = "sdc1_rclk"; 668 bias-pull-down; 669 }; 670 }; 671 672 sdc1_state_off: sdc1-off-state { 673 clk-pins { 674 pins = "sdc1_clk"; 675 drive-strength = <2>; 676 bias-disable; 677 }; 678 679 cmd-pins { 680 pins = "sdc1_cmd"; 681 drive-strength = <2>; 682 bias-pull-up; 683 }; 684 685 data-pins { 686 pins = "sdc1_data"; 687 drive-strength = <2>; 688 bias-pull-up; 689 }; 690 691 rclk-pins { 692 pins = "sdc1_rclk"; 693 bias-pull-down; 694 }; 695 }; 696 697 sdc2_state_on: sdc2-on-state { 698 clk-pins { 699 pins = "sdc2_clk"; 700 drive-strength = <16>; 701 bias-disable; 702 }; 703 704 cmd-pins { 705 pins = "sdc2_cmd"; 706 drive-strength = <10>; 707 bias-pull-up; 708 }; 709 710 data-pins { 711 pins = "sdc2_data"; 712 drive-strength = <10>; 713 bias-pull-up; 714 }; 715 }; 716 717 sdc2_state_off: sdc2-off-state { 718 clk-pins { 719 pins = "sdc2_clk"; 720 drive-strength = <2>; 721 bias-disable; 722 }; 723 724 cmd-pins { 725 pins = "sdc2_cmd"; 726 drive-strength = <2>; 727 bias-pull-up; 728 }; 729 730 data-pins { 731 pins = "sdc2_data"; 732 drive-strength = <2>; 733 bias-pull-up; 734 }; 735 }; 736 }; 737 738 lpass_tlmm: pinctrl@a7c0000 { 739 compatible = "qcom,qcm2290-lpass-lpi-pinctrl", 740 "qcom,sm6115-lpass-lpi-pinctrl"; 741 reg = <0x0 0x0a7c0000 0x0 0x20000>, 742 <0x0 0x0a950000 0x0 0x10000>; 743 744 clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 745 clock-names = "audio"; 746 747 gpio-controller; 748 #gpio-cells = <2>; 749 gpio-ranges = <&lpass_tlmm 0 0 19>; 750 751 lpi_i2s2_active: lpi-i2s2-active-state { 752 sck-pins { 753 pins = "gpio10"; 754 function = "i2s2_clk"; 755 bias-disable; 756 drive-strength = <8>; 757 }; 758 759 ws-pins { 760 pins = "gpio11"; 761 function = "i2s2_ws"; 762 bias-disable; 763 drive-strength = <8>; 764 }; 765 766 data-pins { 767 pins = "gpio12"; 768 function = "i2s2_data"; 769 bias-disable; 770 drive-strength = <8>; 771 }; 772 }; 773 }; 774 775 gcc: clock-controller@1400000 { 776 compatible = "qcom,gcc-qcm2290"; 777 reg = <0x0 0x01400000 0x0 0x1f0000>; 778 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 779 clock-names = "bi_tcxo", "sleep_clk"; 780 #clock-cells = <1>; 781 #reset-cells = <1>; 782 #power-domain-cells = <1>; 783 }; 784 785 usb_hsphy: phy@1613000 { 786 compatible = "qcom,qcm2290-qusb2-phy"; 787 reg = <0x0 0x01613000 0x0 0x180>; 788 789 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 790 <&rpmcc RPM_SMD_XO_CLK_SRC>; 791 clock-names = "cfg_ahb", "ref"; 792 793 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 794 nvmem-cells = <&qusb2_hstx_trim>; 795 #phy-cells = <0>; 796 797 status = "disabled"; 798 }; 799 800 usb_qmpphy: phy@1615000 { 801 compatible = "qcom,qcm2290-qmp-usb3-phy"; 802 reg = <0x0 0x01615000 0x0 0x1000>; 803 804 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 805 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 806 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 807 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 808 clock-names = "cfg_ahb", 809 "ref", 810 "com_aux", 811 "pipe"; 812 813 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 814 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 815 reset-names = "phy", 816 "phy_phy"; 817 818 #clock-cells = <0>; 819 clock-output-names = "usb3_phy_pipe_clk_src"; 820 821 #phy-cells = <0>; 822 orientation-switch; 823 824 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 825 826 status = "disabled"; 827 828 ports { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 port@0 { 833 reg = <0>; 834 835 usb_qmpphy_out: endpoint { 836 }; 837 }; 838 839 port@1 { 840 reg = <1>; 841 842 usb_qmpphy_usb_ss_in: endpoint { 843 remote-endpoint = <&usb_dwc3_ss>; 844 }; 845 }; 846 }; 847 }; 848 849 system_noc: interconnect@1880000 { 850 compatible = "qcom,qcm2290-snoc"; 851 reg = <0x0 0x01880000 0x0 0x60200>; 852 #interconnect-cells = <2>; 853 854 qup_virt: interconnect-qup { 855 compatible = "qcom,qcm2290-qup-virt"; 856 #interconnect-cells = <2>; 857 }; 858 859 mmnrt_virt: interconnect-mmnrt { 860 compatible = "qcom,qcm2290-mmnrt-virt"; 861 #interconnect-cells = <2>; 862 }; 863 864 mmrt_virt: interconnect-mmrt { 865 compatible = "qcom,qcm2290-mmrt-virt"; 866 #interconnect-cells = <2>; 867 }; 868 }; 869 870 config_noc: interconnect@1900000 { 871 compatible = "qcom,qcm2290-cnoc"; 872 reg = <0x0 0x01900000 0x0 0x8200>; 873 #interconnect-cells = <2>; 874 }; 875 876 cryptobam: dma-controller@1b04000 { 877 compatible = "qcom,bam-v1.7.0"; 878 reg = <0x0 0x01b04000 0x0 0x24000>; 879 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 881 clock-names = "bam_clk"; 882 #dma-cells = <1>; 883 qcom,ee = <0>; 884 qcom,controlled-remotely; 885 iommus = <&apps_smmu 0x0084 0x11>, 886 <&apps_smmu 0x0086 0x11>; 887 }; 888 889 crypto: crypto@1b3a000 { 890 compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce"; 891 reg = <0x0 0x01b3a000 0x0 0x6000>; 892 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 893 clock-names = "core"; 894 dmas = <&cryptobam 6>, <&cryptobam 7>; 895 dma-names = "rx", "tx"; 896 iommus = <&apps_smmu 0x0084 0x11>, 897 <&apps_smmu 0x0086 0x11>; 898 }; 899 900 qfprom@1b44000 { 901 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 902 reg = <0x0 0x01b44000 0x0 0x3000>; 903 #address-cells = <1>; 904 #size-cells = <1>; 905 906 qusb2_hstx_trim: hstx-trim@25b { 907 reg = <0x25b 0x1>; 908 bits = <1 4>; 909 }; 910 911 gpu_speed_bin: gpu-speed-bin@2006 { 912 reg = <0x2006 0x2>; 913 bits = <5 8>; 914 }; 915 }; 916 917 pmu@1b8e300 { 918 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 919 reg = <0x0 0x01b8e300 0x0 0x600>; 920 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 921 922 operating-points-v2 = <&cpu_bwmon_opp_table>; 923 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 924 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 925 926 cpu_bwmon_opp_table: opp-table { 927 compatible = "operating-points-v2"; 928 929 opp-0 { 930 opp-peak-kBps = <(200 * 4 * 1000)>; 931 }; 932 933 opp-1 { 934 opp-peak-kBps = <(300 * 4 * 1000)>; 935 }; 936 937 opp-2 { 938 opp-peak-kBps = <(451 * 4 * 1000)>; 939 }; 940 941 opp-3 { 942 opp-peak-kBps = <(547 * 4 * 1000)>; 943 }; 944 945 opp-4 { 946 opp-peak-kBps = <(681 * 4 * 1000)>; 947 }; 948 949 opp-5 { 950 opp-peak-kBps = <(768 * 4 * 1000)>; 951 }; 952 953 opp-6 { 954 opp-peak-kBps = <(1017 * 4 * 1000)>; 955 }; 956 957 opp-7 { 958 opp-peak-kBps = <(1353 * 4 * 1000)>; 959 }; 960 961 opp-8 { 962 opp-peak-kBps = <(1555 * 4 * 1000)>; 963 }; 964 965 opp-9 { 966 opp-peak-kBps = <(1804 * 4 * 1000)>; 967 }; 968 }; 969 }; 970 971 spmi_bus: spmi@1c40000 { 972 compatible = "qcom,spmi-pmic-arb"; 973 reg = <0x0 0x01c40000 0x0 0x1100>, 974 <0x0 0x01e00000 0x0 0x2000000>, 975 <0x0 0x03e00000 0x0 0x100000>, 976 <0x0 0x03f00000 0x0 0xa0000>, 977 <0x0 0x01c0a000 0x0 0x26000>; 978 reg-names = "core", 979 "chnls", 980 "obsrvr", 981 "intr", 982 "cnfg"; 983 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 984 interrupt-names = "periph_irq"; 985 qcom,ee = <0>; 986 qcom,channel = <0>; 987 #address-cells = <2>; 988 #size-cells = <0>; 989 interrupt-controller; 990 #interrupt-cells = <4>; 991 }; 992 993 tsens0: thermal-sensor@4411000 { 994 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 995 reg = <0x0 0x04411000 0x0 0x1ff>, 996 <0x0 0x04410000 0x0 0x8>; 997 #qcom,sensors = <10>; 998 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 999 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1000 interrupt-names = "uplow", "critical"; 1001 #thermal-sensor-cells = <1>; 1002 }; 1003 1004 rng: rng@4453000 { 1005 compatible = "qcom,prng-ee"; 1006 reg = <0x0 0x04453000 0x0 0x1000>; 1007 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 1008 clock-names = "core"; 1009 }; 1010 1011 bimc: interconnect@4480000 { 1012 compatible = "qcom,qcm2290-bimc"; 1013 reg = <0x0 0x04480000 0x0 0x80000>; 1014 #interconnect-cells = <2>; 1015 }; 1016 1017 rpm_msg_ram: sram@45f0000 { 1018 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 1019 reg = <0x0 0x045f0000 0x0 0x7000>; 1020 #address-cells = <1>; 1021 #size-cells = <1>; 1022 ranges = <0 0x0 0x045f0000 0x7000>; 1023 1024 apss_mpm: sram@1b8 { 1025 reg = <0x1b8 0x48>; 1026 }; 1027 }; 1028 1029 sram@4690000 { 1030 compatible = "qcom,rpm-stats"; 1031 reg = <0x0 0x04690000 0x0 0x10000>; 1032 }; 1033 1034 sdhc_1: mmc@4744000 { 1035 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 1036 reg = <0x0 0x04744000 0x0 0x1000>, 1037 <0x0 0x04745000 0x0 0x1000>, 1038 <0x0 0x04748000 0x0 0x8000>; 1039 reg-names = "hc", 1040 "cqhci", 1041 "ice"; 1042 1043 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1045 interrupt-names = "hc_irq", "pwr_irq"; 1046 1047 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1048 <&gcc GCC_SDCC1_APPS_CLK>, 1049 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1050 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1051 clock-names = "iface", 1052 "core", 1053 "xo", 1054 "ice"; 1055 1056 resets = <&gcc GCC_SDCC1_BCR>; 1057 1058 power-domains = <&rpmpd QCM2290_VDDCX>; 1059 operating-points-v2 = <&sdhc1_opp_table>; 1060 iommus = <&apps_smmu 0xc0 0x0>; 1061 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1062 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1063 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1064 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1065 interconnect-names = "sdhc-ddr", 1066 "cpu-sdhc"; 1067 1068 qcom,dll-config = <0x000f642c>; 1069 qcom,ddr-config = <0x80040868>; 1070 bus-width = <8>; 1071 1072 mmc-ddr-1_8v; 1073 mmc-hs200-1_8v; 1074 mmc-hs400-1_8v; 1075 mmc-hs400-enhanced-strobe; 1076 1077 status = "disabled"; 1078 1079 sdhc1_opp_table: opp-table { 1080 compatible = "operating-points-v2"; 1081 1082 opp-100000000 { 1083 opp-hz = /bits/ 64 <100000000>; 1084 required-opps = <&rpmpd_opp_low_svs>; 1085 opp-peak-kBps = <250000 133320>; 1086 opp-avg-kBps = <102400 65000>; 1087 }; 1088 1089 opp-192000000 { 1090 opp-hz = /bits/ 64 <192000000>; 1091 required-opps = <&rpmpd_opp_low_svs>; 1092 opp-peak-kBps = <800000 300000>; 1093 opp-avg-kBps = <204800 200000>; 1094 }; 1095 1096 opp-384000000 { 1097 opp-hz = /bits/ 64 <384000000>; 1098 required-opps = <&rpmpd_opp_svs_plus>; 1099 opp-peak-kBps = <800000 300000>; 1100 opp-avg-kBps = <204800 200000>; 1101 }; 1102 }; 1103 }; 1104 1105 sdhc_2: mmc@4784000 { 1106 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 1107 reg = <0x0 0x04784000 0x0 0x1000>; 1108 reg-names = "hc"; 1109 1110 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1112 interrupt-names = "hc_irq", "pwr_irq"; 1113 1114 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1115 <&gcc GCC_SDCC2_APPS_CLK>, 1116 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1117 clock-names = "iface", 1118 "core", 1119 "xo"; 1120 1121 resets = <&gcc GCC_SDCC2_BCR>; 1122 1123 power-domains = <&rpmpd QCM2290_VDDCX>; 1124 operating-points-v2 = <&sdhc2_opp_table>; 1125 iommus = <&apps_smmu 0xa0 0x0>; 1126 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1127 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1128 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1129 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1130 interconnect-names = "sdhc-ddr", 1131 "cpu-sdhc"; 1132 1133 qcom,dll-config = <0x0007642c>; 1134 qcom,ddr-config = <0x80040868>; 1135 bus-width = <4>; 1136 1137 status = "disabled"; 1138 1139 sdhc2_opp_table: opp-table { 1140 compatible = "operating-points-v2"; 1141 1142 opp-100000000 { 1143 opp-hz = /bits/ 64 <100000000>; 1144 required-opps = <&rpmpd_opp_low_svs>; 1145 opp-peak-kBps = <250000 133320>; 1146 opp-avg-kBps = <261438 150000>; 1147 }; 1148 1149 opp-202000000 { 1150 opp-hz = /bits/ 64 <202000000>; 1151 required-opps = <&rpmpd_opp_svs_plus>; 1152 opp-peak-kBps = <800000 300000>; 1153 opp-avg-kBps = <261438 300000>; 1154 }; 1155 }; 1156 }; 1157 1158 gpi_dma0: dma-controller@4a00000 { 1159 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 1160 reg = <0x0 0x04a00000 0x0 0x60000>; 1161 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1171 dma-channels = <10>; 1172 dma-channel-mask = <0x1f>; 1173 iommus = <&apps_smmu 0xf6 0x0>; 1174 #dma-cells = <3>; 1175 status = "disabled"; 1176 }; 1177 1178 qupv3_id_0: geniqup@4ac0000 { 1179 compatible = "qcom,geni-se-qup"; 1180 reg = <0x0 0x04ac0000 0x0 0x2000>; 1181 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1182 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1183 clock-names = "m-ahb", "s-ahb"; 1184 iommus = <&apps_smmu 0xe3 0x0>; 1185 #address-cells = <2>; 1186 #size-cells = <2>; 1187 ranges; 1188 status = "disabled"; 1189 1190 i2c0: i2c@4a80000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0x0 0x04a80000 0x0 0x4000>; 1193 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1195 clock-names = "se"; 1196 pinctrl-0 = <&qup_i2c0_default>; 1197 pinctrl-names = "default"; 1198 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1199 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1200 dma-names = "tx", "rx"; 1201 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1202 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1203 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1204 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1205 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1206 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1207 interconnect-names = "qup-core", 1208 "qup-config", 1209 "qup-memory"; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 status = "disabled"; 1213 }; 1214 1215 spi0: spi@4a80000 { 1216 compatible = "qcom,geni-spi"; 1217 reg = <0x0 0x04a80000 0x0 0x4000>; 1218 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1220 clock-names = "se"; 1221 pinctrl-0 = <&qup_spi0_default>; 1222 pinctrl-names = "default"; 1223 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1224 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1225 dma-names = "tx", "rx"; 1226 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1227 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1228 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1229 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1230 interconnect-names = "qup-core", 1231 "qup-config"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 uart0: serial@4a80000 { 1238 compatible = "qcom,geni-uart"; 1239 reg = <0x0 0x04a80000 0x0 0x4000>; 1240 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1242 clock-names = "se"; 1243 pinctrl-0 = <&qup_uart0_default>; 1244 pinctrl-names = "default"; 1245 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1246 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1247 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1248 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1249 interconnect-names = "qup-core", 1250 "qup-config"; 1251 status = "disabled"; 1252 }; 1253 1254 i2c1: i2c@4a84000 { 1255 compatible = "qcom,geni-i2c"; 1256 reg = <0x0 0x04a84000 0x0 0x4000>; 1257 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1259 clock-names = "se"; 1260 pinctrl-0 = <&qup_i2c1_default>; 1261 pinctrl-names = "default"; 1262 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1263 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1264 dma-names = "tx", "rx"; 1265 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1266 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1267 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1268 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1269 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1270 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1271 interconnect-names = "qup-core", 1272 "qup-config", 1273 "qup-memory"; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 spi1: spi@4a84000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0x0 0x04a84000 0x0 0x4000>; 1282 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1284 clock-names = "se"; 1285 pinctrl-0 = <&qup_spi1_default>; 1286 pinctrl-names = "default"; 1287 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1288 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1289 dma-names = "tx", "rx"; 1290 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1291 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1292 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1293 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1294 interconnect-names = "qup-core", 1295 "qup-config"; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 uart1: serial@4a84000 { 1302 compatible = "qcom,geni-uart"; 1303 reg = <0x0 0x04a84000 0x0 0x4000>; 1304 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1306 clock-names = "se"; 1307 pinctrl-0 = <&qup_uart1_default>; 1308 pinctrl-names = "default"; 1309 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1310 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1311 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1312 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1313 interconnect-names = "qup-core", 1314 "qup-config"; 1315 status = "disabled"; 1316 }; 1317 1318 i2c2: i2c@4a88000 { 1319 compatible = "qcom,geni-i2c"; 1320 reg = <0x0 0x04a88000 0x0 0x4000>; 1321 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1323 clock-names = "se"; 1324 pinctrl-0 = <&qup_i2c2_default>; 1325 pinctrl-names = "default"; 1326 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1327 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1328 dma-names = "tx", "rx"; 1329 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1330 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1331 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1332 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1333 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1334 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1335 interconnect-names = "qup-core", 1336 "qup-config", 1337 "qup-memory"; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 status = "disabled"; 1341 }; 1342 1343 spi2: spi@4a88000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0x0 0x04a88000 0x0 0x4000>; 1346 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1348 clock-names = "se"; 1349 pinctrl-0 = <&qup_spi2_default>; 1350 pinctrl-names = "default"; 1351 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1352 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1353 dma-names = "tx", "rx"; 1354 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1355 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1356 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1357 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1358 interconnect-names = "qup-core", 1359 "qup-config"; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 uart2: serial@4a88000 { 1366 compatible = "qcom,geni-uart"; 1367 reg = <0x0 0x04a88000 0x0 0x4000>; 1368 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1370 clock-names = "se"; 1371 pinctrl-0 = <&qup_uart2_default>; 1372 pinctrl-names = "default"; 1373 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1374 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1375 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1376 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1377 interconnect-names = "qup-core", 1378 "qup-config"; 1379 status = "disabled"; 1380 }; 1381 1382 i2c3: i2c@4a8c000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0x0 0x04a8c000 0x0 0x4000>; 1385 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1387 clock-names = "se"; 1388 pinctrl-0 = <&qup_i2c3_default>; 1389 pinctrl-names = "default"; 1390 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1391 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1392 dma-names = "tx", "rx"; 1393 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1394 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1395 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1396 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1397 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1398 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1399 interconnect-names = "qup-core", 1400 "qup-config", 1401 "qup-memory"; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 spi3: spi@4a8c000 { 1408 compatible = "qcom,geni-spi"; 1409 reg = <0x0 0x04a8c000 0x0 0x4000>; 1410 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1412 clock-names = "se"; 1413 pinctrl-0 = <&qup_spi3_default>; 1414 pinctrl-names = "default"; 1415 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1416 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1417 dma-names = "tx", "rx"; 1418 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1419 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1420 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1421 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1422 interconnect-names = "qup-core", 1423 "qup-config"; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 status = "disabled"; 1427 }; 1428 1429 uart3: serial@4a8c000 { 1430 compatible = "qcom,geni-uart"; 1431 reg = <0x0 0x04a8c000 0x0 0x4000>; 1432 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1434 clock-names = "se"; 1435 pinctrl-0 = <&qup_uart3_default>; 1436 pinctrl-names = "default"; 1437 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1438 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1439 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1440 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1441 interconnect-names = "qup-core", 1442 "qup-config"; 1443 status = "disabled"; 1444 }; 1445 1446 i2c4: i2c@4a90000 { 1447 compatible = "qcom,geni-i2c"; 1448 reg = <0x0 0x04a90000 0x0 0x4000>; 1449 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1451 clock-names = "se"; 1452 pinctrl-0 = <&qup_i2c4_default>; 1453 pinctrl-names = "default"; 1454 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1455 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1456 dma-names = "tx", "rx"; 1457 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1458 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1459 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1460 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1461 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1462 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1463 interconnect-names = "qup-core", 1464 "qup-config", 1465 "qup-memory"; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 spi4: spi@4a90000 { 1472 compatible = "qcom,geni-spi"; 1473 reg = <0x0 0x04a90000 0x0 0x4000>; 1474 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_spi4_default>; 1479 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1480 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1481 dma-names = "tx", "rx"; 1482 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1483 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1484 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1485 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1486 interconnect-names = "qup-core", 1487 "qup-config"; 1488 #address-cells = <1>; 1489 #size-cells = <0>; 1490 status = "disabled"; 1491 }; 1492 1493 uart4: serial@4a90000 { 1494 compatible = "qcom,geni-uart"; 1495 reg = <0x0 0x04a90000 0x0 0x4000>; 1496 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1498 clock-names = "se"; 1499 pinctrl-0 = <&qup_uart4_default>; 1500 pinctrl-names = "default"; 1501 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1502 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1503 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1504 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1505 interconnect-names = "qup-core", 1506 "qup-config"; 1507 status = "disabled"; 1508 }; 1509 1510 i2c5: i2c@4a94000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0x0 0x04a94000 0x0 0x4000>; 1513 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1515 clock-names = "se"; 1516 pinctrl-0 = <&qup_i2c5_default>; 1517 pinctrl-names = "default"; 1518 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1519 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1520 dma-names = "tx", "rx"; 1521 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1522 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1523 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1524 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1525 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1526 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1527 interconnect-names = "qup-core", 1528 "qup-config", 1529 "qup-memory"; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 spi5: spi@4a94000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0x0 0x04a94000 0x0 0x4000>; 1538 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1539 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1540 clock-names = "se"; 1541 pinctrl-0 = <&qup_spi5_default>; 1542 pinctrl-names = "default"; 1543 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1544 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1545 dma-names = "tx", "rx"; 1546 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1547 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1548 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1549 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1550 interconnect-names = "qup-core", 1551 "qup-config"; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 status = "disabled"; 1555 }; 1556 1557 uart5: serial@4a94000 { 1558 compatible = "qcom,geni-uart"; 1559 reg = <0x0 0x04a94000 0x0 0x4000>; 1560 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1561 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1562 clock-names = "se"; 1563 pinctrl-0 = <&qup_uart5_default>; 1564 pinctrl-names = "default"; 1565 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1566 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1567 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1568 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1569 interconnect-names = "qup-core", 1570 "qup-config"; 1571 status = "disabled"; 1572 }; 1573 }; 1574 1575 usb: usb@4ef8800 { 1576 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1577 reg = <0x0 0x04ef8800 0x0 0x400>; 1578 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1579 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1580 interrupt-names = "hs_phy_irq", 1581 "ss_phy_irq"; 1582 1583 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1584 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1585 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1586 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1587 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1588 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1589 clock-names = "cfg_noc", 1590 "core", 1591 "iface", 1592 "sleep", 1593 "mock_utmi", 1594 "xo"; 1595 1596 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1597 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1598 assigned-clock-rates = <19200000>, <133333333>; 1599 1600 resets = <&gcc GCC_USB30_PRIM_BCR>; 1601 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1602 /* TODO: USB<->IPA path */ 1603 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1604 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1605 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1606 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1607 interconnect-names = "usb-ddr", 1608 "apps-usb"; 1609 wakeup-source; 1610 1611 #address-cells = <2>; 1612 #size-cells = <2>; 1613 ranges; 1614 1615 status = "disabled"; 1616 1617 usb_dwc3: usb@4e00000 { 1618 compatible = "snps,dwc3"; 1619 reg = <0x0 0x04e00000 0x0 0xcd00>; 1620 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1621 phys = <&usb_hsphy>, <&usb_qmpphy>; 1622 phy-names = "usb2-phy", "usb3-phy"; 1623 iommus = <&apps_smmu 0x120 0x0>; 1624 snps,dis_u2_susphy_quirk; 1625 snps,dis_enblslpm_quirk; 1626 snps,has-lpm-erratum; 1627 snps,hird-threshold = /bits/ 8 <0x10>; 1628 snps,usb3_lpm_capable; 1629 snps,parkmode-disable-ss-quirk; 1630 maximum-speed = "super-speed"; 1631 dr_mode = "otg"; 1632 usb-role-switch; 1633 1634 ports { 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 1638 port@0 { 1639 reg = <0>; 1640 1641 usb_dwc3_hs: endpoint { 1642 }; 1643 }; 1644 1645 port@1 { 1646 reg = <1>; 1647 1648 usb_dwc3_ss: endpoint { 1649 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1650 }; 1651 }; 1652 }; 1653 }; 1654 }; 1655 1656 ipa: ipa@5840000 { 1657 compatible = "qcom,qcm2290-ipa", "qcom,sc7180-ipa"; 1658 1659 iommus = <&apps_smmu 0x140 0x0>; 1660 reg = <0x0 0x05840000 0x0 0x7000>, 1661 <0x0 0x05847000 0x0 0x2000>, 1662 <0x0 0x05804000 0x0 0x2c000>; 1663 reg-names = "ipa-reg", 1664 "ipa-shared", 1665 "gsi"; 1666 1667 interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, 1668 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1669 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1670 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1671 interrupt-names = "ipa", 1672 "gsi", 1673 "ipa-clock-query", 1674 "ipa-setup-ready"; 1675 1676 clocks = <&rpmcc RPM_SMD_IPA_CLK>; 1677 clock-names = "core"; 1678 1679 interconnects = <&system_noc MASTER_IPA RPM_ALWAYS_TAG 1680 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1681 <&system_noc MASTER_IPA RPM_ALWAYS_TAG 1682 &system_noc SLAVE_IMEM RPM_ALWAYS_TAG>, 1683 <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 1684 &config_noc SLAVE_IPA_CFG RPM_ACTIVE_TAG>; 1685 interconnect-names = "memory", 1686 "imem", 1687 "config"; 1688 1689 qcom,smem-states = <&ipa_smp2p_out 0>, 1690 <&ipa_smp2p_out 1>; 1691 qcom,smem-state-names = "ipa-clock-enabled-valid", 1692 "ipa-clock-enabled"; 1693 1694 status = "disabled"; 1695 }; 1696 1697 gpu: gpu@5900000 { 1698 compatible = "qcom,adreno-07000200", "qcom,adreno"; 1699 reg = <0x0 0x05900000 0x0 0x40000>, 1700 <0x0 0x0599e000 0x0 0x1000>, 1701 <0x0 0x05961000 0x0 0x800>; 1702 reg-names = "kgsl_3d0_reg_memory", 1703 "cx_mem", 1704 "cx_dbgc"; 1705 1706 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1707 1708 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1709 <&gpucc GPU_CC_AHB_CLK>, 1710 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1711 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1712 <&gpucc GPU_CC_CX_GMU_CLK>, 1713 <&gpucc GPU_CC_CXO_CLK>; 1714 clock-names = "core", 1715 "iface", 1716 "mem_iface", 1717 "alt_mem_iface", 1718 "gmu", 1719 "xo"; 1720 1721 interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG 1722 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1723 interconnect-names = "gfx-mem"; 1724 1725 iommus = <&adreno_smmu 0 1>; 1726 operating-points-v2 = <&gpu_opp_table>; 1727 power-domains = <&rpmpd QCM2290_VDDCX>; 1728 qcom,gmu = <&gmu_wrapper>; 1729 1730 nvmem-cells = <&gpu_speed_bin>; 1731 nvmem-cell-names = "speed_bin"; 1732 #cooling-cells = <2>; 1733 1734 status = "disabled"; 1735 1736 gpu_zap_shader: zap-shader { 1737 memory-region = <&pil_gpu_mem>; 1738 }; 1739 1740 gpu_opp_table: opp-table { 1741 compatible = "operating-points-v2"; 1742 1743 /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ 1744 opp-1123200000 { 1745 opp-hz = /bits/ 64 <1123200000>; 1746 required-opps = <&rpmpd_opp_turbo_plus>; 1747 opp-peak-kBps = <6881000>; 1748 opp-supported-hw = <0x3>; 1749 turbo-mode; 1750 }; 1751 1752 opp-1017600000 { 1753 opp-hz = /bits/ 64 <1017600000>; 1754 required-opps = <&rpmpd_opp_turbo>; 1755 opp-peak-kBps = <6881000>; 1756 opp-supported-hw = <0x3>; 1757 turbo-mode; 1758 }; 1759 1760 opp-921600000 { 1761 opp-hz = /bits/ 64 <921600000>; 1762 required-opps = <&rpmpd_opp_nom_plus>; 1763 opp-peak-kBps = <6881000>; 1764 opp-supported-hw = <0x3>; 1765 }; 1766 1767 opp-844800000 { 1768 opp-hz = /bits/ 64 <844800000>; 1769 required-opps = <&rpmpd_opp_nom>; 1770 opp-peak-kBps = <6881000>; 1771 opp-supported-hw = <0x7>; 1772 }; 1773 1774 opp-672000000 { 1775 opp-hz = /bits/ 64 <672000000>; 1776 required-opps = <&rpmpd_opp_svs_plus>; 1777 opp-peak-kBps = <3879000>; 1778 opp-supported-hw = <0xf>; 1779 }; 1780 1781 opp-537600000 { 1782 opp-hz = /bits/ 64 <537600000>; 1783 required-opps = <&rpmpd_opp_svs>; 1784 opp-peak-kBps = <2929000>; 1785 opp-supported-hw = <0xf>; 1786 }; 1787 1788 opp-355200000 { 1789 opp-hz = /bits/ 64 <355200000>; 1790 required-opps = <&rpmpd_opp_low_svs>; 1791 opp-peak-kBps = <1720000>; 1792 opp-supported-hw = <0xf>; 1793 }; 1794 }; 1795 }; 1796 1797 gmu_wrapper: gmu@596a000 { 1798 compatible = "qcom,adreno-gmu-wrapper"; 1799 reg = <0x0 0x0596a000 0x0 0x30000>; 1800 reg-names = "gmu"; 1801 power-domains = <&gpucc GPU_CX_GDSC>, 1802 <&gpucc GPU_GX_GDSC>; 1803 power-domain-names = "cx", 1804 "gx"; 1805 }; 1806 1807 gpucc: clock-controller@5990000 { 1808 compatible = "qcom,qcm2290-gpucc"; 1809 reg = <0x0 0x05990000 0x0 0x9000>; 1810 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1811 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1812 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1813 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1814 power-domains = <&rpmpd QCM2290_VDDCX>; 1815 required-opps = <&rpmpd_opp_low_svs>; 1816 #clock-cells = <1>; 1817 #reset-cells = <1>; 1818 #power-domain-cells = <1>; 1819 }; 1820 1821 adreno_smmu: iommu@59a0000 { 1822 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", 1823 "qcom,smmu-500", "arm,mmu-500"; 1824 reg = <0x0 0x059a0000 0x0 0x10000>; 1825 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1834 1835 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1836 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1837 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1838 clock-names = "mem", 1839 "hlos", 1840 "iface"; 1841 1842 power-domains = <&gpucc GPU_CX_GDSC>; 1843 1844 #global-interrupts = <1>; 1845 #iommu-cells = <2>; 1846 }; 1847 1848 cci: cci@5c1b000 { 1849 compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; 1850 reg = <0x0 0x5c1b000 0x0 0x1000>; 1851 1852 interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; 1853 1854 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; 1855 clock-names = "ahb", "cci"; 1856 assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; 1857 assigned-clock-rates = <37500000>; 1858 1859 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1860 1861 pinctrl-0 = <&cci0_default &cci1_default>; 1862 pinctrl-names = "default"; 1863 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 1869 cci_i2c0: i2c-bus@0 { 1870 reg = <0>; 1871 clock-frequency = <400000>; 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 }; 1875 1876 cci_i2c1: i2c-bus@1 { 1877 reg = <1>; 1878 clock-frequency = <400000>; 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 }; 1882 }; 1883 1884 camss: camss@5c11000 { 1885 compatible = "qcom,qcm2290-camss"; 1886 1887 reg = <0x0 0x5c11000 0x0 0x1000>, 1888 <0x0 0x5c6e000 0x0 0x1000>, 1889 <0x0 0x5c75000 0x0 0x1000>, 1890 <0x0 0x5c52000 0x0 0x1000>, 1891 <0x0 0x5c53000 0x0 0x1000>, 1892 <0x0 0x5c66000 0x0 0x400>, 1893 <0x0 0x5c68000 0x0 0x400>, 1894 <0x0 0x5c6f000 0x0 0x4000>, 1895 <0x0 0x5c76000 0x0 0x4000>; 1896 reg-names = "top", 1897 "csid0", 1898 "csid1", 1899 "csiphy0", 1900 "csiphy1", 1901 "csitpg0", 1902 "csitpg1", 1903 "vfe0", 1904 "vfe1"; 1905 1906 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 1907 <&gcc GCC_CAMSS_AXI_CLK>, 1908 <&gcc GCC_CAMSS_NRT_AXI_CLK>, 1909 <&gcc GCC_CAMSS_RT_AXI_CLK>, 1910 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, 1911 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, 1912 <&gcc GCC_CAMSS_CPHY_0_CLK>, 1913 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1914 <&gcc GCC_CAMSS_CPHY_1_CLK>, 1915 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1916 <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1917 <&gcc GCC_CAMSS_TFE_0_CLK>, 1918 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, 1919 <&gcc GCC_CAMSS_TFE_1_CLK>, 1920 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK> ; 1921 clock-names = "ahb", 1922 "axi", 1923 "camnoc_nrt_axi", 1924 "camnoc_rt_axi", 1925 "csi0", 1926 "csi1", 1927 "csiphy0", 1928 "csiphy0_timer", 1929 "csiphy1", 1930 "csiphy1_timer", 1931 "top_ahb", 1932 "vfe0", 1933 "vfe0_cphy_rx", 1934 "vfe1", 1935 "vfe1_cphy_rx"; 1936 1937 interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 1938 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 1939 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, 1940 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 1941 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1942 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 1943 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 1944 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 1945 interrupt-names = "csid0", 1946 "csid1", 1947 "csiphy0", 1948 "csiphy1", 1949 "csitpg0", 1950 "csitpg1", 1951 "vfe0", 1952 "vfe1"; 1953 1954 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 1955 &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, 1956 <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG 1957 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1958 <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG 1959 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1960 interconnect-names = "ahb", 1961 "hf_mnoc", 1962 "sf_mnoc"; 1963 1964 iommus = <&apps_smmu 0x400 0x0>, 1965 <&apps_smmu 0x800 0x0>, 1966 <&apps_smmu 0x820 0x0>, 1967 <&apps_smmu 0x840 0x0>; 1968 1969 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1970 1971 status = "disabled"; 1972 1973 ports { 1974 #address-cells = <1>; 1975 #size-cells = <0>; 1976 1977 port@0 { 1978 reg = <0>; 1979 }; 1980 1981 port@1 { 1982 reg = <1>; 1983 }; 1984 }; 1985 }; 1986 1987 mdss: display-subsystem@5e00000 { 1988 compatible = "qcom,qcm2290-mdss"; 1989 reg = <0x0 0x05e00000 0x0 0x1000>; 1990 reg-names = "mdss"; 1991 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1992 interrupt-controller; 1993 #interrupt-cells = <1>; 1994 1995 clocks = <&gcc GCC_DISP_AHB_CLK>, 1996 <&gcc GCC_DISP_HF_AXI_CLK>, 1997 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1998 clock-names = "iface", 1999 "bus", 2000 "core"; 2001 2002 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2003 2004 power-domains = <&dispcc MDSS_GDSC>; 2005 2006 iommus = <&apps_smmu 0x420 0x2>; 2007 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 2008 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 2009 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 2010 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 2011 interconnect-names = "mdp0-mem", 2012 "cpu-cfg"; 2013 2014 #address-cells = <2>; 2015 #size-cells = <2>; 2016 ranges; 2017 2018 status = "disabled"; 2019 2020 mdp: display-controller@5e01000 { 2021 compatible = "qcom,qcm2290-dpu"; 2022 reg = <0x0 0x05e01000 0x0 0x8f000>, 2023 <0x0 0x05eb0000 0x0 0x3000>; 2024 reg-names = "mdp", 2025 "vbif"; 2026 2027 interrupt-parent = <&mdss>; 2028 interrupts = <0>; 2029 2030 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2031 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2032 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2033 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2034 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2035 clock-names = "bus", 2036 "iface", 2037 "core", 2038 "lut", 2039 "vsync"; 2040 2041 operating-points-v2 = <&mdp_opp_table>; 2042 power-domains = <&rpmpd QCM2290_VDDCX>; 2043 2044 ports { 2045 #address-cells = <1>; 2046 #size-cells = <0>; 2047 2048 port@0 { 2049 reg = <0>; 2050 dpu_intf1_out: endpoint { 2051 remote-endpoint = <&mdss_dsi0_in>; 2052 }; 2053 }; 2054 }; 2055 2056 mdp_opp_table: opp-table { 2057 compatible = "operating-points-v2"; 2058 2059 opp-19200000 { 2060 opp-hz = /bits/ 64 <19200000>; 2061 required-opps = <&rpmpd_opp_min_svs>; 2062 }; 2063 2064 opp-192000000 { 2065 opp-hz = /bits/ 64 <192000000>; 2066 required-opps = <&rpmpd_opp_low_svs>; 2067 }; 2068 2069 opp-256000000 { 2070 opp-hz = /bits/ 64 <256000000>; 2071 required-opps = <&rpmpd_opp_svs>; 2072 }; 2073 2074 opp-307200000 { 2075 opp-hz = /bits/ 64 <307200000>; 2076 required-opps = <&rpmpd_opp_svs_plus>; 2077 }; 2078 2079 opp-384000000 { 2080 opp-hz = /bits/ 64 <384000000>; 2081 required-opps = <&rpmpd_opp_nom>; 2082 }; 2083 }; 2084 }; 2085 2086 mdss_dsi0: dsi@5e94000 { 2087 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2088 reg = <0x0 0x05e94000 0x0 0x400>; 2089 reg-names = "dsi_ctrl"; 2090 2091 interrupt-parent = <&mdss>; 2092 interrupts = <4>; 2093 2094 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2095 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2096 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2097 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2098 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2099 <&gcc GCC_DISP_HF_AXI_CLK>; 2100 clock-names = "byte", 2101 "byte_intf", 2102 "pixel", 2103 "core", 2104 "iface", 2105 "bus"; 2106 2107 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2108 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2109 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2110 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2111 2112 operating-points-v2 = <&dsi_opp_table>; 2113 power-domains = <&rpmpd QCM2290_VDDCX>; 2114 phys = <&mdss_dsi0_phy>; 2115 2116 #address-cells = <1>; 2117 #size-cells = <0>; 2118 2119 status = "disabled"; 2120 2121 dsi_opp_table: opp-table { 2122 compatible = "operating-points-v2"; 2123 2124 opp-19200000 { 2125 opp-hz = /bits/ 64 <19200000>; 2126 required-opps = <&rpmpd_opp_min_svs>; 2127 }; 2128 2129 opp-164000000 { 2130 opp-hz = /bits/ 64 <164000000>; 2131 required-opps = <&rpmpd_opp_low_svs>; 2132 }; 2133 2134 opp-187500000 { 2135 opp-hz = /bits/ 64 <187500000>; 2136 required-opps = <&rpmpd_opp_svs>; 2137 }; 2138 }; 2139 2140 ports { 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 2144 port@0 { 2145 reg = <0>; 2146 2147 mdss_dsi0_in: endpoint { 2148 remote-endpoint = <&dpu_intf1_out>; 2149 }; 2150 }; 2151 2152 port@1 { 2153 reg = <1>; 2154 2155 mdss_dsi0_out: endpoint { 2156 }; 2157 }; 2158 }; 2159 }; 2160 2161 mdss_dsi0_phy: phy@5e94400 { 2162 compatible = "qcom,dsi-phy-14nm-2290"; 2163 reg = <0x0 0x05e94400 0x0 0x100>, 2164 <0x0 0x05e94500 0x0 0x300>, 2165 <0x0 0x05e94800 0x0 0x188>; 2166 reg-names = "dsi_phy", 2167 "dsi_phy_lane", 2168 "dsi_pll"; 2169 2170 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2171 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2172 clock-names = "iface", 2173 "ref"; 2174 2175 power-domains = <&rpmpd QCM2290_VDDMX>; 2176 required-opps = <&rpmpd_opp_nom>; 2177 2178 #clock-cells = <1>; 2179 #phy-cells = <0>; 2180 2181 status = "disabled"; 2182 }; 2183 }; 2184 2185 dispcc: clock-controller@5f00000 { 2186 compatible = "qcom,qcm2290-dispcc"; 2187 reg = <0x0 0x05f00000 0x0 0x20000>; 2188 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2189 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 2190 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2191 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 2192 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2193 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2194 clock-names = "bi_tcxo", 2195 "bi_tcxo_ao", 2196 "gcc_disp_gpll0_clk_src", 2197 "gcc_disp_gpll0_div_clk_src", 2198 "dsi0_phy_pll_out_byteclk", 2199 "dsi0_phy_pll_out_dsiclk"; 2200 #power-domain-cells = <1>; 2201 #clock-cells = <1>; 2202 #reset-cells = <1>; 2203 }; 2204 2205 remoteproc_mpss: remoteproc@6080000 { 2206 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 2207 reg = <0x0 0x06080000 0x0 0x100>; 2208 2209 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2210 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2211 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2212 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2213 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2214 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2215 interrupt-names = "wdog", 2216 "fatal", 2217 "ready", 2218 "handover", 2219 "stop-ack", 2220 "shutdown-ack"; 2221 2222 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2223 clock-names = "xo"; 2224 2225 power-domains = <&rpmpd QCM2290_VDDCX>; 2226 2227 memory-region = <&pil_modem_mem>; 2228 2229 qcom,smem-states = <&modem_smp2p_out 0>; 2230 qcom,smem-state-names = "stop"; 2231 2232 status = "disabled"; 2233 2234 glink-edge { 2235 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2236 label = "mpss"; 2237 qcom,remote-pid = <1>; 2238 mboxes = <&apcs_glb 12>; 2239 }; 2240 }; 2241 2242 remoteproc_adsp: remoteproc@ab00000 { 2243 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 2244 reg = <0x0 0x0ab00000 0x0 0x100>; 2245 2246 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2247 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2248 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2249 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2250 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2251 interrupt-names = "wdog", 2252 "fatal", 2253 "ready", 2254 "handover", 2255 "stop-ack"; 2256 2257 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2258 clock-names = "xo"; 2259 2260 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 2261 <&rpmpd QCM2290_VDD_LPI_MX>; 2262 2263 memory-region = <&pil_adsp_mem>; 2264 2265 qcom,smem-states = <&adsp_smp2p_out 0>; 2266 qcom,smem-state-names = "stop"; 2267 2268 status = "disabled"; 2269 2270 glink-edge { 2271 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2272 label = "lpass"; 2273 qcom,remote-pid = <2>; 2274 mboxes = <&apcs_glb 8>; 2275 2276 apr { 2277 compatible = "qcom,apr-v2"; 2278 qcom,glink-channels = "apr_audio_svc"; 2279 qcom,domain = <APR_DOMAIN_ADSP>; 2280 #address-cells = <1>; 2281 #size-cells = <0>; 2282 2283 service@3 { 2284 reg = <APR_SVC_ADSP_CORE>; 2285 compatible = "qcom,q6core"; 2286 qcom,protection-domain = "avs/audio", 2287 "msm/adsp/audio_pd"; 2288 }; 2289 2290 q6afe: service@4 { 2291 compatible = "qcom,q6afe"; 2292 reg = <APR_SVC_AFE>; 2293 qcom,protection-domain = "avs/audio", 2294 "msm/adsp/audio_pd"; 2295 q6afedai: dais { 2296 compatible = "qcom,q6afe-dais"; 2297 #address-cells = <1>; 2298 #size-cells = <0>; 2299 #sound-dai-cells = <1>; 2300 }; 2301 2302 q6afecc: clock-controller { 2303 compatible = "qcom,q6afe-clocks"; 2304 #clock-cells = <2>; 2305 }; 2306 }; 2307 2308 q6asm: service@7 { 2309 compatible = "qcom,q6asm"; 2310 reg = <APR_SVC_ASM>; 2311 qcom,protection-domain = "avs/audio", 2312 "msm/adsp/audio_pd"; 2313 q6asmdai: dais { 2314 compatible = "qcom,q6asm-dais"; 2315 #address-cells = <1>; 2316 #size-cells = <0>; 2317 #sound-dai-cells = <1>; 2318 iommus = <&apps_smmu 0x1c1 0x0>; 2319 2320 dai@0 { 2321 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2322 }; 2323 2324 dai@1 { 2325 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2326 }; 2327 2328 dai@2 { 2329 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2330 }; 2331 }; 2332 }; 2333 2334 q6adm: service@8 { 2335 compatible = "qcom,q6adm"; 2336 reg = <APR_SVC_ADM>; 2337 qcom,protection-domain = "avs/audio", 2338 "msm/adsp/audio_pd"; 2339 q6routing: routing { 2340 compatible = "qcom,q6adm-routing"; 2341 #sound-dai-cells = <0>; 2342 }; 2343 }; 2344 }; 2345 2346 fastrpc { 2347 compatible = "qcom,fastrpc"; 2348 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2349 label = "adsp"; 2350 2351 qcom,non-secure-domain; 2352 2353 #address-cells = <1>; 2354 #size-cells = <0>; 2355 2356 compute-cb@3 { 2357 compatible = "qcom,fastrpc-compute-cb"; 2358 reg = <3>; 2359 iommus = <&apps_smmu 0x1c3 0x0>; 2360 }; 2361 2362 compute-cb@4 { 2363 compatible = "qcom,fastrpc-compute-cb"; 2364 reg = <4>; 2365 iommus = <&apps_smmu 0x1c4 0x0>; 2366 }; 2367 2368 compute-cb@5 { 2369 compatible = "qcom,fastrpc-compute-cb"; 2370 reg = <5>; 2371 iommus = <&apps_smmu 0x1c5 0x0>; 2372 }; 2373 2374 compute-cb@6 { 2375 compatible = "qcom,fastrpc-compute-cb"; 2376 reg = <6>; 2377 iommus = <&apps_smmu 0x1c6 0x0>; 2378 }; 2379 2380 compute-cb@7 { 2381 compatible = "qcom,fastrpc-compute-cb"; 2382 reg = <7>; 2383 iommus = <&apps_smmu 0x1c7 0x0>; 2384 }; 2385 }; 2386 }; 2387 }; 2388 2389 apps_smmu: iommu@c600000 { 2390 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2391 reg = <0x0 0x0c600000 0x0 0x80000>; 2392 #iommu-cells = <2>; 2393 #global-interrupts = <1>; 2394 2395 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2409 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2410 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2411 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2412 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2413 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2414 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2415 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2416 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2417 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2418 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2419 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2420 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2421 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2460 }; 2461 2462 venus: video-codec@5a00000 { 2463 compatible = "qcom,qcm2290-venus"; 2464 reg = <0 0x5a00000 0 0xf0000>; 2465 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 2466 2467 power-domains = <&gcc GCC_VENUS_GDSC>, 2468 <&gcc GCC_VCODEC0_GDSC>, 2469 <&rpmpd QCM2290_VDDCX>; 2470 power-domain-names = "venus", 2471 "vcodec0", 2472 "cx"; 2473 operating-points-v2 = <&venus_opp_table>; 2474 2475 clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, 2476 <&gcc GCC_VIDEO_AHB_CLK>, 2477 <&gcc GCC_VENUS_CTL_AXI_CLK>, 2478 <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, 2479 <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, 2480 <&gcc GCC_VCODEC0_AXI_CLK>; 2481 clock-names = "core", 2482 "iface", 2483 "bus", 2484 "throttle", 2485 "vcodec0_core", 2486 "vcodec0_bus"; 2487 2488 memory-region = <&pil_video_mem>; 2489 iommus = <&apps_smmu 0x860 0x0>, 2490 <&apps_smmu 0x880 0x0>; 2491 2492 interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG 2493 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 2494 <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 2495 &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; 2496 interconnect-names = "video-mem", 2497 "cpu-cfg"; 2498 2499 venus_opp_table: opp-table { 2500 compatible = "operating-points-v2"; 2501 2502 opp-133333333 { 2503 opp-hz = /bits/ 64 <133333333>; 2504 required-opps = <&rpmpd_opp_low_svs>; 2505 }; 2506 2507 opp-240000000 { 2508 opp-hz = /bits/ 64 <240000000>; 2509 required-opps = <&rpmpd_opp_svs>; 2510 }; 2511 2512 opp-300000000 { 2513 opp-hz = /bits/ 64 <300000000>; 2514 required-opps = <&rpmpd_opp_svs_plus>; 2515 }; 2516 2517 opp-384000000 { 2518 opp-hz = /bits/ 64 <384000000>; 2519 required-opps = <&rpmpd_opp_nom>; 2520 }; 2521 }; 2522 }; 2523 2524 wifi: wifi@c800000 { 2525 compatible = "qcom,wcn3990-wifi"; 2526 reg = <0x0 0x0c800000 0x0 0x800000>; 2527 reg-names = "membase"; 2528 memory-region = <&wlan_msa_mem>; 2529 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2533 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2534 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2535 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2538 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2539 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2541 iommus = <&apps_smmu 0x1a0 0x1>; 2542 qcom,msa-fixed-perm; 2543 status = "disabled"; 2544 }; 2545 2546 watchdog@f017000 { 2547 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 2548 reg = <0x0 0x0f017000 0x0 0x1000>; 2549 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 2550 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2551 clocks = <&sleep_clk>; 2552 }; 2553 2554 apcs_glb: mailbox@f111000 { 2555 compatible = "qcom,qcm2290-apcs-hmss-global"; 2556 reg = <0x0 0x0f111000 0x0 0x1000>; 2557 #mbox-cells = <1>; 2558 }; 2559 2560 timer@f120000 { 2561 compatible = "arm,armv7-timer-mem"; 2562 reg = <0x0 0x0f120000 0x0 0x1000>; 2563 #address-cells = <1>; 2564 #size-cells = <1>; 2565 ranges = <0 0x0 0x0f121000 0x8000>; 2566 2567 frame@0 { 2568 reg = <0x0 0x1000>, 2569 <0x1000 0x1000>; 2570 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2571 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2572 frame-number = <0>; 2573 }; 2574 2575 frame@2000 { 2576 reg = <0x2000 0x1000>; 2577 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2578 frame-number = <1>; 2579 status = "disabled"; 2580 }; 2581 2582 frame@3000 { 2583 reg = <0x3000 0x1000>; 2584 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2585 frame-number = <2>; 2586 status = "disabled"; 2587 }; 2588 2589 frame@4000 { 2590 reg = <0x4000 0x1000>; 2591 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2592 frame-number = <3>; 2593 status = "disabled"; 2594 }; 2595 2596 frame@5000 { 2597 reg = <0x5000 0x1000>; 2598 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2599 frame-number = <4>; 2600 status = "disabled"; 2601 }; 2602 2603 frame@6000 { 2604 reg = <0x6000 0x1000>; 2605 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2606 frame-number = <5>; 2607 status = "disabled"; 2608 }; 2609 2610 frame@7000 { 2611 reg = <0x7000 0x1000>; 2612 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2613 frame-number = <6>; 2614 status = "disabled"; 2615 }; 2616 }; 2617 2618 intc: interrupt-controller@f200000 { 2619 compatible = "arm,gic-v3"; 2620 reg = <0x0 0x0f200000 0x0 0x10000>, 2621 <0x0 0x0f300000 0x0 0x100000>; 2622 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2623 #interrupt-cells = <3>; 2624 interrupt-controller; 2625 interrupt-parent = <&intc>; 2626 #redistributor-regions = <1>; 2627 redistributor-stride = <0x0 0x20000>; 2628 }; 2629 2630 cpufreq_hw: cpufreq@f521000 { 2631 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 2632 reg = <0x0 0x0f521000 0x0 0x1000>; 2633 reg-names = "freq-domain0"; 2634 interrupts-extended = <&lmh_cluster 0>; 2635 interrupt-names = "dcvsh-irq-0"; 2636 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2637 clock-names = "xo", "alternate"; 2638 2639 #freq-domain-cells = <1>; 2640 #clock-cells = <1>; 2641 }; 2642 2643 lmh_cluster: lmh@f550800 { 2644 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; 2645 reg = <0x0 0x0f550800 0x0 0x400>; 2646 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2647 cpus = <&cpu0>; 2648 qcom,lmh-temp-arm-millicelsius = <65000>; 2649 qcom,lmh-temp-low-millicelsius = <94500>; 2650 qcom,lmh-temp-high-millicelsius = <95000>; 2651 interrupt-controller; 2652 #interrupt-cells = <1>; 2653 }; 2654 }; 2655 2656 thermal-zones { 2657 mapss-thermal { 2658 thermal-sensors = <&tsens0 0>; 2659 2660 trips { 2661 mapss_alert0: trip-point0 { 2662 temperature = <90000>; 2663 hysteresis = <2000>; 2664 type = "passive"; 2665 }; 2666 2667 mapss_alert1: trip-point1 { 2668 temperature = <95000>; 2669 hysteresis = <2000>; 2670 type = "passive"; 2671 }; 2672 2673 mapss_crit: mapss-crit { 2674 temperature = <110000>; 2675 hysteresis = <1000>; 2676 type = "critical"; 2677 }; 2678 }; 2679 }; 2680 2681 video-thermal { 2682 thermal-sensors = <&tsens0 1>; 2683 2684 trips { 2685 video_alert0: trip-point0 { 2686 temperature = <90000>; 2687 hysteresis = <2000>; 2688 type = "passive"; 2689 }; 2690 2691 video_alert1: trip-point1 { 2692 temperature = <95000>; 2693 hysteresis = <2000>; 2694 type = "passive"; 2695 }; 2696 2697 video_crit: video-crit { 2698 temperature = <110000>; 2699 hysteresis = <1000>; 2700 type = "critical"; 2701 }; 2702 }; 2703 }; 2704 2705 wlan-thermal { 2706 thermal-sensors = <&tsens0 2>; 2707 2708 trips { 2709 wlan_alert0: trip-point0 { 2710 temperature = <90000>; 2711 hysteresis = <2000>; 2712 type = "passive"; 2713 }; 2714 2715 wlan_alert1: trip-point1 { 2716 temperature = <95000>; 2717 hysteresis = <2000>; 2718 type = "passive"; 2719 }; 2720 2721 wlan_crit: wlan-crit { 2722 temperature = <110000>; 2723 hysteresis = <1000>; 2724 type = "critical"; 2725 }; 2726 }; 2727 }; 2728 2729 cpuss0-thermal { 2730 thermal-sensors = <&tsens0 3>; 2731 2732 trips { 2733 cpuss0_alert0: trip-point0 { 2734 temperature = <90000>; 2735 hysteresis = <2000>; 2736 type = "passive"; 2737 }; 2738 2739 cpuss0_alert1: trip-point1 { 2740 temperature = <95000>; 2741 hysteresis = <2000>; 2742 type = "passive"; 2743 }; 2744 2745 cpuss0_crit: cpuss0-crit { 2746 temperature = <110000>; 2747 hysteresis = <1000>; 2748 type = "critical"; 2749 }; 2750 }; 2751 }; 2752 2753 cpuss1-thermal { 2754 thermal-sensors = <&tsens0 4>; 2755 2756 trips { 2757 cpuss1_alert0: trip-point0 { 2758 temperature = <90000>; 2759 hysteresis = <2000>; 2760 type = "passive"; 2761 }; 2762 2763 cpuss1_alert1: trip-point1 { 2764 temperature = <95000>; 2765 hysteresis = <2000>; 2766 type = "passive"; 2767 }; 2768 2769 cpuss1_crit: cpuss1-crit { 2770 temperature = <110000>; 2771 hysteresis = <1000>; 2772 type = "critical"; 2773 }; 2774 }; 2775 }; 2776 2777 mdm0-thermal { 2778 thermal-sensors = <&tsens0 5>; 2779 2780 trips { 2781 mdm0_alert0: trip-point0 { 2782 temperature = <90000>; 2783 hysteresis = <2000>; 2784 type = "passive"; 2785 }; 2786 2787 mdm0_alert1: trip-point1 { 2788 temperature = <95000>; 2789 hysteresis = <2000>; 2790 type = "passive"; 2791 }; 2792 2793 mdm0_crit: mdm0-crit { 2794 temperature = <110000>; 2795 hysteresis = <1000>; 2796 type = "critical"; 2797 }; 2798 }; 2799 }; 2800 2801 mdm1-thermal { 2802 thermal-sensors = <&tsens0 6>; 2803 2804 trips { 2805 mdm1_alert0: trip-point0 { 2806 temperature = <90000>; 2807 hysteresis = <2000>; 2808 type = "passive"; 2809 }; 2810 2811 mdm1_alert1: trip-point1 { 2812 temperature = <95000>; 2813 hysteresis = <2000>; 2814 type = "passive"; 2815 }; 2816 2817 mdm1_crit: mdm1-crit { 2818 temperature = <110000>; 2819 hysteresis = <1000>; 2820 type = "critical"; 2821 }; 2822 }; 2823 }; 2824 2825 gpu-thermal { 2826 thermal-sensors = <&tsens0 7>; 2827 2828 trips { 2829 gpu_alert0: trip-point0 { 2830 temperature = <90000>; 2831 hysteresis = <2000>; 2832 type = "passive"; 2833 }; 2834 2835 gpu_alert1: trip-point1 { 2836 temperature = <95000>; 2837 hysteresis = <2000>; 2838 type = "passive"; 2839 }; 2840 2841 gpu_crit: gpu-crit { 2842 temperature = <110000>; 2843 hysteresis = <1000>; 2844 type = "critical"; 2845 }; 2846 }; 2847 }; 2848 2849 hm-center-thermal { 2850 thermal-sensors = <&tsens0 8>; 2851 2852 trips { 2853 hm_center_alert0: trip-point0 { 2854 temperature = <90000>; 2855 hysteresis = <2000>; 2856 type = "passive"; 2857 }; 2858 2859 hm_center_alert1: trip-point1 { 2860 temperature = <95000>; 2861 hysteresis = <2000>; 2862 type = "passive"; 2863 }; 2864 2865 hm_center_crit: hm-center-crit { 2866 temperature = <110000>; 2867 hysteresis = <1000>; 2868 type = "critical"; 2869 }; 2870 }; 2871 }; 2872 2873 camera-thermal { 2874 thermal-sensors = <&tsens0 9>; 2875 2876 trips { 2877 camera_alert0: trip-point0 { 2878 temperature = <90000>; 2879 hysteresis = <2000>; 2880 type = "passive"; 2881 }; 2882 2883 camera_alert1: trip-point1 { 2884 temperature = <95000>; 2885 hysteresis = <2000>; 2886 type = "passive"; 2887 }; 2888 2889 camera_crit: camera-crit { 2890 temperature = <110000>; 2891 hysteresis = <1000>; 2892 type = "critical"; 2893 }; 2894 }; 2895 }; 2896 }; 2897 2898 timer { 2899 compatible = "arm,armv8-timer"; 2900 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 2901 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 2902 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 2903 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 2904 }; 2905}; 2906