1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Intel Corporation */
3
4 #include "igc.h"
5 #include "igc_base.h"
6 #include "igc_hw.h"
7 #include "igc_tsn.h"
8
9 #define MIN_MULTPLIER_TX_MIN_FRAG 0
10 #define MAX_MULTPLIER_TX_MIN_FRAG 3
11 /* Frag size is based on the Section 8.12.2 of the SW User Manual */
12 #define TX_MIN_FRAG_SIZE 64
13 #define TX_MAX_FRAG_SIZE (TX_MIN_FRAG_SIZE * \
14 (MAX_MULTPLIER_TX_MIN_FRAG + 1))
15
16 enum tx_queue {
17 TX_QUEUE_0 = 0,
18 TX_QUEUE_1,
19 TX_QUEUE_2,
20 TX_QUEUE_3,
21 };
22
23 DEFINE_STATIC_KEY_FALSE(igc_fpe_enabled);
24
igc_fpe_init_smd_frame(struct igc_ring * ring,struct igc_tx_buffer * buffer,struct sk_buff * skb)25 static int igc_fpe_init_smd_frame(struct igc_ring *ring,
26 struct igc_tx_buffer *buffer,
27 struct sk_buff *skb)
28 {
29 dma_addr_t dma = dma_map_single(ring->dev, skb->data, skb->len,
30 DMA_TO_DEVICE);
31
32 if (dma_mapping_error(ring->dev, dma)) {
33 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n");
34 return -ENOMEM;
35 }
36
37 buffer->type = IGC_TX_BUFFER_TYPE_SKB;
38 buffer->skb = skb;
39 buffer->protocol = 0;
40 buffer->bytecount = skb->len;
41 buffer->gso_segs = 1;
42 buffer->time_stamp = jiffies;
43 dma_unmap_len_set(buffer, len, skb->len);
44 dma_unmap_addr_set(buffer, dma, dma);
45
46 return 0;
47 }
48
igc_fpe_init_tx_descriptor(struct igc_ring * ring,struct sk_buff * skb,enum igc_txd_popts_type type)49 static int igc_fpe_init_tx_descriptor(struct igc_ring *ring,
50 struct sk_buff *skb,
51 enum igc_txd_popts_type type)
52 {
53 u32 cmd_type, olinfo_status = 0;
54 struct igc_tx_buffer *buffer;
55 union igc_adv_tx_desc *desc;
56 int err;
57
58 if (!igc_desc_unused(ring))
59 return -EBUSY;
60
61 buffer = &ring->tx_buffer_info[ring->next_to_use];
62 err = igc_fpe_init_smd_frame(ring, buffer, skb);
63 if (err)
64 return err;
65
66 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
67 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |
68 buffer->bytecount;
69
70 olinfo_status |= FIELD_PREP(IGC_ADVTXD_PAYLEN_MASK, buffer->bytecount);
71
72 switch (type) {
73 case SMD_V:
74 case SMD_R:
75 olinfo_status |= FIELD_PREP(IGC_TXD_POPTS_SMD_MASK, type);
76 break;
77 }
78
79 desc = IGC_TX_DESC(ring, ring->next_to_use);
80 desc->read.cmd_type_len = cpu_to_le32(cmd_type);
81 desc->read.olinfo_status = cpu_to_le32(olinfo_status);
82 desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(buffer, dma));
83
84 netdev_tx_sent_queue(txring_txq(ring), skb->len);
85
86 buffer->next_to_watch = desc;
87 ring->next_to_use = (ring->next_to_use + 1) % ring->count;
88
89 return 0;
90 }
91
igc_fpe_xmit_smd_frame(struct igc_adapter * adapter,enum igc_txd_popts_type type)92 static int igc_fpe_xmit_smd_frame(struct igc_adapter *adapter,
93 enum igc_txd_popts_type type)
94 {
95 int cpu = smp_processor_id();
96 struct netdev_queue *nq;
97 struct igc_ring *ring;
98 struct sk_buff *skb;
99 int err;
100
101 ring = igc_get_tx_ring(adapter, cpu);
102 nq = txring_txq(ring);
103
104 skb = alloc_skb(SMD_FRAME_SIZE, GFP_ATOMIC);
105 if (!skb)
106 return -ENOMEM;
107
108 skb_put_zero(skb, SMD_FRAME_SIZE);
109
110 __netif_tx_lock(nq, cpu);
111
112 err = igc_fpe_init_tx_descriptor(ring, skb, type);
113 if (err)
114 goto err_free_skb_any;
115
116 igc_flush_tx_descriptors(ring);
117 __netif_tx_unlock(nq);
118 return 0;
119
120 err_free_skb_any:
121 __netif_tx_unlock(nq);
122 dev_kfree_skb_any(skb);
123 return err;
124 }
125
igc_fpe_configure_tx(struct ethtool_mmsv * mmsv,bool tx_enable)126 static void igc_fpe_configure_tx(struct ethtool_mmsv *mmsv, bool tx_enable)
127 {
128 struct igc_fpe_t *fpe = container_of(mmsv, struct igc_fpe_t, mmsv);
129 struct igc_adapter *adapter;
130
131 adapter = container_of(fpe, struct igc_adapter, fpe);
132 adapter->fpe.tx_enabled = tx_enable;
133
134 /* Update config since tx_enabled affects preemptible queue configuration */
135 igc_tsn_offload_apply(adapter);
136 }
137
igc_fpe_send_mpacket(struct ethtool_mmsv * mmsv,enum ethtool_mpacket type)138 static void igc_fpe_send_mpacket(struct ethtool_mmsv *mmsv,
139 enum ethtool_mpacket type)
140 {
141 struct igc_fpe_t *fpe = container_of(mmsv, struct igc_fpe_t, mmsv);
142 struct igc_adapter *adapter;
143 int err;
144
145 adapter = container_of(fpe, struct igc_adapter, fpe);
146
147 if (type == ETHTOOL_MPACKET_VERIFY) {
148 err = igc_fpe_xmit_smd_frame(adapter, SMD_V);
149 if (err && net_ratelimit())
150 netdev_err(adapter->netdev, "Error sending SMD-V\n");
151 } else if (type == ETHTOOL_MPACKET_RESPONSE) {
152 err = igc_fpe_xmit_smd_frame(adapter, SMD_R);
153 if (err && net_ratelimit())
154 netdev_err(adapter->netdev, "Error sending SMD-R frame\n");
155 }
156 }
157
158 static const struct ethtool_mmsv_ops igc_mmsv_ops = {
159 .configure_tx = igc_fpe_configure_tx,
160 .send_mpacket = igc_fpe_send_mpacket,
161 };
162
igc_fpe_init(struct igc_adapter * adapter)163 void igc_fpe_init(struct igc_adapter *adapter)
164 {
165 adapter->fpe.tx_min_frag_size = TX_MIN_FRAG_SIZE;
166 adapter->fpe.tx_enabled = false;
167 ethtool_mmsv_init(&adapter->fpe.mmsv, adapter->netdev, &igc_mmsv_ops);
168 }
169
igc_fpe_clear_preempt_queue(struct igc_adapter * adapter)170 void igc_fpe_clear_preempt_queue(struct igc_adapter *adapter)
171 {
172 for (int i = 0; i < adapter->num_tx_queues; i++) {
173 struct igc_ring *tx_ring = adapter->tx_ring[i];
174
175 tx_ring->preemptible = false;
176 }
177 }
178
igc_fpe_map_preempt_tc_to_queue(const struct igc_adapter * adapter,unsigned long preemptible_tcs)179 static u32 igc_fpe_map_preempt_tc_to_queue(const struct igc_adapter *adapter,
180 unsigned long preemptible_tcs)
181 {
182 struct net_device *dev = adapter->netdev;
183 u32 i, queue = 0;
184
185 for (i = 0; i < netdev_get_num_tc(dev); i++) {
186 struct netdev_tc_txq res;
187 u32 offset, count;
188
189 if (!(preemptible_tcs & BIT(i)))
190 continue;
191
192 res.combined = READ_ONCE(dev->tc_to_txq[i].combined);
193 offset = res.offset;
194 count = res.count;
195 queue |= GENMASK(offset + count - 1, offset);
196 }
197
198 return queue;
199 }
200
igc_fpe_save_preempt_queue(struct igc_adapter * adapter,const struct tc_mqprio_qopt_offload * mqprio)201 void igc_fpe_save_preempt_queue(struct igc_adapter *adapter,
202 const struct tc_mqprio_qopt_offload *mqprio)
203 {
204 u32 preemptible_queue = igc_fpe_map_preempt_tc_to_queue(adapter,
205 mqprio->preemptible_tcs);
206
207 for (int i = 0; i < adapter->num_tx_queues; i++) {
208 struct igc_ring *tx_ring = adapter->tx_ring[i];
209
210 tx_ring->preemptible = !!(preemptible_queue & BIT(i));
211 }
212 }
213
is_any_launchtime(struct igc_adapter * adapter)214 static bool is_any_launchtime(struct igc_adapter *adapter)
215 {
216 int i;
217
218 for (i = 0; i < adapter->num_tx_queues; i++) {
219 struct igc_ring *ring = adapter->tx_ring[i];
220
221 if (ring->launchtime_enable)
222 return true;
223 }
224
225 return false;
226 }
227
is_cbs_enabled(struct igc_adapter * adapter)228 static bool is_cbs_enabled(struct igc_adapter *adapter)
229 {
230 int i;
231
232 for (i = 0; i < adapter->num_tx_queues; i++) {
233 struct igc_ring *ring = adapter->tx_ring[i];
234
235 if (ring->cbs_enable)
236 return true;
237 }
238
239 return false;
240 }
241
igc_tsn_new_flags(struct igc_adapter * adapter)242 static unsigned int igc_tsn_new_flags(struct igc_adapter *adapter)
243 {
244 unsigned int new_flags = adapter->flags & ~IGC_FLAG_TSN_ANY_ENABLED;
245
246
247 if (adapter->taprio_offload_enable || is_any_launchtime(adapter) ||
248 adapter->strict_priority_enable)
249 new_flags |= IGC_FLAG_TSN_QBV_ENABLED;
250
251 if (is_cbs_enabled(adapter))
252 new_flags |= IGC_FLAG_TSN_QAV_ENABLED;
253
254 if (adapter->fpe.mmsv.pmac_enabled)
255 new_flags |= IGC_FLAG_TSN_PREEMPT_ENABLED;
256
257 return new_flags;
258 }
259
igc_tsn_is_tx_mode_in_tsn(struct igc_adapter * adapter)260 static bool igc_tsn_is_tx_mode_in_tsn(struct igc_adapter *adapter)
261 {
262 struct igc_hw *hw = &adapter->hw;
263
264 return !!(rd32(IGC_TQAVCTRL) & IGC_TQAVCTRL_TRANSMIT_MODE_TSN);
265 }
266
igc_tsn_adjust_txtime_offset(struct igc_adapter * adapter)267 void igc_tsn_adjust_txtime_offset(struct igc_adapter *adapter)
268 {
269 struct igc_hw *hw = &adapter->hw;
270 u16 txoffset;
271
272 if (!igc_tsn_is_tx_mode_in_tsn(adapter))
273 return;
274
275 switch (adapter->link_speed) {
276 case SPEED_10:
277 txoffset = IGC_TXOFFSET_SPEED_10;
278 break;
279 case SPEED_100:
280 txoffset = IGC_TXOFFSET_SPEED_100;
281 break;
282 case SPEED_1000:
283 txoffset = IGC_TXOFFSET_SPEED_1000;
284 break;
285 case SPEED_2500:
286 txoffset = IGC_TXOFFSET_SPEED_2500;
287 break;
288 default:
289 txoffset = 0;
290 break;
291 }
292
293 wr32(IGC_GTXOFFSET, txoffset);
294 }
295
igc_tsn_restore_retx_default(struct igc_adapter * adapter)296 static void igc_tsn_restore_retx_default(struct igc_adapter *adapter)
297 {
298 struct igc_hw *hw = &adapter->hw;
299 u32 retxctl;
300
301 retxctl = rd32(IGC_RETX_CTL) & IGC_RETX_CTL_WATERMARK_MASK;
302 wr32(IGC_RETX_CTL, retxctl);
303 }
304
igc_tsn_is_taprio_activated_by_user(struct igc_adapter * adapter)305 bool igc_tsn_is_taprio_activated_by_user(struct igc_adapter *adapter)
306 {
307 struct igc_hw *hw = &adapter->hw;
308
309 return (rd32(IGC_BASET_H) || rd32(IGC_BASET_L)) &&
310 adapter->taprio_offload_enable;
311 }
312
igc_tsn_tx_arb(struct igc_adapter * adapter,bool reverse_prio)313 static void igc_tsn_tx_arb(struct igc_adapter *adapter, bool reverse_prio)
314 {
315 struct igc_hw *hw = &adapter->hw;
316 u32 txarb;
317
318 txarb = rd32(IGC_TXARB);
319
320 txarb &= ~(IGC_TXARB_TXQ_PRIO_0_MASK |
321 IGC_TXARB_TXQ_PRIO_1_MASK |
322 IGC_TXARB_TXQ_PRIO_2_MASK |
323 IGC_TXARB_TXQ_PRIO_3_MASK);
324
325 if (reverse_prio) {
326 txarb |= IGC_TXARB_TXQ_PRIO_0(TX_QUEUE_3);
327 txarb |= IGC_TXARB_TXQ_PRIO_1(TX_QUEUE_2);
328 txarb |= IGC_TXARB_TXQ_PRIO_2(TX_QUEUE_1);
329 txarb |= IGC_TXARB_TXQ_PRIO_3(TX_QUEUE_0);
330 } else {
331 txarb |= IGC_TXARB_TXQ_PRIO_0(TX_QUEUE_0);
332 txarb |= IGC_TXARB_TXQ_PRIO_1(TX_QUEUE_1);
333 txarb |= IGC_TXARB_TXQ_PRIO_2(TX_QUEUE_2);
334 txarb |= IGC_TXARB_TXQ_PRIO_3(TX_QUEUE_3);
335 }
336
337 wr32(IGC_TXARB, txarb);
338 }
339
340 /**
341 * igc_tsn_set_rxpbsize - Set the receive packet buffer size
342 * @adapter: Pointer to the igc_adapter structure
343 * @rxpbs_exp_bmc_be: Value to set the receive packet buffer size, including
344 * express buffer, BMC buffer, and Best Effort buffer
345 *
346 * The IGC_RXPBS register value may include allocations for the Express buffer,
347 * BMC buffer, Best Effort buffer, and the timestamp descriptor buffer
348 * (IGC_RXPBS_CFG_TS_EN).
349 */
igc_tsn_set_rxpbsize(struct igc_adapter * adapter,u32 rxpbs_exp_bmc_be)350 static void igc_tsn_set_rxpbsize(struct igc_adapter *adapter,
351 u32 rxpbs_exp_bmc_be)
352 {
353 struct igc_hw *hw = &adapter->hw;
354 u32 rxpbs = rd32(IGC_RXPBS);
355
356 rxpbs &= ~(IGC_RXPBSIZE_EXP_MASK | IGC_BMC2OSPBSIZE_MASK |
357 IGC_RXPBSIZE_BE_MASK);
358 rxpbs |= rxpbs_exp_bmc_be;
359
360 wr32(IGC_RXPBS, rxpbs);
361 }
362
363 /* Returns the TSN specific registers to their default values after
364 * the adapter is reset.
365 */
igc_tsn_disable_offload(struct igc_adapter * adapter)366 static int igc_tsn_disable_offload(struct igc_adapter *adapter)
367 {
368 struct igc_hw *hw = &adapter->hw;
369 u32 tqavctrl;
370 int i;
371
372 wr32(IGC_GTXOFFSET, 0);
373 wr32(IGC_TXPBS, IGC_TXPBSIZE_DEFAULT);
374 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT);
375
376 igc_tsn_set_rxpbsize(adapter, IGC_RXPBSIZE_EXP_BMC_DEFAULT);
377
378 if (igc_is_device_id_i226(hw))
379 igc_tsn_restore_retx_default(adapter);
380
381 tqavctrl = rd32(IGC_TQAVCTRL);
382 tqavctrl &= ~(IGC_TQAVCTRL_TRANSMIT_MODE_TSN |
383 IGC_TQAVCTRL_ENHANCED_QAV | IGC_TQAVCTRL_FUTSCDDIS |
384 IGC_TQAVCTRL_PREEMPT_ENA | IGC_TQAVCTRL_MIN_FRAG_MASK);
385
386 wr32(IGC_TQAVCTRL, tqavctrl);
387
388 for (i = 0; i < adapter->num_tx_queues; i++) {
389 int reg_idx = adapter->tx_ring[i]->reg_idx;
390 u32 txdctl;
391
392 wr32(IGC_TXQCTL(i), 0);
393 wr32(IGC_STQT(i), 0);
394 wr32(IGC_ENDQT(i), NSEC_PER_SEC);
395
396 txdctl = rd32(IGC_TXDCTL(reg_idx));
397 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH;
398 wr32(IGC_TXDCTL(reg_idx), txdctl);
399 }
400
401 wr32(IGC_QBVCYCLET_S, 0);
402 wr32(IGC_QBVCYCLET, NSEC_PER_SEC);
403
404 /* Restore the default Tx arbitration: Priority 0 has the highest
405 * priority and is assigned to queue 0 and so on and so forth.
406 */
407 igc_tsn_tx_arb(adapter, false);
408
409 adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;
410
411 return 0;
412 }
413
414 /* To partially fix i226 HW errata, reduce MAC internal buffering from 192 Bytes
415 * to 88 Bytes by setting RETX_CTL register using the recommendation from:
416 * a) Ethernet Controller I225/I226 Specification Update Rev 2.1
417 * Item 9: TSN: Packet Transmission Might Cross the Qbv Window
418 * b) I225/6 SW User Manual Rev 1.2.4: Section 8.11.5 Retry Buffer Control
419 */
igc_tsn_set_retx_qbvfullthreshold(struct igc_adapter * adapter)420 static void igc_tsn_set_retx_qbvfullthreshold(struct igc_adapter *adapter)
421 {
422 struct igc_hw *hw = &adapter->hw;
423 u32 retxctl, watermark;
424
425 retxctl = rd32(IGC_RETX_CTL);
426 watermark = retxctl & IGC_RETX_CTL_WATERMARK_MASK;
427 /* Set QBVFULLTH value using watermark and set QBVFULLEN */
428 retxctl |= (watermark << IGC_RETX_CTL_QBVFULLTH_SHIFT) |
429 IGC_RETX_CTL_QBVFULLEN;
430 wr32(IGC_RETX_CTL, retxctl);
431 }
432
igc_fpe_get_frag_size_mult(const struct igc_fpe_t * fpe)433 static u8 igc_fpe_get_frag_size_mult(const struct igc_fpe_t *fpe)
434 {
435 u8 mult = (fpe->tx_min_frag_size / TX_MIN_FRAG_SIZE) - 1;
436
437 return clamp_t(u8, mult, MIN_MULTPLIER_TX_MIN_FRAG,
438 MAX_MULTPLIER_TX_MIN_FRAG);
439 }
440
igc_fpe_get_supported_frag_size(u32 frag_size)441 u32 igc_fpe_get_supported_frag_size(u32 frag_size)
442 {
443 static const u32 supported_sizes[] = { 64, 128, 192, 256 };
444
445 /* Find the smallest supported size that is >= frag_size */
446 for (int i = 0; i < ARRAY_SIZE(supported_sizes); i++) {
447 if (frag_size <= supported_sizes[i])
448 return supported_sizes[i];
449 }
450
451 /* Should not happen */
452 return TX_MAX_FRAG_SIZE;
453 }
454
igc_tsn_enable_offload(struct igc_adapter * adapter)455 static int igc_tsn_enable_offload(struct igc_adapter *adapter)
456 {
457 struct igc_hw *hw = &adapter->hw;
458 u32 tqavctrl, baset_l, baset_h;
459 u32 sec, nsec, cycle;
460 ktime_t base_time, systim;
461 u32 frag_size_mult;
462 int i;
463
464 wr32(IGC_TSAUXC, 0);
465 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN);
466 wr32(IGC_TXPBS, IGC_TXPBSIZE_TSN);
467
468 igc_tsn_set_rxpbsize(adapter, IGC_RXPBSIZE_EXP_BMC_BE_TSN);
469
470 if (igc_is_device_id_i226(hw))
471 igc_tsn_set_retx_qbvfullthreshold(adapter);
472
473 if (adapter->strict_priority_enable ||
474 adapter->flags & IGC_FLAG_TSN_REVERSE_TXQ_PRIO)
475 igc_tsn_tx_arb(adapter, true);
476
477 for (i = 0; i < adapter->num_tx_queues; i++) {
478 struct igc_ring *ring = adapter->tx_ring[i];
479 u32 txdctl = rd32(IGC_TXDCTL(ring->reg_idx));
480 u32 txqctl = 0;
481 u16 cbs_value;
482 u32 tqavcc;
483
484 wr32(IGC_STQT(i), ring->start_time);
485 wr32(IGC_ENDQT(i), ring->end_time);
486
487 if (adapter->taprio_offload_enable) {
488 /* If taprio_offload_enable is set we are in "taprio"
489 * mode and we need to be strict about the
490 * cycles: only transmit a packet if it can be
491 * completed during that cycle.
492 *
493 * If taprio_offload_enable is NOT true when
494 * enabling TSN offload, the cycle should have
495 * no external effects, but is only used internally
496 * to adapt the base time register after a second
497 * has passed.
498 *
499 * Enabling strict mode in this case would
500 * unnecessarily prevent the transmission of
501 * certain packets (i.e. at the boundary of a
502 * second) and thus interfere with the launchtime
503 * feature that promises transmission at a
504 * certain point in time.
505 */
506 txqctl |= IGC_TXQCTL_STRICT_CYCLE |
507 IGC_TXQCTL_STRICT_END;
508 }
509
510 if (ring->launchtime_enable)
511 txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;
512
513 if (!adapter->fpe.tx_enabled) {
514 /* fpe inactive: clear both flags */
515 txqctl &= ~IGC_TXQCTL_PREEMPTIBLE;
516 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH;
517 } else if (ring->preemptible) {
518 /* fpe active + preemptible: enable preemptible queue + set low priority */
519 txqctl |= IGC_TXQCTL_PREEMPTIBLE;
520 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH;
521 } else {
522 /* fpe active + express: enable express queue + set high priority */
523 txqctl &= ~IGC_TXQCTL_PREEMPTIBLE;
524 txdctl |= IGC_TXDCTL_PRIORITY_HIGH;
525 }
526
527 wr32(IGC_TXDCTL(ring->reg_idx), txdctl);
528
529 /* Skip configuring CBS for Q2 and Q3 */
530 if (i > 1)
531 goto skip_cbs;
532
533 if (ring->cbs_enable) {
534 if (i == 0)
535 txqctl |= IGC_TXQCTL_QAV_SEL_CBS0;
536 else
537 txqctl |= IGC_TXQCTL_QAV_SEL_CBS1;
538
539 /* According to i225 datasheet section 7.5.2.7, we
540 * should set the 'idleSlope' field from TQAVCC
541 * register following the equation:
542 *
543 * value = link-speed 0x7736 * BW * 0.2
544 * ---------- * ----------------- (E1)
545 * 100Mbps 2.5
546 *
547 * Note that 'link-speed' is in Mbps.
548 *
549 * 'BW' is the percentage bandwidth out of full
550 * link speed which can be found with the
551 * following equation. Note that idleSlope here
552 * is the parameter from this function
553 * which is in kbps.
554 *
555 * BW = idleSlope
556 * ----------------- (E2)
557 * link-speed * 1000
558 *
559 * That said, we can come up with a generic
560 * equation to calculate the value we should set
561 * it TQAVCC register by replacing 'BW' in E1 by E2.
562 * The resulting equation is:
563 *
564 * value = link-speed * 0x7736 * idleSlope * 0.2
565 * ------------------------------------- (E3)
566 * 100 * 2.5 * link-speed * 1000
567 *
568 * 'link-speed' is present in both sides of the
569 * fraction so it is canceled out. The final
570 * equation is the following:
571 *
572 * value = idleSlope * 61036
573 * ----------------- (E4)
574 * 2500000
575 *
576 * NOTE: For i225, given the above, we can see
577 * that idleslope is represented in
578 * 40.959433 kbps units by the value at
579 * the TQAVCC register (2.5Gbps / 61036),
580 * which reduces the granularity for
581 * idleslope increments.
582 *
583 * In i225 controller, the sendSlope and loCredit
584 * parameters from CBS are not configurable
585 * by software so we don't do any
586 * 'controller configuration' in respect to
587 * these parameters.
588 */
589 cbs_value = DIV_ROUND_UP_ULL(ring->idleslope
590 * 61036ULL, 2500000);
591
592 tqavcc = rd32(IGC_TQAVCC(i));
593 tqavcc &= ~IGC_TQAVCC_IDLESLOPE_MASK;
594 tqavcc |= cbs_value | IGC_TQAVCC_KEEP_CREDITS;
595 wr32(IGC_TQAVCC(i), tqavcc);
596
597 wr32(IGC_TQAVHC(i),
598 0x80000000 + ring->hicredit * 0x7736);
599 } else {
600 /* Disable any CBS for the queue */
601 txqctl &= ~(IGC_TXQCTL_QAV_SEL_MASK);
602
603 /* Set idleSlope to zero. */
604 tqavcc = rd32(IGC_TQAVCC(i));
605 tqavcc &= ~(IGC_TQAVCC_IDLESLOPE_MASK |
606 IGC_TQAVCC_KEEP_CREDITS);
607 wr32(IGC_TQAVCC(i), tqavcc);
608
609 /* Set hiCredit to zero. */
610 wr32(IGC_TQAVHC(i), 0);
611 }
612 skip_cbs:
613 wr32(IGC_TXQCTL(i), txqctl);
614 }
615
616 tqavctrl = rd32(IGC_TQAVCTRL) & ~(IGC_TQAVCTRL_FUTSCDDIS |
617 IGC_TQAVCTRL_PREEMPT_ENA | IGC_TQAVCTRL_MIN_FRAG_MASK);
618 tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;
619
620 if (adapter->fpe.mmsv.pmac_enabled)
621 tqavctrl |= IGC_TQAVCTRL_PREEMPT_ENA;
622
623 frag_size_mult = igc_fpe_get_frag_size_mult(&adapter->fpe);
624 tqavctrl |= FIELD_PREP(IGC_TQAVCTRL_MIN_FRAG_MASK, frag_size_mult);
625
626 adapter->qbv_count++;
627
628 cycle = adapter->cycle_time;
629 base_time = adapter->base_time;
630
631 nsec = rd32(IGC_SYSTIML);
632 sec = rd32(IGC_SYSTIMH);
633
634 systim = ktime_set(sec, nsec);
635 if (ktime_compare(systim, base_time) > 0) {
636 s64 n = div64_s64(ktime_sub_ns(systim, base_time), cycle);
637
638 base_time = ktime_add_ns(base_time, (n + 1) * cycle);
639 } else {
640 if (igc_is_device_id_i226(hw)) {
641 ktime_t adjust_time, expires_time;
642
643 /* According to datasheet section 7.5.2.9.3.3, FutScdDis bit
644 * has to be configured before the cycle time and base time.
645 * Tx won't hang if a GCL is already running,
646 * so in this case we don't need to set FutScdDis.
647 */
648 if (!(rd32(IGC_BASET_H) || rd32(IGC_BASET_L)))
649 tqavctrl |= IGC_TQAVCTRL_FUTSCDDIS;
650
651 nsec = rd32(IGC_SYSTIML);
652 sec = rd32(IGC_SYSTIMH);
653 systim = ktime_set(sec, nsec);
654
655 adjust_time = adapter->base_time;
656 expires_time = ktime_sub_ns(adjust_time, systim);
657 hrtimer_start(&adapter->hrtimer, expires_time, HRTIMER_MODE_REL);
658 }
659 }
660
661 wr32(IGC_TQAVCTRL, tqavctrl);
662
663 wr32(IGC_QBVCYCLET_S, cycle);
664 wr32(IGC_QBVCYCLET, cycle);
665
666 baset_h = div_s64_rem(base_time, NSEC_PER_SEC, &baset_l);
667 wr32(IGC_BASET_H, baset_h);
668
669 /* In i226, Future base time is only supported when FutScdDis bit
670 * is enabled and only active for re-configuration.
671 * In this case, initialize the base time with zero to create
672 * "re-configuration" scenario then only set the desired base time.
673 */
674 if (tqavctrl & IGC_TQAVCTRL_FUTSCDDIS)
675 wr32(IGC_BASET_L, 0);
676 wr32(IGC_BASET_L, baset_l);
677
678 return 0;
679 }
680
igc_tsn_reset(struct igc_adapter * adapter)681 int igc_tsn_reset(struct igc_adapter *adapter)
682 {
683 unsigned int new_flags;
684 int err = 0;
685
686 if (adapter->fpe.mmsv.pmac_enabled) {
687 err = igc_enable_empty_addr_recv(adapter);
688 if (err && net_ratelimit())
689 netdev_err(adapter->netdev, "Error adding empty address to MAC filter\n");
690 } else {
691 igc_disable_empty_addr_recv(adapter);
692 }
693
694 new_flags = igc_tsn_new_flags(adapter);
695
696 if (!(new_flags & IGC_FLAG_TSN_ANY_ENABLED))
697 return igc_tsn_disable_offload(adapter);
698
699 err = igc_tsn_enable_offload(adapter);
700 if (err < 0)
701 return err;
702
703 adapter->flags = new_flags;
704
705 return err;
706 }
707
igc_tsn_will_tx_mode_change(struct igc_adapter * adapter)708 static bool igc_tsn_will_tx_mode_change(struct igc_adapter *adapter)
709 {
710 bool any_tsn_enabled = !!(igc_tsn_new_flags(adapter) &
711 IGC_FLAG_TSN_ANY_ENABLED);
712
713 return (any_tsn_enabled && !igc_tsn_is_tx_mode_in_tsn(adapter)) ||
714 (!any_tsn_enabled && igc_tsn_is_tx_mode_in_tsn(adapter));
715 }
716
igc_tsn_offload_apply(struct igc_adapter * adapter)717 int igc_tsn_offload_apply(struct igc_adapter *adapter)
718 {
719 /* Per I225/6 HW Design Section 7.5.2.1 guideline, if tx mode change
720 * from legacy->tsn or tsn->legacy, then reset adapter is needed.
721 */
722 if (netif_running(adapter->netdev) &&
723 igc_tsn_will_tx_mode_change(adapter)) {
724 schedule_work(&adapter->reset_task);
725 return 0;
726 }
727
728 igc_tsn_reset(adapter);
729
730 return 0;
731 }
732