1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * FU740 DesignWare PCIe Controller integration
4 * Copyright (C) 2019-2021 SiFive, Inc.
5 * Paul Walmsley
6 * Greentime Hu
7 *
8 * Based in part on the i.MX6 PCIe host controller shim which is:
9 *
10 * Copyright (C) 2013 Kosagi
11 * https://www.kosagi.com
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/platform_device.h>
21 #include <linux/resource.h>
22 #include <linux/types.h>
23 #include <linux/interrupt.h>
24 #include <linux/iopoll.h>
25 #include <linux/reset.h>
26
27 #include "pcie-designware.h"
28
29 #define to_fu740_pcie(x) dev_get_drvdata((x)->dev)
30
31 struct fu740_pcie {
32 struct dw_pcie pci;
33 void __iomem *mgmt_base;
34 struct gpio_desc *reset;
35 struct gpio_desc *pwren;
36 struct clk *pcie_aux;
37 struct reset_control *rst;
38 };
39
40 #define SIFIVE_DEVICESRESETREG 0x28
41
42 #define PCIEX8MGMT_PERST_N 0x0
43 #define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
44 #define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
45 #define PCIEX8MGMT_DEVICE_TYPE 0x708
46 #define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
47 #define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
48 #define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
49 #define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
50 #define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
51 #define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
52 #define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
53 #define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
54 #define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
55 #define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
56 #define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
57 #define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
58 #define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
59 #define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
60
61 #define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0)
62 #define PCIEX8MGMT_PHY_LOS_THRSHLD BIT(5)
63 #define PCIEX8MGMT_PHY_TERM_EN BIT(9)
64 #define PCIEX8MGMT_PHY_TERM_ACDC BIT(10)
65 #define PCIEX8MGMT_PHY_EN BIT(11)
66 #define PCIEX8MGMT_PHY_INIT_VAL (PCIEX8MGMT_PHY_CDR_TRACK_EN|\
67 PCIEX8MGMT_PHY_LOS_THRSHLD|\
68 PCIEX8MGMT_PHY_TERM_EN|\
69 PCIEX8MGMT_PHY_TERM_ACDC|\
70 PCIEX8MGMT_PHY_EN)
71
72 #define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 0x1008
73 #define PCIEX8MGMT_PHY_LANE_OFF 0x100
74 #define PCIEX8MGMT_PHY_LANE0_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 0)
75 #define PCIEX8MGMT_PHY_LANE1_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 1)
76 #define PCIEX8MGMT_PHY_LANE2_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 2)
77 #define PCIEX8MGMT_PHY_LANE3_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 3)
78
fu740_pcie_assert_reset(struct fu740_pcie * afp)79 static void fu740_pcie_assert_reset(struct fu740_pcie *afp)
80 {
81 /* Assert PERST_N GPIO */
82 gpiod_set_value_cansleep(afp->reset, 0);
83 /* Assert controller PERST_N */
84 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);
85 }
86
fu740_pcie_deassert_reset(struct fu740_pcie * afp)87 static void fu740_pcie_deassert_reset(struct fu740_pcie *afp)
88 {
89 /* Deassert controller PERST_N */
90 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);
91 /* Deassert PERST_N GPIO */
92 gpiod_set_value_cansleep(afp->reset, 1);
93 }
94
fu740_pcie_power_on(struct fu740_pcie * afp)95 static void fu740_pcie_power_on(struct fu740_pcie *afp)
96 {
97 gpiod_set_value_cansleep(afp->pwren, 1);
98 /*
99 * Ensure that PERST has been asserted for at least 100 ms.
100 * Section 2.2 of PCI Express Card Electromechanical Specification
101 * Revision 3.0
102 */
103 msleep(100);
104 }
105
fu740_pcie_drive_reset(struct fu740_pcie * afp)106 static void fu740_pcie_drive_reset(struct fu740_pcie *afp)
107 {
108 fu740_pcie_assert_reset(afp);
109 fu740_pcie_power_on(afp);
110 fu740_pcie_deassert_reset(afp);
111 }
112
fu740_phyregwrite(const uint8_t phy,const uint16_t addr,const uint16_t wrdata,struct fu740_pcie * afp)113 static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr,
114 const uint16_t wrdata, struct fu740_pcie *afp)
115 {
116 struct device *dev = afp->pci.dev;
117 void __iomem *phy_cr_para_addr;
118 void __iomem *phy_cr_para_wr_data;
119 void __iomem *phy_cr_para_wr_en;
120 void __iomem *phy_cr_para_ack;
121 int ret, val;
122
123 /* Setup */
124 if (phy) {
125 phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR;
126 phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA;
127 phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN;
128 phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK;
129 } else {
130 phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR;
131 phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA;
132 phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN;
133 phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK;
134 }
135
136 writel_relaxed(addr, phy_cr_para_addr);
137 writel_relaxed(wrdata, phy_cr_para_wr_data);
138 writel_relaxed(1, phy_cr_para_wr_en);
139
140 /* Wait for wait_idle */
141 ret = readl_poll_timeout(phy_cr_para_ack, val, val, 10, 5000);
142 if (ret)
143 dev_warn(dev, "Wait for wait_idle state failed!\n");
144
145 /* Clear */
146 writel_relaxed(0, phy_cr_para_wr_en);
147
148 /* Wait for ~wait_idle */
149 ret = readl_poll_timeout(phy_cr_para_ack, val, !val, 10, 5000);
150 if (ret)
151 dev_warn(dev, "Wait for !wait_idle state failed!\n");
152 }
153
fu740_pcie_init_phy(struct fu740_pcie * afp)154 static void fu740_pcie_init_phy(struct fu740_pcie *afp)
155 {
156 /* Enable phy cr_para_sel interfaces */
157 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
158 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
159
160 /*
161 * Wait 10 cr_para cycles to guarantee that the registers are ready
162 * to be edited.
163 */
164 ndelay(10);
165
166 /* Set PHY AC termination mode */
167 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
168 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
169 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
170 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
171 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
172 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
173 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
174 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
175 }
176
fu740_pcie_start_link(struct dw_pcie * pci)177 static int fu740_pcie_start_link(struct dw_pcie *pci)
178 {
179 struct device *dev = pci->dev;
180 struct fu740_pcie *afp = dev_get_drvdata(dev);
181 u8 cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
182 int ret;
183 u32 orig, tmp;
184
185 /*
186 * Force 2.5GT/s when starting the link, due to some devices not
187 * probing at higher speeds. This happens with the PCIe switch
188 * on the Unmatched board when U-Boot has not initialised the PCIe.
189 * The fix in U-Boot is to force 2.5GT/s, which then gets cleared
190 * by the soft reset done by this driver.
191 */
192 dev_dbg(dev, "cap_exp at %x\n", cap_exp);
193 dw_pcie_dbi_ro_wr_en(pci);
194
195 tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
196 orig = tmp & PCI_EXP_LNKCAP_SLS;
197 tmp &= ~PCI_EXP_LNKCAP_SLS;
198 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
199 dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
200
201 /* Enable LTSSM */
202 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
203
204 ret = dw_pcie_wait_for_link(pci);
205 if (ret) {
206 dev_err(dev, "error: link did not start\n");
207 goto err;
208 }
209
210 tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
211 if ((tmp & PCI_EXP_LNKCAP_SLS) != orig) {
212 dev_dbg(dev, "changing speed back to original\n");
213
214 tmp &= ~PCI_EXP_LNKCAP_SLS;
215 tmp |= orig;
216 dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
217
218 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
219 tmp |= PORT_LOGIC_SPEED_CHANGE;
220 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
221
222 ret = dw_pcie_wait_for_link(pci);
223 if (ret) {
224 dev_err(dev, "error: link did not start at new speed\n");
225 goto err;
226 }
227 }
228
229 ret = 0;
230 err:
231 WARN_ON(ret); /* we assume that errors will be very rare */
232 dw_pcie_dbi_ro_wr_dis(pci);
233 return ret;
234 }
235
fu740_pcie_host_init(struct dw_pcie_rp * pp)236 static int fu740_pcie_host_init(struct dw_pcie_rp *pp)
237 {
238 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
239 struct fu740_pcie *afp = to_fu740_pcie(pci);
240 struct device *dev = pci->dev;
241 int ret;
242
243 /* Power on reset */
244 fu740_pcie_drive_reset(afp);
245
246 /* Enable pcieauxclk */
247 ret = clk_prepare_enable(afp->pcie_aux);
248 if (ret) {
249 dev_err(dev, "unable to enable pcie_aux clock\n");
250 return ret;
251 }
252
253 /*
254 * Assert hold_phy_rst (hold the controller LTSSM in reset after
255 * power_up_rst_n for register programming with cr_para)
256 */
257 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
258
259 /* Deassert power_up_rst_n */
260 ret = reset_control_deassert(afp->rst);
261 if (ret) {
262 dev_err(dev, "unable to deassert pcie_power_up_rst_n\n");
263 return ret;
264 }
265
266 fu740_pcie_init_phy(afp);
267
268 /* Disable pcieauxclk */
269 clk_disable_unprepare(afp->pcie_aux);
270 /* Clear hold_phy_rst */
271 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
272 /* Enable pcieauxclk */
273 clk_prepare_enable(afp->pcie_aux);
274 /* Set RC mode */
275 writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);
276
277 return 0;
278 }
279
280 static const struct dw_pcie_host_ops fu740_pcie_host_ops = {
281 .init = fu740_pcie_host_init,
282 };
283
284 static const struct dw_pcie_ops dw_pcie_ops = {
285 .start_link = fu740_pcie_start_link,
286 };
287
fu740_pcie_probe(struct platform_device * pdev)288 static int fu740_pcie_probe(struct platform_device *pdev)
289 {
290 struct device *dev = &pdev->dev;
291 struct dw_pcie *pci;
292 struct fu740_pcie *afp;
293
294 afp = devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL);
295 if (!afp)
296 return -ENOMEM;
297 pci = &afp->pci;
298 pci->dev = dev;
299 pci->ops = &dw_pcie_ops;
300 pci->pp.ops = &fu740_pcie_host_ops;
301 pci->pp.num_vectors = MAX_MSI_IRQS;
302
303 /* SiFive specific region: mgmt */
304 afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");
305 if (IS_ERR(afp->mgmt_base))
306 return PTR_ERR(afp->mgmt_base);
307
308 /* Fetch GPIOs */
309 afp->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
310 if (IS_ERR(afp->reset))
311 return dev_err_probe(dev, PTR_ERR(afp->reset), "unable to get reset-gpios\n");
312
313 afp->pwren = devm_gpiod_get_optional(dev, "pwren", GPIOD_OUT_LOW);
314 if (IS_ERR(afp->pwren))
315 return dev_err_probe(dev, PTR_ERR(afp->pwren), "unable to get pwren-gpios\n");
316
317 /* Fetch clocks */
318 afp->pcie_aux = devm_clk_get(dev, "pcie_aux");
319 if (IS_ERR(afp->pcie_aux))
320 return dev_err_probe(dev, PTR_ERR(afp->pcie_aux),
321 "pcie_aux clock source missing or invalid\n");
322
323 /* Fetch reset */
324 afp->rst = devm_reset_control_get_exclusive(dev, NULL);
325 if (IS_ERR(afp->rst))
326 return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n");
327
328 platform_set_drvdata(pdev, afp);
329
330 return dw_pcie_host_init(&pci->pp);
331 }
332
fu740_pcie_shutdown(struct platform_device * pdev)333 static void fu740_pcie_shutdown(struct platform_device *pdev)
334 {
335 struct fu740_pcie *afp = platform_get_drvdata(pdev);
336
337 /* Bring down link, so bootloader gets clean state in case of reboot */
338 fu740_pcie_assert_reset(afp);
339 }
340
341 static const struct of_device_id fu740_pcie_of_match[] = {
342 { .compatible = "sifive,fu740-pcie", },
343 {},
344 };
345
346 static struct platform_driver fu740_pcie_driver = {
347 .driver = {
348 .name = "fu740-pcie",
349 .of_match_table = fu740_pcie_of_match,
350 .suppress_bind_attrs = true,
351 },
352 .probe = fu740_pcie_probe,
353 .shutdown = fu740_pcie_shutdown,
354 };
355
356 builtin_platform_driver(fu740_pcie_driver);
357