1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (c) 2014 Protonic Holland 4 */ 5 6/dts-v1/; 7#include "imx6q.dtsi" 8#include "imx6qdl-prti6q.dtsi" 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/sound/fsl-imx-audmux.h> 11 12/ { 13 model = "Protonic PRTI6Q board"; 14 compatible = "prt,prti6q", "fsl,imx6q"; 15 16 memory@10000000 { 17 device_type = "memory"; 18 reg = <0x10000000 0xf0000000>; 19 }; 20 21 backlight_lcd: backlight-lcd { 22 compatible = "pwm-backlight"; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_backlight>; 25 pwms = <&pwm1 0 5000000 0>; 26 brightness-levels = <0 16 64 255>; 27 num-interpolated-steps = <16>; 28 default-brightness-level = <1>; 29 power-supply = <®_3v3>; 30 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 31 }; 32 33 can_osc: can-osc { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <25000000>; 37 }; 38 39 leds { 40 compatible = "gpio-leds"; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_leds>; 43 44 led-debug0 { 45 function = LED_FUNCTION_STATUS; 46 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 47 linux,default-trigger = "heartbeat"; 48 }; 49 50 led-debug1 { 51 function = LED_FUNCTION_SD; 52 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 53 linux,default-trigger = "disk-activity"; 54 }; 55 }; 56 57 panel { 58 compatible = "kyo,tcg121xglp"; 59 backlight = <&backlight_lcd>; 60 power-supply = <®_3v3>; 61 62 port { 63 panel_in: endpoint { 64 remote-endpoint = <&lvds0_out>; 65 }; 66 }; 67 }; 68 69 reg_1v8: regulator-1v8 { 70 compatible = "regulator-fixed"; 71 regulator-name = "1v8"; 72 regulator-min-microvolt = <1800000>; 73 regulator-max-microvolt = <1800000>; 74 }; 75 76 reg_3v3: regulator-3v3 { 77 compatible = "regulator-fixed"; 78 regulator-name = "3v3"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 }; 82 83 reg_wifi: regulator-wifi { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_wifi_npd>; 87 enable-active-high; 88 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; 89 regulator-max-microvolt = <1800000>; 90 regulator-min-microvolt = <1800000>; 91 regulator-name = "regulator-WL12xx"; 92 startup-delay-us = <70000>; 93 }; 94 95 sound { 96 compatible = "simple-audio-card"; 97 simple-audio-card,name = "prti6q-sgtl5000"; 98 simple-audio-card,format = "i2s"; 99 simple-audio-card,widgets = 100 "Microphone", "Microphone Jack", 101 "Line", "Line In Jack", 102 "Headphone", "Headphone Jack", 103 "Speaker", "External Speaker"; 104 simple-audio-card,routing = 105 "MIC_IN", "Microphone Jack", 106 "LINE_IN", "Line In Jack", 107 "Headphone Jack", "HP_OUT", 108 "External Speaker", "LINE_OUT"; 109 110 simple-audio-card,cpu { 111 sound-dai = <&ssi1>; 112 system-clock-frequency = <0>; 113 }; 114 115 simple-audio-card,codec { 116 sound-dai = <&sgtl5000>; 117 bitclock-master; 118 frame-master; 119 }; 120 }; 121 122 spdif_out: spdif-out { 123 compatible = "linux,spdif-dit"; 124 #sound-dai-cells = <0>; 125 }; 126 127 spdif_in: spdif-in { 128 compatible = "linux,spdif-dir"; 129 #sound-dai-cells = <0>; 130 }; 131 132 sound-spdif { 133 compatible = "fsl,imx-audio-spdif"; 134 model = "imx-spdif"; 135 audio-cpu = <&spdif>; 136 audio-codec = <&spdif_out>, <&spdif_in>; 137 }; 138}; 139 140&audmux { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_audmux>; 143 status = "okay"; 144 145 mux-ssi1 { 146 fsl,audmux-port = <0>; 147 fsl,port-config = < 148 IMX_AUDMUX_V2_PTCR_SYN 0 149 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 150 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 151 IMX_AUDMUX_V2_PTCR_TFSDIR 0 152 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) 153 >; 154 }; 155 156 mux-pins3 { 157 fsl,audmux-port = <2>; 158 fsl,port-config = < 159 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) 160 0 IMX_AUDMUX_V2_PDCR_TXRXEN 161 >; 162 }; 163}; 164 165&can1 { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_can1>; 168 status = "okay"; 169}; 170 171&can2 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_can2>; 174 status = "okay"; 175}; 176 177&ecspi1 { 178 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_ecspi1>; 181 status = "okay"; 182 183 flash@0 { 184 compatible = "jedec,spi-nor"; 185 reg = <0>; 186 spi-max-frequency = <20000000>; 187 }; 188}; 189 190&ecspi2 { 191 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; 194 status = "okay"; 195 196 can@0 { 197 compatible = "microchip,mcp2515"; 198 reg = <0>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_can3>; 201 clocks = <&can_osc>; 202 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; 203 spi-max-frequency = <5000000>; 204 }; 205 206 adc@1 { 207 compatible = "ti,adc128s052"; 208 reg = <1>; 209 spi-max-frequency = <2000000>; 210 vref-supply = <®_3v3>; 211 }; 212}; 213 214&ecspi3 { 215 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_ecspi3>; 218 status = "okay"; 219}; 220 221&fec { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_enet>; 224 phy-mode = "rgmii-id"; 225 phy-handle = <&rgmii_phy>; 226 status = "okay"; 227 228 mdio { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 /* Microchip KSZ9031RNX PHY */ 233 rgmii_phy: ethernet-phy@0 { 234 reg = <0>; 235 interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; 236 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 237 reset-assert-us = <10000>; 238 reset-deassert-us = <300>; 239 }; 240 }; 241}; 242 243&hdmi { 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_hdmi>; 246 ddc-i2c-bus = <&i2c2>; 247 status = "okay"; 248}; 249 250&i2c1 { 251 sgtl5000: audio-codec@a { 252 compatible = "fsl,sgtl5000"; 253 reg = <0xa>; 254 #sound-dai-cells = <0>; 255 clocks = <&clks 201>; 256 VDDA-supply = <®_3v3>; 257 VDDIO-supply = <®_3v3>; 258 VDDD-supply = <®_1v8>; 259 }; 260}; 261 262/* DDC */ 263&i2c2 { 264 clock-frequency = <100000>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_i2c2>; 267 status = "okay"; 268}; 269 270&i2c3 { 271 adc@49 { 272 compatible = "ti,ads1015"; 273 reg = <0x49>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 277 /* can2_l */ 278 channel@4 { 279 reg = <4>; 280 ti,gain = <3>; 281 ti,datarate = <3>; 282 }; 283 284 /* can2_h */ 285 channel@5 { 286 reg = <5>; 287 ti,gain = <3>; 288 ti,datarate = <3>; 289 }; 290 291 /* can1_l */ 292 channel@6 { 293 reg = <6>; 294 ti,gain = <3>; 295 ti,datarate = <3>; 296 }; 297 298 /* can1_h */ 299 channel@7 { 300 reg = <7>; 301 ti,gain = <3>; 302 ti,datarate = <3>; 303 }; 304 }; 305}; 306 307&pcie { 308 status = "okay"; 309}; 310 311&pwm1 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_pwm1>; 314 status = "okay"; 315}; 316 317&ldb { 318 status = "okay"; 319 320 lvds-channel@0 { 321 status = "okay"; 322 323 port@4 { 324 reg = <4>; 325 326 lvds0_out: endpoint { 327 remote-endpoint = <&panel_in>; 328 }; 329 }; 330 }; 331}; 332 333&sata { 334 status = "okay"; 335}; 336 337&snvs_poweroff { 338 status = "okay"; 339}; 340 341&spdif { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_spdif>; 344 status = "okay"; 345}; 346 347&ssi1 { 348 #sound-dai-cells = <0>; 349 fsl,mode = "ac97-slave"; 350 status = "okay"; 351}; 352 353&uart2 { 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_uart2>; 356 status = "okay"; 357}; 358 359&uart5 { 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_uart5>; 362 status = "okay"; 363}; 364 365&usbotg { 366 pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; 367}; 368 369&usdhc2 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_usdhc2>; 372 non-removable; 373 vmmc-supply = <®_wifi>; 374 cap-power-off-card; 375 keep-power-in-suspend; 376 status = "okay"; 377 378 #address-cells = <1>; 379 #size-cells = <0>; 380 wifi@2 { 381 compatible = "ti,wl1271"; 382 reg = <2>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_wifi>; 385 interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; 386 ref-clock-frequency = <38400000>; 387 tcxo-clock-frequency = <19200000>; 388 }; 389}; 390 391&iomuxc { 392 pinctrl_audmux: audmuxgrp { 393 fsl,pins = < 394 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 395 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 396 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 397 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 398 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 399 >; 400 }; 401 402 pinctrl_backlight: backlightgrp { 403 fsl,pins = < 404 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 405 >; 406 }; 407 408 pinctrl_can2: can2grp { 409 fsl,pins = < 410 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008 411 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008 412 >; 413 }; 414 415 pinctrl_can3: can3grp { 416 fsl,pins = < 417 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 418 >; 419 }; 420 421 pinctrl_ecspi1: ecspi1grp { 422 fsl,pins = < 423 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 424 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 425 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 426 /* CS */ 427 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 428 >; 429 }; 430 431 pinctrl_ecspi2: ecspi2grp { 432 fsl,pins = < 433 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 434 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 435 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 436 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 437 >; 438 }; 439 440 pinctrl_ecspi2_cs: ecspi2csgrp { 441 fsl,pins = < 442 /* ADC128S022 CS */ 443 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 444 >; 445 }; 446 447 pinctrl_ecspi3: ecspi3grp { 448 fsl,pins = < 449 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 450 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 451 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 452 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 453 >; 454 }; 455 456 pinctrl_enet: enetgrp { 457 fsl,pins = < 458 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 459 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 460 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 461 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 462 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 463 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 464 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 465 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 466 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 467 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 468 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 469 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 470 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 471 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 472 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 473 474 /* Phy reset */ 475 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 476 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 477 >; 478 }; 479 480 pinctrl_hdmi: hdmigrp { 481 fsl,pins = < 482 /* NOTE: DDC is done via I2C2, so DON'T 483 * configure DDC pins for HDMI! 484 */ 485 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 486 >; 487 }; 488 489 /* DDC */ 490 pinctrl_i2c2: i2c2grp { 491 fsl,pins = < 492 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 493 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 494 >; 495 }; 496 497 pinctrl_leds: ledsgrp { 498 fsl,pins = < 499 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 500 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 501 >; 502 }; 503 504 pinctrl_pwm1: pwm1grp { 505 fsl,pins = < 506 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 507 >; 508 }; 509 510 pinctrl_spdif: spdifgrp { 511 fsl,pins = < 512 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 513 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 514 >; 515 }; 516 517 pinctrl_uart2: uart2grp { 518 fsl,pins = < 519 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 520 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 521 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 522 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 523 >; 524 }; 525 526 pinctrl_uart5: uart5grp { 527 fsl,pins = < 528 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 529 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 530 >; 531 }; 532 533 pinctrl_usbotg_id: usbotgidgrp { 534 fsl,pins = < 535 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 536 >; 537 }; 538 539 pinctrl_usdhc2: usdhc2grp { 540 fsl,pins = < 541 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 542 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 543 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 544 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 545 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 546 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 547 >; 548 }; 549 550 pinctrl_wifi: wifigrp { 551 fsl,pins = < 552 /* WL12xx IRQ */ 553 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 554 >; 555 }; 556 557 pinctrl_wifi_npd: wifinpdgrp { 558 fsl,pins = < 559 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 560 >; 561 }; 562}; 563