1 /*
2 * Driver for the ST Microelectronics SPEAr1340 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <vireshk@kernel.org>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include "pinctrl-spear.h"
16
17 #define DRIVER_NAME "spear1340-pinmux"
18
19 /* pins */
20 static const struct pinctrl_pin_desc spear1340_pins[] = {
21 SPEAR_PIN_0_TO_101,
22 SPEAR_PIN_102_TO_245,
23 PINCTRL_PIN(246, "PLGPIO246"),
24 PINCTRL_PIN(247, "PLGPIO247"),
25 PINCTRL_PIN(248, "PLGPIO248"),
26 PINCTRL_PIN(249, "PLGPIO249"),
27 PINCTRL_PIN(250, "PLGPIO250"),
28 PINCTRL_PIN(251, "PLGPIO251"),
29 };
30
31 /* In SPEAr1340 there are two levels of pad muxing */
32 /* - pads as gpio OR peripherals */
33 #define PAD_FUNCTION_EN_1 0x668
34 #define PAD_FUNCTION_EN_2 0x66C
35 #define PAD_FUNCTION_EN_3 0x670
36 #define PAD_FUNCTION_EN_4 0x674
37 #define PAD_FUNCTION_EN_5 0x690
38 #define PAD_FUNCTION_EN_6 0x694
39 #define PAD_FUNCTION_EN_7 0x698
40 #define PAD_FUNCTION_EN_8 0x69C
41
42 /* - If peripherals, then primary OR alternate peripheral */
43 #define PAD_SHARED_IP_EN_1 0x6A0
44 #define PAD_SHARED_IP_EN_2 0x6A4
45
46 /*
47 * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
48 * registers with 32 bits each for handling gpio pads, register 8 has only 26
49 * relevant bits.
50 */
51 /* macro's for making pads as gpio's */
52 #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
53 #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
54 #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
55
56 /* macro's for making pads as peripherals */
57 #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
58 #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
59 #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
60 #define I2C1_REG0_MASK 0x01080000
61 #define SPDIF_IN_REG0_MASK 0x00100000
62 #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
63 #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
64 #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
65 #define VIP_AND_CAM3_REG0_MASK 0xFC200000
66 #define VIP_AND_CAM3_REG1_MASK 0x0000000F
67 #define VIP_REG1_MASK 0x00001EF0
68 #define VIP_AND_CAM2_REG1_MASK 0x007FE100
69 #define VIP_AND_CAM1_REG1_MASK 0xFF800000
70 #define VIP_AND_CAM1_REG2_MASK 0x00000003
71 #define VIP_AND_CAM0_REG2_MASK 0x00001FFC
72 #define SMI_REG2_MASK 0x0021E000
73 #define SSP0_REG2_MASK 0x001E0000
74 #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
75 #define UART0_REG2_MASK 0x01800000
76 #define UART1_REG2_MASK 0x06000000
77 #define I2S_IN_REG2_MASK 0xF8000000
78 #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
79 #define I2S_OUT_REG3_MASK 0x000001EF
80 #define I2S_IN_REG3_MASK 0x00000010
81 #define GMAC_REG3_MASK 0xFFFFFE00
82 #define GMAC_REG4_MASK 0x0000001F
83 #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
84 #define SSP0_CS3_REG4_MASK 0x00000020
85 #define I2C0_REG4_MASK 0x000000C0
86 #define CEC0_REG4_MASK 0x00000100
87 #define CEC1_REG4_MASK 0x00000200
88 #define SPDIF_OUT_REG4_MASK 0x00000400
89 #define CLCD_REG4_MASK 0x7FFFF800
90 #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
91 #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
92 #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
93 #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
94 #define MCIF_REG6_MASK 0xF8C00000
95 #define MCIF_REG7_MASK 0x000043FF
96 #define FSMC_8BIT_REG7_MASK 0x07FFBC00
97
98 /* other registers */
99 #define PERIP_CFG 0x42C
100 /* PERIP_CFG register masks */
101 #define SSP_CS_CTL_HW 0
102 #define SSP_CS_CTL_SW 1
103 #define SSP_CS_CTL_MASK 1
104 #define SSP_CS_CTL_SHIFT 21
105 #define SSP_CS_VAL_MASK 1
106 #define SSP_CS_VAL_SHIFT 20
107 #define SSP_CS_SEL_CS0 0
108 #define SSP_CS_SEL_CS1 1
109 #define SSP_CS_SEL_CS2 2
110 #define SSP_CS_SEL_MASK 3
111 #define SSP_CS_SEL_SHIFT 18
112
113 #define I2S_CHNL_2_0 (0)
114 #define I2S_CHNL_3_1 (1)
115 #define I2S_CHNL_5_1 (2)
116 #define I2S_CHNL_7_1 (3)
117 #define I2S_CHNL_PLAY_SHIFT (4)
118 #define I2S_CHNL_PLAY_MASK (3 << 4)
119 #define I2S_CHNL_REC_SHIFT (6)
120 #define I2S_CHNL_REC_MASK (3 << 6)
121
122 #define SPDIF_OUT_ENB_MASK (1 << 2)
123 #define SPDIF_OUT_ENB_SHIFT 2
124
125 #define MCIF_SEL_SD 1
126 #define MCIF_SEL_CF 2
127 #define MCIF_SEL_XD 3
128 #define MCIF_SEL_MASK 3
129 #define MCIF_SEL_SHIFT 0
130
131 #define GMAC_CLK_CFG 0x248
132 #define GMAC_PHY_IF_GMII_VAL (0 << 3)
133 #define GMAC_PHY_IF_RGMII_VAL (1 << 3)
134 #define GMAC_PHY_IF_SGMII_VAL (2 << 3)
135 #define GMAC_PHY_IF_RMII_VAL (4 << 3)
136 #define GMAC_PHY_IF_SEL_MASK (7 << 3)
137 #define GMAC_PHY_INPUT_ENB_VAL 0
138 #define GMAC_PHY_SYNT_ENB_VAL 1
139 #define GMAC_PHY_CLK_MASK 1
140 #define GMAC_PHY_CLK_SHIFT 2
141 #define GMAC_PHY_125M_PAD_VAL 0
142 #define GMAC_PHY_PLL2_VAL 1
143 #define GMAC_PHY_OSC3_VAL 2
144 #define GMAC_PHY_INPUT_CLK_MASK 3
145 #define GMAC_PHY_INPUT_CLK_SHIFT 0
146
147 #define PCIE_SATA_CFG 0x424
148 /* PCIE CFG MASks */
149 #define PCIE_CFG_DEVICE_PRESENT (1 << 11)
150 #define PCIE_CFG_POWERUP_RESET (1 << 10)
151 #define PCIE_CFG_CORE_CLK_EN (1 << 9)
152 #define PCIE_CFG_AUX_CLK_EN (1 << 8)
153 #define SATA_CFG_TX_CLK_EN (1 << 4)
154 #define SATA_CFG_RX_CLK_EN (1 << 3)
155 #define SATA_CFG_POWERUP_RESET (1 << 2)
156 #define SATA_CFG_PM_CLK_EN (1 << 1)
157 #define PCIE_SATA_SEL_PCIE (0)
158 #define PCIE_SATA_SEL_SATA (1)
159 #define SATA_PCIE_CFG_MASK 0xF1F
160 #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
161 PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
162 PCIE_CFG_DEVICE_PRESENT)
163 #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
164 SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
165 SATA_CFG_TX_CLK_EN)
166
167 /* Macro's for second level of pmx - pads as primary OR alternate peripheral */
168 /* Write 0 to enable FSMC_16_BIT */
169 #define KBD_ROW_COL_MASK (1 << 0)
170
171 /* Write 0 to enable UART0_ENH */
172 #define GPT_MASK (1 << 1) /* Only clk & cpt */
173
174 /* Write 0 to enable PWM1 */
175 #define KBD_COL5_MASK (1 << 2)
176
177 /* Write 0 to enable PWM2 */
178 #define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
179
180 /* Write 0 to enable PWM3 */
181 #define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
182
183 /* Write 0 to enable PWM0 */
184 #define SSP0_CS1_MASK (1 << 5)
185
186 /* Write 0 to enable VIP */
187 #define CAM3_MASK (1 << 6)
188
189 /* Write 0 to enable VIP */
190 #define CAM2_MASK (1 << 7)
191
192 /* Write 0 to enable VIP */
193 #define CAM1_MASK (1 << 8)
194
195 /* Write 0 to enable VIP */
196 #define CAM0_MASK (1 << 9)
197
198 /* Write 0 to enable TS */
199 #define SSP0_CS2_MASK (1 << 10)
200
201 /* Write 0 to enable FSMC PNOR */
202 #define MCIF_MASK (1 << 11)
203
204 /* Write 0 to enable CLCD */
205 #define ARM_TRACE_MASK (1 << 12)
206
207 /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
208 #define MIPHY_DBG_MASK (1 << 13)
209
210 /*
211 * Pad multiplexing for making all pads as gpio's. This is done to override the
212 * values passed from bootloader and start from scratch.
213 */
214 static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 };
215 static struct spear_muxreg pads_as_gpio_muxreg[] = {
216 {
217 .reg = PAD_FUNCTION_EN_1,
218 .mask = PADS_AS_GPIO_REG0_MASK,
219 .val = 0x0,
220 }, {
221 .reg = PAD_FUNCTION_EN_2,
222 .mask = PADS_AS_GPIO_REGS_MASK,
223 .val = 0x0,
224 }, {
225 .reg = PAD_FUNCTION_EN_3,
226 .mask = PADS_AS_GPIO_REGS_MASK,
227 .val = 0x0,
228 }, {
229 .reg = PAD_FUNCTION_EN_4,
230 .mask = PADS_AS_GPIO_REGS_MASK,
231 .val = 0x0,
232 }, {
233 .reg = PAD_FUNCTION_EN_5,
234 .mask = PADS_AS_GPIO_REGS_MASK,
235 .val = 0x0,
236 }, {
237 .reg = PAD_FUNCTION_EN_6,
238 .mask = PADS_AS_GPIO_REGS_MASK,
239 .val = 0x0,
240 }, {
241 .reg = PAD_FUNCTION_EN_7,
242 .mask = PADS_AS_GPIO_REGS_MASK,
243 .val = 0x0,
244 }, {
245 .reg = PAD_FUNCTION_EN_8,
246 .mask = PADS_AS_GPIO_REG7_MASK,
247 .val = 0x0,
248 },
249 };
250
251 static struct spear_modemux pads_as_gpio_modemux[] = {
252 {
253 .muxregs = pads_as_gpio_muxreg,
254 .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
255 },
256 };
257
258 static struct spear_pingroup pads_as_gpio_pingroup = {
259 .name = "pads_as_gpio_grp",
260 .pins = pads_as_gpio_pins,
261 .npins = ARRAY_SIZE(pads_as_gpio_pins),
262 .modemuxs = pads_as_gpio_modemux,
263 .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
264 };
265
266 static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
267 static struct spear_function pads_as_gpio_function = {
268 .name = "pads_as_gpio",
269 .groups = pads_as_gpio_grps,
270 .ngroups = ARRAY_SIZE(pads_as_gpio_grps),
271 };
272
273 /* Pad multiplexing for fsmc_8bit device */
274 static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
275 241, 242, 243, 244, 245, 246, 247, 248, 249 };
276 static struct spear_muxreg fsmc_8bit_muxreg[] = {
277 {
278 .reg = PAD_FUNCTION_EN_8,
279 .mask = FSMC_8BIT_REG7_MASK,
280 .val = FSMC_8BIT_REG7_MASK,
281 }
282 };
283
284 static struct spear_modemux fsmc_8bit_modemux[] = {
285 {
286 .muxregs = fsmc_8bit_muxreg,
287 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
288 },
289 };
290
291 static struct spear_pingroup fsmc_8bit_pingroup = {
292 .name = "fsmc_8bit_grp",
293 .pins = fsmc_8bit_pins,
294 .npins = ARRAY_SIZE(fsmc_8bit_pins),
295 .modemuxs = fsmc_8bit_modemux,
296 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
297 };
298
299 /* Pad multiplexing for fsmc_16bit device */
300 static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
301 static struct spear_muxreg fsmc_16bit_muxreg[] = {
302 {
303 .reg = PAD_SHARED_IP_EN_1,
304 .mask = KBD_ROW_COL_MASK,
305 .val = 0,
306 }, {
307 .reg = PAD_FUNCTION_EN_1,
308 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
309 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
310 },
311 };
312
313 static struct spear_modemux fsmc_16bit_modemux[] = {
314 {
315 .muxregs = fsmc_16bit_muxreg,
316 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
317 },
318 };
319
320 static struct spear_pingroup fsmc_16bit_pingroup = {
321 .name = "fsmc_16bit_grp",
322 .pins = fsmc_16bit_pins,
323 .npins = ARRAY_SIZE(fsmc_16bit_pins),
324 .modemuxs = fsmc_16bit_modemux,
325 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
326 };
327
328 /* pad multiplexing for fsmc_pnor device */
329 static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
330 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
331 215, 216, 217 };
332 static struct spear_muxreg fsmc_pnor_muxreg[] = {
333 {
334 .reg = PAD_SHARED_IP_EN_1,
335 .mask = MCIF_MASK,
336 .val = 0,
337 }, {
338 .reg = PAD_FUNCTION_EN_7,
339 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
340 .val = FSMC_PNOR_AND_MCIF_REG6_MASK,
341 },
342 };
343
344 static struct spear_modemux fsmc_pnor_modemux[] = {
345 {
346 .muxregs = fsmc_pnor_muxreg,
347 .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
348 },
349 };
350
351 static struct spear_pingroup fsmc_pnor_pingroup = {
352 .name = "fsmc_pnor_grp",
353 .pins = fsmc_pnor_pins,
354 .npins = ARRAY_SIZE(fsmc_pnor_pins),
355 .modemuxs = fsmc_pnor_modemux,
356 .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
357 };
358
359 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
360 "fsmc_pnor_grp" };
361 static struct spear_function fsmc_function = {
362 .name = "fsmc",
363 .groups = fsmc_grps,
364 .ngroups = ARRAY_SIZE(fsmc_grps),
365 };
366
367 /* pad multiplexing for keyboard rows-cols device */
368 static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
369 10 };
370 static struct spear_muxreg keyboard_row_col_muxreg[] = {
371 {
372 .reg = PAD_SHARED_IP_EN_1,
373 .mask = KBD_ROW_COL_MASK,
374 .val = KBD_ROW_COL_MASK,
375 }, {
376 .reg = PAD_FUNCTION_EN_1,
377 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
378 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
379 },
380 };
381
382 static struct spear_modemux keyboard_row_col_modemux[] = {
383 {
384 .muxregs = keyboard_row_col_muxreg,
385 .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
386 },
387 };
388
389 static struct spear_pingroup keyboard_row_col_pingroup = {
390 .name = "keyboard_row_col_grp",
391 .pins = keyboard_row_col_pins,
392 .npins = ARRAY_SIZE(keyboard_row_col_pins),
393 .modemuxs = keyboard_row_col_modemux,
394 .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
395 };
396
397 /* pad multiplexing for keyboard col5 device */
398 static const unsigned keyboard_col5_pins[] = { 17 };
399 static struct spear_muxreg keyboard_col5_muxreg[] = {
400 {
401 .reg = PAD_SHARED_IP_EN_1,
402 .mask = KBD_COL5_MASK,
403 .val = KBD_COL5_MASK,
404 }, {
405 .reg = PAD_FUNCTION_EN_1,
406 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
407 .val = PWM1_AND_KBD_COL5_REG0_MASK,
408 },
409 };
410
411 static struct spear_modemux keyboard_col5_modemux[] = {
412 {
413 .muxregs = keyboard_col5_muxreg,
414 .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
415 },
416 };
417
418 static struct spear_pingroup keyboard_col5_pingroup = {
419 .name = "keyboard_col5_grp",
420 .pins = keyboard_col5_pins,
421 .npins = ARRAY_SIZE(keyboard_col5_pins),
422 .modemuxs = keyboard_col5_modemux,
423 .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
424 };
425
426 static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
427 "keyboard_col5_grp" };
428 static struct spear_function keyboard_function = {
429 .name = "keyboard",
430 .groups = keyboard_grps,
431 .ngroups = ARRAY_SIZE(keyboard_grps),
432 };
433
434 /* pad multiplexing for spdif_in device */
435 static const unsigned spdif_in_pins[] = { 19 };
436 static struct spear_muxreg spdif_in_muxreg[] = {
437 {
438 .reg = PAD_FUNCTION_EN_1,
439 .mask = SPDIF_IN_REG0_MASK,
440 .val = SPDIF_IN_REG0_MASK,
441 },
442 };
443
444 static struct spear_modemux spdif_in_modemux[] = {
445 {
446 .muxregs = spdif_in_muxreg,
447 .nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
448 },
449 };
450
451 static struct spear_pingroup spdif_in_pingroup = {
452 .name = "spdif_in_grp",
453 .pins = spdif_in_pins,
454 .npins = ARRAY_SIZE(spdif_in_pins),
455 .modemuxs = spdif_in_modemux,
456 .nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
457 };
458
459 static const char *const spdif_in_grps[] = { "spdif_in_grp" };
460 static struct spear_function spdif_in_function = {
461 .name = "spdif_in",
462 .groups = spdif_in_grps,
463 .ngroups = ARRAY_SIZE(spdif_in_grps),
464 };
465
466 /* pad multiplexing for spdif_out device */
467 static const unsigned spdif_out_pins[] = { 137 };
468 static struct spear_muxreg spdif_out_muxreg[] = {
469 {
470 .reg = PAD_FUNCTION_EN_5,
471 .mask = SPDIF_OUT_REG4_MASK,
472 .val = SPDIF_OUT_REG4_MASK,
473 }, {
474 .reg = PERIP_CFG,
475 .mask = SPDIF_OUT_ENB_MASK,
476 .val = SPDIF_OUT_ENB_MASK,
477 }
478 };
479
480 static struct spear_modemux spdif_out_modemux[] = {
481 {
482 .muxregs = spdif_out_muxreg,
483 .nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
484 },
485 };
486
487 static struct spear_pingroup spdif_out_pingroup = {
488 .name = "spdif_out_grp",
489 .pins = spdif_out_pins,
490 .npins = ARRAY_SIZE(spdif_out_pins),
491 .modemuxs = spdif_out_modemux,
492 .nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
493 };
494
495 static const char *const spdif_out_grps[] = { "spdif_out_grp" };
496 static struct spear_function spdif_out_function = {
497 .name = "spdif_out",
498 .groups = spdif_out_grps,
499 .ngroups = ARRAY_SIZE(spdif_out_grps),
500 };
501
502 /* pad multiplexing for gpt_0_1 device */
503 static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
504 static struct spear_muxreg gpt_0_1_muxreg[] = {
505 {
506 .reg = PAD_SHARED_IP_EN_1,
507 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
508 .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
509 }, {
510 .reg = PAD_FUNCTION_EN_1,
511 .mask = UART0_ENH_AND_GPT_REG0_MASK |
512 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
513 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
514 .val = UART0_ENH_AND_GPT_REG0_MASK |
515 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
516 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
517 },
518 };
519
520 static struct spear_modemux gpt_0_1_modemux[] = {
521 {
522 .muxregs = gpt_0_1_muxreg,
523 .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
524 },
525 };
526
527 static struct spear_pingroup gpt_0_1_pingroup = {
528 .name = "gpt_0_1_grp",
529 .pins = gpt_0_1_pins,
530 .npins = ARRAY_SIZE(gpt_0_1_pins),
531 .modemuxs = gpt_0_1_modemux,
532 .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
533 };
534
535 static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
536 static struct spear_function gpt_0_1_function = {
537 .name = "gpt_0_1",
538 .groups = gpt_0_1_grps,
539 .ngroups = ARRAY_SIZE(gpt_0_1_grps),
540 };
541
542 /* pad multiplexing for pwm0 device */
543 static const unsigned pwm0_pins[] = { 24 };
544 static struct spear_muxreg pwm0_muxreg[] = {
545 {
546 .reg = PAD_SHARED_IP_EN_1,
547 .mask = SSP0_CS1_MASK,
548 .val = 0,
549 }, {
550 .reg = PAD_FUNCTION_EN_1,
551 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
552 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
553 },
554 };
555
556 static struct spear_modemux pwm0_modemux[] = {
557 {
558 .muxregs = pwm0_muxreg,
559 .nmuxregs = ARRAY_SIZE(pwm0_muxreg),
560 },
561 };
562
563 static struct spear_pingroup pwm0_pingroup = {
564 .name = "pwm0_grp",
565 .pins = pwm0_pins,
566 .npins = ARRAY_SIZE(pwm0_pins),
567 .modemuxs = pwm0_modemux,
568 .nmodemuxs = ARRAY_SIZE(pwm0_modemux),
569 };
570
571 /* pad multiplexing for pwm1 device */
572 static const unsigned pwm1_pins[] = { 17 };
573 static struct spear_muxreg pwm1_muxreg[] = {
574 {
575 .reg = PAD_SHARED_IP_EN_1,
576 .mask = KBD_COL5_MASK,
577 .val = 0,
578 }, {
579 .reg = PAD_FUNCTION_EN_1,
580 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
581 .val = PWM1_AND_KBD_COL5_REG0_MASK,
582 },
583 };
584
585 static struct spear_modemux pwm1_modemux[] = {
586 {
587 .muxregs = pwm1_muxreg,
588 .nmuxregs = ARRAY_SIZE(pwm1_muxreg),
589 },
590 };
591
592 static struct spear_pingroup pwm1_pingroup = {
593 .name = "pwm1_grp",
594 .pins = pwm1_pins,
595 .npins = ARRAY_SIZE(pwm1_pins),
596 .modemuxs = pwm1_modemux,
597 .nmodemuxs = ARRAY_SIZE(pwm1_modemux),
598 };
599
600 /* pad multiplexing for pwm2 device */
601 static const unsigned pwm2_pins[] = { 21 };
602 static struct spear_muxreg pwm2_muxreg[] = {
603 {
604 .reg = PAD_SHARED_IP_EN_1,
605 .mask = GPT0_TMR0_CPT_MASK,
606 .val = 0,
607 }, {
608 .reg = PAD_FUNCTION_EN_1,
609 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
610 .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
611 },
612 };
613
614 static struct spear_modemux pwm2_modemux[] = {
615 {
616 .muxregs = pwm2_muxreg,
617 .nmuxregs = ARRAY_SIZE(pwm2_muxreg),
618 },
619 };
620
621 static struct spear_pingroup pwm2_pingroup = {
622 .name = "pwm2_grp",
623 .pins = pwm2_pins,
624 .npins = ARRAY_SIZE(pwm2_pins),
625 .modemuxs = pwm2_modemux,
626 .nmodemuxs = ARRAY_SIZE(pwm2_modemux),
627 };
628
629 /* pad multiplexing for pwm3 device */
630 static const unsigned pwm3_pins[] = { 22 };
631 static struct spear_muxreg pwm3_muxreg[] = {
632 {
633 .reg = PAD_SHARED_IP_EN_1,
634 .mask = GPT0_TMR1_CLK_MASK,
635 .val = 0,
636 }, {
637 .reg = PAD_FUNCTION_EN_1,
638 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
639 .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
640 },
641 };
642
643 static struct spear_modemux pwm3_modemux[] = {
644 {
645 .muxregs = pwm3_muxreg,
646 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
647 },
648 };
649
650 static struct spear_pingroup pwm3_pingroup = {
651 .name = "pwm3_grp",
652 .pins = pwm3_pins,
653 .npins = ARRAY_SIZE(pwm3_pins),
654 .modemuxs = pwm3_modemux,
655 .nmodemuxs = ARRAY_SIZE(pwm3_modemux),
656 };
657
658 static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
659 "pwm3_grp" };
660 static struct spear_function pwm_function = {
661 .name = "pwm",
662 .groups = pwm_grps,
663 .ngroups = ARRAY_SIZE(pwm_grps),
664 };
665
666 /* pad multiplexing for vip_mux device */
667 static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
668 static struct spear_muxreg vip_mux_muxreg[] = {
669 {
670 .reg = PAD_FUNCTION_EN_2,
671 .mask = VIP_REG1_MASK,
672 .val = VIP_REG1_MASK,
673 },
674 };
675
676 static struct spear_modemux vip_mux_modemux[] = {
677 {
678 .muxregs = vip_mux_muxreg,
679 .nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
680 },
681 };
682
683 static struct spear_pingroup vip_mux_pingroup = {
684 .name = "vip_mux_grp",
685 .pins = vip_mux_pins,
686 .npins = ARRAY_SIZE(vip_mux_pins),
687 .modemuxs = vip_mux_modemux,
688 .nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
689 };
690
691 /* pad multiplexing for vip_mux_cam0 (disables cam0) device */
692 static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
693 73, 74, 75 };
694 static struct spear_muxreg vip_mux_cam0_muxreg[] = {
695 {
696 .reg = PAD_SHARED_IP_EN_1,
697 .mask = CAM0_MASK,
698 .val = 0,
699 }, {
700 .reg = PAD_FUNCTION_EN_3,
701 .mask = VIP_AND_CAM0_REG2_MASK,
702 .val = VIP_AND_CAM0_REG2_MASK,
703 },
704 };
705
706 static struct spear_modemux vip_mux_cam0_modemux[] = {
707 {
708 .muxregs = vip_mux_cam0_muxreg,
709 .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
710 },
711 };
712
713 static struct spear_pingroup vip_mux_cam0_pingroup = {
714 .name = "vip_mux_cam0_grp",
715 .pins = vip_mux_cam0_pins,
716 .npins = ARRAY_SIZE(vip_mux_cam0_pins),
717 .modemuxs = vip_mux_cam0_modemux,
718 .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
719 };
720
721 /* pad multiplexing for vip_mux_cam1 (disables cam1) device */
722 static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
723 62, 63, 64 };
724 static struct spear_muxreg vip_mux_cam1_muxreg[] = {
725 {
726 .reg = PAD_SHARED_IP_EN_1,
727 .mask = CAM1_MASK,
728 .val = 0,
729 }, {
730 .reg = PAD_FUNCTION_EN_2,
731 .mask = VIP_AND_CAM1_REG1_MASK,
732 .val = VIP_AND_CAM1_REG1_MASK,
733 }, {
734 .reg = PAD_FUNCTION_EN_3,
735 .mask = VIP_AND_CAM1_REG2_MASK,
736 .val = VIP_AND_CAM1_REG2_MASK,
737 },
738 };
739
740 static struct spear_modemux vip_mux_cam1_modemux[] = {
741 {
742 .muxregs = vip_mux_cam1_muxreg,
743 .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
744 },
745 };
746
747 static struct spear_pingroup vip_mux_cam1_pingroup = {
748 .name = "vip_mux_cam1_grp",
749 .pins = vip_mux_cam1_pins,
750 .npins = ARRAY_SIZE(vip_mux_cam1_pins),
751 .modemuxs = vip_mux_cam1_modemux,
752 .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
753 };
754
755 /* pad multiplexing for vip_mux_cam2 (disables cam2) device */
756 static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
757 51, 52, 53 };
758 static struct spear_muxreg vip_mux_cam2_muxreg[] = {
759 {
760 .reg = PAD_SHARED_IP_EN_1,
761 .mask = CAM2_MASK,
762 .val = 0,
763 }, {
764 .reg = PAD_FUNCTION_EN_2,
765 .mask = VIP_AND_CAM2_REG1_MASK,
766 .val = VIP_AND_CAM2_REG1_MASK,
767 },
768 };
769
770 static struct spear_modemux vip_mux_cam2_modemux[] = {
771 {
772 .muxregs = vip_mux_cam2_muxreg,
773 .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
774 },
775 };
776
777 static struct spear_pingroup vip_mux_cam2_pingroup = {
778 .name = "vip_mux_cam2_grp",
779 .pins = vip_mux_cam2_pins,
780 .npins = ARRAY_SIZE(vip_mux_cam2_pins),
781 .modemuxs = vip_mux_cam2_modemux,
782 .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
783 };
784
785 /* pad multiplexing for vip_mux_cam3 (disables cam3) device */
786 static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
787 32, 33, 34 };
788 static struct spear_muxreg vip_mux_cam3_muxreg[] = {
789 {
790 .reg = PAD_SHARED_IP_EN_1,
791 .mask = CAM3_MASK,
792 .val = 0,
793 }, {
794 .reg = PAD_FUNCTION_EN_1,
795 .mask = VIP_AND_CAM3_REG0_MASK,
796 .val = VIP_AND_CAM3_REG0_MASK,
797 }, {
798 .reg = PAD_FUNCTION_EN_2,
799 .mask = VIP_AND_CAM3_REG1_MASK,
800 .val = VIP_AND_CAM3_REG1_MASK,
801 },
802 };
803
804 static struct spear_modemux vip_mux_cam3_modemux[] = {
805 {
806 .muxregs = vip_mux_cam3_muxreg,
807 .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
808 },
809 };
810
811 static struct spear_pingroup vip_mux_cam3_pingroup = {
812 .name = "vip_mux_cam3_grp",
813 .pins = vip_mux_cam3_pins,
814 .npins = ARRAY_SIZE(vip_mux_cam3_pins),
815 .modemuxs = vip_mux_cam3_modemux,
816 .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
817 };
818
819 static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
820 "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
821 static struct spear_function vip_function = {
822 .name = "vip",
823 .groups = vip_grps,
824 .ngroups = ARRAY_SIZE(vip_grps),
825 };
826
827 /* pad multiplexing for cam0 device */
828 static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
829 };
830 static struct spear_muxreg cam0_muxreg[] = {
831 {
832 .reg = PAD_SHARED_IP_EN_1,
833 .mask = CAM0_MASK,
834 .val = CAM0_MASK,
835 }, {
836 .reg = PAD_FUNCTION_EN_3,
837 .mask = VIP_AND_CAM0_REG2_MASK,
838 .val = VIP_AND_CAM0_REG2_MASK,
839 },
840 };
841
842 static struct spear_modemux cam0_modemux[] = {
843 {
844 .muxregs = cam0_muxreg,
845 .nmuxregs = ARRAY_SIZE(cam0_muxreg),
846 },
847 };
848
849 static struct spear_pingroup cam0_pingroup = {
850 .name = "cam0_grp",
851 .pins = cam0_pins,
852 .npins = ARRAY_SIZE(cam0_pins),
853 .modemuxs = cam0_modemux,
854 .nmodemuxs = ARRAY_SIZE(cam0_modemux),
855 };
856
857 static const char *const cam0_grps[] = { "cam0_grp" };
858 static struct spear_function cam0_function = {
859 .name = "cam0",
860 .groups = cam0_grps,
861 .ngroups = ARRAY_SIZE(cam0_grps),
862 };
863
864 /* pad multiplexing for cam1 device */
865 static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
866 };
867 static struct spear_muxreg cam1_muxreg[] = {
868 {
869 .reg = PAD_SHARED_IP_EN_1,
870 .mask = CAM1_MASK,
871 .val = CAM1_MASK,
872 }, {
873 .reg = PAD_FUNCTION_EN_2,
874 .mask = VIP_AND_CAM1_REG1_MASK,
875 .val = VIP_AND_CAM1_REG1_MASK,
876 }, {
877 .reg = PAD_FUNCTION_EN_3,
878 .mask = VIP_AND_CAM1_REG2_MASK,
879 .val = VIP_AND_CAM1_REG2_MASK,
880 },
881 };
882
883 static struct spear_modemux cam1_modemux[] = {
884 {
885 .muxregs = cam1_muxreg,
886 .nmuxregs = ARRAY_SIZE(cam1_muxreg),
887 },
888 };
889
890 static struct spear_pingroup cam1_pingroup = {
891 .name = "cam1_grp",
892 .pins = cam1_pins,
893 .npins = ARRAY_SIZE(cam1_pins),
894 .modemuxs = cam1_modemux,
895 .nmodemuxs = ARRAY_SIZE(cam1_modemux),
896 };
897
898 static const char *const cam1_grps[] = { "cam1_grp" };
899 static struct spear_function cam1_function = {
900 .name = "cam1",
901 .groups = cam1_grps,
902 .ngroups = ARRAY_SIZE(cam1_grps),
903 };
904
905 /* pad multiplexing for cam2 device */
906 static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
907 };
908 static struct spear_muxreg cam2_muxreg[] = {
909 {
910 .reg = PAD_SHARED_IP_EN_1,
911 .mask = CAM2_MASK,
912 .val = CAM2_MASK,
913 }, {
914 .reg = PAD_FUNCTION_EN_2,
915 .mask = VIP_AND_CAM2_REG1_MASK,
916 .val = VIP_AND_CAM2_REG1_MASK,
917 },
918 };
919
920 static struct spear_modemux cam2_modemux[] = {
921 {
922 .muxregs = cam2_muxreg,
923 .nmuxregs = ARRAY_SIZE(cam2_muxreg),
924 },
925 };
926
927 static struct spear_pingroup cam2_pingroup = {
928 .name = "cam2_grp",
929 .pins = cam2_pins,
930 .npins = ARRAY_SIZE(cam2_pins),
931 .modemuxs = cam2_modemux,
932 .nmodemuxs = ARRAY_SIZE(cam2_modemux),
933 };
934
935 static const char *const cam2_grps[] = { "cam2_grp" };
936 static struct spear_function cam2_function = {
937 .name = "cam2",
938 .groups = cam2_grps,
939 .ngroups = ARRAY_SIZE(cam2_grps),
940 };
941
942 /* pad multiplexing for cam3 device */
943 static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
944 };
945 static struct spear_muxreg cam3_muxreg[] = {
946 {
947 .reg = PAD_SHARED_IP_EN_1,
948 .mask = CAM3_MASK,
949 .val = CAM3_MASK,
950 }, {
951 .reg = PAD_FUNCTION_EN_1,
952 .mask = VIP_AND_CAM3_REG0_MASK,
953 .val = VIP_AND_CAM3_REG0_MASK,
954 }, {
955 .reg = PAD_FUNCTION_EN_2,
956 .mask = VIP_AND_CAM3_REG1_MASK,
957 .val = VIP_AND_CAM3_REG1_MASK,
958 },
959 };
960
961 static struct spear_modemux cam3_modemux[] = {
962 {
963 .muxregs = cam3_muxreg,
964 .nmuxregs = ARRAY_SIZE(cam3_muxreg),
965 },
966 };
967
968 static struct spear_pingroup cam3_pingroup = {
969 .name = "cam3_grp",
970 .pins = cam3_pins,
971 .npins = ARRAY_SIZE(cam3_pins),
972 .modemuxs = cam3_modemux,
973 .nmodemuxs = ARRAY_SIZE(cam3_modemux),
974 };
975
976 static const char *const cam3_grps[] = { "cam3_grp" };
977 static struct spear_function cam3_function = {
978 .name = "cam3",
979 .groups = cam3_grps,
980 .ngroups = ARRAY_SIZE(cam3_grps),
981 };
982
983 /* pad multiplexing for smi device */
984 static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
985 static struct spear_muxreg smi_muxreg[] = {
986 {
987 .reg = PAD_FUNCTION_EN_3,
988 .mask = SMI_REG2_MASK,
989 .val = SMI_REG2_MASK,
990 },
991 };
992
993 static struct spear_modemux smi_modemux[] = {
994 {
995 .muxregs = smi_muxreg,
996 .nmuxregs = ARRAY_SIZE(smi_muxreg),
997 },
998 };
999
1000 static struct spear_pingroup smi_pingroup = {
1001 .name = "smi_grp",
1002 .pins = smi_pins,
1003 .npins = ARRAY_SIZE(smi_pins),
1004 .modemuxs = smi_modemux,
1005 .nmodemuxs = ARRAY_SIZE(smi_modemux),
1006 };
1007
1008 static const char *const smi_grps[] = { "smi_grp" };
1009 static struct spear_function smi_function = {
1010 .name = "smi",
1011 .groups = smi_grps,
1012 .ngroups = ARRAY_SIZE(smi_grps),
1013 };
1014
1015 /* pad multiplexing for ssp0 device */
1016 static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
1017 static struct spear_muxreg ssp0_muxreg[] = {
1018 {
1019 .reg = PAD_FUNCTION_EN_3,
1020 .mask = SSP0_REG2_MASK,
1021 .val = SSP0_REG2_MASK,
1022 },
1023 };
1024
1025 static struct spear_modemux ssp0_modemux[] = {
1026 {
1027 .muxregs = ssp0_muxreg,
1028 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
1029 },
1030 };
1031
1032 static struct spear_pingroup ssp0_pingroup = {
1033 .name = "ssp0_grp",
1034 .pins = ssp0_pins,
1035 .npins = ARRAY_SIZE(ssp0_pins),
1036 .modemuxs = ssp0_modemux,
1037 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
1038 };
1039
1040 /* pad multiplexing for ssp0_cs1 device */
1041 static const unsigned ssp0_cs1_pins[] = { 24 };
1042 static struct spear_muxreg ssp0_cs1_muxreg[] = {
1043 {
1044 .reg = PAD_SHARED_IP_EN_1,
1045 .mask = SSP0_CS1_MASK,
1046 .val = SSP0_CS1_MASK,
1047 }, {
1048 .reg = PAD_FUNCTION_EN_1,
1049 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
1050 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
1051 },
1052 };
1053
1054 static struct spear_modemux ssp0_cs1_modemux[] = {
1055 {
1056 .muxregs = ssp0_cs1_muxreg,
1057 .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
1058 },
1059 };
1060
1061 static struct spear_pingroup ssp0_cs1_pingroup = {
1062 .name = "ssp0_cs1_grp",
1063 .pins = ssp0_cs1_pins,
1064 .npins = ARRAY_SIZE(ssp0_cs1_pins),
1065 .modemuxs = ssp0_cs1_modemux,
1066 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
1067 };
1068
1069 /* pad multiplexing for ssp0_cs2 device */
1070 static const unsigned ssp0_cs2_pins[] = { 85 };
1071 static struct spear_muxreg ssp0_cs2_muxreg[] = {
1072 {
1073 .reg = PAD_SHARED_IP_EN_1,
1074 .mask = SSP0_CS2_MASK,
1075 .val = SSP0_CS2_MASK,
1076 }, {
1077 .reg = PAD_FUNCTION_EN_3,
1078 .mask = TS_AND_SSP0_CS2_REG2_MASK,
1079 .val = TS_AND_SSP0_CS2_REG2_MASK,
1080 },
1081 };
1082
1083 static struct spear_modemux ssp0_cs2_modemux[] = {
1084 {
1085 .muxregs = ssp0_cs2_muxreg,
1086 .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
1087 },
1088 };
1089
1090 static struct spear_pingroup ssp0_cs2_pingroup = {
1091 .name = "ssp0_cs2_grp",
1092 .pins = ssp0_cs2_pins,
1093 .npins = ARRAY_SIZE(ssp0_cs2_pins),
1094 .modemuxs = ssp0_cs2_modemux,
1095 .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
1096 };
1097
1098 /* pad multiplexing for ssp0_cs3 device */
1099 static const unsigned ssp0_cs3_pins[] = { 132 };
1100 static struct spear_muxreg ssp0_cs3_muxreg[] = {
1101 {
1102 .reg = PAD_FUNCTION_EN_5,
1103 .mask = SSP0_CS3_REG4_MASK,
1104 .val = SSP0_CS3_REG4_MASK,
1105 },
1106 };
1107
1108 static struct spear_modemux ssp0_cs3_modemux[] = {
1109 {
1110 .muxregs = ssp0_cs3_muxreg,
1111 .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
1112 },
1113 };
1114
1115 static struct spear_pingroup ssp0_cs3_pingroup = {
1116 .name = "ssp0_cs3_grp",
1117 .pins = ssp0_cs3_pins,
1118 .npins = ARRAY_SIZE(ssp0_cs3_pins),
1119 .modemuxs = ssp0_cs3_modemux,
1120 .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
1121 };
1122
1123 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
1124 "ssp0_cs2_grp", "ssp0_cs3_grp" };
1125 static struct spear_function ssp0_function = {
1126 .name = "ssp0",
1127 .groups = ssp0_grps,
1128 .ngroups = ARRAY_SIZE(ssp0_grps),
1129 };
1130
1131 /* pad multiplexing for uart0 device */
1132 static const unsigned uart0_pins[] = { 86, 87 };
1133 static struct spear_muxreg uart0_muxreg[] = {
1134 {
1135 .reg = PAD_FUNCTION_EN_3,
1136 .mask = UART0_REG2_MASK,
1137 .val = UART0_REG2_MASK,
1138 },
1139 };
1140
1141 static struct spear_modemux uart0_modemux[] = {
1142 {
1143 .muxregs = uart0_muxreg,
1144 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
1145 },
1146 };
1147
1148 static struct spear_pingroup uart0_pingroup = {
1149 .name = "uart0_grp",
1150 .pins = uart0_pins,
1151 .npins = ARRAY_SIZE(uart0_pins),
1152 .modemuxs = uart0_modemux,
1153 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
1154 };
1155
1156 /* pad multiplexing for uart0_enh device */
1157 static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
1158 static struct spear_muxreg uart0_enh_muxreg[] = {
1159 {
1160 .reg = PAD_SHARED_IP_EN_1,
1161 .mask = GPT_MASK,
1162 .val = 0,
1163 }, {
1164 .reg = PAD_FUNCTION_EN_1,
1165 .mask = UART0_ENH_AND_GPT_REG0_MASK,
1166 .val = UART0_ENH_AND_GPT_REG0_MASK,
1167 },
1168 };
1169
1170 static struct spear_modemux uart0_enh_modemux[] = {
1171 {
1172 .muxregs = uart0_enh_muxreg,
1173 .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
1174 },
1175 };
1176
1177 static struct spear_pingroup uart0_enh_pingroup = {
1178 .name = "uart0_enh_grp",
1179 .pins = uart0_enh_pins,
1180 .npins = ARRAY_SIZE(uart0_enh_pins),
1181 .modemuxs = uart0_enh_modemux,
1182 .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
1183 };
1184
1185 static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
1186 static struct spear_function uart0_function = {
1187 .name = "uart0",
1188 .groups = uart0_grps,
1189 .ngroups = ARRAY_SIZE(uart0_grps),
1190 };
1191
1192 /* pad multiplexing for uart1 device */
1193 static const unsigned uart1_pins[] = { 88, 89 };
1194 static struct spear_muxreg uart1_muxreg[] = {
1195 {
1196 .reg = PAD_FUNCTION_EN_3,
1197 .mask = UART1_REG2_MASK,
1198 .val = UART1_REG2_MASK,
1199 },
1200 };
1201
1202 static struct spear_modemux uart1_modemux[] = {
1203 {
1204 .muxregs = uart1_muxreg,
1205 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
1206 },
1207 };
1208
1209 static struct spear_pingroup uart1_pingroup = {
1210 .name = "uart1_grp",
1211 .pins = uart1_pins,
1212 .npins = ARRAY_SIZE(uart1_pins),
1213 .modemuxs = uart1_modemux,
1214 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
1215 };
1216
1217 static const char *const uart1_grps[] = { "uart1_grp" };
1218 static struct spear_function uart1_function = {
1219 .name = "uart1",
1220 .groups = uart1_grps,
1221 .ngroups = ARRAY_SIZE(uart1_grps),
1222 };
1223
1224 /* pad multiplexing for i2s_in device */
1225 static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
1226 static struct spear_muxreg i2s_in_muxreg[] = {
1227 {
1228 .reg = PAD_FUNCTION_EN_3,
1229 .mask = I2S_IN_REG2_MASK,
1230 .val = I2S_IN_REG2_MASK,
1231 }, {
1232 .reg = PAD_FUNCTION_EN_4,
1233 .mask = I2S_IN_REG3_MASK,
1234 .val = I2S_IN_REG3_MASK,
1235 },
1236 };
1237
1238 static struct spear_modemux i2s_in_modemux[] = {
1239 {
1240 .muxregs = i2s_in_muxreg,
1241 .nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
1242 },
1243 };
1244
1245 static struct spear_pingroup i2s_in_pingroup = {
1246 .name = "i2s_in_grp",
1247 .pins = i2s_in_pins,
1248 .npins = ARRAY_SIZE(i2s_in_pins),
1249 .modemuxs = i2s_in_modemux,
1250 .nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
1251 };
1252
1253 /* pad multiplexing for i2s_out device */
1254 static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
1255 static struct spear_muxreg i2s_out_muxreg[] = {
1256 {
1257 .reg = PAD_FUNCTION_EN_4,
1258 .mask = I2S_OUT_REG3_MASK,
1259 .val = I2S_OUT_REG3_MASK,
1260 },
1261 };
1262
1263 static struct spear_modemux i2s_out_modemux[] = {
1264 {
1265 .muxregs = i2s_out_muxreg,
1266 .nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
1267 },
1268 };
1269
1270 static struct spear_pingroup i2s_out_pingroup = {
1271 .name = "i2s_out_grp",
1272 .pins = i2s_out_pins,
1273 .npins = ARRAY_SIZE(i2s_out_pins),
1274 .modemuxs = i2s_out_modemux,
1275 .nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
1276 };
1277
1278 static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
1279 static struct spear_function i2s_function = {
1280 .name = "i2s",
1281 .groups = i2s_grps,
1282 .ngroups = ARRAY_SIZE(i2s_grps),
1283 };
1284
1285 /* pad multiplexing for gmac device */
1286 static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
1287 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
1288 126, 127, 128, 129, 130, 131 };
1289 #define GMAC_MUXREG \
1290 { \
1291 .reg = PAD_FUNCTION_EN_4, \
1292 .mask = GMAC_REG3_MASK, \
1293 .val = GMAC_REG3_MASK, \
1294 }, { \
1295 .reg = PAD_FUNCTION_EN_5, \
1296 .mask = GMAC_REG4_MASK, \
1297 .val = GMAC_REG4_MASK, \
1298 }
1299
1300 /* pad multiplexing for gmii device */
1301 static struct spear_muxreg gmii_muxreg[] = {
1302 GMAC_MUXREG,
1303 {
1304 .reg = GMAC_CLK_CFG,
1305 .mask = GMAC_PHY_IF_SEL_MASK,
1306 .val = GMAC_PHY_IF_GMII_VAL,
1307 },
1308 };
1309
1310 static struct spear_modemux gmii_modemux[] = {
1311 {
1312 .muxregs = gmii_muxreg,
1313 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
1314 },
1315 };
1316
1317 static struct spear_pingroup gmii_pingroup = {
1318 .name = "gmii_grp",
1319 .pins = gmac_pins,
1320 .npins = ARRAY_SIZE(gmac_pins),
1321 .modemuxs = gmii_modemux,
1322 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
1323 };
1324
1325 /* pad multiplexing for rgmii device */
1326 static struct spear_muxreg rgmii_muxreg[] = {
1327 GMAC_MUXREG,
1328 {
1329 .reg = GMAC_CLK_CFG,
1330 .mask = GMAC_PHY_IF_SEL_MASK,
1331 .val = GMAC_PHY_IF_RGMII_VAL,
1332 },
1333 };
1334
1335 static struct spear_modemux rgmii_modemux[] = {
1336 {
1337 .muxregs = rgmii_muxreg,
1338 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
1339 },
1340 };
1341
1342 static struct spear_pingroup rgmii_pingroup = {
1343 .name = "rgmii_grp",
1344 .pins = gmac_pins,
1345 .npins = ARRAY_SIZE(gmac_pins),
1346 .modemuxs = rgmii_modemux,
1347 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
1348 };
1349
1350 /* pad multiplexing for rmii device */
1351 static struct spear_muxreg rmii_muxreg[] = {
1352 GMAC_MUXREG,
1353 {
1354 .reg = GMAC_CLK_CFG,
1355 .mask = GMAC_PHY_IF_SEL_MASK,
1356 .val = GMAC_PHY_IF_RMII_VAL,
1357 },
1358 };
1359
1360 static struct spear_modemux rmii_modemux[] = {
1361 {
1362 .muxregs = rmii_muxreg,
1363 .nmuxregs = ARRAY_SIZE(rmii_muxreg),
1364 },
1365 };
1366
1367 static struct spear_pingroup rmii_pingroup = {
1368 .name = "rmii_grp",
1369 .pins = gmac_pins,
1370 .npins = ARRAY_SIZE(gmac_pins),
1371 .modemuxs = rmii_modemux,
1372 .nmodemuxs = ARRAY_SIZE(rmii_modemux),
1373 };
1374
1375 /* pad multiplexing for sgmii device */
1376 static struct spear_muxreg sgmii_muxreg[] = {
1377 GMAC_MUXREG,
1378 {
1379 .reg = GMAC_CLK_CFG,
1380 .mask = GMAC_PHY_IF_SEL_MASK,
1381 .val = GMAC_PHY_IF_SGMII_VAL,
1382 },
1383 };
1384
1385 static struct spear_modemux sgmii_modemux[] = {
1386 {
1387 .muxregs = sgmii_muxreg,
1388 .nmuxregs = ARRAY_SIZE(sgmii_muxreg),
1389 },
1390 };
1391
1392 static struct spear_pingroup sgmii_pingroup = {
1393 .name = "sgmii_grp",
1394 .pins = gmac_pins,
1395 .npins = ARRAY_SIZE(gmac_pins),
1396 .modemuxs = sgmii_modemux,
1397 .nmodemuxs = ARRAY_SIZE(sgmii_modemux),
1398 };
1399
1400 static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
1401 "sgmii_grp" };
1402 static struct spear_function gmac_function = {
1403 .name = "gmac",
1404 .groups = gmac_grps,
1405 .ngroups = ARRAY_SIZE(gmac_grps),
1406 };
1407
1408 /* pad multiplexing for i2c0 device */
1409 static const unsigned i2c0_pins[] = { 133, 134 };
1410 static struct spear_muxreg i2c0_muxreg[] = {
1411 {
1412 .reg = PAD_FUNCTION_EN_5,
1413 .mask = I2C0_REG4_MASK,
1414 .val = I2C0_REG4_MASK,
1415 },
1416 };
1417
1418 static struct spear_modemux i2c0_modemux[] = {
1419 {
1420 .muxregs = i2c0_muxreg,
1421 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
1422 },
1423 };
1424
1425 static struct spear_pingroup i2c0_pingroup = {
1426 .name = "i2c0_grp",
1427 .pins = i2c0_pins,
1428 .npins = ARRAY_SIZE(i2c0_pins),
1429 .modemuxs = i2c0_modemux,
1430 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
1431 };
1432
1433 static const char *const i2c0_grps[] = { "i2c0_grp" };
1434 static struct spear_function i2c0_function = {
1435 .name = "i2c0",
1436 .groups = i2c0_grps,
1437 .ngroups = ARRAY_SIZE(i2c0_grps),
1438 };
1439
1440 /* pad multiplexing for i2c1 device */
1441 static const unsigned i2c1_pins[] = { 18, 23 };
1442 static struct spear_muxreg i2c1_muxreg[] = {
1443 {
1444 .reg = PAD_FUNCTION_EN_1,
1445 .mask = I2C1_REG0_MASK,
1446 .val = I2C1_REG0_MASK,
1447 },
1448 };
1449
1450 static struct spear_modemux i2c1_modemux[] = {
1451 {
1452 .muxregs = i2c1_muxreg,
1453 .nmuxregs = ARRAY_SIZE(i2c1_muxreg),
1454 },
1455 };
1456
1457 static struct spear_pingroup i2c1_pingroup = {
1458 .name = "i2c1_grp",
1459 .pins = i2c1_pins,
1460 .npins = ARRAY_SIZE(i2c1_pins),
1461 .modemuxs = i2c1_modemux,
1462 .nmodemuxs = ARRAY_SIZE(i2c1_modemux),
1463 };
1464
1465 static const char *const i2c1_grps[] = { "i2c1_grp" };
1466 static struct spear_function i2c1_function = {
1467 .name = "i2c1",
1468 .groups = i2c1_grps,
1469 .ngroups = ARRAY_SIZE(i2c1_grps),
1470 };
1471
1472 /* pad multiplexing for cec0 device */
1473 static const unsigned cec0_pins[] = { 135 };
1474 static struct spear_muxreg cec0_muxreg[] = {
1475 {
1476 .reg = PAD_FUNCTION_EN_5,
1477 .mask = CEC0_REG4_MASK,
1478 .val = CEC0_REG4_MASK,
1479 },
1480 };
1481
1482 static struct spear_modemux cec0_modemux[] = {
1483 {
1484 .muxregs = cec0_muxreg,
1485 .nmuxregs = ARRAY_SIZE(cec0_muxreg),
1486 },
1487 };
1488
1489 static struct spear_pingroup cec0_pingroup = {
1490 .name = "cec0_grp",
1491 .pins = cec0_pins,
1492 .npins = ARRAY_SIZE(cec0_pins),
1493 .modemuxs = cec0_modemux,
1494 .nmodemuxs = ARRAY_SIZE(cec0_modemux),
1495 };
1496
1497 static const char *const cec0_grps[] = { "cec0_grp" };
1498 static struct spear_function cec0_function = {
1499 .name = "cec0",
1500 .groups = cec0_grps,
1501 .ngroups = ARRAY_SIZE(cec0_grps),
1502 };
1503
1504 /* pad multiplexing for cec1 device */
1505 static const unsigned cec1_pins[] = { 136 };
1506 static struct spear_muxreg cec1_muxreg[] = {
1507 {
1508 .reg = PAD_FUNCTION_EN_5,
1509 .mask = CEC1_REG4_MASK,
1510 .val = CEC1_REG4_MASK,
1511 },
1512 };
1513
1514 static struct spear_modemux cec1_modemux[] = {
1515 {
1516 .muxregs = cec1_muxreg,
1517 .nmuxregs = ARRAY_SIZE(cec1_muxreg),
1518 },
1519 };
1520
1521 static struct spear_pingroup cec1_pingroup = {
1522 .name = "cec1_grp",
1523 .pins = cec1_pins,
1524 .npins = ARRAY_SIZE(cec1_pins),
1525 .modemuxs = cec1_modemux,
1526 .nmodemuxs = ARRAY_SIZE(cec1_modemux),
1527 };
1528
1529 static const char *const cec1_grps[] = { "cec1_grp" };
1530 static struct spear_function cec1_function = {
1531 .name = "cec1",
1532 .groups = cec1_grps,
1533 .ngroups = ARRAY_SIZE(cec1_grps),
1534 };
1535
1536 /* pad multiplexing for mcif devices */
1537 static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
1538 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
1539 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1540 229, 230, 231, 232, 237 };
1541 #define MCIF_MUXREG \
1542 { \
1543 .reg = PAD_SHARED_IP_EN_1, \
1544 .mask = MCIF_MASK, \
1545 .val = MCIF_MASK, \
1546 }, { \
1547 .reg = PAD_FUNCTION_EN_7, \
1548 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1549 .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1550 }, { \
1551 .reg = PAD_FUNCTION_EN_8, \
1552 .mask = MCIF_REG7_MASK, \
1553 .val = MCIF_REG7_MASK, \
1554 }
1555
1556 /* Pad multiplexing for sdhci device */
1557 static struct spear_muxreg sdhci_muxreg[] = {
1558 MCIF_MUXREG,
1559 {
1560 .reg = PERIP_CFG,
1561 .mask = MCIF_SEL_MASK,
1562 .val = MCIF_SEL_SD,
1563 },
1564 };
1565
1566 static struct spear_modemux sdhci_modemux[] = {
1567 {
1568 .muxregs = sdhci_muxreg,
1569 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1570 },
1571 };
1572
1573 static struct spear_pingroup sdhci_pingroup = {
1574 .name = "sdhci_grp",
1575 .pins = mcif_pins,
1576 .npins = ARRAY_SIZE(mcif_pins),
1577 .modemuxs = sdhci_modemux,
1578 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1579 };
1580
1581 static const char *const sdhci_grps[] = { "sdhci_grp" };
1582 static struct spear_function sdhci_function = {
1583 .name = "sdhci",
1584 .groups = sdhci_grps,
1585 .ngroups = ARRAY_SIZE(sdhci_grps),
1586 };
1587
1588 /* Pad multiplexing for cf device */
1589 static struct spear_muxreg cf_muxreg[] = {
1590 MCIF_MUXREG,
1591 {
1592 .reg = PERIP_CFG,
1593 .mask = MCIF_SEL_MASK,
1594 .val = MCIF_SEL_CF,
1595 },
1596 };
1597
1598 static struct spear_modemux cf_modemux[] = {
1599 {
1600 .muxregs = cf_muxreg,
1601 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1602 },
1603 };
1604
1605 static struct spear_pingroup cf_pingroup = {
1606 .name = "cf_grp",
1607 .pins = mcif_pins,
1608 .npins = ARRAY_SIZE(mcif_pins),
1609 .modemuxs = cf_modemux,
1610 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1611 };
1612
1613 static const char *const cf_grps[] = { "cf_grp" };
1614 static struct spear_function cf_function = {
1615 .name = "cf",
1616 .groups = cf_grps,
1617 .ngroups = ARRAY_SIZE(cf_grps),
1618 };
1619
1620 /* Pad multiplexing for xd device */
1621 static struct spear_muxreg xd_muxreg[] = {
1622 MCIF_MUXREG,
1623 {
1624 .reg = PERIP_CFG,
1625 .mask = MCIF_SEL_MASK,
1626 .val = MCIF_SEL_XD,
1627 },
1628 };
1629
1630 static struct spear_modemux xd_modemux[] = {
1631 {
1632 .muxregs = xd_muxreg,
1633 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1634 },
1635 };
1636
1637 static struct spear_pingroup xd_pingroup = {
1638 .name = "xd_grp",
1639 .pins = mcif_pins,
1640 .npins = ARRAY_SIZE(mcif_pins),
1641 .modemuxs = xd_modemux,
1642 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1643 };
1644
1645 static const char *const xd_grps[] = { "xd_grp" };
1646 static struct spear_function xd_function = {
1647 .name = "xd",
1648 .groups = xd_grps,
1649 .ngroups = ARRAY_SIZE(xd_grps),
1650 };
1651
1652 /* pad multiplexing for clcd device */
1653 static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
1654 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
1655 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
1656 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
1657 188, 189, 190, 191 };
1658 static struct spear_muxreg clcd_muxreg[] = {
1659 {
1660 .reg = PAD_SHARED_IP_EN_1,
1661 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1662 .val = 0,
1663 }, {
1664 .reg = PAD_FUNCTION_EN_5,
1665 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1666 .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1667 }, {
1668 .reg = PAD_FUNCTION_EN_6,
1669 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1670 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1671 }, {
1672 .reg = PAD_FUNCTION_EN_7,
1673 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1674 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1675 },
1676 };
1677
1678 static struct spear_modemux clcd_modemux[] = {
1679 {
1680 .muxregs = clcd_muxreg,
1681 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
1682 },
1683 };
1684
1685 static struct spear_pingroup clcd_pingroup = {
1686 .name = "clcd_grp",
1687 .pins = clcd_pins,
1688 .npins = ARRAY_SIZE(clcd_pins),
1689 .modemuxs = clcd_modemux,
1690 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
1691 };
1692
1693 /* Disable cld runtime to save panel damage */
1694 static struct spear_muxreg clcd_sleep_muxreg[] = {
1695 {
1696 .reg = PAD_SHARED_IP_EN_1,
1697 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1698 .val = 0,
1699 }, {
1700 .reg = PAD_FUNCTION_EN_5,
1701 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1702 .val = 0x0,
1703 }, {
1704 .reg = PAD_FUNCTION_EN_6,
1705 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1706 .val = 0x0,
1707 }, {
1708 .reg = PAD_FUNCTION_EN_7,
1709 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1710 .val = 0x0,
1711 },
1712 };
1713
1714 static struct spear_modemux clcd_sleep_modemux[] = {
1715 {
1716 .muxregs = clcd_sleep_muxreg,
1717 .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg),
1718 },
1719 };
1720
1721 static struct spear_pingroup clcd_sleep_pingroup = {
1722 .name = "clcd_sleep_grp",
1723 .pins = clcd_pins,
1724 .npins = ARRAY_SIZE(clcd_pins),
1725 .modemuxs = clcd_sleep_modemux,
1726 .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux),
1727 };
1728
1729 static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" };
1730 static struct spear_function clcd_function = {
1731 .name = "clcd",
1732 .groups = clcd_grps,
1733 .ngroups = ARRAY_SIZE(clcd_grps),
1734 };
1735
1736 /* pad multiplexing for arm_trace device */
1737 static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
1738 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
1739 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
1740 193, 194, 195, 196, 197, 198, 199, 200 };
1741 static struct spear_muxreg arm_trace_muxreg[] = {
1742 {
1743 .reg = PAD_SHARED_IP_EN_1,
1744 .mask = ARM_TRACE_MASK,
1745 .val = ARM_TRACE_MASK,
1746 }, {
1747 .reg = PAD_FUNCTION_EN_5,
1748 .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
1749 .val = CLCD_AND_ARM_TRACE_REG4_MASK,
1750 }, {
1751 .reg = PAD_FUNCTION_EN_6,
1752 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1753 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1754 }, {
1755 .reg = PAD_FUNCTION_EN_7,
1756 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1757 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1758 },
1759 };
1760
1761 static struct spear_modemux arm_trace_modemux[] = {
1762 {
1763 .muxregs = arm_trace_muxreg,
1764 .nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
1765 },
1766 };
1767
1768 static struct spear_pingroup arm_trace_pingroup = {
1769 .name = "arm_trace_grp",
1770 .pins = arm_trace_pins,
1771 .npins = ARRAY_SIZE(arm_trace_pins),
1772 .modemuxs = arm_trace_modemux,
1773 .nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
1774 };
1775
1776 static const char *const arm_trace_grps[] = { "arm_trace_grp" };
1777 static struct spear_function arm_trace_function = {
1778 .name = "arm_trace",
1779 .groups = arm_trace_grps,
1780 .ngroups = ARRAY_SIZE(arm_trace_grps),
1781 };
1782
1783 /* pad multiplexing for miphy_dbg device */
1784 static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
1785 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
1786 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
1787 static struct spear_muxreg miphy_dbg_muxreg[] = {
1788 {
1789 .reg = PAD_SHARED_IP_EN_1,
1790 .mask = MIPHY_DBG_MASK,
1791 .val = MIPHY_DBG_MASK,
1792 }, {
1793 .reg = PAD_FUNCTION_EN_5,
1794 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1795 .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1796 },
1797 };
1798
1799 static struct spear_modemux miphy_dbg_modemux[] = {
1800 {
1801 .muxregs = miphy_dbg_muxreg,
1802 .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
1803 },
1804 };
1805
1806 static struct spear_pingroup miphy_dbg_pingroup = {
1807 .name = "miphy_dbg_grp",
1808 .pins = miphy_dbg_pins,
1809 .npins = ARRAY_SIZE(miphy_dbg_pins),
1810 .modemuxs = miphy_dbg_modemux,
1811 .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
1812 };
1813
1814 static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
1815 static struct spear_function miphy_dbg_function = {
1816 .name = "miphy_dbg",
1817 .groups = miphy_dbg_grps,
1818 .ngroups = ARRAY_SIZE(miphy_dbg_grps),
1819 };
1820
1821 /* pad multiplexing for pcie device */
1822 static const unsigned pcie_pins[] = { 250 };
1823 static struct spear_muxreg pcie_muxreg[] = {
1824 {
1825 .reg = PCIE_SATA_CFG,
1826 .mask = SATA_PCIE_CFG_MASK,
1827 .val = PCIE_CFG_VAL,
1828 },
1829 };
1830
1831 static struct spear_modemux pcie_modemux[] = {
1832 {
1833 .muxregs = pcie_muxreg,
1834 .nmuxregs = ARRAY_SIZE(pcie_muxreg),
1835 },
1836 };
1837
1838 static struct spear_pingroup pcie_pingroup = {
1839 .name = "pcie_grp",
1840 .pins = pcie_pins,
1841 .npins = ARRAY_SIZE(pcie_pins),
1842 .modemuxs = pcie_modemux,
1843 .nmodemuxs = ARRAY_SIZE(pcie_modemux),
1844 };
1845
1846 static const char *const pcie_grps[] = { "pcie_grp" };
1847 static struct spear_function pcie_function = {
1848 .name = "pcie",
1849 .groups = pcie_grps,
1850 .ngroups = ARRAY_SIZE(pcie_grps),
1851 };
1852
1853 /* pad multiplexing for sata device */
1854 static const unsigned sata_pins[] = { 250 };
1855 static struct spear_muxreg sata_muxreg[] = {
1856 {
1857 .reg = PCIE_SATA_CFG,
1858 .mask = SATA_PCIE_CFG_MASK,
1859 .val = SATA_CFG_VAL,
1860 },
1861 };
1862
1863 static struct spear_modemux sata_modemux[] = {
1864 {
1865 .muxregs = sata_muxreg,
1866 .nmuxregs = ARRAY_SIZE(sata_muxreg),
1867 },
1868 };
1869
1870 static struct spear_pingroup sata_pingroup = {
1871 .name = "sata_grp",
1872 .pins = sata_pins,
1873 .npins = ARRAY_SIZE(sata_pins),
1874 .modemuxs = sata_modemux,
1875 .nmodemuxs = ARRAY_SIZE(sata_modemux),
1876 };
1877
1878 static const char *const sata_grps[] = { "sata_grp" };
1879 static struct spear_function sata_function = {
1880 .name = "sata",
1881 .groups = sata_grps,
1882 .ngroups = ARRAY_SIZE(sata_grps),
1883 };
1884
1885 /* pingroups */
1886 static struct spear_pingroup *spear1340_pingroups[] = {
1887 &pads_as_gpio_pingroup,
1888 &fsmc_8bit_pingroup,
1889 &fsmc_16bit_pingroup,
1890 &fsmc_pnor_pingroup,
1891 &keyboard_row_col_pingroup,
1892 &keyboard_col5_pingroup,
1893 &spdif_in_pingroup,
1894 &spdif_out_pingroup,
1895 &gpt_0_1_pingroup,
1896 &pwm0_pingroup,
1897 &pwm1_pingroup,
1898 &pwm2_pingroup,
1899 &pwm3_pingroup,
1900 &vip_mux_pingroup,
1901 &vip_mux_cam0_pingroup,
1902 &vip_mux_cam1_pingroup,
1903 &vip_mux_cam2_pingroup,
1904 &vip_mux_cam3_pingroup,
1905 &cam0_pingroup,
1906 &cam1_pingroup,
1907 &cam2_pingroup,
1908 &cam3_pingroup,
1909 &smi_pingroup,
1910 &ssp0_pingroup,
1911 &ssp0_cs1_pingroup,
1912 &ssp0_cs2_pingroup,
1913 &ssp0_cs3_pingroup,
1914 &uart0_pingroup,
1915 &uart0_enh_pingroup,
1916 &uart1_pingroup,
1917 &i2s_in_pingroup,
1918 &i2s_out_pingroup,
1919 &gmii_pingroup,
1920 &rgmii_pingroup,
1921 &rmii_pingroup,
1922 &sgmii_pingroup,
1923 &i2c0_pingroup,
1924 &i2c1_pingroup,
1925 &cec0_pingroup,
1926 &cec1_pingroup,
1927 &sdhci_pingroup,
1928 &cf_pingroup,
1929 &xd_pingroup,
1930 &clcd_sleep_pingroup,
1931 &clcd_pingroup,
1932 &arm_trace_pingroup,
1933 &miphy_dbg_pingroup,
1934 &pcie_pingroup,
1935 &sata_pingroup,
1936 };
1937
1938 /* functions */
1939 static struct spear_function *spear1340_functions[] = {
1940 &pads_as_gpio_function,
1941 &fsmc_function,
1942 &keyboard_function,
1943 &spdif_in_function,
1944 &spdif_out_function,
1945 &gpt_0_1_function,
1946 &pwm_function,
1947 &vip_function,
1948 &cam0_function,
1949 &cam1_function,
1950 &cam2_function,
1951 &cam3_function,
1952 &smi_function,
1953 &ssp0_function,
1954 &uart0_function,
1955 &uart1_function,
1956 &i2s_function,
1957 &gmac_function,
1958 &i2c0_function,
1959 &i2c1_function,
1960 &cec0_function,
1961 &cec1_function,
1962 &sdhci_function,
1963 &cf_function,
1964 &xd_function,
1965 &clcd_function,
1966 &arm_trace_function,
1967 &miphy_dbg_function,
1968 &pcie_function,
1969 &sata_function,
1970 };
1971
gpio_request_endisable(struct spear_pmx * pmx,int pin,bool enable)1972 static void gpio_request_endisable(struct spear_pmx *pmx, int pin,
1973 bool enable)
1974 {
1975 unsigned int regoffset, regindex, bitoffset;
1976 unsigned int val;
1977
1978 /* pin++ as gpio configuration starts from 2nd bit of base register */
1979 pin++;
1980
1981 regindex = pin / 32;
1982 bitoffset = pin % 32;
1983
1984 if (regindex <= 3)
1985 regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *);
1986 else
1987 regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *);
1988
1989 val = pmx_readl(pmx, regoffset);
1990 if (enable)
1991 val &= ~(0x1 << bitoffset);
1992 else
1993 val |= 0x1 << bitoffset;
1994
1995 pmx_writel(pmx, val, regoffset);
1996 }
1997
1998 static struct spear_pinctrl_machdata spear1340_machdata = {
1999 .pins = spear1340_pins,
2000 .npins = ARRAY_SIZE(spear1340_pins),
2001 .groups = spear1340_pingroups,
2002 .ngroups = ARRAY_SIZE(spear1340_pingroups),
2003 .functions = spear1340_functions,
2004 .nfunctions = ARRAY_SIZE(spear1340_functions),
2005 .gpio_request_endisable = gpio_request_endisable,
2006 .modes_supported = false,
2007 };
2008
2009 static const struct of_device_id spear1340_pinctrl_of_match[] = {
2010 {
2011 .compatible = "st,spear1340-pinmux",
2012 },
2013 {},
2014 };
2015
spear1340_pinctrl_probe(struct platform_device * pdev)2016 static int spear1340_pinctrl_probe(struct platform_device *pdev)
2017 {
2018 return spear_pinctrl_probe(pdev, &spear1340_machdata);
2019 }
2020
2021 static struct platform_driver spear1340_pinctrl_driver = {
2022 .driver = {
2023 .name = DRIVER_NAME,
2024 .of_match_table = spear1340_pinctrl_of_match,
2025 },
2026 .probe = spear1340_pinctrl_probe,
2027 };
2028
spear1340_pinctrl_init(void)2029 static int __init spear1340_pinctrl_init(void)
2030 {
2031 return platform_driver_register(&spear1340_pinctrl_driver);
2032 }
2033 arch_initcall(spear1340_pinctrl_init);
2034