1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Roy Luo <royluo@google.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
6 */
7
8 #include <linux/firmware.h>
9 #include "mt7615.h"
10 #include "mcu.h"
11 #include "mac.h"
12 #include "eeprom.h"
13
14 static bool prefer_offload_fw = true;
15 module_param(prefer_offload_fw, bool, 0644);
16 MODULE_PARM_DESC(prefer_offload_fw,
17 "Prefer client mode offload firmware (MT7663)");
18
19 struct mt7615_patch_hdr {
20 char build_date[16];
21 char platform[4];
22 __be32 hw_sw_ver;
23 __be32 patch_ver;
24 __be16 checksum;
25 } __packed;
26
27 struct mt7615_fw_trailer {
28 __le32 addr;
29 u8 chip_id;
30 u8 feature_set;
31 u8 eco_code;
32 char fw_ver[10];
33 char build_date[15];
34 __le32 len;
35 } __packed;
36
37 #define FW_V3_COMMON_TAILER_SIZE 36
38 #define FW_V3_REGION_TAILER_SIZE 40
39 #define FW_START_OVERRIDE BIT(0)
40 #define FW_START_DLYCAL BIT(1)
41 #define FW_START_WORKING_PDA_CR4 BIT(2)
42
43 struct mt7663_fw_buf {
44 __le32 crc;
45 __le32 d_img_size;
46 __le32 block_size;
47 u8 rsv[4];
48 __le32 img_dest_addr;
49 __le32 img_size;
50 u8 feature_set;
51 };
52
53 #define MT7615_PATCH_ADDRESS 0x80000
54 #define MT7622_PATCH_ADDRESS 0x9c000
55 #define MT7663_PATCH_ADDRESS 0xdc000
56
57 #define N9_REGION_NUM 2
58 #define CR4_REGION_NUM 1
59
60 #define IMG_CRC_LEN 4
61
mt7615_mcu_fill_msg(struct mt7615_dev * dev,struct sk_buff * skb,int cmd,int * wait_seq)62 void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb,
63 int cmd, int *wait_seq)
64 {
65 int txd_len, mcu_cmd = FIELD_GET(__MCU_CMD_FIELD_ID, cmd);
66 struct mt7615_uni_txd *uni_txd;
67 struct mt7615_mcu_txd *mcu_txd;
68 u8 seq, q_idx, pkt_fmt;
69 __le32 *txd;
70 u32 val;
71
72 /* TODO: make dynamic based on msg type */
73 dev->mt76.mcu.timeout = 20 * HZ;
74
75 seq = ++dev->mt76.mcu.msg_seq & 0xf;
76 if (!seq)
77 seq = ++dev->mt76.mcu.msg_seq & 0xf;
78 if (wait_seq)
79 *wait_seq = seq;
80
81 txd_len = cmd & __MCU_CMD_FIELD_UNI ? sizeof(*uni_txd) : sizeof(*mcu_txd);
82 txd = (__le32 *)skb_push(skb, txd_len);
83
84 if (cmd != MCU_CMD(FW_SCATTER)) {
85 q_idx = MT_TX_MCU_PORT_RX_Q0;
86 pkt_fmt = MT_TX_TYPE_CMD;
87 } else {
88 q_idx = MT_TX_MCU_PORT_RX_FWDL;
89 pkt_fmt = MT_TX_TYPE_FW;
90 }
91
92 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) |
93 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_MCU) |
94 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
95 txd[0] = cpu_to_le32(val);
96
97 val = MT_TXD1_LONG_FORMAT |
98 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD) |
99 FIELD_PREP(MT_TXD1_PKT_FMT, pkt_fmt);
100 txd[1] = cpu_to_le32(val);
101
102 if (cmd & __MCU_CMD_FIELD_UNI) {
103 uni_txd = (struct mt7615_uni_txd *)txd;
104 uni_txd->len = cpu_to_le16(skb->len - sizeof(uni_txd->txd));
105 uni_txd->option = MCU_CMD_UNI_EXT_ACK;
106 uni_txd->cid = cpu_to_le16(mcu_cmd);
107 uni_txd->s2d_index = MCU_S2D_H2N;
108 uni_txd->pkt_type = MCU_PKT_ID;
109 uni_txd->seq = seq;
110
111 return;
112 }
113
114 mcu_txd = (struct mt7615_mcu_txd *)txd;
115 mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd));
116 mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, q_idx));
117 mcu_txd->s2d_index = MCU_S2D_H2N;
118 mcu_txd->pkt_type = MCU_PKT_ID;
119 mcu_txd->seq = seq;
120 mcu_txd->cid = mcu_cmd;
121 mcu_txd->ext_cid = FIELD_GET(__MCU_CMD_FIELD_EXT_ID, cmd);
122
123 if (mcu_txd->ext_cid || (cmd & __MCU_CMD_FIELD_CE)) {
124 if (cmd & __MCU_CMD_FIELD_QUERY)
125 mcu_txd->set_query = MCU_Q_QUERY;
126 else
127 mcu_txd->set_query = MCU_Q_SET;
128 mcu_txd->ext_cid_ack = !!mcu_txd->ext_cid;
129 } else {
130 mcu_txd->set_query = MCU_Q_NA;
131 }
132 }
133 EXPORT_SYMBOL_GPL(mt7615_mcu_fill_msg);
134
mt7615_mcu_parse_response(struct mt76_dev * mdev,int cmd,struct sk_buff * skb,int seq)135 int mt7615_mcu_parse_response(struct mt76_dev *mdev, int cmd,
136 struct sk_buff *skb, int seq)
137 {
138 struct mt7615_mcu_rxd *rxd;
139 int ret = 0;
140
141 if (!skb) {
142 dev_err(mdev->dev, "Message %08x (seq %d) timeout\n",
143 cmd, seq);
144 return -ETIMEDOUT;
145 }
146
147 rxd = (struct mt7615_mcu_rxd *)skb->data;
148 if (seq != rxd->seq)
149 return -EAGAIN;
150
151 if (cmd == MCU_CMD(PATCH_SEM_CONTROL)) {
152 skb_pull(skb, sizeof(*rxd) - 4);
153 ret = *skb->data;
154 } else if (cmd == MCU_EXT_CMD(THERMAL_CTRL)) {
155 skb_pull(skb, sizeof(*rxd));
156 ret = le32_to_cpu(*(__le32 *)skb->data);
157 } else if (cmd == MCU_EXT_QUERY(RF_REG_ACCESS)) {
158 skb_pull(skb, sizeof(*rxd));
159 ret = le32_to_cpu(*(__le32 *)&skb->data[8]);
160 } else if (cmd == MCU_UNI_CMD(DEV_INFO_UPDATE) ||
161 cmd == MCU_UNI_CMD(BSS_INFO_UPDATE) ||
162 cmd == MCU_UNI_CMD(STA_REC_UPDATE) ||
163 cmd == MCU_UNI_CMD(HIF_CTRL) ||
164 cmd == MCU_UNI_CMD(OFFLOAD) ||
165 cmd == MCU_UNI_CMD(SUSPEND)) {
166 struct mt76_connac_mcu_uni_event *event;
167
168 skb_pull(skb, sizeof(*rxd));
169 event = (struct mt76_connac_mcu_uni_event *)skb->data;
170 ret = le32_to_cpu(event->status);
171 } else if (cmd == MCU_CE_QUERY(REG_READ)) {
172 struct mt76_connac_mcu_reg_event *event;
173
174 skb_pull(skb, sizeof(*rxd));
175 event = (struct mt76_connac_mcu_reg_event *)skb->data;
176 ret = (int)le32_to_cpu(event->val);
177 }
178
179 return ret;
180 }
181 EXPORT_SYMBOL_GPL(mt7615_mcu_parse_response);
182
183 static int
mt7615_mcu_send_message(struct mt76_dev * mdev,struct sk_buff * skb,int cmd,int * seq)184 mt7615_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
185 int cmd, int *seq)
186 {
187 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
188 enum mt76_mcuq_id qid;
189
190 mt7615_mcu_fill_msg(dev, skb, cmd, seq);
191 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
192 qid = MT_MCUQ_WM;
193 else
194 qid = MT_MCUQ_FWDL;
195
196 return mt76_tx_queue_skb_raw(dev, dev->mt76.q_mcu[qid], skb, 0);
197 }
198
mt7615_rf_rr(struct mt7615_dev * dev,u32 wf,u32 reg)199 u32 mt7615_rf_rr(struct mt7615_dev *dev, u32 wf, u32 reg)
200 {
201 struct {
202 __le32 wifi_stream;
203 __le32 address;
204 __le32 data;
205 } req = {
206 .wifi_stream = cpu_to_le32(wf),
207 .address = cpu_to_le32(reg),
208 };
209
210 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_QUERY(RF_REG_ACCESS),
211 &req, sizeof(req), true);
212 }
213
mt7615_rf_wr(struct mt7615_dev * dev,u32 wf,u32 reg,u32 val)214 int mt7615_rf_wr(struct mt7615_dev *dev, u32 wf, u32 reg, u32 val)
215 {
216 struct {
217 __le32 wifi_stream;
218 __le32 address;
219 __le32 data;
220 } req = {
221 .wifi_stream = cpu_to_le32(wf),
222 .address = cpu_to_le32(reg),
223 .data = cpu_to_le32(val),
224 };
225
226 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_REG_ACCESS),
227 &req, sizeof(req), false);
228 }
229
mt7622_trigger_hif_int(struct mt7615_dev * dev,bool en)230 void mt7622_trigger_hif_int(struct mt7615_dev *dev, bool en)
231 {
232 if (!is_mt7622(&dev->mt76))
233 return;
234
235 #if defined(__linux__)
236 regmap_update_bits(dev->infracfg, MT_INFRACFG_MISC,
237 MT_INFRACFG_MISC_AP2CONN_WAKE,
238 !en * MT_INFRACFG_MISC_AP2CONN_WAKE);
239 #elif defined(__FreeBSD__)
240 panic("%s: LinuxKPI needs regmap\n", __func__);
241 #endif
242 }
243 EXPORT_SYMBOL_GPL(mt7622_trigger_hif_int);
244
mt7615_mcu_drv_pmctrl(struct mt7615_dev * dev)245 static int mt7615_mcu_drv_pmctrl(struct mt7615_dev *dev)
246 {
247 struct mt76_phy *mphy = &dev->mt76.phy;
248 struct mt76_connac_pm *pm = &dev->pm;
249 struct mt76_dev *mdev = &dev->mt76;
250 u32 addr;
251 int err;
252
253 if (is_mt7663(mdev)) {
254 /* Clear firmware own via N9 eint */
255 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN);
256 mt76_poll(dev, MT_CONN_ON_MISC, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000);
257
258 addr = MT_CONN_HIF_ON_LPCTL;
259 } else {
260 addr = MT_CFG_LPCR_HOST;
261 }
262
263 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_DRV_OWN);
264
265 mt7622_trigger_hif_int(dev, true);
266
267 err = !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000);
268
269 mt7622_trigger_hif_int(dev, false);
270
271 if (err) {
272 dev_err(mdev->dev, "driver own failed\n");
273 return -ETIMEDOUT;
274 }
275
276 clear_bit(MT76_STATE_PM, &mphy->state);
277
278 pm->stats.last_wake_event = jiffies;
279 pm->stats.doze_time += pm->stats.last_wake_event -
280 pm->stats.last_doze_event;
281
282 return 0;
283 }
284
mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev * dev)285 static int mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev *dev)
286 {
287 struct mt76_phy *mphy = &dev->mt76.phy;
288 struct mt76_connac_pm *pm = &dev->pm;
289 int i, err = 0;
290
291 mutex_lock(&pm->mutex);
292
293 if (!test_bit(MT76_STATE_PM, &mphy->state))
294 goto out;
295
296 for (i = 0; i < MT7615_DRV_OWN_RETRY_COUNT; i++) {
297 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN);
298 if (mt76_poll_msec(dev, MT_CONN_HIF_ON_LPCTL,
299 MT_CFG_LPCR_HOST_FW_OWN, 0, 50))
300 break;
301 }
302
303 if (i == MT7615_DRV_OWN_RETRY_COUNT) {
304 dev_err(dev->mt76.dev, "driver own failed\n");
305 err = -EIO;
306 goto out;
307 }
308 clear_bit(MT76_STATE_PM, &mphy->state);
309
310 pm->stats.last_wake_event = jiffies;
311 pm->stats.doze_time += pm->stats.last_wake_event -
312 pm->stats.last_doze_event;
313 out:
314 mutex_unlock(&pm->mutex);
315
316 return err;
317 }
318
mt7615_mcu_fw_pmctrl(struct mt7615_dev * dev)319 static int mt7615_mcu_fw_pmctrl(struct mt7615_dev *dev)
320 {
321 struct mt76_phy *mphy = &dev->mt76.phy;
322 struct mt76_connac_pm *pm = &dev->pm;
323 int err = 0;
324 u32 addr;
325
326 mutex_lock(&pm->mutex);
327
328 if (mt76_connac_skip_fw_pmctrl(mphy, pm))
329 goto out;
330
331 mt7622_trigger_hif_int(dev, true);
332
333 addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST;
334 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_FW_OWN);
335
336 if (is_mt7622(&dev->mt76) &&
337 !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN,
338 MT_CFG_LPCR_HOST_FW_OWN, 3000)) {
339 dev_err(dev->mt76.dev, "Timeout for firmware own\n");
340 clear_bit(MT76_STATE_PM, &mphy->state);
341 err = -EIO;
342 }
343
344 mt7622_trigger_hif_int(dev, false);
345 if (!err) {
346 pm->stats.last_doze_event = jiffies;
347 pm->stats.awake_time += pm->stats.last_doze_event -
348 pm->stats.last_wake_event;
349 }
350 out:
351 mutex_unlock(&pm->mutex);
352
353 return err;
354 }
355
356 static void
mt7615_mcu_csa_finish(void * priv,u8 * mac,struct ieee80211_vif * vif)357 mt7615_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif)
358 {
359 if (vif->bss_conf.csa_active)
360 ieee80211_csa_finish(vif, 0);
361 }
362
363 static void
mt7615_mcu_rx_csa_notify(struct mt7615_dev * dev,struct sk_buff * skb)364 mt7615_mcu_rx_csa_notify(struct mt7615_dev *dev, struct sk_buff *skb)
365 {
366 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev);
367 struct mt76_phy *mphy = &dev->mt76.phy;
368 struct mt7615_mcu_csa_notify *c;
369
370 c = (struct mt7615_mcu_csa_notify *)skb->data;
371
372 if (c->omac_idx > EXT_BSSID_MAX)
373 return;
374
375 if (ext_phy && ext_phy->omac_mask & BIT_ULL(c->omac_idx))
376 mphy = dev->mt76.phys[MT_BAND1];
377
378 ieee80211_iterate_active_interfaces_atomic(mphy->hw,
379 IEEE80211_IFACE_ITER_RESUME_ALL,
380 mt7615_mcu_csa_finish, mphy->hw);
381 }
382
383 static void
mt7615_mcu_rx_radar_detected(struct mt7615_dev * dev,struct sk_buff * skb)384 mt7615_mcu_rx_radar_detected(struct mt7615_dev *dev, struct sk_buff *skb)
385 {
386 struct mt76_phy *mphy = &dev->mt76.phy;
387 struct mt7615_mcu_rdd_report *r;
388
389 r = (struct mt7615_mcu_rdd_report *)skb->data;
390
391 if (!dev->radar_pattern.n_pulses && !r->long_detected &&
392 !r->constant_prf_detected && !r->staggered_prf_detected)
393 return;
394
395 if (r->band_idx && dev->mt76.phys[MT_BAND1])
396 mphy = dev->mt76.phys[MT_BAND1];
397
398 if (mt76_phy_dfs_state(mphy) < MT_DFS_STATE_CAC)
399 return;
400
401 ieee80211_radar_detected(mphy->hw, NULL);
402 dev->hw_pattern++;
403 }
404
405 static void
mt7615_mcu_rx_log_message(struct mt7615_dev * dev,struct sk_buff * skb)406 mt7615_mcu_rx_log_message(struct mt7615_dev *dev, struct sk_buff *skb)
407 {
408 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
409 const char *data = (char *)&rxd[1];
410 const char *type;
411
412 switch (rxd->s2d_index) {
413 case 0:
414 type = "N9";
415 break;
416 case 2:
417 type = "CR4";
418 break;
419 default:
420 type = "unknown";
421 break;
422 }
423
424 wiphy_info(mt76_hw(dev)->wiphy, "%s: %.*s", type,
425 (int)(skb->len - sizeof(*rxd)), data);
426 }
427
428 static void
mt7615_mcu_rx_ext_event(struct mt7615_dev * dev,struct sk_buff * skb)429 mt7615_mcu_rx_ext_event(struct mt7615_dev *dev, struct sk_buff *skb)
430 {
431 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
432
433 switch (rxd->ext_eid) {
434 case MCU_EXT_EVENT_RDD_REPORT:
435 mt7615_mcu_rx_radar_detected(dev, skb);
436 break;
437 case MCU_EXT_EVENT_CSA_NOTIFY:
438 mt7615_mcu_rx_csa_notify(dev, skb);
439 break;
440 case MCU_EXT_EVENT_FW_LOG_2_HOST:
441 mt7615_mcu_rx_log_message(dev, skb);
442 break;
443 default:
444 break;
445 }
446 }
447
448 static void
mt7615_mcu_scan_event(struct mt7615_dev * dev,struct sk_buff * skb)449 mt7615_mcu_scan_event(struct mt7615_dev *dev, struct sk_buff *skb)
450 {
451 u8 *seq_num = skb->data + sizeof(struct mt7615_mcu_rxd);
452 struct mt7615_phy *phy;
453 struct mt76_phy *mphy;
454
455 if (*seq_num & BIT(7) && dev->mt76.phys[MT_BAND1])
456 mphy = dev->mt76.phys[MT_BAND1];
457 else
458 mphy = &dev->mt76.phy;
459
460 phy = mphy->priv;
461
462 spin_lock_bh(&dev->mt76.lock);
463 __skb_queue_tail(&phy->scan_event_list, skb);
464 spin_unlock_bh(&dev->mt76.lock);
465
466 ieee80211_queue_delayed_work(mphy->hw, &phy->scan_work,
467 MT7615_HW_SCAN_TIMEOUT);
468 }
469
470 static void
mt7615_mcu_roc_event(struct mt7615_dev * dev,struct sk_buff * skb)471 mt7615_mcu_roc_event(struct mt7615_dev *dev, struct sk_buff *skb)
472 {
473 struct mt7615_roc_tlv *event;
474 struct mt7615_phy *phy;
475 struct mt76_phy *mphy;
476 int duration;
477
478 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
479 event = (struct mt7615_roc_tlv *)skb->data;
480
481 if (event->dbdc_band && dev->mt76.phys[MT_BAND1])
482 mphy = dev->mt76.phys[MT_BAND1];
483 else
484 mphy = &dev->mt76.phy;
485
486 ieee80211_ready_on_channel(mphy->hw);
487
488 phy = mphy->priv;
489 phy->roc_grant = true;
490 wake_up(&phy->roc_wait);
491
492 duration = le32_to_cpu(event->max_interval);
493 mod_timer(&phy->roc_timer,
494 round_jiffies_up(jiffies + msecs_to_jiffies(duration)));
495 }
496
497 static void
mt7615_mcu_beacon_loss_event(struct mt7615_dev * dev,struct sk_buff * skb)498 mt7615_mcu_beacon_loss_event(struct mt7615_dev *dev, struct sk_buff *skb)
499 {
500 struct mt76_connac_beacon_loss_event *event;
501 struct mt76_phy *mphy;
502 u8 band_idx = 0; /* DBDC support */
503
504 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
505 event = (struct mt76_connac_beacon_loss_event *)skb->data;
506 if (band_idx && dev->mt76.phys[MT_BAND1])
507 mphy = dev->mt76.phys[MT_BAND1];
508 else
509 mphy = &dev->mt76.phy;
510
511 ieee80211_iterate_active_interfaces_atomic(mphy->hw,
512 IEEE80211_IFACE_ITER_RESUME_ALL,
513 mt76_connac_mcu_beacon_loss_iter,
514 event);
515 }
516
517 static void
mt7615_mcu_bss_event(struct mt7615_dev * dev,struct sk_buff * skb)518 mt7615_mcu_bss_event(struct mt7615_dev *dev, struct sk_buff *skb)
519 {
520 struct mt76_connac_mcu_bss_event *event;
521 struct mt76_phy *mphy;
522 u8 band_idx = 0; /* DBDC support */
523
524 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
525 event = (struct mt76_connac_mcu_bss_event *)skb->data;
526
527 if (band_idx && dev->mt76.phys[MT_BAND1])
528 mphy = dev->mt76.phys[MT_BAND1];
529 else
530 mphy = &dev->mt76.phy;
531
532 if (event->is_absent)
533 ieee80211_stop_queues(mphy->hw);
534 else
535 ieee80211_wake_queues(mphy->hw);
536 }
537
538 static void
mt7615_mcu_rx_unsolicited_event(struct mt7615_dev * dev,struct sk_buff * skb)539 mt7615_mcu_rx_unsolicited_event(struct mt7615_dev *dev, struct sk_buff *skb)
540 {
541 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
542
543 switch (rxd->eid) {
544 case MCU_EVENT_EXT:
545 mt7615_mcu_rx_ext_event(dev, skb);
546 break;
547 case MCU_EVENT_BSS_BEACON_LOSS:
548 mt7615_mcu_beacon_loss_event(dev, skb);
549 break;
550 case MCU_EVENT_ROC:
551 mt7615_mcu_roc_event(dev, skb);
552 break;
553 case MCU_EVENT_SCHED_SCAN_DONE:
554 case MCU_EVENT_SCAN_DONE:
555 mt7615_mcu_scan_event(dev, skb);
556 return;
557 case MCU_EVENT_BSS_ABSENCE:
558 mt7615_mcu_bss_event(dev, skb);
559 break;
560 case MCU_EVENT_COREDUMP:
561 mt76_connac_mcu_coredump_event(&dev->mt76, skb,
562 &dev->coredump);
563 return;
564 default:
565 break;
566 }
567 dev_kfree_skb(skb);
568 }
569
mt7615_mcu_rx_event(struct mt7615_dev * dev,struct sk_buff * skb)570 void mt7615_mcu_rx_event(struct mt7615_dev *dev, struct sk_buff *skb)
571 {
572 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
573
574 if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT ||
575 rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST ||
576 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP ||
577 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC ||
578 rxd->eid == MCU_EVENT_BSS_BEACON_LOSS ||
579 rxd->eid == MCU_EVENT_SCHED_SCAN_DONE ||
580 rxd->eid == MCU_EVENT_BSS_ABSENCE ||
581 rxd->eid == MCU_EVENT_SCAN_DONE ||
582 rxd->eid == MCU_EVENT_COREDUMP ||
583 rxd->eid == MCU_EVENT_ROC ||
584 !rxd->seq)
585 mt7615_mcu_rx_unsolicited_event(dev, skb);
586 else
587 mt76_mcu_rx_event(&dev->mt76, skb);
588 }
589
590 static int
mt7615_mcu_muar_config(struct mt7615_dev * dev,struct ieee80211_vif * vif,bool bssid,bool enable)591 mt7615_mcu_muar_config(struct mt7615_dev *dev, struct ieee80211_vif *vif,
592 bool bssid, bool enable)
593 {
594 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
595 u32 idx = mvif->mt76.omac_idx - REPEATER_BSSID_START;
596 u32 mask = dev->omac_mask >> 32 & ~BIT(idx);
597 const u8 *addr = vif->addr;
598 struct {
599 u8 mode;
600 u8 force_clear;
601 u8 clear_bitmap[8];
602 u8 entry_count;
603 u8 write;
604
605 u8 index;
606 u8 bssid;
607 u8 addr[ETH_ALEN];
608 } __packed req = {
609 .mode = !!mask || enable,
610 .entry_count = 1,
611 .write = 1,
612
613 .index = idx * 2 + bssid,
614 };
615
616 if (bssid)
617 addr = vif->bss_conf.bssid;
618
619 if (enable)
620 ether_addr_copy(req.addr, addr);
621
622 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MUAR_UPDATE),
623 &req, sizeof(req), true);
624 }
625
626 static int
mt7615_mcu_add_dev(struct mt7615_phy * phy,struct ieee80211_vif * vif,bool enable)627 mt7615_mcu_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif,
628 bool enable)
629 {
630 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
631 struct mt7615_dev *dev = phy->dev;
632 struct {
633 struct req_hdr {
634 u8 omac_idx;
635 u8 band_idx;
636 __le16 tlv_num;
637 u8 is_tlv_append;
638 u8 rsv[3];
639 } __packed hdr;
640 struct req_tlv {
641 __le16 tag;
642 __le16 len;
643 u8 active;
644 u8 band_idx;
645 u8 omac_addr[ETH_ALEN];
646 } __packed tlv;
647 } data = {
648 .hdr = {
649 .omac_idx = mvif->mt76.omac_idx,
650 .band_idx = mvif->mt76.band_idx,
651 .tlv_num = cpu_to_le16(1),
652 .is_tlv_append = 1,
653 },
654 .tlv = {
655 .tag = cpu_to_le16(DEV_INFO_ACTIVE),
656 .len = cpu_to_le16(sizeof(struct req_tlv)),
657 .active = enable,
658 .band_idx = mvif->mt76.band_idx,
659 },
660 };
661
662 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START)
663 return mt7615_mcu_muar_config(dev, vif, false, enable);
664
665 memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN);
666 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DEV_INFO_UPDATE),
667 &data, sizeof(data), true);
668 }
669
670 static int
mt7615_mcu_add_beacon_offload(struct mt7615_dev * dev,struct ieee80211_hw * hw,struct ieee80211_vif * vif,bool enable)671 mt7615_mcu_add_beacon_offload(struct mt7615_dev *dev,
672 struct ieee80211_hw *hw,
673 struct ieee80211_vif *vif, bool enable)
674 {
675 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
676 struct mt76_wcid *wcid = &dev->mt76.global_wcid;
677 struct ieee80211_mutable_offsets offs;
678 struct ieee80211_tx_info *info;
679 struct req {
680 u8 omac_idx;
681 u8 enable;
682 u8 wlan_idx;
683 u8 band_idx;
684 u8 pkt_type;
685 u8 need_pre_tbtt_int;
686 __le16 csa_ie_pos;
687 __le16 pkt_len;
688 __le16 tim_ie_pos;
689 u8 pkt[512];
690 u8 csa_cnt;
691 /* bss color change */
692 u8 bcc_cnt;
693 __le16 bcc_ie_pos;
694 } __packed req = {
695 .omac_idx = mvif->mt76.omac_idx,
696 .enable = enable,
697 .wlan_idx = wcid->idx,
698 .band_idx = mvif->mt76.band_idx,
699 };
700 struct sk_buff *skb;
701
702 if (!enable)
703 goto out;
704
705 skb = ieee80211_beacon_get_template(hw, vif, &offs, 0);
706 if (!skb)
707 return -EINVAL;
708
709 if (skb->len > 512 - MT_TXD_SIZE) {
710 dev_err(dev->mt76.dev, "Bcn size limit exceed\n");
711 dev_kfree_skb(skb);
712 return -EINVAL;
713 }
714
715 info = IEEE80211_SKB_CB(skb);
716 info->hw_queue |= FIELD_PREP(MT_TX_HW_QUEUE_PHY, mvif->mt76.band_idx);
717
718 mt7615_mac_write_txwi(dev, (__le32 *)(req.pkt), skb, wcid, NULL,
719 0, NULL, 0, true);
720 memcpy(req.pkt + MT_TXD_SIZE, skb->data, skb->len);
721 req.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len);
722 req.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset);
723 if (offs.cntdwn_counter_offs[0]) {
724 u16 csa_offs;
725
726 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4;
727 req.csa_ie_pos = cpu_to_le16(csa_offs);
728 req.csa_cnt = skb->data[offs.cntdwn_counter_offs[0]];
729 }
730 dev_kfree_skb(skb);
731
732 out:
733 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(BCN_OFFLOAD), &req,
734 sizeof(req), true);
735 }
736
737 static int
mt7615_mcu_ctrl_pm_state(struct mt7615_dev * dev,int band,int state)738 mt7615_mcu_ctrl_pm_state(struct mt7615_dev *dev, int band, int state)
739 {
740 return mt76_connac_mcu_set_pm(&dev->mt76, band, state);
741 }
742
743 static int
mt7615_mcu_add_bss(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)744 mt7615_mcu_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif,
745 struct ieee80211_sta *sta, bool enable)
746 {
747 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
748 struct mt7615_dev *dev = phy->dev;
749 struct sk_buff *skb;
750
751 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START)
752 mt7615_mcu_muar_config(dev, vif, true, enable);
753
754 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, NULL);
755 if (IS_ERR(skb))
756 return PTR_ERR(skb);
757
758 if (enable)
759 mt76_connac_mcu_bss_omac_tlv(skb, vif);
760
761 mt76_connac_mcu_bss_basic_tlv(skb, vif, sta, phy->mt76,
762 mvif->sta.wcid.idx, enable);
763
764 if (enable && mvif->mt76.omac_idx >= EXT_BSSID_START &&
765 mvif->mt76.omac_idx < REPEATER_BSSID_START)
766 mt76_connac_mcu_bss_ext_tlv(skb, &mvif->mt76);
767
768 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
769 MCU_EXT_CMD(BSS_INFO_UPDATE), true);
770 }
771
772 static int
mt7615_mcu_wtbl_tx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)773 mt7615_mcu_wtbl_tx_ba(struct mt7615_dev *dev,
774 struct ieee80211_ampdu_params *params,
775 bool enable)
776 {
777 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
778 struct mt7615_vif *mvif = msta->vif;
779 struct wtbl_req_hdr *wtbl_hdr;
780 struct sk_buff *skb = NULL;
781 int err;
782
783 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
784 WTBL_SET, NULL, &skb);
785 if (IS_ERR(wtbl_hdr))
786 return PTR_ERR(wtbl_hdr);
787
788 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, true,
789 NULL, wtbl_hdr);
790
791 err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
792 MCU_EXT_CMD(WTBL_UPDATE), true);
793 if (err < 0)
794 return err;
795
796 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
797 &msta->wcid);
798 if (IS_ERR(skb))
799 return PTR_ERR(skb);
800
801 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, true);
802
803 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
804 MCU_EXT_CMD(STA_REC_UPDATE), true);
805 }
806
807 static int
mt7615_mcu_wtbl_rx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)808 mt7615_mcu_wtbl_rx_ba(struct mt7615_dev *dev,
809 struct ieee80211_ampdu_params *params,
810 bool enable)
811 {
812 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
813 struct mt7615_vif *mvif = msta->vif;
814 struct wtbl_req_hdr *wtbl_hdr;
815 struct sk_buff *skb;
816 int err;
817
818 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
819 &msta->wcid);
820 if (IS_ERR(skb))
821 return PTR_ERR(skb);
822
823 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false);
824
825 err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
826 MCU_EXT_CMD(STA_REC_UPDATE), true);
827 if (err < 0 || !enable)
828 return err;
829
830 skb = NULL;
831 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
832 WTBL_SET, NULL, &skb);
833 if (IS_ERR(wtbl_hdr))
834 return PTR_ERR(wtbl_hdr);
835
836 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false,
837 NULL, wtbl_hdr);
838
839 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
840 MCU_EXT_CMD(WTBL_UPDATE), true);
841 }
842
843 static int
mt7615_mcu_wtbl_sta_add(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)844 mt7615_mcu_wtbl_sta_add(struct mt7615_phy *phy, struct ieee80211_vif *vif,
845 struct ieee80211_sta *sta, bool enable)
846 {
847 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
848 struct sk_buff *skb, *sskb, *wskb = NULL;
849 struct ieee80211_link_sta *link_sta;
850 struct mt7615_dev *dev = phy->dev;
851 struct wtbl_req_hdr *wtbl_hdr;
852 struct mt7615_sta *msta;
853 bool new_entry = true;
854 int conn_state;
855 int cmd, err;
856
857 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta;
858 link_sta = sta ? &sta->deflink : NULL;
859
860 sskb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
861 &msta->wcid);
862 if (IS_ERR(sskb))
863 return PTR_ERR(sskb);
864
865 if (!sta) {
866 if (mvif->sta_added)
867 new_entry = false;
868 else
869 mvif->sta_added = true;
870 }
871 conn_state = enable ? CONN_STATE_PORT_SECURE : CONN_STATE_DISCONNECT;
872 mt76_connac_mcu_sta_basic_tlv(&dev->mt76, sskb, &vif->bss_conf,
873 link_sta, conn_state, new_entry);
874 if (enable && sta)
875 mt76_connac_mcu_sta_tlv(phy->mt76, sskb, sta, vif, 0,
876 MT76_STA_INFO_STATE_ASSOC);
877
878 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
879 WTBL_RESET_AND_SET, NULL,
880 &wskb);
881 if (IS_ERR(wtbl_hdr)) {
882 dev_kfree_skb(sskb);
883 return PTR_ERR(wtbl_hdr);
884 }
885
886 if (enable) {
887 mt76_connac_mcu_wtbl_generic_tlv(&dev->mt76, wskb, vif, sta,
888 NULL, wtbl_hdr);
889 if (sta)
890 mt76_connac_mcu_wtbl_ht_tlv(&dev->mt76, wskb, sta,
891 NULL, wtbl_hdr, true, true);
892 mt76_connac_mcu_wtbl_hdr_trans_tlv(wskb, vif, &msta->wcid,
893 NULL, wtbl_hdr);
894 }
895
896 cmd = enable ? MCU_EXT_CMD(WTBL_UPDATE) : MCU_EXT_CMD(STA_REC_UPDATE);
897 skb = enable ? wskb : sskb;
898
899 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true);
900 if (err < 0) {
901 skb = enable ? sskb : wskb;
902 dev_kfree_skb(skb);
903
904 return err;
905 }
906
907 cmd = enable ? MCU_EXT_CMD(STA_REC_UPDATE) : MCU_EXT_CMD(WTBL_UPDATE);
908 skb = enable ? sskb : wskb;
909
910 return mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true);
911 }
912
913 static int
mt7615_mcu_wtbl_update_hdr_trans(struct mt7615_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)914 mt7615_mcu_wtbl_update_hdr_trans(struct mt7615_dev *dev,
915 struct ieee80211_vif *vif,
916 struct ieee80211_sta *sta)
917 {
918 return mt76_connac_mcu_wtbl_update_hdr_trans(&dev->mt76, vif, sta);
919 }
920
921 static const struct mt7615_mcu_ops wtbl_update_ops = {
922 .add_beacon_offload = mt7615_mcu_add_beacon_offload,
923 .set_pm_state = mt7615_mcu_ctrl_pm_state,
924 .add_dev_info = mt7615_mcu_add_dev,
925 .add_bss_info = mt7615_mcu_add_bss,
926 .add_tx_ba = mt7615_mcu_wtbl_tx_ba,
927 .add_rx_ba = mt7615_mcu_wtbl_rx_ba,
928 .sta_add = mt7615_mcu_wtbl_sta_add,
929 .set_drv_ctrl = mt7615_mcu_drv_pmctrl,
930 .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
931 .set_sta_decap_offload = mt7615_mcu_wtbl_update_hdr_trans,
932 };
933
934 static int
mt7615_mcu_sta_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable,bool tx)935 mt7615_mcu_sta_ba(struct mt7615_dev *dev,
936 struct ieee80211_ampdu_params *params,
937 bool enable, bool tx)
938 {
939 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
940 struct mt7615_vif *mvif = msta->vif;
941 struct wtbl_req_hdr *wtbl_hdr;
942 struct tlv *sta_wtbl;
943 struct sk_buff *skb;
944
945 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
946 &msta->wcid);
947 if (IS_ERR(skb))
948 return PTR_ERR(skb);
949
950 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
951
952 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv));
953
954 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
955 WTBL_SET, sta_wtbl, &skb);
956 if (IS_ERR(wtbl_hdr))
957 return PTR_ERR(wtbl_hdr);
958
959 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, tx,
960 sta_wtbl, wtbl_hdr);
961
962 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
963 MCU_EXT_CMD(STA_REC_UPDATE), true);
964 }
965
966 static int
mt7615_mcu_sta_tx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)967 mt7615_mcu_sta_tx_ba(struct mt7615_dev *dev,
968 struct ieee80211_ampdu_params *params,
969 bool enable)
970 {
971 return mt7615_mcu_sta_ba(dev, params, enable, true);
972 }
973
974 static int
mt7615_mcu_sta_rx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)975 mt7615_mcu_sta_rx_ba(struct mt7615_dev *dev,
976 struct ieee80211_ampdu_params *params,
977 bool enable)
978 {
979 return mt7615_mcu_sta_ba(dev, params, enable, false);
980 }
981
982 static int
__mt7615_mcu_add_sta(struct mt76_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable,int cmd,bool offload_fw)983 __mt7615_mcu_add_sta(struct mt76_phy *phy, struct ieee80211_vif *vif,
984 struct ieee80211_sta *sta, bool enable, int cmd,
985 bool offload_fw)
986 {
987 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
988 struct mt76_sta_cmd_info info = {
989 .sta = sta,
990 .vif = vif,
991 .offload_fw = offload_fw,
992 .enable = enable,
993 .newly = true,
994 .cmd = cmd,
995 };
996
997 info.wcid = sta ? (struct mt76_wcid *)sta->drv_priv : &mvif->sta.wcid;
998 return mt76_connac_mcu_sta_cmd(phy, &info);
999 }
1000
1001 static int
mt7615_mcu_add_sta(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)1002 mt7615_mcu_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1003 struct ieee80211_sta *sta, bool enable)
1004 {
1005 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable,
1006 MCU_EXT_CMD(STA_REC_UPDATE), false);
1007 }
1008
1009 static int
mt7615_mcu_sta_update_hdr_trans(struct mt7615_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1010 mt7615_mcu_sta_update_hdr_trans(struct mt7615_dev *dev,
1011 struct ieee80211_vif *vif,
1012 struct ieee80211_sta *sta)
1013 {
1014 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
1015
1016 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76,
1017 vif, &msta->wcid,
1018 MCU_EXT_CMD(STA_REC_UPDATE));
1019 }
1020
1021 static const struct mt7615_mcu_ops sta_update_ops = {
1022 .add_beacon_offload = mt7615_mcu_add_beacon_offload,
1023 .set_pm_state = mt7615_mcu_ctrl_pm_state,
1024 .add_dev_info = mt7615_mcu_add_dev,
1025 .add_bss_info = mt7615_mcu_add_bss,
1026 .add_tx_ba = mt7615_mcu_sta_tx_ba,
1027 .add_rx_ba = mt7615_mcu_sta_rx_ba,
1028 .sta_add = mt7615_mcu_add_sta,
1029 .set_drv_ctrl = mt7615_mcu_drv_pmctrl,
1030 .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
1031 .set_sta_decap_offload = mt7615_mcu_sta_update_hdr_trans,
1032 };
1033
1034 static int
mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev * dev,int band,int state)1035 mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev *dev, int band, int state)
1036 {
1037 return 0;
1038 }
1039
1040 static int
mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev * dev,struct ieee80211_hw * hw,struct ieee80211_vif * vif,bool enable)1041 mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev *dev,
1042 struct ieee80211_hw *hw,
1043 struct ieee80211_vif *vif,
1044 bool enable)
1045 {
1046 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1047 struct mt76_wcid *wcid = &dev->mt76.global_wcid;
1048 struct ieee80211_mutable_offsets offs;
1049 struct {
1050 struct req_hdr {
1051 u8 bss_idx;
1052 u8 pad[3];
1053 } __packed hdr;
1054 struct bcn_content_tlv {
1055 __le16 tag;
1056 __le16 len;
1057 __le16 tim_ie_pos;
1058 __le16 csa_ie_pos;
1059 __le16 bcc_ie_pos;
1060 /* 0: disable beacon offload
1061 * 1: enable beacon offload
1062 * 2: update probe respond offload
1063 */
1064 u8 enable;
1065 /* 0: legacy format (TXD + payload)
1066 * 1: only cap field IE
1067 */
1068 u8 type;
1069 __le16 pkt_len;
1070 u8 pkt[512];
1071 } __packed beacon_tlv;
1072 } req = {
1073 .hdr = {
1074 .bss_idx = mvif->mt76.idx,
1075 },
1076 .beacon_tlv = {
1077 .tag = cpu_to_le16(UNI_BSS_INFO_BCN_CONTENT),
1078 .len = cpu_to_le16(sizeof(struct bcn_content_tlv)),
1079 .enable = enable,
1080 },
1081 };
1082 struct sk_buff *skb;
1083
1084 if (!enable)
1085 goto out;
1086
1087 skb = ieee80211_beacon_get_template(mt76_hw(dev), vif, &offs, 0);
1088 if (!skb)
1089 return -EINVAL;
1090
1091 if (skb->len > 512 - MT_TXD_SIZE) {
1092 dev_err(dev->mt76.dev, "beacon size limit exceed\n");
1093 dev_kfree_skb(skb);
1094 return -EINVAL;
1095 }
1096
1097 mt7615_mac_write_txwi(dev, (__le32 *)(req.beacon_tlv.pkt), skb,
1098 wcid, NULL, 0, NULL, 0, true);
1099 memcpy(req.beacon_tlv.pkt + MT_TXD_SIZE, skb->data, skb->len);
1100 req.beacon_tlv.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len);
1101 req.beacon_tlv.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset);
1102
1103 if (offs.cntdwn_counter_offs[0]) {
1104 u16 csa_offs;
1105
1106 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4;
1107 req.beacon_tlv.csa_ie_pos = cpu_to_le16(csa_offs);
1108 }
1109 dev_kfree_skb(skb);
1110
1111 out:
1112 return mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD(BSS_INFO_UPDATE),
1113 &req, sizeof(req), true);
1114 }
1115
1116 static int
mt7615_mcu_uni_add_dev(struct mt7615_phy * phy,struct ieee80211_vif * vif,bool enable)1117 mt7615_mcu_uni_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1118 bool enable)
1119 {
1120 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1121
1122 return mt76_connac_mcu_uni_add_dev(phy->mt76, &vif->bss_conf, &mvif->mt76,
1123 &mvif->sta.wcid, enable);
1124 }
1125
1126 static int
mt7615_mcu_uni_add_bss(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)1127 mt7615_mcu_uni_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1128 struct ieee80211_sta *sta, bool enable)
1129 {
1130 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1131
1132 return mt76_connac_mcu_uni_add_bss(phy->mt76, vif, &mvif->sta.wcid,
1133 enable, NULL);
1134 }
1135
1136 static inline int
mt7615_mcu_uni_add_sta(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)1137 mt7615_mcu_uni_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1138 struct ieee80211_sta *sta, bool enable)
1139 {
1140 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable,
1141 MCU_UNI_CMD(STA_REC_UPDATE), true);
1142 }
1143
1144 static int
mt7615_mcu_uni_tx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)1145 mt7615_mcu_uni_tx_ba(struct mt7615_dev *dev,
1146 struct ieee80211_ampdu_params *params,
1147 bool enable)
1148 {
1149 struct mt7615_sta *sta = (struct mt7615_sta *)params->sta->drv_priv;
1150
1151 return mt76_connac_mcu_sta_ba(&dev->mt76, &sta->vif->mt76, params,
1152 MCU_UNI_CMD(STA_REC_UPDATE), enable,
1153 true);
1154 }
1155
1156 static int
mt7615_mcu_uni_rx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)1157 mt7615_mcu_uni_rx_ba(struct mt7615_dev *dev,
1158 struct ieee80211_ampdu_params *params,
1159 bool enable)
1160 {
1161 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
1162 struct mt7615_vif *mvif = msta->vif;
1163 struct wtbl_req_hdr *wtbl_hdr;
1164 struct tlv *sta_wtbl;
1165 struct sk_buff *skb;
1166 int err;
1167
1168 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
1169 &msta->wcid);
1170 if (IS_ERR(skb))
1171 return PTR_ERR(skb);
1172
1173 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false);
1174
1175 err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
1176 MCU_UNI_CMD(STA_REC_UPDATE), true);
1177 if (err < 0 || !enable)
1178 return err;
1179
1180 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
1181 &msta->wcid);
1182 if (IS_ERR(skb))
1183 return PTR_ERR(skb);
1184
1185 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL,
1186 sizeof(struct tlv));
1187
1188 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
1189 WTBL_SET, sta_wtbl, &skb);
1190 if (IS_ERR(wtbl_hdr))
1191 return PTR_ERR(wtbl_hdr);
1192
1193 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false,
1194 sta_wtbl, wtbl_hdr);
1195
1196 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
1197 MCU_UNI_CMD(STA_REC_UPDATE), true);
1198 }
1199
1200 static int
mt7615_mcu_sta_uni_update_hdr_trans(struct mt7615_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1201 mt7615_mcu_sta_uni_update_hdr_trans(struct mt7615_dev *dev,
1202 struct ieee80211_vif *vif,
1203 struct ieee80211_sta *sta)
1204 {
1205 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
1206
1207 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76,
1208 vif, &msta->wcid,
1209 MCU_UNI_CMD(STA_REC_UPDATE));
1210 }
1211
1212 static const struct mt7615_mcu_ops uni_update_ops = {
1213 .add_beacon_offload = mt7615_mcu_uni_add_beacon_offload,
1214 .set_pm_state = mt7615_mcu_uni_ctrl_pm_state,
1215 .add_dev_info = mt7615_mcu_uni_add_dev,
1216 .add_bss_info = mt7615_mcu_uni_add_bss,
1217 .add_tx_ba = mt7615_mcu_uni_tx_ba,
1218 .add_rx_ba = mt7615_mcu_uni_rx_ba,
1219 .sta_add = mt7615_mcu_uni_add_sta,
1220 .set_drv_ctrl = mt7615_mcu_lp_drv_pmctrl,
1221 .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
1222 .set_sta_decap_offload = mt7615_mcu_sta_uni_update_hdr_trans,
1223 };
1224
mt7615_mcu_restart(struct mt76_dev * dev)1225 int mt7615_mcu_restart(struct mt76_dev *dev)
1226 {
1227 return mt76_mcu_send_msg(dev, MCU_CMD(RESTART_DL_REQ), NULL, 0, true);
1228 }
1229 EXPORT_SYMBOL_GPL(mt7615_mcu_restart);
1230
mt7615_load_patch(struct mt7615_dev * dev,u32 addr,const char * name)1231 static int mt7615_load_patch(struct mt7615_dev *dev, u32 addr, const char *name)
1232 {
1233 const struct mt7615_patch_hdr *hdr;
1234 const struct firmware *fw = NULL;
1235 int len, ret, sem;
1236
1237 ret = firmware_request_nowarn(&fw, name, dev->mt76.dev);
1238 if (ret)
1239 return ret;
1240
1241 if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
1242 dev_err(dev->mt76.dev, "Invalid firmware\n");
1243 ret = -EINVAL;
1244 goto release_fw;
1245 }
1246
1247 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, true);
1248 switch (sem) {
1249 case PATCH_IS_DL:
1250 goto release_fw;
1251 case PATCH_NOT_DL_SEM_SUCCESS:
1252 break;
1253 default:
1254 dev_err(dev->mt76.dev, "Failed to get patch semaphore\n");
1255 ret = -EAGAIN;
1256 goto release_fw;
1257 }
1258
1259 hdr = (const struct mt7615_patch_hdr *)(fw->data);
1260
1261 dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n",
1262 be32_to_cpu(hdr->hw_sw_ver), hdr->build_date);
1263
1264 len = fw->size - sizeof(*hdr);
1265
1266 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1267 DL_MODE_NEED_RSP);
1268 if (ret) {
1269 dev_err(dev->mt76.dev, "Download request failed\n");
1270 goto out;
1271 }
1272
1273 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1274 fw->data + sizeof(*hdr), len);
1275 if (ret) {
1276 dev_err(dev->mt76.dev, "Failed to send firmware to device\n");
1277 goto out;
1278 }
1279
1280 ret = mt76_connac_mcu_start_patch(&dev->mt76);
1281 if (ret)
1282 dev_err(dev->mt76.dev, "Failed to start patch\n");
1283
1284 out:
1285 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, false);
1286 switch (sem) {
1287 case PATCH_REL_SEM_SUCCESS:
1288 break;
1289 default:
1290 ret = -EAGAIN;
1291 dev_err(dev->mt76.dev, "Failed to release patch semaphore\n");
1292 break;
1293 }
1294
1295 release_fw:
1296 release_firmware(fw);
1297
1298 return ret;
1299 }
1300
1301 static int
mt7615_mcu_send_ram_firmware(struct mt7615_dev * dev,const struct mt7615_fw_trailer * hdr,const u8 * data,bool is_cr4)1302 mt7615_mcu_send_ram_firmware(struct mt7615_dev *dev,
1303 const struct mt7615_fw_trailer *hdr,
1304 const u8 *data, bool is_cr4)
1305 {
1306 int n_region = is_cr4 ? CR4_REGION_NUM : N9_REGION_NUM;
1307 int err, i, offset = 0;
1308 u32 len, addr, mode;
1309
1310 for (i = 0; i < n_region; i++) {
1311 mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76,
1312 hdr[i].feature_set, is_cr4);
1313 len = le32_to_cpu(hdr[i].len) + IMG_CRC_LEN;
1314 addr = le32_to_cpu(hdr[i].addr);
1315
1316 err = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1317 mode);
1318 if (err) {
1319 dev_err(dev->mt76.dev, "Download request failed\n");
1320 return err;
1321 }
1322
1323 err = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1324 data + offset, len);
1325 if (err) {
1326 dev_err(dev->mt76.dev, "Failed to send firmware to device\n");
1327 return err;
1328 }
1329
1330 offset += len;
1331 }
1332
1333 return 0;
1334 }
1335
mt7615_load_n9(struct mt7615_dev * dev,const char * name)1336 static int mt7615_load_n9(struct mt7615_dev *dev, const char *name)
1337 {
1338 const struct mt7615_fw_trailer *hdr;
1339 const struct firmware *fw;
1340 int ret;
1341
1342 ret = request_firmware(&fw, name, dev->mt76.dev);
1343 if (ret)
1344 return ret;
1345
1346 if (!fw || !fw->data || fw->size < N9_REGION_NUM * sizeof(*hdr)) {
1347 dev_err(dev->mt76.dev, "Invalid firmware\n");
1348 ret = -EINVAL;
1349 goto out;
1350 }
1351
1352 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size -
1353 N9_REGION_NUM * sizeof(*hdr));
1354
1355 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n",
1356 hdr->fw_ver, hdr->build_date);
1357
1358 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, false);
1359 if (ret)
1360 goto out;
1361
1362 ret = mt76_connac_mcu_start_firmware(&dev->mt76,
1363 le32_to_cpu(hdr->addr),
1364 FW_START_OVERRIDE);
1365 if (ret) {
1366 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n");
1367 goto out;
1368 }
1369
1370 snprintf(dev->mt76.hw->wiphy->fw_version,
1371 sizeof(dev->mt76.hw->wiphy->fw_version),
1372 "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
1373
1374 if (!is_mt7615(&dev->mt76)) {
1375 dev->fw_ver = MT7615_FIRMWARE_V2;
1376 dev->mcu_ops = &sta_update_ops;
1377 } else {
1378 dev->fw_ver = MT7615_FIRMWARE_V1;
1379 dev->mcu_ops = &wtbl_update_ops;
1380 }
1381
1382 out:
1383 release_firmware(fw);
1384 return ret;
1385 }
1386
mt7615_load_cr4(struct mt7615_dev * dev,const char * name)1387 static int mt7615_load_cr4(struct mt7615_dev *dev, const char *name)
1388 {
1389 const struct mt7615_fw_trailer *hdr;
1390 const struct firmware *fw;
1391 int ret;
1392
1393 ret = request_firmware(&fw, name, dev->mt76.dev);
1394 if (ret)
1395 return ret;
1396
1397 if (!fw || !fw->data || fw->size < CR4_REGION_NUM * sizeof(*hdr)) {
1398 dev_err(dev->mt76.dev, "Invalid firmware\n");
1399 ret = -EINVAL;
1400 goto out;
1401 }
1402
1403 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size -
1404 CR4_REGION_NUM * sizeof(*hdr));
1405
1406 dev_info(dev->mt76.dev, "CR4 Firmware Version: %.10s, Build Time: %.15s\n",
1407 hdr->fw_ver, hdr->build_date);
1408
1409 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, true);
1410 if (ret)
1411 goto out;
1412
1413 ret = mt76_connac_mcu_start_firmware(&dev->mt76, 0,
1414 FW_START_WORKING_PDA_CR4);
1415 if (ret) {
1416 dev_err(dev->mt76.dev, "Failed to start CR4 firmware\n");
1417 goto out;
1418 }
1419
1420 out:
1421 release_firmware(fw);
1422
1423 return ret;
1424 }
1425
mt7615_load_ram(struct mt7615_dev * dev)1426 static int mt7615_load_ram(struct mt7615_dev *dev)
1427 {
1428 int ret;
1429
1430 ret = mt7615_load_n9(dev, MT7615_FIRMWARE_N9);
1431 if (ret)
1432 return ret;
1433
1434 return mt7615_load_cr4(dev, MT7615_FIRMWARE_CR4);
1435 }
1436
mt7615_load_firmware(struct mt7615_dev * dev)1437 static int mt7615_load_firmware(struct mt7615_dev *dev)
1438 {
1439 int ret;
1440 u32 val;
1441
1442 val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE);
1443
1444 if (val != FW_STATE_FW_DOWNLOAD) {
1445 dev_err(dev->mt76.dev, "Firmware is not ready for download\n");
1446 return -EIO;
1447 }
1448
1449 ret = mt7615_load_patch(dev, MT7615_PATCH_ADDRESS, MT7615_ROM_PATCH);
1450 if (ret)
1451 return ret;
1452
1453 ret = mt7615_load_ram(dev);
1454 if (ret)
1455 return ret;
1456
1457 if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE,
1458 FIELD_PREP(MT_TOP_MISC2_FW_STATE,
1459 FW_STATE_RDY), 500)) {
1460 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1461 return -EIO;
1462 }
1463
1464 return 0;
1465 }
1466
mt7622_load_firmware(struct mt7615_dev * dev)1467 static int mt7622_load_firmware(struct mt7615_dev *dev)
1468 {
1469 int ret;
1470 u32 val;
1471
1472 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1473
1474 val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE);
1475 if (val != FW_STATE_FW_DOWNLOAD) {
1476 dev_err(dev->mt76.dev, "Firmware is not ready for download\n");
1477 return -EIO;
1478 }
1479
1480 ret = mt7615_load_patch(dev, MT7622_PATCH_ADDRESS, MT7622_ROM_PATCH);
1481 if (ret)
1482 return ret;
1483
1484 ret = mt7615_load_n9(dev, MT7622_FIRMWARE_N9);
1485 if (ret)
1486 return ret;
1487
1488 if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE,
1489 FIELD_PREP(MT_TOP_OFF_RSV_FW_STATE,
1490 FW_STATE_NORMAL_TRX), 1500)) {
1491 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1492 return -EIO;
1493 }
1494
1495 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1496
1497 return 0;
1498 }
1499
mt7615_mcu_fw_log_2_host(struct mt7615_dev * dev,u8 ctrl)1500 int mt7615_mcu_fw_log_2_host(struct mt7615_dev *dev, u8 ctrl)
1501 {
1502 struct {
1503 u8 ctrl_val;
1504 u8 pad[3];
1505 } data = {
1506 .ctrl_val = ctrl
1507 };
1508
1509 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(FW_LOG_2_HOST),
1510 &data, sizeof(data), true);
1511 }
1512
mt7615_mcu_cal_cache_apply(struct mt7615_dev * dev)1513 static int mt7615_mcu_cal_cache_apply(struct mt7615_dev *dev)
1514 {
1515 struct {
1516 bool cache_enable;
1517 u8 pad[3];
1518 } data = {
1519 .cache_enable = true
1520 };
1521
1522 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CAL_CACHE), &data,
1523 sizeof(data), false);
1524 }
1525
mt7663_load_n9(struct mt7615_dev * dev,const char * name)1526 static int mt7663_load_n9(struct mt7615_dev *dev, const char *name)
1527 {
1528 u32 offset = 0, override_addr = 0, flag = FW_START_DLYCAL;
1529 const struct mt76_connac2_fw_trailer *hdr;
1530 const struct mt7663_fw_buf *buf;
1531 const struct firmware *fw;
1532 const u8 *base_addr;
1533 int i, ret;
1534
1535 ret = request_firmware(&fw, name, dev->mt76.dev);
1536 if (ret)
1537 return ret;
1538
1539 if (!fw || !fw->data || fw->size < FW_V3_COMMON_TAILER_SIZE) {
1540 dev_err(dev->mt76.dev, "Invalid firmware\n");
1541 ret = -EINVAL;
1542 goto out;
1543 }
1544
1545 hdr = (const void *)(fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE);
1546 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n",
1547 hdr->fw_ver, hdr->build_date);
1548 dev_info(dev->mt76.dev, "Region number: 0x%x\n", hdr->n_region);
1549
1550 base_addr = fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE;
1551 for (i = 0; i < hdr->n_region; i++) {
1552 u32 shift = (hdr->n_region - i) * FW_V3_REGION_TAILER_SIZE;
1553 u32 len, addr, mode;
1554
1555 dev_info(dev->mt76.dev, "Parsing tailer Region: %d\n", i);
1556
1557 buf = (const struct mt7663_fw_buf *)(base_addr - shift);
1558 mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76,
1559 buf->feature_set, false);
1560 addr = le32_to_cpu(buf->img_dest_addr);
1561 len = le32_to_cpu(buf->img_size);
1562
1563 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1564 mode);
1565 if (ret) {
1566 dev_err(dev->mt76.dev, "Download request failed\n");
1567 goto out;
1568 }
1569
1570 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1571 fw->data + offset, len);
1572 if (ret) {
1573 dev_err(dev->mt76.dev, "Failed to send firmware\n");
1574 goto out;
1575 }
1576
1577 offset += le32_to_cpu(buf->img_size);
1578 if (buf->feature_set & DL_MODE_VALID_RAM_ENTRY) {
1579 override_addr = le32_to_cpu(buf->img_dest_addr);
1580 dev_info(dev->mt76.dev, "Region %d, override_addr = 0x%08x\n",
1581 i, override_addr);
1582 }
1583 }
1584
1585 if (override_addr)
1586 flag |= FW_START_OVERRIDE;
1587
1588 dev_info(dev->mt76.dev, "override_addr = 0x%08x, option = %d\n",
1589 override_addr, flag);
1590
1591 ret = mt76_connac_mcu_start_firmware(&dev->mt76, override_addr, flag);
1592 if (ret) {
1593 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n");
1594 goto out;
1595 }
1596
1597 snprintf(dev->mt76.hw->wiphy->fw_version,
1598 sizeof(dev->mt76.hw->wiphy->fw_version),
1599 "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
1600
1601 out:
1602 release_firmware(fw);
1603
1604 return ret;
1605 }
1606
1607 static int
mt7663_load_rom_patch(struct mt7615_dev * dev,const char ** n9_firmware)1608 mt7663_load_rom_patch(struct mt7615_dev *dev, const char **n9_firmware)
1609 {
1610 const char *selected_rom, *secondary_rom = MT7663_ROM_PATCH;
1611 const char *primary_rom = MT7663_OFFLOAD_ROM_PATCH;
1612 int ret;
1613
1614 if (!prefer_offload_fw) {
1615 secondary_rom = MT7663_OFFLOAD_ROM_PATCH;
1616 primary_rom = MT7663_ROM_PATCH;
1617 }
1618 selected_rom = primary_rom;
1619
1620 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, primary_rom);
1621 if (ret) {
1622 dev_info(dev->mt76.dev, "%s not found, switching to %s",
1623 primary_rom, secondary_rom);
1624 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS,
1625 secondary_rom);
1626 if (ret) {
1627 dev_err(dev->mt76.dev, "failed to load %s",
1628 secondary_rom);
1629 return ret;
1630 }
1631 selected_rom = secondary_rom;
1632 }
1633
1634 if (!strcmp(selected_rom, MT7663_OFFLOAD_ROM_PATCH)) {
1635 *n9_firmware = MT7663_OFFLOAD_FIRMWARE_N9;
1636 dev->fw_ver = MT7615_FIRMWARE_V3;
1637 dev->mcu_ops = &uni_update_ops;
1638 } else {
1639 *n9_firmware = MT7663_FIRMWARE_N9;
1640 dev->fw_ver = MT7615_FIRMWARE_V2;
1641 dev->mcu_ops = &sta_update_ops;
1642 }
1643
1644 return 0;
1645 }
1646
__mt7663_load_firmware(struct mt7615_dev * dev)1647 int __mt7663_load_firmware(struct mt7615_dev *dev)
1648 {
1649 const char *n9_firmware;
1650 int ret;
1651
1652 ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY);
1653 if (ret) {
1654 dev_dbg(dev->mt76.dev, "Firmware is already download\n");
1655 return -EIO;
1656 }
1657
1658 ret = mt7663_load_rom_patch(dev, &n9_firmware);
1659 if (ret)
1660 return ret;
1661
1662 ret = mt7663_load_n9(dev, n9_firmware);
1663 if (ret)
1664 return ret;
1665
1666 if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY,
1667 MT_TOP_MISC2_FW_N9_RDY, 1500)) {
1668 ret = mt76_get_field(dev, MT_CONN_ON_MISC,
1669 MT7663_TOP_MISC2_FW_STATE);
1670 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1671 return -EIO;
1672 }
1673
1674 #ifdef CONFIG_PM
1675 if (mt7615_firmware_offload(dev))
1676 dev->mt76.hw->wiphy->wowlan = &mt76_connac_wowlan_support;
1677 #endif /* CONFIG_PM */
1678
1679 dev_dbg(dev->mt76.dev, "Firmware init done\n");
1680
1681 return 0;
1682 }
1683 EXPORT_SYMBOL_GPL(__mt7663_load_firmware);
1684
mt7663_load_firmware(struct mt7615_dev * dev)1685 static int mt7663_load_firmware(struct mt7615_dev *dev)
1686 {
1687 int ret;
1688
1689 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1690
1691 ret = __mt7663_load_firmware(dev);
1692 if (ret)
1693 return ret;
1694
1695 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1696
1697 return 0;
1698 }
1699
mt7615_mcu_init(struct mt7615_dev * dev)1700 int mt7615_mcu_init(struct mt7615_dev *dev)
1701 {
1702 static const struct mt76_mcu_ops mt7615_mcu_ops = {
1703 .headroom = sizeof(struct mt7615_mcu_txd),
1704 .mcu_skb_send_msg = mt7615_mcu_send_message,
1705 .mcu_parse_response = mt7615_mcu_parse_response,
1706 };
1707 int ret;
1708
1709 dev->mt76.mcu_ops = &mt7615_mcu_ops;
1710
1711 ret = mt7615_mcu_drv_pmctrl(dev);
1712 if (ret)
1713 return ret;
1714
1715 switch (mt76_chip(&dev->mt76)) {
1716 case 0x7622:
1717 ret = mt7622_load_firmware(dev);
1718 break;
1719 case 0x7663:
1720 ret = mt7663_load_firmware(dev);
1721 break;
1722 default:
1723 ret = mt7615_load_firmware(dev);
1724 break;
1725 }
1726 if (ret)
1727 return ret;
1728
1729 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_FWDL], false);
1730 dev_dbg(dev->mt76.dev, "Firmware init done\n");
1731 set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
1732
1733 if (dev->dbdc_support) {
1734 ret = mt7615_mcu_cal_cache_apply(dev);
1735 if (ret)
1736 return ret;
1737 }
1738
1739 return mt7615_mcu_fw_log_2_host(dev, 0);
1740 }
1741 EXPORT_SYMBOL_GPL(mt7615_mcu_init);
1742
mt7615_mcu_exit(struct mt7615_dev * dev)1743 void mt7615_mcu_exit(struct mt7615_dev *dev)
1744 {
1745 mt7615_mcu_restart(&dev->mt76);
1746 mt7615_mcu_set_fw_ctrl(dev);
1747 skb_queue_purge(&dev->mt76.mcu.res_q);
1748 }
1749 EXPORT_SYMBOL_GPL(mt7615_mcu_exit);
1750
mt7615_mcu_set_eeprom(struct mt7615_dev * dev)1751 int mt7615_mcu_set_eeprom(struct mt7615_dev *dev)
1752 {
1753 struct {
1754 u8 buffer_mode;
1755 u8 content_format;
1756 __le16 len;
1757 } __packed req_hdr = {
1758 .buffer_mode = 1,
1759 };
1760 u8 *eep = (u8 *)dev->mt76.eeprom.data;
1761 struct sk_buff *skb;
1762 int eep_len, offset;
1763
1764 switch (mt76_chip(&dev->mt76)) {
1765 case 0x7622:
1766 eep_len = MT7622_EE_MAX - MT_EE_NIC_CONF_0;
1767 offset = MT_EE_NIC_CONF_0;
1768 break;
1769 case 0x7663:
1770 eep_len = MT7663_EE_MAX - MT_EE_CHIP_ID;
1771 req_hdr.content_format = 1;
1772 offset = MT_EE_CHIP_ID;
1773 break;
1774 default:
1775 eep_len = MT7615_EE_MAX - MT_EE_NIC_CONF_0;
1776 offset = MT_EE_NIC_CONF_0;
1777 break;
1778 }
1779
1780 req_hdr.len = cpu_to_le16(eep_len);
1781
1782 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + eep_len);
1783 if (!skb)
1784 return -ENOMEM;
1785
1786 skb_put_data(skb, &req_hdr, sizeof(req_hdr));
1787 skb_put_data(skb, eep + offset, eep_len);
1788
1789 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
1790 MCU_EXT_CMD(EFUSE_BUFFER_MODE), true);
1791 }
1792
mt7615_mcu_set_wmm(struct mt7615_dev * dev,u8 queue,const struct ieee80211_tx_queue_params * params)1793 int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue,
1794 const struct ieee80211_tx_queue_params *params)
1795 {
1796 #define WMM_AIFS_SET BIT(0)
1797 #define WMM_CW_MIN_SET BIT(1)
1798 #define WMM_CW_MAX_SET BIT(2)
1799 #define WMM_TXOP_SET BIT(3)
1800 #define WMM_PARAM_SET (WMM_AIFS_SET | WMM_CW_MIN_SET | \
1801 WMM_CW_MAX_SET | WMM_TXOP_SET)
1802 struct req_data {
1803 u8 number;
1804 u8 rsv[3];
1805 u8 queue;
1806 u8 valid;
1807 u8 aifs;
1808 u8 cw_min;
1809 __le16 cw_max;
1810 __le16 txop;
1811 } __packed req = {
1812 .number = 1,
1813 .queue = queue,
1814 .valid = WMM_PARAM_SET,
1815 .aifs = params->aifs,
1816 .cw_min = 5,
1817 .cw_max = cpu_to_le16(10),
1818 .txop = cpu_to_le16(params->txop),
1819 };
1820
1821 if (params->cw_min)
1822 req.cw_min = fls(params->cw_min);
1823 if (params->cw_max)
1824 req.cw_max = cpu_to_le16(fls(params->cw_max));
1825
1826 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EDCA_UPDATE),
1827 &req, sizeof(req), true);
1828 }
1829
mt7615_mcu_set_dbdc(struct mt7615_dev * dev)1830 int mt7615_mcu_set_dbdc(struct mt7615_dev *dev)
1831 {
1832 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev);
1833 struct dbdc_entry {
1834 u8 type;
1835 u8 index;
1836 u8 band;
1837 u8 _rsv;
1838 };
1839 struct {
1840 u8 enable;
1841 u8 num;
1842 u8 _rsv[2];
1843 struct dbdc_entry entry[64];
1844 } req = {
1845 .enable = !!ext_phy,
1846 };
1847 int i;
1848
1849 if (!ext_phy)
1850 goto out;
1851
1852 #define ADD_DBDC_ENTRY(_type, _idx, _band) \
1853 do { \
1854 req.entry[req.num].type = _type; \
1855 req.entry[req.num].index = _idx; \
1856 req.entry[req.num++].band = _band; \
1857 } while (0)
1858
1859 for (i = 0; i < 4; i++) {
1860 bool band = !!(ext_phy->omac_mask & BIT_ULL(i));
1861
1862 ADD_DBDC_ENTRY(DBDC_TYPE_BSS, i, band);
1863 }
1864
1865 for (i = 0; i < 14; i++) {
1866 bool band = !!(ext_phy->omac_mask & BIT_ULL(0x11 + i));
1867
1868 ADD_DBDC_ENTRY(DBDC_TYPE_MBSS, i, band);
1869 }
1870
1871 ADD_DBDC_ENTRY(DBDC_TYPE_MU, 0, 1);
1872
1873 for (i = 0; i < 3; i++)
1874 ADD_DBDC_ENTRY(DBDC_TYPE_BF, i, 1);
1875
1876 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 0, 0);
1877 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 1, 0);
1878 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 2, 1);
1879 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 3, 1);
1880
1881 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 0, 0);
1882 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 1, 1);
1883
1884 out:
1885 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DBDC_CTRL), &req,
1886 sizeof(req), true);
1887 }
1888
mt7615_mcu_set_fcc5_lpn(struct mt7615_dev * dev,int val)1889 int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val)
1890 {
1891 struct {
1892 __le16 tag;
1893 __le16 min_lpn;
1894 } req = {
1895 .tag = cpu_to_le16(0x1),
1896 .min_lpn = cpu_to_le16(val),
1897 };
1898
1899 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1900 &req, sizeof(req), true);
1901 }
1902
mt7615_mcu_set_pulse_th(struct mt7615_dev * dev,const struct mt7615_dfs_pulse * pulse)1903 int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev,
1904 const struct mt7615_dfs_pulse *pulse)
1905 {
1906 struct {
1907 __le16 tag;
1908 __le32 max_width; /* us */
1909 __le32 max_pwr; /* dbm */
1910 __le32 min_pwr; /* dbm */
1911 __le32 min_stgr_pri; /* us */
1912 __le32 max_stgr_pri; /* us */
1913 __le32 min_cr_pri; /* us */
1914 __le32 max_cr_pri; /* us */
1915 } req = {
1916 .tag = cpu_to_le16(0x3),
1917 #define __req_field(field) .field = cpu_to_le32(pulse->field)
1918 __req_field(max_width),
1919 __req_field(max_pwr),
1920 __req_field(min_pwr),
1921 __req_field(min_stgr_pri),
1922 __req_field(max_stgr_pri),
1923 __req_field(min_cr_pri),
1924 __req_field(max_cr_pri),
1925 #undef __req_field
1926 };
1927
1928 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1929 &req, sizeof(req), true);
1930 }
1931
mt7615_mcu_set_radar_th(struct mt7615_dev * dev,int index,const struct mt7615_dfs_pattern * pattern)1932 int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index,
1933 const struct mt7615_dfs_pattern *pattern)
1934 {
1935 struct {
1936 __le16 tag;
1937 __le16 radar_type;
1938 u8 enb;
1939 u8 stgr;
1940 u8 min_crpn;
1941 u8 max_crpn;
1942 u8 min_crpr;
1943 u8 min_pw;
1944 u8 max_pw;
1945 __le32 min_pri;
1946 __le32 max_pri;
1947 u8 min_crbn;
1948 u8 max_crbn;
1949 u8 min_stgpn;
1950 u8 max_stgpn;
1951 u8 min_stgpr;
1952 } req = {
1953 .tag = cpu_to_le16(0x2),
1954 .radar_type = cpu_to_le16(index),
1955 #define __req_field_u8(field) .field = pattern->field
1956 #define __req_field_u32(field) .field = cpu_to_le32(pattern->field)
1957 __req_field_u8(enb),
1958 __req_field_u8(stgr),
1959 __req_field_u8(min_crpn),
1960 __req_field_u8(max_crpn),
1961 __req_field_u8(min_crpr),
1962 __req_field_u8(min_pw),
1963 __req_field_u8(max_pw),
1964 __req_field_u32(min_pri),
1965 __req_field_u32(max_pri),
1966 __req_field_u8(min_crbn),
1967 __req_field_u8(max_crbn),
1968 __req_field_u8(min_stgpn),
1969 __req_field_u8(max_stgpn),
1970 __req_field_u8(min_stgpr),
1971 #undef __req_field_u8
1972 #undef __req_field_u32
1973 };
1974
1975 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1976 &req, sizeof(req), true);
1977 }
1978
mt7615_mcu_rdd_send_pattern(struct mt7615_dev * dev)1979 int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev)
1980 {
1981 struct {
1982 u8 pulse_num;
1983 u8 rsv[3];
1984 struct {
1985 __le32 start_time;
1986 __le16 width;
1987 __le16 power;
1988 } pattern[32];
1989 } req = {
1990 .pulse_num = dev->radar_pattern.n_pulses,
1991 };
1992 u32 start_time = ktime_to_ms(ktime_get_boottime());
1993 int i;
1994
1995 if (dev->radar_pattern.n_pulses > ARRAY_SIZE(req.pattern))
1996 return -EINVAL;
1997
1998 /* TODO: add some noise here */
1999 for (i = 0; i < dev->radar_pattern.n_pulses; i++) {
2000 u32 ts = start_time + i * dev->radar_pattern.period;
2001
2002 req.pattern[i].width = cpu_to_le16(dev->radar_pattern.width);
2003 req.pattern[i].power = cpu_to_le16(dev->radar_pattern.power);
2004 req.pattern[i].start_time = cpu_to_le32(ts);
2005 }
2006
2007 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RDD_PATTERN),
2008 &req, sizeof(req), false);
2009 }
2010
mt7615_mcu_set_txpower_sku(struct mt7615_phy * phy,u8 * sku)2011 static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku)
2012 {
2013 struct mt76_phy *mphy = phy->mt76;
2014 struct ieee80211_hw *hw = mphy->hw;
2015 struct mt76_power_limits limits;
2016 s8 *limits_array = (s8 *)&limits;
2017 int n_chains = hweight8(mphy->antenna_mask);
2018 int tx_power = hw->conf.power_level * 2;
2019 int i;
2020 static const u8 sku_mapping[] = {
2021 #define SKU_FIELD(_type, _field) \
2022 [MT_SKU_##_type] = offsetof(struct mt76_power_limits, _field)
2023 SKU_FIELD(CCK_1_2, cck[0]),
2024 SKU_FIELD(CCK_55_11, cck[2]),
2025 SKU_FIELD(OFDM_6_9, ofdm[0]),
2026 SKU_FIELD(OFDM_12_18, ofdm[2]),
2027 SKU_FIELD(OFDM_24_36, ofdm[4]),
2028 SKU_FIELD(OFDM_48, ofdm[6]),
2029 SKU_FIELD(OFDM_54, ofdm[7]),
2030 SKU_FIELD(HT20_0_8, mcs[0][0]),
2031 SKU_FIELD(HT20_32, ofdm[0]),
2032 SKU_FIELD(HT20_1_2_9_10, mcs[0][1]),
2033 SKU_FIELD(HT20_3_4_11_12, mcs[0][3]),
2034 SKU_FIELD(HT20_5_13, mcs[0][5]),
2035 SKU_FIELD(HT20_6_14, mcs[0][6]),
2036 SKU_FIELD(HT20_7_15, mcs[0][7]),
2037 SKU_FIELD(HT40_0_8, mcs[1][0]),
2038 SKU_FIELD(HT40_32, ofdm[0]),
2039 SKU_FIELD(HT40_1_2_9_10, mcs[1][1]),
2040 SKU_FIELD(HT40_3_4_11_12, mcs[1][3]),
2041 SKU_FIELD(HT40_5_13, mcs[1][5]),
2042 SKU_FIELD(HT40_6_14, mcs[1][6]),
2043 SKU_FIELD(HT40_7_15, mcs[1][7]),
2044 SKU_FIELD(VHT20_0, mcs[0][0]),
2045 SKU_FIELD(VHT20_1_2, mcs[0][1]),
2046 SKU_FIELD(VHT20_3_4, mcs[0][3]),
2047 SKU_FIELD(VHT20_5_6, mcs[0][5]),
2048 SKU_FIELD(VHT20_7, mcs[0][7]),
2049 SKU_FIELD(VHT20_8, mcs[0][8]),
2050 SKU_FIELD(VHT20_9, mcs[0][9]),
2051 SKU_FIELD(VHT40_0, mcs[1][0]),
2052 SKU_FIELD(VHT40_1_2, mcs[1][1]),
2053 SKU_FIELD(VHT40_3_4, mcs[1][3]),
2054 SKU_FIELD(VHT40_5_6, mcs[1][5]),
2055 SKU_FIELD(VHT40_7, mcs[1][7]),
2056 SKU_FIELD(VHT40_8, mcs[1][8]),
2057 SKU_FIELD(VHT40_9, mcs[1][9]),
2058 SKU_FIELD(VHT80_0, mcs[2][0]),
2059 SKU_FIELD(VHT80_1_2, mcs[2][1]),
2060 SKU_FIELD(VHT80_3_4, mcs[2][3]),
2061 SKU_FIELD(VHT80_5_6, mcs[2][5]),
2062 SKU_FIELD(VHT80_7, mcs[2][7]),
2063 SKU_FIELD(VHT80_8, mcs[2][8]),
2064 SKU_FIELD(VHT80_9, mcs[2][9]),
2065 SKU_FIELD(VHT160_0, mcs[3][0]),
2066 SKU_FIELD(VHT160_1_2, mcs[3][1]),
2067 SKU_FIELD(VHT160_3_4, mcs[3][3]),
2068 SKU_FIELD(VHT160_5_6, mcs[3][5]),
2069 SKU_FIELD(VHT160_7, mcs[3][7]),
2070 SKU_FIELD(VHT160_8, mcs[3][8]),
2071 SKU_FIELD(VHT160_9, mcs[3][9]),
2072 #undef SKU_FIELD
2073 };
2074
2075 tx_power = mt76_get_sar_power(mphy, mphy->chandef.chan, tx_power);
2076 tx_power -= mt76_tx_power_path_delta(n_chains);
2077 tx_power = mt76_get_rate_power_limits(mphy, mphy->chandef.chan,
2078 &limits, tx_power);
2079 mphy->txpower_cur = tx_power;
2080
2081 if (is_mt7663(mphy->dev)) {
2082 memset(sku, tx_power, MT_SKU_4SS_DELTA + 1);
2083 return;
2084 }
2085
2086 for (i = 0; i < MT_SKU_1SS_DELTA; i++)
2087 sku[i] = limits_array[sku_mapping[i]];
2088
2089 for (i = 0; i < 4; i++) {
2090 int delta = 0;
2091
2092 if (i < n_chains - 1)
2093 delta = mt76_tx_power_path_delta(n_chains) -
2094 mt76_tx_power_path_delta(i + 1);
2095 sku[MT_SKU_1SS_DELTA + i] = delta;
2096 }
2097 }
2098
mt7615_mcu_chan_bw(struct cfg80211_chan_def * chandef)2099 static u8 mt7615_mcu_chan_bw(struct cfg80211_chan_def *chandef)
2100 {
2101 static const u8 width_to_bw[] = {
2102 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
2103 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
2104 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
2105 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
2106 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
2107 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
2108 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
2109 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
2110 };
2111
2112 if (chandef->width >= ARRAY_SIZE(width_to_bw))
2113 return 0;
2114
2115 return width_to_bw[chandef->width];
2116 }
2117
mt7615_mcu_set_chan_info(struct mt7615_phy * phy,int cmd)2118 int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd)
2119 {
2120 struct mt7615_dev *dev = phy->dev;
2121 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2122 int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2;
2123 struct {
2124 u8 control_chan;
2125 u8 center_chan;
2126 u8 bw;
2127 u8 tx_streams;
2128 u8 rx_streams_mask;
2129 u8 switch_reason;
2130 u8 band_idx;
2131 /* for 80+80 only */
2132 u8 center_chan2;
2133 __le16 cac_case;
2134 u8 channel_band;
2135 u8 rsv0;
2136 __le32 outband_freq;
2137 u8 txpower_drop;
2138 u8 rsv1[3];
2139 u8 txpower_sku[53];
2140 u8 rsv2[3];
2141 } req = {
2142 .control_chan = chandef->chan->hw_value,
2143 .center_chan = ieee80211_frequency_to_channel(freq1),
2144 .tx_streams = hweight8(phy->mt76->antenna_mask),
2145 .rx_streams_mask = phy->mt76->chainmask,
2146 .center_chan2 = ieee80211_frequency_to_channel(freq2),
2147 };
2148
2149 if (cmd == MCU_EXT_CMD(SET_RX_PATH) ||
2150 phy->mt76->hw->conf.flags & IEEE80211_CONF_MONITOR)
2151 req.switch_reason = CH_SWITCH_NORMAL;
2152 else if (phy->mt76->offchannel)
2153 req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD;
2154 else if (!cfg80211_reg_can_beacon(phy->mt76->hw->wiphy, chandef,
2155 NL80211_IFTYPE_AP))
2156 req.switch_reason = CH_SWITCH_DFS;
2157 else
2158 req.switch_reason = CH_SWITCH_NORMAL;
2159
2160 req.band_idx = phy != &dev->phy;
2161 req.bw = mt7615_mcu_chan_bw(chandef);
2162
2163 if (mt76_testmode_enabled(phy->mt76))
2164 memset(req.txpower_sku, 0x3f, 49);
2165 else
2166 mt7615_mcu_set_txpower_sku(phy, req.txpower_sku);
2167
2168 return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true);
2169 }
2170
mt7615_mcu_get_temperature(struct mt7615_dev * dev)2171 int mt7615_mcu_get_temperature(struct mt7615_dev *dev)
2172 {
2173 struct {
2174 u8 action;
2175 u8 rsv[3];
2176 } req = {};
2177
2178 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(THERMAL_CTRL),
2179 &req, sizeof(req), true);
2180 }
2181
mt7615_mcu_set_test_param(struct mt7615_dev * dev,u8 param,bool test_mode,u32 val)2182 int mt7615_mcu_set_test_param(struct mt7615_dev *dev, u8 param, bool test_mode,
2183 u32 val)
2184 {
2185 struct {
2186 u8 test_mode_en;
2187 u8 param_idx;
2188 u8 _rsv[2];
2189
2190 __le32 value;
2191
2192 u8 pad[8];
2193 } req = {
2194 .test_mode_en = test_mode,
2195 .param_idx = param,
2196 .value = cpu_to_le32(val),
2197 };
2198
2199 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL),
2200 &req, sizeof(req), false);
2201 }
2202
mt7615_mcu_set_sku_en(struct mt7615_phy * phy,bool enable)2203 int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable)
2204 {
2205 struct mt7615_dev *dev = phy->dev;
2206 struct {
2207 u8 format_id;
2208 u8 sku_enable;
2209 u8 band_idx;
2210 u8 rsv;
2211 } req = {
2212 .format_id = 0,
2213 .band_idx = phy != &dev->phy,
2214 .sku_enable = enable,
2215 };
2216
2217 return mt76_mcu_send_msg(&dev->mt76,
2218 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
2219 &req, sizeof(req), true);
2220 }
2221
mt7615_find_freq_idx(const u16 * freqs,int n_freqs,u16 cur)2222 static int mt7615_find_freq_idx(const u16 *freqs, int n_freqs, u16 cur)
2223 {
2224 int i;
2225
2226 for (i = 0; i < n_freqs; i++)
2227 if (cur == freqs[i])
2228 return i;
2229
2230 return -1;
2231 }
2232
mt7615_dcoc_freq_idx(u16 freq,u8 bw)2233 static int mt7615_dcoc_freq_idx(u16 freq, u8 bw)
2234 {
2235 static const u16 freq_list[] = {
2236 4980, 5805, 5905, 5190,
2237 5230, 5270, 5310, 5350,
2238 5390, 5430, 5470, 5510,
2239 5550, 5590, 5630, 5670,
2240 5710, 5755, 5795, 5835,
2241 5875, 5210, 5290, 5370,
2242 5450, 5530, 5610, 5690,
2243 5775, 5855
2244 };
2245 static const u16 freq_bw40[] = {
2246 5190, 5230, 5270, 5310,
2247 5350, 5390, 5430, 5470,
2248 5510, 5550, 5590, 5630,
2249 5670, 5710, 5755, 5795,
2250 5835, 5875
2251 };
2252 int offset_2g = ARRAY_SIZE(freq_list);
2253 int idx;
2254
2255 if (freq < 4000) {
2256 if (freq < 2427)
2257 return offset_2g;
2258 if (freq < 2442)
2259 return offset_2g + 1;
2260 if (freq < 2457)
2261 return offset_2g + 2;
2262
2263 return offset_2g + 3;
2264 }
2265
2266 switch (bw) {
2267 case NL80211_CHAN_WIDTH_80:
2268 case NL80211_CHAN_WIDTH_80P80:
2269 case NL80211_CHAN_WIDTH_160:
2270 break;
2271 default:
2272 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2273 freq + 10);
2274 if (idx >= 0) {
2275 freq = freq_bw40[idx];
2276 break;
2277 }
2278
2279 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2280 freq - 10);
2281 if (idx >= 0) {
2282 freq = freq_bw40[idx];
2283 break;
2284 }
2285 fallthrough;
2286 case NL80211_CHAN_WIDTH_40:
2287 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2288 freq);
2289 if (idx >= 0)
2290 break;
2291
2292 return -1;
2293
2294 }
2295
2296 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq);
2297 }
2298
mt7615_mcu_apply_rx_dcoc(struct mt7615_phy * phy)2299 int mt7615_mcu_apply_rx_dcoc(struct mt7615_phy *phy)
2300 {
2301 struct mt7615_dev *dev = phy->dev;
2302 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2303 int freq2 = chandef->center_freq2;
2304 int ret;
2305 struct {
2306 u8 direction;
2307 u8 runtime_calibration;
2308 u8 _rsv[2];
2309
2310 __le16 center_freq;
2311 u8 bw;
2312 u8 band;
2313 u8 is_freq2;
2314 u8 success;
2315 u8 dbdc_en;
2316
2317 u8 _rsv2;
2318
2319 struct {
2320 __le32 sx0_i_lna[4];
2321 __le32 sx0_q_lna[4];
2322
2323 __le32 sx2_i_lna[4];
2324 __le32 sx2_q_lna[4];
2325 } dcoc_data[4];
2326 } req = {
2327 .direction = 1,
2328
2329 .bw = mt7615_mcu_chan_bw(chandef),
2330 .band = chandef->center_freq1 > 4000,
2331 .dbdc_en = !!dev->mt76.phys[MT_BAND1],
2332 };
2333 u16 center_freq = chandef->center_freq1;
2334 int freq_idx;
2335 u8 *eep = dev->mt76.eeprom.data;
2336
2337 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_RX_CAL))
2338 return 0;
2339
2340 if (chandef->width == NL80211_CHAN_WIDTH_160) {
2341 freq2 = center_freq + 40;
2342 center_freq -= 40;
2343 }
2344
2345 again:
2346 req.runtime_calibration = 1;
2347 freq_idx = mt7615_dcoc_freq_idx(center_freq, chandef->width);
2348 if (freq_idx < 0)
2349 goto out;
2350
2351 memcpy(req.dcoc_data, eep + MT7615_EEPROM_DCOC_OFFSET +
2352 freq_idx * MT7615_EEPROM_DCOC_SIZE,
2353 sizeof(req.dcoc_data));
2354 req.runtime_calibration = 0;
2355
2356 out:
2357 req.center_freq = cpu_to_le16(center_freq);
2358 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RXDCOC_CAL), &req,
2359 sizeof(req), true);
2360
2361 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 ||
2362 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) {
2363 req.is_freq2 = true;
2364 center_freq = freq2;
2365 goto again;
2366 }
2367
2368 return ret;
2369 }
2370
mt7615_dpd_freq_idx(u16 freq,u8 bw)2371 static int mt7615_dpd_freq_idx(u16 freq, u8 bw)
2372 {
2373 static const u16 freq_list[] = {
2374 4920, 4940, 4960, 4980,
2375 5040, 5060, 5080, 5180,
2376 5200, 5220, 5240, 5260,
2377 5280, 5300, 5320, 5340,
2378 5360, 5380, 5400, 5420,
2379 5440, 5460, 5480, 5500,
2380 5520, 5540, 5560, 5580,
2381 5600, 5620, 5640, 5660,
2382 5680, 5700, 5720, 5745,
2383 5765, 5785, 5805, 5825,
2384 5845, 5865, 5885, 5905
2385 };
2386 int offset_2g = ARRAY_SIZE(freq_list);
2387 int idx;
2388
2389 if (freq < 4000) {
2390 if (freq < 2432)
2391 return offset_2g;
2392 if (freq < 2457)
2393 return offset_2g + 1;
2394
2395 return offset_2g + 2;
2396 }
2397
2398 if (bw != NL80211_CHAN_WIDTH_20) {
2399 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list),
2400 freq + 10);
2401 if (idx >= 0)
2402 return idx;
2403
2404 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list),
2405 freq - 10);
2406 if (idx >= 0)
2407 return idx;
2408 }
2409
2410 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq);
2411 }
2412
2413
mt7615_mcu_apply_tx_dpd(struct mt7615_phy * phy)2414 int mt7615_mcu_apply_tx_dpd(struct mt7615_phy *phy)
2415 {
2416 struct mt7615_dev *dev = phy->dev;
2417 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2418 int freq2 = chandef->center_freq2;
2419 int ret;
2420 struct {
2421 u8 direction;
2422 u8 runtime_calibration;
2423 u8 _rsv[2];
2424
2425 __le16 center_freq;
2426 u8 bw;
2427 u8 band;
2428 u8 is_freq2;
2429 u8 success;
2430 u8 dbdc_en;
2431
2432 u8 _rsv2;
2433
2434 struct {
2435 struct {
2436 u32 dpd_g0;
2437 u8 data[32];
2438 } wf0, wf1;
2439
2440 struct {
2441 u32 dpd_g0_prim;
2442 u32 dpd_g0_sec;
2443 u8 data_prim[32];
2444 u8 data_sec[32];
2445 } wf2, wf3;
2446 } dpd_data;
2447 } req = {
2448 .direction = 1,
2449
2450 .bw = mt7615_mcu_chan_bw(chandef),
2451 .band = chandef->center_freq1 > 4000,
2452 .dbdc_en = !!dev->mt76.phys[MT_BAND1],
2453 };
2454 u16 center_freq = chandef->center_freq1;
2455 int freq_idx;
2456 u8 *eep = dev->mt76.eeprom.data;
2457
2458 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_TX_DPD))
2459 return 0;
2460
2461 if (chandef->width == NL80211_CHAN_WIDTH_160) {
2462 freq2 = center_freq + 40;
2463 center_freq -= 40;
2464 }
2465
2466 again:
2467 req.runtime_calibration = 1;
2468 freq_idx = mt7615_dpd_freq_idx(center_freq, chandef->width);
2469 if (freq_idx < 0)
2470 goto out;
2471
2472 memcpy(&req.dpd_data, eep + MT7615_EEPROM_TXDPD_OFFSET +
2473 freq_idx * MT7615_EEPROM_TXDPD_SIZE,
2474 sizeof(req.dpd_data));
2475 req.runtime_calibration = 0;
2476
2477 out:
2478 req.center_freq = cpu_to_le16(center_freq);
2479 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXDPD_CAL),
2480 &req, sizeof(req), true);
2481
2482 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 ||
2483 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) {
2484 req.is_freq2 = true;
2485 center_freq = freq2;
2486 goto again;
2487 }
2488
2489 return ret;
2490 }
2491
mt7615_mcu_set_rx_hdr_trans_blacklist(struct mt7615_dev * dev)2492 int mt7615_mcu_set_rx_hdr_trans_blacklist(struct mt7615_dev *dev)
2493 {
2494 struct {
2495 u8 operation;
2496 u8 count;
2497 u8 _rsv[2];
2498 u8 index;
2499 u8 enable;
2500 __le16 etype;
2501 } req = {
2502 .operation = 1,
2503 .count = 1,
2504 .enable = 1,
2505 .etype = cpu_to_le16(ETH_P_PAE),
2506 };
2507
2508 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_HDR_TRANS),
2509 &req, sizeof(req), false);
2510 }
2511
mt7615_mcu_set_bss_pm(struct mt7615_dev * dev,struct ieee80211_vif * vif,bool enable)2512 int mt7615_mcu_set_bss_pm(struct mt7615_dev *dev, struct ieee80211_vif *vif,
2513 bool enable)
2514 {
2515 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
2516 struct {
2517 u8 bss_idx;
2518 u8 dtim_period;
2519 __le16 aid;
2520 __le16 bcn_interval;
2521 __le16 atim_window;
2522 u8 uapsd;
2523 u8 bmc_delivered_ac;
2524 u8 bmc_triggered_ac;
2525 u8 pad;
2526 } req = {
2527 .bss_idx = mvif->mt76.idx,
2528 .aid = cpu_to_le16(vif->cfg.aid),
2529 .dtim_period = vif->bss_conf.dtim_period,
2530 .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int),
2531 };
2532 struct {
2533 u8 bss_idx;
2534 u8 pad[3];
2535 } req_hdr = {
2536 .bss_idx = mvif->mt76.idx,
2537 };
2538 int err;
2539
2540 if (vif->type != NL80211_IFTYPE_STATION)
2541 return 0;
2542
2543 err = mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_ABORT),
2544 &req_hdr, sizeof(req_hdr), false);
2545 if (err < 0 || !enable)
2546 return err;
2547
2548 return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_CONNECTED),
2549 &req, sizeof(req), false);
2550 }
2551
mt7615_mcu_set_roc(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration)2552 int mt7615_mcu_set_roc(struct mt7615_phy *phy, struct ieee80211_vif *vif,
2553 struct ieee80211_channel *chan, int duration)
2554 {
2555 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
2556 struct mt7615_dev *dev = phy->dev;
2557 struct mt7615_roc_tlv req = {
2558 .bss_idx = mvif->mt76.idx,
2559 .active = !chan,
2560 .max_interval = cpu_to_le32(duration),
2561 .primary_chan = chan ? chan->hw_value : 0,
2562 .band = chan ? chan->band : 0,
2563 .req_type = 2,
2564 };
2565
2566 phy->roc_grant = false;
2567
2568 return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_ROC),
2569 &req, sizeof(req), false);
2570 }
2571