1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_FIVE 0x40a00000 42 #define FLOAT_SIX 0x40c00000 43 #define FLOAT_EIGHT 0x41000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_DSP 0x16 47 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55 #define MASTERCONTROL 0x80 56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59 #define WIDGET_CHIP_CTRL 0x15 60 #define WIDGET_DSP_CTRL 0x16 61 62 #define MEM_CONNID_MICIN1 3 63 #define MEM_CONNID_MICIN2 5 64 #define MEM_CONNID_MICOUT1 12 65 #define MEM_CONNID_MICOUT2 14 66 #define MEM_CONNID_WUH 10 67 #define MEM_CONNID_DSP 16 68 #define MEM_CONNID_DMIC 100 69 70 #define SCP_SET 0 71 #define SCP_GET 1 72 73 #define EFX_FILE "ctefx.bin" 74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75 #define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80 MODULE_FIRMWARE(R3DI_EFX_FILE); 81 #endif 82 83 static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85 #define NUM_OF_OUTPUTS 2 86 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87 enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90 }; 91 92 enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95 }; 96 97 /* Strings for Input Source Enum Control */ 98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 99 #define IN_SRC_NUM_OF_INPUTS 3 100 enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104 }; 105 106 enum { 107 #define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117 #define EFFECT_START_NID 0x90 118 #define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155 }; 156 157 /* Effects values size*/ 158 #define EFFECT_VALS_MAX_COUNT 12 159 160 /* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166 /* Amount of effect level sliders for ca0132_alt controls. */ 167 #define EFFECT_LEVEL_SLIDERS 5 168 169 /* Latency introduced by DSP blocks in milliseconds. */ 170 #define DSP_CAPTURE_INIT_LATENCY 0 171 #define DSP_CRYSTAL_VOICE_LATENCY 124 172 #define DSP_PLAYBACK_INIT_LATENCY 13 173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 174 #define DSP_SPEAKER_OUT_LATENCY 7 175 176 struct ct_effect { 177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185 }; 186 187 #define EFX_DIR_OUT 0 188 #define EFX_DIR_IN 1 189 190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284 }; 285 286 /* Tuning controls */ 287 #ifdef ENABLE_TUNING_CONTROLS 288 289 enum { 290 #define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305 }; 306 307 struct ct_tuning_ctl { 308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315 }; 316 317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414 }; 415 #endif 416 417 /* Voice FX Presets */ 418 #define VOICEFX_MAX_PARAM_COUNT 9 419 420 struct ct_voicefx { 421 char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425 }; 426 427 struct ct_voicefx_preset { 428 char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430 }; 431 432 static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437 }; 438 439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510 }; 511 512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514 #define EQ_PRESET_MAX_PARAM_COUNT 11 515 516 struct ct_eq { 517 char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521 }; 522 523 struct ct_eq_preset { 524 char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526 }; 527 528 static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533 }; 534 535 536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597 }; 598 599 /* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606 enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615 }; 616 617 /* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621 enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669 }; 670 671 /* Surround output channel count configuration structures. */ 672 #define SPEAKER_CHANNEL_CFG_COUNT 5 673 enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679 }; 680 681 struct ca0132_alt_speaker_channel_cfg { 682 char *name; 683 unsigned int val; 684 }; 685 686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702 }; 703 704 /* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709 #define DSP_VOL_OUT 0 710 #define DSP_VOL_IN 1 711 712 struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716 }; 717 718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727 }; 728 729 /* Values for ca0113_mmio_command_set for selecting output. */ 730 #define AE_CA0113_OUT_SET_COMMANDS 6 731 struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735 }; 736 737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744 }; 745 746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753 }; 754 755 /* ae5 ca0113 command sequences to set headphone gain levels. */ 756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757 struct ae5_headphone_gain_set { 758 char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760 }; 761 762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772 }; 773 774 struct ae5_filter_set { 775 char *name; 776 unsigned int val; 777 }; 778 779 static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789 }; 790 791 /* 792 * Data structures for storing audio router remapping data. These are used to 793 * remap a currently active streams ports. 794 */ 795 struct chipio_stream_remap_data { 796 unsigned int stream_id; 797 unsigned int count; 798 799 unsigned int offset[16]; 800 unsigned int value[16]; 801 }; 802 803 static const struct chipio_stream_remap_data stream_remap_data[] = { 804 { .stream_id = 0x14, 805 .count = 0x04, 806 .offset = { 0x00, 0x04, 0x08, 0x0c }, 807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 808 }, 809 { .stream_id = 0x0c, 810 .count = 0x0c, 811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 812 0x20, 0x24, 0x28, 0x2c }, 813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 816 }, 817 { .stream_id = 0x0c, 818 .count = 0x08, 819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 822 } 823 }; 824 825 enum hda_cmd_vendor_io { 826 /* for DspIO node */ 827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 829 830 VENDOR_DSPIO_STATUS = 0xF01, 831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 833 VENDOR_DSPIO_DSP_INIT = 0x703, 834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 836 837 /* for ChipIO node */ 838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 841 VENDOR_CHIPIO_DATA_LOW = 0x300, 842 VENDOR_CHIPIO_DATA_HIGH = 0x400, 843 844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 846 847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 848 VENDOR_CHIPIO_STATUS = 0xF01, 849 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 851 852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 857 858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 860 861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 865 VENDOR_CHIPIO_FLAG_SET = 0x70F, 866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 867 VENDOR_CHIPIO_PARAM_SET = 0x710, 868 VENDOR_CHIPIO_PARAM_GET = 0xF10, 869 870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 874 875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 879 880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 886 887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 888 }; 889 890 /* 891 * Control flag IDs 892 */ 893 enum control_flag_id { 894 /* Connection manager stream setup is bypassed/enabled */ 895 CONTROL_FLAG_C_MGR = 0, 896 /* DSP DMA is bypassed/enabled */ 897 CONTROL_FLAG_DMA = 1, 898 /* 8051 'idle' mode is disabled/enabled */ 899 CONTROL_FLAG_IDLE_ENABLE = 2, 900 /* Tracker for the SPDIF-in path is bypassed/enabled */ 901 CONTROL_FLAG_TRACKER = 3, 902 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 903 CONTROL_FLAG_SPDIF2OUT = 4, 904 /* Digital Microphone is disabled/enabled */ 905 CONTROL_FLAG_DMIC = 5, 906 /* ADC_B rate is 48 kHz/96 kHz */ 907 CONTROL_FLAG_ADC_B_96KHZ = 6, 908 /* ADC_C rate is 48 kHz/96 kHz */ 909 CONTROL_FLAG_ADC_C_96KHZ = 7, 910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 911 CONTROL_FLAG_DAC_96KHZ = 8, 912 /* DSP rate is 48 kHz/96 kHz */ 913 CONTROL_FLAG_DSP_96KHZ = 9, 914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 917 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 919 CONTROL_FLAG_DECODE_LOOP = 12, 920 /* De-emphasis filter on DAC-1 disabled/enabled */ 921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 922 /* De-emphasis filter on DAC-2 disabled/enabled */ 923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 924 /* De-emphasis filter on DAC-3 disabled/enabled */ 925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 926 /* High-pass filter on ADC_B disabled/enabled */ 927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 928 /* High-pass filter on ADC_C disabled/enabled */ 929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 930 /* Common mode on Port_A disabled/enabled */ 931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 932 /* Common mode on Port_D disabled/enabled */ 933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 938 /* ASI rate is 48kHz/96kHz */ 939 CONTROL_FLAG_ASI_96KHZ = 22, 940 /* DAC power settings able to control attached ports no/yes */ 941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 942 /* Clock Stop OK reporting is disabled/enabled */ 943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 944 /* Number of control flags */ 945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 946 }; 947 948 /* 949 * Control parameter IDs 950 */ 951 enum control_param_id { 952 /* 0: None, 1: Mic1In*/ 953 CONTROL_PARAM_VIP_SOURCE = 1, 954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 955 CONTROL_PARAM_SPDIF1_SOURCE = 2, 956 /* Port A output stage gain setting to use when 16 Ohm output 957 * impedance is selected*/ 958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 959 /* Port D output stage gain setting to use when 16 Ohm output 960 * impedance is selected*/ 961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 962 963 /* 964 * This control param name was found in the 8051 memory, and makes 965 * sense given the fact the AE-5 uses it and has the ASI flag set. 966 */ 967 CONTROL_PARAM_ASI = 23, 968 969 /* Stream Control */ 970 971 /* Select stream with the given ID */ 972 CONTROL_PARAM_STREAM_ID = 24, 973 /* Source connection point for the selected stream */ 974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 975 /* Destination connection point for the selected stream */ 976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 977 /* Number of audio channels in the selected stream */ 978 CONTROL_PARAM_STREAMS_CHANNELS = 27, 979 /*Enable control for the selected stream */ 980 CONTROL_PARAM_STREAM_CONTROL = 28, 981 982 /* Connection Point Control */ 983 984 /* Select connection point with the given ID */ 985 CONTROL_PARAM_CONN_POINT_ID = 29, 986 /* Connection point sample rate */ 987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 988 989 /* Node Control */ 990 991 /* Select HDA node with the given ID */ 992 CONTROL_PARAM_NODE_ID = 31 993 }; 994 995 /* 996 * Dsp Io Status codes 997 */ 998 enum hda_vendor_status_dspio { 999 /* Success */ 1000 VENDOR_STATUS_DSPIO_OK = 0x00, 1001 /* Busy, unable to accept new command, the host must retry */ 1002 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1003 /* SCP command queue is full */ 1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1005 /* SCP response queue is empty */ 1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1007 }; 1008 1009 /* 1010 * Chip Io Status codes 1011 */ 1012 enum hda_vendor_status_chipio { 1013 /* Success */ 1014 VENDOR_STATUS_CHIPIO_OK = 0x00, 1015 /* Busy, unable to accept new command, the host must retry */ 1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1017 }; 1018 1019 /* 1020 * CA0132 sample rate 1021 */ 1022 enum ca0132_sample_rate { 1023 SR_6_000 = 0x00, 1024 SR_8_000 = 0x01, 1025 SR_9_600 = 0x02, 1026 SR_11_025 = 0x03, 1027 SR_16_000 = 0x04, 1028 SR_22_050 = 0x05, 1029 SR_24_000 = 0x06, 1030 SR_32_000 = 0x07, 1031 SR_44_100 = 0x08, 1032 SR_48_000 = 0x09, 1033 SR_88_200 = 0x0A, 1034 SR_96_000 = 0x0B, 1035 SR_144_000 = 0x0C, 1036 SR_176_400 = 0x0D, 1037 SR_192_000 = 0x0E, 1038 SR_384_000 = 0x0F, 1039 1040 SR_COUNT = 0x10, 1041 1042 SR_RATE_UNKNOWN = 0x1F 1043 }; 1044 1045 enum dsp_download_state { 1046 DSP_DOWNLOAD_FAILED = -1, 1047 DSP_DOWNLOAD_INIT = 0, 1048 DSP_DOWNLOADING = 1, 1049 DSP_DOWNLOADED = 2 1050 }; 1051 1052 /* retrieve parameters from hda format */ 1053 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1057 1058 /* 1059 * CA0132 specific 1060 */ 1061 1062 struct ca0132_spec { 1063 const struct snd_kcontrol_new *mixers[5]; 1064 unsigned int num_mixers; 1065 const struct hda_verb *base_init_verbs; 1066 const struct hda_verb *base_exit_verbs; 1067 const struct hda_verb *chip_init_verbs; 1068 const struct hda_verb *desktop_init_verbs; 1069 struct hda_verb *spec_init_verbs; 1070 struct auto_pin_cfg autocfg; 1071 1072 /* Nodes configurations */ 1073 struct hda_multi_out multiout; 1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1076 unsigned int num_outputs; 1077 hda_nid_t input_pins[AUTO_PIN_LAST]; 1078 hda_nid_t adcs[AUTO_PIN_LAST]; 1079 hda_nid_t dig_out; 1080 hda_nid_t dig_in; 1081 unsigned int num_inputs; 1082 hda_nid_t shared_mic_nid; 1083 hda_nid_t shared_out_nid; 1084 hda_nid_t unsol_tag_hp; 1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1086 hda_nid_t unsol_tag_amic1; 1087 1088 /* chip access */ 1089 struct mutex chipio_mutex; /* chip access mutex */ 1090 u32 curr_chip_addx; 1091 1092 /* DSP download related */ 1093 enum dsp_download_state dsp_state; 1094 unsigned int dsp_stream_id; 1095 unsigned int wait_scp; 1096 unsigned int wait_scp_header; 1097 unsigned int wait_num_data; 1098 unsigned int scp_resp_header; 1099 unsigned int scp_resp_data[4]; 1100 unsigned int scp_resp_count; 1101 bool startup_check_entered; 1102 bool dsp_reload; 1103 1104 /* mixer and effects related */ 1105 unsigned char dmic_ctl; 1106 int cur_out_type; 1107 int cur_mic_type; 1108 long vnode_lvol[VNODES_COUNT]; 1109 long vnode_rvol[VNODES_COUNT]; 1110 long vnode_lswitch[VNODES_COUNT]; 1111 long vnode_rswitch[VNODES_COUNT]; 1112 long effects_switch[EFFECTS_COUNT]; 1113 long voicefx_val; 1114 long cur_mic_boost; 1115 /* ca0132_alt control related values */ 1116 unsigned char in_enum_val; 1117 unsigned char out_enum_val; 1118 unsigned char channel_cfg_val; 1119 unsigned char speaker_range_val[2]; 1120 unsigned char mic_boost_enum_val; 1121 unsigned char smart_volume_setting; 1122 unsigned char bass_redirection_val; 1123 long bass_redirect_xover_freq; 1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1125 long xbass_xover_freq; 1126 long eq_preset_val; 1127 unsigned int tlv[4]; 1128 struct hda_vmaster_mute_hook vmaster_mute; 1129 /* AE-5 Control values */ 1130 unsigned char ae5_headphone_gain_val; 1131 unsigned char ae5_filter_val; 1132 /* ZxR Control Values */ 1133 unsigned char zxr_gain_set; 1134 1135 struct hda_codec *codec; 1136 struct delayed_work unsol_hp_work; 1137 1138 #ifdef ENABLE_TUNING_CONTROLS 1139 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1140 #endif 1141 /* 1142 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1143 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1144 * things. 1145 */ 1146 bool use_pci_mmio; 1147 void __iomem *mem_base; 1148 1149 /* 1150 * Whether or not to use the alt functions like alt_select_out, 1151 * alt_select_in, etc. Only used on desktop codecs for now, because of 1152 * surround sound support. 1153 */ 1154 bool use_alt_functions; 1155 1156 /* 1157 * Whether or not to use alt controls: volume effect sliders, EQ 1158 * presets, smart volume presets, and new control names with FX prefix. 1159 * Renames PlayEnhancement and CrystalVoice too. 1160 */ 1161 bool use_alt_controls; 1162 }; 1163 1164 /* 1165 * CA0132 quirks table 1166 */ 1167 enum { 1168 QUIRK_ALIENWARE, 1169 QUIRK_ALIENWARE_M17XR4, 1170 QUIRK_SBZ, 1171 QUIRK_ZXR, 1172 QUIRK_ZXR_DBPRO, 1173 QUIRK_R3DI, 1174 QUIRK_R3D, 1175 QUIRK_AE5, 1176 QUIRK_AE7, 1177 QUIRK_NONE = HDA_FIXUP_ID_NOT_SET, 1178 }; 1179 1180 #ifdef CONFIG_PCI 1181 #define ca0132_quirk(spec) ((spec)->codec->fixup_id) 1182 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1183 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1184 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1185 #else 1186 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1187 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1188 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1189 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1190 #endif 1191 1192 static const struct hda_pintbl alienware_pincfgs[] = { 1193 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1194 { 0x0c, 0x411111f0 }, /* N/A */ 1195 { 0x0d, 0x411111f0 }, /* N/A */ 1196 { 0x0e, 0x411111f0 }, /* N/A */ 1197 { 0x0f, 0x0321101f }, /* HP */ 1198 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1199 { 0x11, 0x03a11021 }, /* Mic */ 1200 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1201 { 0x13, 0x411111f0 }, /* N/A */ 1202 { 0x18, 0x411111f0 }, /* N/A */ 1203 {} 1204 }; 1205 1206 /* Sound Blaster Z pin configs taken from Windows Driver */ 1207 static const struct hda_pintbl sbz_pincfgs[] = { 1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1210 { 0x0d, 0x014510f0 }, /* Digital Out */ 1211 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1216 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1217 { 0x18, 0x50d000f0 }, /* N/A */ 1218 {} 1219 }; 1220 1221 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1222 static const struct hda_pintbl zxr_pincfgs[] = { 1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1225 { 0x0d, 0x014510f0 }, /* Digital Out */ 1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1231 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1232 { 0x18, 0x50d000f0 }, /* N/A */ 1233 {} 1234 }; 1235 1236 /* Recon3D pin configs taken from Windows Driver */ 1237 static const struct hda_pintbl r3d_pincfgs[] = { 1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1240 { 0x0d, 0x014510f0 }, /* Digital Out */ 1241 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1246 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1247 { 0x18, 0x50d000f0 }, /* N/A */ 1248 {} 1249 }; 1250 1251 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1252 static const struct hda_pintbl ae5_pincfgs[] = { 1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1255 { 0x0d, 0x014510f0 }, /* Digital Out */ 1256 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1261 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1262 { 0x18, 0x50d000f0 }, /* N/A */ 1263 {} 1264 }; 1265 1266 /* Recon3D integrated pin configs taken from Windows Driver */ 1267 static const struct hda_pintbl r3di_pincfgs[] = { 1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1270 { 0x0d, 0x014510f0 }, /* Digital Out */ 1271 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1276 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1277 { 0x18, 0x500000f0 }, /* N/A */ 1278 {} 1279 }; 1280 1281 static const struct hda_pintbl ae7_pincfgs[] = { 1282 { 0x0b, 0x01017010 }, 1283 { 0x0c, 0x014510f0 }, 1284 { 0x0d, 0x414510f0 }, 1285 { 0x0e, 0x01c520f0 }, 1286 { 0x0f, 0x01017114 }, 1287 { 0x10, 0x01017011 }, 1288 { 0x11, 0x018170ff }, 1289 { 0x12, 0x01a170f0 }, 1290 { 0x13, 0x908700f0 }, 1291 { 0x18, 0x500000f0 }, 1292 {} 1293 }; 1294 1295 static const struct hda_quirk ca0132_quirks[] = { 1296 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1297 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1298 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1299 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1300 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1301 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1302 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1303 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1304 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1305 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1307 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1308 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), 1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1315 {} 1316 }; 1317 1318 static const struct hda_model_fixup ca0132_quirk_models[] = { 1319 { .id = QUIRK_ALIENWARE, .name = "alienware" }, 1320 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" }, 1321 { .id = QUIRK_SBZ, .name = "sbz" }, 1322 { .id = QUIRK_ZXR, .name = "zxr" }, 1323 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" }, 1324 { .id = QUIRK_R3DI, .name = "r3di" }, 1325 { .id = QUIRK_R3D, .name = "r3d" }, 1326 { .id = QUIRK_AE5, .name = "ae5" }, 1327 { .id = QUIRK_AE7, .name = "ae7" }, 1328 {} 1329 }; 1330 1331 /* Output selection quirk info structures. */ 1332 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1333 #define MAX_QUIRK_SCP_SET_VALS 2 1334 struct ca0132_alt_out_set_info { 1335 unsigned int dac2port; /* ParamID 0x0d value. */ 1336 1337 bool has_hda_gpio; 1338 char hda_gpio_pin; 1339 char hda_gpio_set; 1340 1341 unsigned int mmio_gpio_count; 1342 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1343 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1344 1345 unsigned int scp_cmds_count; 1346 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1347 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1348 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1349 1350 bool has_chipio_write; 1351 unsigned int chipio_write_addr; 1352 unsigned int chipio_write_data; 1353 }; 1354 1355 struct ca0132_alt_out_set_quirk_data { 1356 int quirk_id; 1357 1358 bool has_headphone_gain; 1359 bool is_ae_series; 1360 1361 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1362 }; 1363 1364 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1365 { .quirk_id = QUIRK_R3DI, 1366 .has_headphone_gain = false, 1367 .is_ae_series = false, 1368 .out_set_info = { 1369 /* Speakers. */ 1370 { .dac2port = 0x24, 1371 .has_hda_gpio = true, 1372 .hda_gpio_pin = 2, 1373 .hda_gpio_set = 1, 1374 .mmio_gpio_count = 0, 1375 .scp_cmds_count = 0, 1376 .has_chipio_write = false, 1377 }, 1378 /* Headphones. */ 1379 { .dac2port = 0x21, 1380 .has_hda_gpio = true, 1381 .hda_gpio_pin = 2, 1382 .hda_gpio_set = 0, 1383 .mmio_gpio_count = 0, 1384 .scp_cmds_count = 0, 1385 .has_chipio_write = false, 1386 } }, 1387 }, 1388 { .quirk_id = QUIRK_R3D, 1389 .has_headphone_gain = false, 1390 .is_ae_series = false, 1391 .out_set_info = { 1392 /* Speakers. */ 1393 { .dac2port = 0x24, 1394 .has_hda_gpio = false, 1395 .mmio_gpio_count = 1, 1396 .mmio_gpio_pin = { 1 }, 1397 .mmio_gpio_set = { 1 }, 1398 .scp_cmds_count = 0, 1399 .has_chipio_write = false, 1400 }, 1401 /* Headphones. */ 1402 { .dac2port = 0x21, 1403 .has_hda_gpio = false, 1404 .mmio_gpio_count = 1, 1405 .mmio_gpio_pin = { 1 }, 1406 .mmio_gpio_set = { 0 }, 1407 .scp_cmds_count = 0, 1408 .has_chipio_write = false, 1409 } }, 1410 }, 1411 { .quirk_id = QUIRK_SBZ, 1412 .has_headphone_gain = false, 1413 .is_ae_series = false, 1414 .out_set_info = { 1415 /* Speakers. */ 1416 { .dac2port = 0x18, 1417 .has_hda_gpio = false, 1418 .mmio_gpio_count = 3, 1419 .mmio_gpio_pin = { 7, 4, 1 }, 1420 .mmio_gpio_set = { 0, 1, 1 }, 1421 .scp_cmds_count = 0, 1422 .has_chipio_write = false, }, 1423 /* Headphones. */ 1424 { .dac2port = 0x12, 1425 .has_hda_gpio = false, 1426 .mmio_gpio_count = 3, 1427 .mmio_gpio_pin = { 7, 4, 1 }, 1428 .mmio_gpio_set = { 1, 1, 0 }, 1429 .scp_cmds_count = 0, 1430 .has_chipio_write = false, 1431 } }, 1432 }, 1433 { .quirk_id = QUIRK_ZXR, 1434 .has_headphone_gain = true, 1435 .is_ae_series = false, 1436 .out_set_info = { 1437 /* Speakers. */ 1438 { .dac2port = 0x24, 1439 .has_hda_gpio = false, 1440 .mmio_gpio_count = 3, 1441 .mmio_gpio_pin = { 2, 3, 5 }, 1442 .mmio_gpio_set = { 1, 1, 0 }, 1443 .scp_cmds_count = 0, 1444 .has_chipio_write = false, 1445 }, 1446 /* Headphones. */ 1447 { .dac2port = 0x21, 1448 .has_hda_gpio = false, 1449 .mmio_gpio_count = 3, 1450 .mmio_gpio_pin = { 2, 3, 5 }, 1451 .mmio_gpio_set = { 0, 1, 1 }, 1452 .scp_cmds_count = 0, 1453 .has_chipio_write = false, 1454 } }, 1455 }, 1456 { .quirk_id = QUIRK_AE5, 1457 .has_headphone_gain = true, 1458 .is_ae_series = true, 1459 .out_set_info = { 1460 /* Speakers. */ 1461 { .dac2port = 0xa4, 1462 .has_hda_gpio = false, 1463 .mmio_gpio_count = 0, 1464 .scp_cmds_count = 2, 1465 .scp_cmd_mid = { 0x96, 0x96 }, 1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1468 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1469 .has_chipio_write = true, 1470 .chipio_write_addr = 0x0018b03c, 1471 .chipio_write_data = 0x00000012 1472 }, 1473 /* Headphones. */ 1474 { .dac2port = 0xa1, 1475 .has_hda_gpio = false, 1476 .mmio_gpio_count = 0, 1477 .scp_cmds_count = 2, 1478 .scp_cmd_mid = { 0x96, 0x96 }, 1479 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1480 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1481 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1482 .has_chipio_write = true, 1483 .chipio_write_addr = 0x0018b03c, 1484 .chipio_write_data = 0x00000012 1485 } }, 1486 }, 1487 { .quirk_id = QUIRK_AE7, 1488 .has_headphone_gain = true, 1489 .is_ae_series = true, 1490 .out_set_info = { 1491 /* Speakers. */ 1492 { .dac2port = 0x58, 1493 .has_hda_gpio = false, 1494 .mmio_gpio_count = 1, 1495 .mmio_gpio_pin = { 0 }, 1496 .mmio_gpio_set = { 1 }, 1497 .scp_cmds_count = 2, 1498 .scp_cmd_mid = { 0x96, 0x96 }, 1499 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1500 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1501 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1502 .has_chipio_write = true, 1503 .chipio_write_addr = 0x0018b03c, 1504 .chipio_write_data = 0x00000000 1505 }, 1506 /* Headphones. */ 1507 { .dac2port = 0x58, 1508 .has_hda_gpio = false, 1509 .mmio_gpio_count = 1, 1510 .mmio_gpio_pin = { 0 }, 1511 .mmio_gpio_set = { 1 }, 1512 .scp_cmds_count = 2, 1513 .scp_cmd_mid = { 0x96, 0x96 }, 1514 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1515 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1516 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1517 .has_chipio_write = true, 1518 .chipio_write_addr = 0x0018b03c, 1519 .chipio_write_data = 0x00000010 1520 } }, 1521 } 1522 }; 1523 1524 /* 1525 * CA0132 codec access 1526 */ 1527 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1528 unsigned int verb, unsigned int parm, unsigned int *res) 1529 { 1530 unsigned int response; 1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1532 *res = response; 1533 1534 return ((response == -1) ? -1 : 0); 1535 } 1536 1537 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1538 unsigned short converter_format, unsigned int *res) 1539 { 1540 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1541 converter_format & 0xffff, res); 1542 } 1543 1544 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1545 hda_nid_t nid, unsigned char stream, 1546 unsigned char channel, unsigned int *res) 1547 { 1548 unsigned char converter_stream_channel = 0; 1549 1550 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1551 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1552 converter_stream_channel, res); 1553 } 1554 1555 /* Chip access helper function */ 1556 static int chipio_send(struct hda_codec *codec, 1557 unsigned int reg, 1558 unsigned int data) 1559 { 1560 unsigned int res; 1561 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1562 1563 /* send bits of data specified by reg */ 1564 do { 1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1566 reg, data); 1567 if (res == VENDOR_STATUS_CHIPIO_OK) 1568 return 0; 1569 msleep(20); 1570 } while (time_before(jiffies, timeout)); 1571 1572 return -EIO; 1573 } 1574 1575 /* 1576 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1577 */ 1578 static int chipio_write_address(struct hda_codec *codec, 1579 unsigned int chip_addx) 1580 { 1581 struct ca0132_spec *spec = codec->spec; 1582 int res; 1583 1584 if (spec->curr_chip_addx == chip_addx) 1585 return 0; 1586 1587 /* send low 16 bits of the address */ 1588 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1589 chip_addx & 0xffff); 1590 1591 if (res != -EIO) { 1592 /* send high 16 bits of the address */ 1593 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1594 chip_addx >> 16); 1595 } 1596 1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1598 1599 return res; 1600 } 1601 1602 /* 1603 * Write data through the vendor widget -- NOT protected by the Mutex! 1604 */ 1605 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1606 { 1607 struct ca0132_spec *spec = codec->spec; 1608 int res; 1609 1610 /* send low 16 bits of the data */ 1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1612 1613 if (res != -EIO) { 1614 /* send high 16 bits of the data */ 1615 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1616 data >> 16); 1617 } 1618 1619 /*If no error encountered, automatically increment the address 1620 as per chip behaviour*/ 1621 spec->curr_chip_addx = (res != -EIO) ? 1622 (spec->curr_chip_addx + 4) : ~0U; 1623 return res; 1624 } 1625 1626 /* 1627 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1628 */ 1629 static int chipio_write_data_multiple(struct hda_codec *codec, 1630 const u32 *data, 1631 unsigned int count) 1632 { 1633 int status = 0; 1634 1635 if (data == NULL) { 1636 codec_dbg(codec, "chipio_write_data null ptr\n"); 1637 return -EINVAL; 1638 } 1639 1640 while ((count-- != 0) && (status == 0)) 1641 status = chipio_write_data(codec, *data++); 1642 1643 return status; 1644 } 1645 1646 1647 /* 1648 * Read data through the vendor widget -- NOT protected by the Mutex! 1649 */ 1650 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1651 { 1652 struct ca0132_spec *spec = codec->spec; 1653 int res; 1654 1655 /* post read */ 1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1657 1658 if (res != -EIO) { 1659 /* read status */ 1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1661 } 1662 1663 if (res != -EIO) { 1664 /* read data */ 1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1666 VENDOR_CHIPIO_HIC_READ_DATA, 1667 0); 1668 } 1669 1670 /*If no error encountered, automatically increment the address 1671 as per chip behaviour*/ 1672 spec->curr_chip_addx = (res != -EIO) ? 1673 (spec->curr_chip_addx + 4) : ~0U; 1674 return res; 1675 } 1676 1677 /* 1678 * Write given value to the given address through the chip I/O widget. 1679 * protected by the Mutex 1680 */ 1681 static int chipio_write(struct hda_codec *codec, 1682 unsigned int chip_addx, const unsigned int data) 1683 { 1684 struct ca0132_spec *spec = codec->spec; 1685 int err; 1686 1687 mutex_lock(&spec->chipio_mutex); 1688 1689 /* write the address, and if successful proceed to write data */ 1690 err = chipio_write_address(codec, chip_addx); 1691 if (err < 0) 1692 goto exit; 1693 1694 err = chipio_write_data(codec, data); 1695 if (err < 0) 1696 goto exit; 1697 1698 exit: 1699 mutex_unlock(&spec->chipio_mutex); 1700 return err; 1701 } 1702 1703 /* 1704 * Write given value to the given address through the chip I/O widget. 1705 * not protected by the Mutex 1706 */ 1707 static int chipio_write_no_mutex(struct hda_codec *codec, 1708 unsigned int chip_addx, const unsigned int data) 1709 { 1710 int err; 1711 1712 1713 /* write the address, and if successful proceed to write data */ 1714 err = chipio_write_address(codec, chip_addx); 1715 if (err < 0) 1716 goto exit; 1717 1718 err = chipio_write_data(codec, data); 1719 if (err < 0) 1720 goto exit; 1721 1722 exit: 1723 return err; 1724 } 1725 1726 /* 1727 * Write multiple values to the given address through the chip I/O widget. 1728 * protected by the Mutex 1729 */ 1730 static int chipio_write_multiple(struct hda_codec *codec, 1731 u32 chip_addx, 1732 const u32 *data, 1733 unsigned int count) 1734 { 1735 struct ca0132_spec *spec = codec->spec; 1736 int status; 1737 1738 mutex_lock(&spec->chipio_mutex); 1739 status = chipio_write_address(codec, chip_addx); 1740 if (status < 0) 1741 goto error; 1742 1743 status = chipio_write_data_multiple(codec, data, count); 1744 error: 1745 mutex_unlock(&spec->chipio_mutex); 1746 1747 return status; 1748 } 1749 1750 /* 1751 * Read the given address through the chip I/O widget 1752 * protected by the Mutex 1753 */ 1754 static int chipio_read(struct hda_codec *codec, 1755 unsigned int chip_addx, unsigned int *data) 1756 { 1757 struct ca0132_spec *spec = codec->spec; 1758 int err; 1759 1760 mutex_lock(&spec->chipio_mutex); 1761 1762 /* write the address, and if successful proceed to write data */ 1763 err = chipio_write_address(codec, chip_addx); 1764 if (err < 0) 1765 goto exit; 1766 1767 err = chipio_read_data(codec, data); 1768 if (err < 0) 1769 goto exit; 1770 1771 exit: 1772 mutex_unlock(&spec->chipio_mutex); 1773 return err; 1774 } 1775 1776 /* 1777 * Set chip control flags through the chip I/O widget. 1778 */ 1779 static void chipio_set_control_flag(struct hda_codec *codec, 1780 enum control_flag_id flag_id, 1781 bool flag_state) 1782 { 1783 unsigned int val; 1784 unsigned int flag_bit; 1785 1786 flag_bit = (flag_state ? 1 : 0); 1787 val = (flag_bit << 7) | (flag_id); 1788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1789 VENDOR_CHIPIO_FLAG_SET, val); 1790 } 1791 1792 /* 1793 * Set chip parameters through the chip I/O widget. 1794 */ 1795 static void chipio_set_control_param(struct hda_codec *codec, 1796 enum control_param_id param_id, int param_val) 1797 { 1798 struct ca0132_spec *spec = codec->spec; 1799 int val; 1800 1801 if ((param_id < 32) && (param_val < 8)) { 1802 val = (param_val << 5) | (param_id); 1803 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1804 VENDOR_CHIPIO_PARAM_SET, val); 1805 } else { 1806 mutex_lock(&spec->chipio_mutex); 1807 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1808 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1809 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1810 param_id); 1811 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1812 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1813 param_val); 1814 } 1815 mutex_unlock(&spec->chipio_mutex); 1816 } 1817 } 1818 1819 /* 1820 * Set chip parameters through the chip I/O widget. NO MUTEX. 1821 */ 1822 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1823 enum control_param_id param_id, int param_val) 1824 { 1825 int val; 1826 1827 if ((param_id < 32) && (param_val < 8)) { 1828 val = (param_val << 5) | (param_id); 1829 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1830 VENDOR_CHIPIO_PARAM_SET, val); 1831 } else { 1832 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1833 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1834 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1835 param_id); 1836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1837 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1838 param_val); 1839 } 1840 } 1841 } 1842 /* 1843 * Connect stream to a source point, and then connect 1844 * that source point to a destination point. 1845 */ 1846 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1847 int streamid, int source_point, int dest_point) 1848 { 1849 chipio_set_control_param_no_mutex(codec, 1850 CONTROL_PARAM_STREAM_ID, streamid); 1851 chipio_set_control_param_no_mutex(codec, 1852 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1853 chipio_set_control_param_no_mutex(codec, 1854 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1855 } 1856 1857 /* 1858 * Set number of channels in the selected stream. 1859 */ 1860 static void chipio_set_stream_channels(struct hda_codec *codec, 1861 int streamid, unsigned int channels) 1862 { 1863 chipio_set_control_param_no_mutex(codec, 1864 CONTROL_PARAM_STREAM_ID, streamid); 1865 chipio_set_control_param_no_mutex(codec, 1866 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1867 } 1868 1869 /* 1870 * Enable/Disable audio stream. 1871 */ 1872 static void chipio_set_stream_control(struct hda_codec *codec, 1873 int streamid, int enable) 1874 { 1875 chipio_set_control_param_no_mutex(codec, 1876 CONTROL_PARAM_STREAM_ID, streamid); 1877 chipio_set_control_param_no_mutex(codec, 1878 CONTROL_PARAM_STREAM_CONTROL, enable); 1879 } 1880 1881 /* 1882 * Get ChipIO audio stream's status. 1883 */ 1884 static void chipio_get_stream_control(struct hda_codec *codec, 1885 int streamid, unsigned int *enable) 1886 { 1887 chipio_set_control_param_no_mutex(codec, 1888 CONTROL_PARAM_STREAM_ID, streamid); 1889 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1890 VENDOR_CHIPIO_PARAM_GET, 1891 CONTROL_PARAM_STREAM_CONTROL); 1892 } 1893 1894 /* 1895 * Set sampling rate of the connection point. NO MUTEX. 1896 */ 1897 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1898 int connid, enum ca0132_sample_rate rate) 1899 { 1900 chipio_set_control_param_no_mutex(codec, 1901 CONTROL_PARAM_CONN_POINT_ID, connid); 1902 chipio_set_control_param_no_mutex(codec, 1903 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1904 } 1905 1906 /* 1907 * Set sampling rate of the connection point. 1908 */ 1909 static void chipio_set_conn_rate(struct hda_codec *codec, 1910 int connid, enum ca0132_sample_rate rate) 1911 { 1912 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1913 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1914 rate); 1915 } 1916 1917 /* 1918 * Writes to the 8051's internal address space directly instead of indirectly, 1919 * giving access to the special function registers located at addresses 1920 * 0x80-0xFF. 1921 */ 1922 static void chipio_8051_write_direct(struct hda_codec *codec, 1923 unsigned int addr, unsigned int data) 1924 { 1925 unsigned int verb; 1926 1927 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1929 } 1930 1931 /* 1932 * Writes to the 8051's exram, which has 16-bits of address space. 1933 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1934 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1935 * setting the pmem bank selection SFR. 1936 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1937 * being writable. 1938 */ 1939 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1940 { 1941 unsigned int tmp; 1942 1943 /* Lower 8-bits. */ 1944 tmp = addr & 0xff; 1945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1946 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1947 1948 /* Upper 8-bits. */ 1949 tmp = (addr >> 8) & 0xff; 1950 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1951 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1952 } 1953 1954 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1955 { 1956 /* 8-bits of data. */ 1957 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1958 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1959 } 1960 1961 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1962 { 1963 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1964 VENDOR_CHIPIO_8051_DATA_READ, 0); 1965 } 1966 1967 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1968 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1969 { 1970 /* 8-bits of data. */ 1971 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1972 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1973 } 1974 1975 static void chipio_8051_write_exram(struct hda_codec *codec, 1976 unsigned int addr, unsigned int data) 1977 { 1978 struct ca0132_spec *spec = codec->spec; 1979 1980 mutex_lock(&spec->chipio_mutex); 1981 1982 chipio_8051_set_address(codec, addr); 1983 chipio_8051_set_data(codec, data); 1984 1985 mutex_unlock(&spec->chipio_mutex); 1986 } 1987 1988 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 1989 unsigned int addr, unsigned int data) 1990 { 1991 chipio_8051_set_address(codec, addr); 1992 chipio_8051_set_data(codec, data); 1993 } 1994 1995 /* Readback data from the 8051's exram. No mutex. */ 1996 static void chipio_8051_read_exram(struct hda_codec *codec, 1997 unsigned int addr, unsigned int *data) 1998 { 1999 chipio_8051_set_address(codec, addr); 2000 *data = chipio_8051_get_data(codec); 2001 } 2002 2003 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 2004 unsigned int addr, unsigned int data) 2005 { 2006 struct ca0132_spec *spec = codec->spec; 2007 2008 mutex_lock(&spec->chipio_mutex); 2009 2010 chipio_8051_set_address(codec, addr & 0xff); 2011 chipio_8051_set_data_pll(codec, data); 2012 2013 mutex_unlock(&spec->chipio_mutex); 2014 } 2015 2016 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 2017 unsigned int addr, unsigned int data) 2018 { 2019 chipio_8051_set_address(codec, addr & 0xff); 2020 chipio_8051_set_data_pll(codec, data); 2021 } 2022 2023 /* 2024 * Enable clocks. 2025 */ 2026 static void chipio_enable_clocks(struct hda_codec *codec) 2027 { 2028 struct ca0132_spec *spec = codec->spec; 2029 2030 mutex_lock(&spec->chipio_mutex); 2031 2032 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2033 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2034 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2035 2036 mutex_unlock(&spec->chipio_mutex); 2037 } 2038 2039 /* 2040 * CA0132 DSP IO stuffs 2041 */ 2042 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2043 unsigned int data) 2044 { 2045 int res; 2046 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2047 2048 /* send bits of data specified by reg to dsp */ 2049 do { 2050 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2051 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2052 return res; 2053 msleep(20); 2054 } while (time_before(jiffies, timeout)); 2055 2056 return -EIO; 2057 } 2058 2059 /* 2060 * Wait for DSP to be ready for commands 2061 */ 2062 static void dspio_write_wait(struct hda_codec *codec) 2063 { 2064 int status; 2065 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2066 2067 do { 2068 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2069 VENDOR_DSPIO_STATUS, 0); 2070 if ((status == VENDOR_STATUS_DSPIO_OK) || 2071 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2072 break; 2073 msleep(1); 2074 } while (time_before(jiffies, timeout)); 2075 } 2076 2077 /* 2078 * Write SCP data to DSP 2079 */ 2080 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2081 { 2082 struct ca0132_spec *spec = codec->spec; 2083 int status; 2084 2085 dspio_write_wait(codec); 2086 2087 mutex_lock(&spec->chipio_mutex); 2088 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2089 scp_data & 0xffff); 2090 if (status < 0) 2091 goto error; 2092 2093 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2094 scp_data >> 16); 2095 if (status < 0) 2096 goto error; 2097 2098 /* OK, now check if the write itself has executed*/ 2099 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2100 VENDOR_DSPIO_STATUS, 0); 2101 error: 2102 mutex_unlock(&spec->chipio_mutex); 2103 2104 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2105 -EIO : 0; 2106 } 2107 2108 /* 2109 * Write multiple SCP data to DSP 2110 */ 2111 static int dspio_write_multiple(struct hda_codec *codec, 2112 unsigned int *buffer, unsigned int size) 2113 { 2114 int status = 0; 2115 unsigned int count; 2116 2117 if (buffer == NULL) 2118 return -EINVAL; 2119 2120 count = 0; 2121 while (count < size) { 2122 status = dspio_write(codec, *buffer++); 2123 if (status != 0) 2124 break; 2125 count++; 2126 } 2127 2128 return status; 2129 } 2130 2131 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2132 { 2133 int status; 2134 2135 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2136 if (status == -EIO) 2137 return status; 2138 2139 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2140 if (status == -EIO || 2141 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2142 return -EIO; 2143 2144 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2145 VENDOR_DSPIO_SCP_READ_DATA, 0); 2146 2147 return 0; 2148 } 2149 2150 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2151 unsigned int *buf_size, unsigned int size_count) 2152 { 2153 int status = 0; 2154 unsigned int size = *buf_size; 2155 unsigned int count; 2156 unsigned int skip_count; 2157 unsigned int dummy; 2158 2159 if (buffer == NULL) 2160 return -1; 2161 2162 count = 0; 2163 while (count < size && count < size_count) { 2164 status = dspio_read(codec, buffer++); 2165 if (status != 0) 2166 break; 2167 count++; 2168 } 2169 2170 skip_count = count; 2171 if (status == 0) { 2172 while (skip_count < size) { 2173 status = dspio_read(codec, &dummy); 2174 if (status != 0) 2175 break; 2176 skip_count++; 2177 } 2178 } 2179 *buf_size = count; 2180 2181 return status; 2182 } 2183 2184 /* 2185 * Construct the SCP header using corresponding fields 2186 */ 2187 static inline unsigned int 2188 make_scp_header(unsigned int target_id, unsigned int source_id, 2189 unsigned int get_flag, unsigned int req, 2190 unsigned int device_flag, unsigned int resp_flag, 2191 unsigned int error_flag, unsigned int data_size) 2192 { 2193 unsigned int header = 0; 2194 2195 header = (data_size & 0x1f) << 27; 2196 header |= (error_flag & 0x01) << 26; 2197 header |= (resp_flag & 0x01) << 25; 2198 header |= (device_flag & 0x01) << 24; 2199 header |= (req & 0x7f) << 17; 2200 header |= (get_flag & 0x01) << 16; 2201 header |= (source_id & 0xff) << 8; 2202 header |= target_id & 0xff; 2203 2204 return header; 2205 } 2206 2207 /* 2208 * Extract corresponding fields from SCP header 2209 */ 2210 static inline void 2211 extract_scp_header(unsigned int header, 2212 unsigned int *target_id, unsigned int *source_id, 2213 unsigned int *get_flag, unsigned int *req, 2214 unsigned int *device_flag, unsigned int *resp_flag, 2215 unsigned int *error_flag, unsigned int *data_size) 2216 { 2217 if (data_size) 2218 *data_size = (header >> 27) & 0x1f; 2219 if (error_flag) 2220 *error_flag = (header >> 26) & 0x01; 2221 if (resp_flag) 2222 *resp_flag = (header >> 25) & 0x01; 2223 if (device_flag) 2224 *device_flag = (header >> 24) & 0x01; 2225 if (req) 2226 *req = (header >> 17) & 0x7f; 2227 if (get_flag) 2228 *get_flag = (header >> 16) & 0x01; 2229 if (source_id) 2230 *source_id = (header >> 8) & 0xff; 2231 if (target_id) 2232 *target_id = header & 0xff; 2233 } 2234 2235 #define SCP_MAX_DATA_WORDS (16) 2236 2237 /* Structure to contain any SCP message */ 2238 struct scp_msg { 2239 unsigned int hdr; 2240 unsigned int data[SCP_MAX_DATA_WORDS]; 2241 }; 2242 2243 static void dspio_clear_response_queue(struct hda_codec *codec) 2244 { 2245 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2246 unsigned int dummy = 0; 2247 int status; 2248 2249 /* clear all from the response queue */ 2250 do { 2251 status = dspio_read(codec, &dummy); 2252 } while (status == 0 && time_before(jiffies, timeout)); 2253 } 2254 2255 static int dspio_get_response_data(struct hda_codec *codec) 2256 { 2257 struct ca0132_spec *spec = codec->spec; 2258 unsigned int data = 0; 2259 unsigned int count; 2260 2261 if (dspio_read(codec, &data) < 0) 2262 return -EIO; 2263 2264 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2265 spec->scp_resp_header = data; 2266 spec->scp_resp_count = data >> 27; 2267 count = spec->wait_num_data; 2268 dspio_read_multiple(codec, spec->scp_resp_data, 2269 &spec->scp_resp_count, count); 2270 return 0; 2271 } 2272 2273 return -EIO; 2274 } 2275 2276 /* 2277 * Send SCP message to DSP 2278 */ 2279 static int dspio_send_scp_message(struct hda_codec *codec, 2280 unsigned char *send_buf, 2281 unsigned int send_buf_size, 2282 unsigned char *return_buf, 2283 unsigned int return_buf_size, 2284 unsigned int *bytes_returned) 2285 { 2286 struct ca0132_spec *spec = codec->spec; 2287 int status; 2288 unsigned int scp_send_size = 0; 2289 unsigned int total_size; 2290 bool waiting_for_resp = false; 2291 unsigned int header; 2292 struct scp_msg *ret_msg; 2293 unsigned int resp_src_id, resp_target_id; 2294 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2295 2296 if (bytes_returned) 2297 *bytes_returned = 0; 2298 2299 /* get scp header from buffer */ 2300 header = *((unsigned int *)send_buf); 2301 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2302 &device_flag, NULL, NULL, &data_size); 2303 scp_send_size = data_size + 1; 2304 total_size = (scp_send_size * 4); 2305 2306 if (send_buf_size < total_size) 2307 return -EINVAL; 2308 2309 if (get_flag || device_flag) { 2310 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2311 return -EINVAL; 2312 2313 spec->wait_scp_header = *((unsigned int *)send_buf); 2314 2315 /* swap source id with target id */ 2316 resp_target_id = src_id; 2317 resp_src_id = target_id; 2318 spec->wait_scp_header &= 0xffff0000; 2319 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2320 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2321 spec->wait_scp = 1; 2322 waiting_for_resp = true; 2323 } 2324 2325 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2326 scp_send_size); 2327 if (status < 0) { 2328 spec->wait_scp = 0; 2329 return status; 2330 } 2331 2332 if (waiting_for_resp) { 2333 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2334 memset(return_buf, 0, return_buf_size); 2335 do { 2336 msleep(20); 2337 } while (spec->wait_scp && time_before(jiffies, timeout)); 2338 waiting_for_resp = false; 2339 if (!spec->wait_scp) { 2340 ret_msg = (struct scp_msg *)return_buf; 2341 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2342 memcpy(&ret_msg->data, spec->scp_resp_data, 2343 spec->wait_num_data); 2344 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2345 status = 0; 2346 } else { 2347 status = -EIO; 2348 } 2349 spec->wait_scp = 0; 2350 } 2351 2352 return status; 2353 } 2354 2355 /** 2356 * dspio_scp - Prepare and send the SCP message to DSP 2357 * @codec: the HDA codec 2358 * @mod_id: ID of the DSP module to send the command 2359 * @src_id: ID of the source 2360 * @req: ID of request to send to the DSP module 2361 * @dir: SET or GET 2362 * @data: pointer to the data to send with the request, request specific 2363 * @len: length of the data, in bytes 2364 * @reply: point to the buffer to hold data returned for a reply 2365 * @reply_len: length of the reply buffer returned from GET 2366 * 2367 * Returns zero or a negative error code. 2368 */ 2369 static int dspio_scp(struct hda_codec *codec, 2370 int mod_id, int src_id, int req, int dir, const void *data, 2371 unsigned int len, void *reply, unsigned int *reply_len) 2372 { 2373 int status = 0; 2374 struct scp_msg scp_send, scp_reply; 2375 unsigned int ret_bytes, send_size, ret_size; 2376 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2377 unsigned int reply_data_size; 2378 2379 memset(&scp_send, 0, sizeof(scp_send)); 2380 memset(&scp_reply, 0, sizeof(scp_reply)); 2381 2382 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2383 return -EINVAL; 2384 2385 if (dir == SCP_GET && reply == NULL) { 2386 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2387 return -EINVAL; 2388 } 2389 2390 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2391 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2392 return -EINVAL; 2393 } 2394 2395 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2396 0, 0, 0, len/sizeof(unsigned int)); 2397 if (data != NULL && len > 0) { 2398 len = min((unsigned int)(sizeof(scp_send.data)), len); 2399 memcpy(scp_send.data, data, len); 2400 } 2401 2402 ret_bytes = 0; 2403 send_size = sizeof(unsigned int) + len; 2404 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2405 send_size, (unsigned char *)&scp_reply, 2406 sizeof(scp_reply), &ret_bytes); 2407 2408 if (status < 0) { 2409 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2410 return status; 2411 } 2412 2413 /* extract send and reply headers members */ 2414 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2415 NULL, NULL, NULL, NULL, NULL); 2416 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2417 &reply_resp_flag, &reply_error_flag, 2418 &reply_data_size); 2419 2420 if (!send_get_flag) 2421 return 0; 2422 2423 if (reply_resp_flag && !reply_error_flag) { 2424 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2425 / sizeof(unsigned int); 2426 2427 if (*reply_len < ret_size*sizeof(unsigned int)) { 2428 codec_dbg(codec, "reply too long for buf\n"); 2429 return -EINVAL; 2430 } else if (ret_size != reply_data_size) { 2431 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2432 return -EINVAL; 2433 } else if (!reply) { 2434 codec_dbg(codec, "NULL reply\n"); 2435 return -EINVAL; 2436 } else { 2437 *reply_len = ret_size*sizeof(unsigned int); 2438 memcpy(reply, scp_reply.data, *reply_len); 2439 } 2440 } else { 2441 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2442 return -EIO; 2443 } 2444 2445 return status; 2446 } 2447 2448 /* 2449 * Set DSP parameters 2450 */ 2451 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2452 int src_id, int req, const void *data, unsigned int len) 2453 { 2454 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2455 NULL); 2456 } 2457 2458 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2459 int req, const unsigned int data) 2460 { 2461 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2462 sizeof(unsigned int)); 2463 } 2464 2465 /* 2466 * Allocate a DSP DMA channel via an SCP message 2467 */ 2468 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2469 { 2470 int status = 0; 2471 unsigned int size = sizeof(*dma_chan); 2472 2473 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2474 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2475 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2476 dma_chan, &size); 2477 2478 if (status < 0) { 2479 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2480 return status; 2481 } 2482 2483 if ((*dma_chan + 1) == 0) { 2484 codec_dbg(codec, "no free dma channels to allocate\n"); 2485 return -EBUSY; 2486 } 2487 2488 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2489 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2490 2491 return status; 2492 } 2493 2494 /* 2495 * Free a DSP DMA via an SCP message 2496 */ 2497 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2498 { 2499 int status = 0; 2500 unsigned int dummy = 0; 2501 2502 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2503 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2504 2505 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2506 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2507 sizeof(dma_chan), NULL, &dummy); 2508 2509 if (status < 0) { 2510 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2511 return status; 2512 } 2513 2514 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2515 2516 return status; 2517 } 2518 2519 /* 2520 * (Re)start the DSP 2521 */ 2522 static int dsp_set_run_state(struct hda_codec *codec) 2523 { 2524 unsigned int dbg_ctrl_reg; 2525 unsigned int halt_state; 2526 int err; 2527 2528 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2529 if (err < 0) 2530 return err; 2531 2532 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2533 DSP_DBGCNTL_STATE_LOBIT; 2534 2535 if (halt_state != 0) { 2536 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2537 DSP_DBGCNTL_SS_MASK); 2538 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2539 dbg_ctrl_reg); 2540 if (err < 0) 2541 return err; 2542 2543 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2544 DSP_DBGCNTL_EXEC_MASK; 2545 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2546 dbg_ctrl_reg); 2547 if (err < 0) 2548 return err; 2549 } 2550 2551 return 0; 2552 } 2553 2554 /* 2555 * Reset the DSP 2556 */ 2557 static int dsp_reset(struct hda_codec *codec) 2558 { 2559 unsigned int res; 2560 int retry = 20; 2561 2562 codec_dbg(codec, "dsp_reset\n"); 2563 do { 2564 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2565 retry--; 2566 } while (res == -EIO && retry); 2567 2568 if (!retry) { 2569 codec_dbg(codec, "dsp_reset timeout\n"); 2570 return -EIO; 2571 } 2572 2573 return 0; 2574 } 2575 2576 /* 2577 * Convert chip address to DSP address 2578 */ 2579 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2580 bool *code, bool *yram) 2581 { 2582 *code = *yram = false; 2583 2584 if (UC_RANGE(chip_addx, 1)) { 2585 *code = true; 2586 return UC_OFF(chip_addx); 2587 } else if (X_RANGE_ALL(chip_addx, 1)) { 2588 return X_OFF(chip_addx); 2589 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2590 *yram = true; 2591 return Y_OFF(chip_addx); 2592 } 2593 2594 return INVALID_CHIP_ADDRESS; 2595 } 2596 2597 /* 2598 * Check if the DSP DMA is active 2599 */ 2600 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2601 { 2602 unsigned int dma_chnlstart_reg; 2603 2604 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2605 2606 return ((dma_chnlstart_reg & (1 << 2607 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2608 } 2609 2610 static int dsp_dma_setup_common(struct hda_codec *codec, 2611 unsigned int chip_addx, 2612 unsigned int dma_chan, 2613 unsigned int port_map_mask, 2614 bool ovly) 2615 { 2616 int status = 0; 2617 unsigned int chnl_prop; 2618 unsigned int dsp_addx; 2619 unsigned int active; 2620 bool code, yram; 2621 2622 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2623 2624 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2625 codec_dbg(codec, "dma chan num invalid\n"); 2626 return -EINVAL; 2627 } 2628 2629 if (dsp_is_dma_active(codec, dma_chan)) { 2630 codec_dbg(codec, "dma already active\n"); 2631 return -EBUSY; 2632 } 2633 2634 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2635 2636 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2637 codec_dbg(codec, "invalid chip addr\n"); 2638 return -ENXIO; 2639 } 2640 2641 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2642 active = 0; 2643 2644 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2645 2646 if (ovly) { 2647 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2648 &chnl_prop); 2649 2650 if (status < 0) { 2651 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2652 return status; 2653 } 2654 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2655 } 2656 2657 if (!code) 2658 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2659 else 2660 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2661 2662 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2663 2664 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2665 if (status < 0) { 2666 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2667 return status; 2668 } 2669 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2670 2671 if (ovly) { 2672 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2673 &active); 2674 2675 if (status < 0) { 2676 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2677 return status; 2678 } 2679 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2680 } 2681 2682 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2683 DSPDMAC_ACTIVE_AAR_MASK; 2684 2685 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2686 if (status < 0) { 2687 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2688 return status; 2689 } 2690 2691 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2692 2693 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2694 port_map_mask); 2695 if (status < 0) { 2696 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2697 return status; 2698 } 2699 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2700 2701 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2702 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2703 if (status < 0) { 2704 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2705 return status; 2706 } 2707 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2708 2709 codec_dbg(codec, 2710 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2711 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2712 chip_addx, dsp_addx, dma_chan, 2713 port_map_mask, chnl_prop, active); 2714 2715 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2716 2717 return 0; 2718 } 2719 2720 /* 2721 * Setup the DSP DMA per-transfer-specific registers 2722 */ 2723 static int dsp_dma_setup(struct hda_codec *codec, 2724 unsigned int chip_addx, 2725 unsigned int count, 2726 unsigned int dma_chan) 2727 { 2728 int status = 0; 2729 bool code, yram; 2730 unsigned int dsp_addx; 2731 unsigned int addr_field; 2732 unsigned int incr_field; 2733 unsigned int base_cnt; 2734 unsigned int cur_cnt; 2735 unsigned int dma_cfg = 0; 2736 unsigned int adr_ofs = 0; 2737 unsigned int xfr_cnt = 0; 2738 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2739 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2740 2741 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2742 2743 if (count > max_dma_count) { 2744 codec_dbg(codec, "count too big\n"); 2745 return -EINVAL; 2746 } 2747 2748 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2749 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2750 codec_dbg(codec, "invalid chip addr\n"); 2751 return -ENXIO; 2752 } 2753 2754 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2755 2756 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2757 incr_field = 0; 2758 2759 if (!code) { 2760 addr_field <<= 1; 2761 if (yram) 2762 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2763 2764 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2765 } 2766 2767 dma_cfg = addr_field + incr_field; 2768 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2769 dma_cfg); 2770 if (status < 0) { 2771 codec_dbg(codec, "write DMACFG Reg fail\n"); 2772 return status; 2773 } 2774 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2775 2776 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2777 (code ? 0 : 1)); 2778 2779 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2780 adr_ofs); 2781 if (status < 0) { 2782 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2783 return status; 2784 } 2785 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2786 2787 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2788 2789 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2790 2791 xfr_cnt = base_cnt | cur_cnt; 2792 2793 status = chipio_write(codec, 2794 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2795 if (status < 0) { 2796 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2797 return status; 2798 } 2799 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2800 2801 codec_dbg(codec, 2802 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2803 "ADROFS=0x%x, XFRCNT=0x%x\n", 2804 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2805 2806 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2807 2808 return 0; 2809 } 2810 2811 /* 2812 * Start the DSP DMA 2813 */ 2814 static int dsp_dma_start(struct hda_codec *codec, 2815 unsigned int dma_chan, bool ovly) 2816 { 2817 unsigned int reg = 0; 2818 int status = 0; 2819 2820 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2821 2822 if (ovly) { 2823 status = chipio_read(codec, 2824 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2825 2826 if (status < 0) { 2827 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2828 return status; 2829 } 2830 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2831 2832 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2833 DSPDMAC_CHNLSTART_DIS_MASK); 2834 } 2835 2836 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2837 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2838 if (status < 0) { 2839 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2840 return status; 2841 } 2842 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2843 2844 return status; 2845 } 2846 2847 /* 2848 * Stop the DSP DMA 2849 */ 2850 static int dsp_dma_stop(struct hda_codec *codec, 2851 unsigned int dma_chan, bool ovly) 2852 { 2853 unsigned int reg = 0; 2854 int status = 0; 2855 2856 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2857 2858 if (ovly) { 2859 status = chipio_read(codec, 2860 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2861 2862 if (status < 0) { 2863 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2864 return status; 2865 } 2866 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2867 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2868 DSPDMAC_CHNLSTART_DIS_MASK); 2869 } 2870 2871 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2872 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2873 if (status < 0) { 2874 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2875 return status; 2876 } 2877 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2878 2879 return status; 2880 } 2881 2882 /** 2883 * dsp_allocate_router_ports - Allocate router ports 2884 * 2885 * @codec: the HDA codec 2886 * @num_chans: number of channels in the stream 2887 * @ports_per_channel: number of ports per channel 2888 * @start_device: start device 2889 * @port_map: pointer to the port list to hold the allocated ports 2890 * 2891 * Returns zero or a negative error code. 2892 */ 2893 static int dsp_allocate_router_ports(struct hda_codec *codec, 2894 unsigned int num_chans, 2895 unsigned int ports_per_channel, 2896 unsigned int start_device, 2897 unsigned int *port_map) 2898 { 2899 int status = 0; 2900 int res; 2901 u8 val; 2902 2903 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2904 if (status < 0) 2905 return status; 2906 2907 val = start_device << 6; 2908 val |= (ports_per_channel - 1) << 4; 2909 val |= num_chans - 1; 2910 2911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2912 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2913 val); 2914 2915 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2916 VENDOR_CHIPIO_PORT_ALLOC_SET, 2917 MEM_CONNID_DSP); 2918 2919 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2920 if (status < 0) 2921 return status; 2922 2923 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2924 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2925 2926 *port_map = res; 2927 2928 return (res < 0) ? res : 0; 2929 } 2930 2931 /* 2932 * Free router ports 2933 */ 2934 static int dsp_free_router_ports(struct hda_codec *codec) 2935 { 2936 int status = 0; 2937 2938 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2939 if (status < 0) 2940 return status; 2941 2942 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2943 VENDOR_CHIPIO_PORT_FREE_SET, 2944 MEM_CONNID_DSP); 2945 2946 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2947 2948 return status; 2949 } 2950 2951 /* 2952 * Allocate DSP ports for the download stream 2953 */ 2954 static int dsp_allocate_ports(struct hda_codec *codec, 2955 unsigned int num_chans, 2956 unsigned int rate_multi, unsigned int *port_map) 2957 { 2958 int status; 2959 2960 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2961 2962 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2963 codec_dbg(codec, "bad rate multiple\n"); 2964 return -EINVAL; 2965 } 2966 2967 status = dsp_allocate_router_ports(codec, num_chans, 2968 rate_multi, 0, port_map); 2969 2970 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2971 2972 return status; 2973 } 2974 2975 static int dsp_allocate_ports_format(struct hda_codec *codec, 2976 const unsigned short fmt, 2977 unsigned int *port_map) 2978 { 2979 unsigned int num_chans; 2980 2981 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2982 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2983 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2984 2985 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2986 codec_dbg(codec, "bad rate multiple\n"); 2987 return -EINVAL; 2988 } 2989 2990 num_chans = get_hdafmt_chs(fmt) + 1; 2991 2992 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2993 } 2994 2995 /* 2996 * free DSP ports 2997 */ 2998 static int dsp_free_ports(struct hda_codec *codec) 2999 { 3000 int status; 3001 3002 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 3003 3004 status = dsp_free_router_ports(codec); 3005 if (status < 0) { 3006 codec_dbg(codec, "free router ports fail\n"); 3007 return status; 3008 } 3009 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 3010 3011 return status; 3012 } 3013 3014 /* 3015 * HDA DMA engine stuffs for DSP code download 3016 */ 3017 struct dma_engine { 3018 struct hda_codec *codec; 3019 unsigned short m_converter_format; 3020 struct snd_dma_buffer *dmab; 3021 unsigned int buf_size; 3022 }; 3023 3024 3025 enum dma_state { 3026 DMA_STATE_STOP = 0, 3027 DMA_STATE_RUN = 1 3028 }; 3029 3030 static int dma_convert_to_hda_format(struct hda_codec *codec, 3031 unsigned int sample_rate, 3032 unsigned short channels, 3033 unsigned short *hda_format) 3034 { 3035 unsigned int format_val; 3036 3037 format_val = snd_hdac_stream_format(channels, 32, sample_rate); 3038 3039 if (hda_format) 3040 *hda_format = (unsigned short)format_val; 3041 3042 return 0; 3043 } 3044 3045 /* 3046 * Reset DMA for DSP download 3047 */ 3048 static int dma_reset(struct dma_engine *dma) 3049 { 3050 struct hda_codec *codec = dma->codec; 3051 struct ca0132_spec *spec = codec->spec; 3052 int status; 3053 3054 if (dma->dmab->area) 3055 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3056 3057 status = snd_hda_codec_load_dsp_prepare(codec, 3058 dma->m_converter_format, 3059 dma->buf_size, 3060 dma->dmab); 3061 if (status < 0) 3062 return status; 3063 spec->dsp_stream_id = status; 3064 return 0; 3065 } 3066 3067 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3068 { 3069 bool cmd; 3070 3071 switch (state) { 3072 case DMA_STATE_STOP: 3073 cmd = false; 3074 break; 3075 case DMA_STATE_RUN: 3076 cmd = true; 3077 break; 3078 default: 3079 return 0; 3080 } 3081 3082 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3083 return 0; 3084 } 3085 3086 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3087 { 3088 return dma->dmab->bytes; 3089 } 3090 3091 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3092 { 3093 return dma->dmab->area; 3094 } 3095 3096 static int dma_xfer(struct dma_engine *dma, 3097 const unsigned int *data, 3098 unsigned int count) 3099 { 3100 memcpy(dma->dmab->area, data, count); 3101 return 0; 3102 } 3103 3104 static void dma_get_converter_format( 3105 struct dma_engine *dma, 3106 unsigned short *format) 3107 { 3108 if (format) 3109 *format = dma->m_converter_format; 3110 } 3111 3112 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3113 { 3114 struct ca0132_spec *spec = dma->codec->spec; 3115 3116 return spec->dsp_stream_id; 3117 } 3118 3119 struct dsp_image_seg { 3120 u32 magic; 3121 u32 chip_addr; 3122 u32 count; 3123 u32 data[]; 3124 }; 3125 3126 static const u32 g_magic_value = 0x4c46584d; 3127 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3128 3129 static bool is_valid(const struct dsp_image_seg *p) 3130 { 3131 return p->magic == g_magic_value; 3132 } 3133 3134 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3135 { 3136 return g_chip_addr_magic_value == p->chip_addr; 3137 } 3138 3139 static bool is_last(const struct dsp_image_seg *p) 3140 { 3141 return p->count == 0; 3142 } 3143 3144 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3145 { 3146 return struct_size(p, data, p->count); 3147 } 3148 3149 static const struct dsp_image_seg *get_next_seg_ptr( 3150 const struct dsp_image_seg *p) 3151 { 3152 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3153 } 3154 3155 /* 3156 * CA0132 chip DSP transfer stuffs. For DSP download. 3157 */ 3158 #define INVALID_DMA_CHANNEL (~0U) 3159 3160 /* 3161 * Program a list of address/data pairs via the ChipIO widget. 3162 * The segment data is in the format of successive pairs of words. 3163 * These are repeated as indicated by the segment's count field. 3164 */ 3165 static int dspxfr_hci_write(struct hda_codec *codec, 3166 const struct dsp_image_seg *fls) 3167 { 3168 int status; 3169 const u32 *data; 3170 unsigned int count; 3171 3172 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3173 codec_dbg(codec, "hci_write invalid params\n"); 3174 return -EINVAL; 3175 } 3176 3177 count = fls->count; 3178 data = (u32 *)(fls->data); 3179 while (count >= 2) { 3180 status = chipio_write(codec, data[0], data[1]); 3181 if (status < 0) { 3182 codec_dbg(codec, "hci_write chipio failed\n"); 3183 return status; 3184 } 3185 count -= 2; 3186 data += 2; 3187 } 3188 return 0; 3189 } 3190 3191 /** 3192 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3193 * 3194 * @codec: the HDA codec 3195 * @fls: pointer to a fast load image 3196 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3197 * no relocation 3198 * @dma_engine: pointer to DMA engine to be used for DSP download 3199 * @dma_chan: The number of DMA channels used for DSP download 3200 * @port_map_mask: port mapping 3201 * @ovly: TRUE if overlay format is required 3202 * 3203 * Returns zero or a negative error code. 3204 */ 3205 static int dspxfr_one_seg(struct hda_codec *codec, 3206 const struct dsp_image_seg *fls, 3207 unsigned int reloc, 3208 struct dma_engine *dma_engine, 3209 unsigned int dma_chan, 3210 unsigned int port_map_mask, 3211 bool ovly) 3212 { 3213 int status = 0; 3214 bool comm_dma_setup_done = false; 3215 const unsigned int *data; 3216 unsigned int chip_addx; 3217 unsigned int words_to_write; 3218 unsigned int buffer_size_words; 3219 unsigned char *buffer_addx; 3220 unsigned short hda_format; 3221 unsigned int sample_rate_div; 3222 unsigned int sample_rate_mul; 3223 unsigned int num_chans; 3224 unsigned int hda_frame_size_words; 3225 unsigned int remainder_words; 3226 const u32 *data_remainder; 3227 u32 chip_addx_remainder; 3228 unsigned int run_size_words; 3229 const struct dsp_image_seg *hci_write = NULL; 3230 unsigned long timeout; 3231 bool dma_active; 3232 3233 if (fls == NULL) 3234 return -EINVAL; 3235 if (is_hci_prog_list_seg(fls)) { 3236 hci_write = fls; 3237 fls = get_next_seg_ptr(fls); 3238 } 3239 3240 if (hci_write && (!fls || is_last(fls))) { 3241 codec_dbg(codec, "hci_write\n"); 3242 return dspxfr_hci_write(codec, hci_write); 3243 } 3244 3245 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3246 codec_dbg(codec, "Invalid Params\n"); 3247 return -EINVAL; 3248 } 3249 3250 data = fls->data; 3251 chip_addx = fls->chip_addr; 3252 words_to_write = fls->count; 3253 3254 if (!words_to_write) 3255 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3256 if (reloc) 3257 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3258 3259 if (!UC_RANGE(chip_addx, words_to_write) && 3260 !X_RANGE_ALL(chip_addx, words_to_write) && 3261 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3262 codec_dbg(codec, "Invalid chip_addx Params\n"); 3263 return -EINVAL; 3264 } 3265 3266 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3267 sizeof(u32); 3268 3269 buffer_addx = dma_get_buffer_addr(dma_engine); 3270 3271 if (buffer_addx == NULL) { 3272 codec_dbg(codec, "dma_engine buffer NULL\n"); 3273 return -EINVAL; 3274 } 3275 3276 dma_get_converter_format(dma_engine, &hda_format); 3277 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3278 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3279 num_chans = get_hdafmt_chs(hda_format) + 1; 3280 3281 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3282 (num_chans * sample_rate_mul / sample_rate_div)); 3283 3284 if (hda_frame_size_words == 0) { 3285 codec_dbg(codec, "frmsz zero\n"); 3286 return -EINVAL; 3287 } 3288 3289 buffer_size_words = min(buffer_size_words, 3290 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3291 65536 : 32768)); 3292 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3293 codec_dbg(codec, 3294 "chpadr=0x%08x frmsz=%u nchan=%u " 3295 "rate_mul=%u div=%u bufsz=%u\n", 3296 chip_addx, hda_frame_size_words, num_chans, 3297 sample_rate_mul, sample_rate_div, buffer_size_words); 3298 3299 if (buffer_size_words < hda_frame_size_words) { 3300 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3301 return -EINVAL; 3302 } 3303 3304 remainder_words = words_to_write % hda_frame_size_words; 3305 data_remainder = data; 3306 chip_addx_remainder = chip_addx; 3307 3308 data += remainder_words; 3309 chip_addx += remainder_words*sizeof(u32); 3310 words_to_write -= remainder_words; 3311 3312 while (words_to_write != 0) { 3313 run_size_words = min(buffer_size_words, words_to_write); 3314 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3315 words_to_write, run_size_words, remainder_words); 3316 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3317 if (!comm_dma_setup_done) { 3318 status = dsp_dma_stop(codec, dma_chan, ovly); 3319 if (status < 0) 3320 return status; 3321 status = dsp_dma_setup_common(codec, chip_addx, 3322 dma_chan, port_map_mask, ovly); 3323 if (status < 0) 3324 return status; 3325 comm_dma_setup_done = true; 3326 } 3327 3328 status = dsp_dma_setup(codec, chip_addx, 3329 run_size_words, dma_chan); 3330 if (status < 0) 3331 return status; 3332 status = dsp_dma_start(codec, dma_chan, ovly); 3333 if (status < 0) 3334 return status; 3335 if (!dsp_is_dma_active(codec, dma_chan)) { 3336 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3337 return -EIO; 3338 } 3339 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3340 if (status < 0) 3341 return status; 3342 if (remainder_words != 0) { 3343 status = chipio_write_multiple(codec, 3344 chip_addx_remainder, 3345 data_remainder, 3346 remainder_words); 3347 if (status < 0) 3348 return status; 3349 remainder_words = 0; 3350 } 3351 if (hci_write) { 3352 status = dspxfr_hci_write(codec, hci_write); 3353 if (status < 0) 3354 return status; 3355 hci_write = NULL; 3356 } 3357 3358 timeout = jiffies + msecs_to_jiffies(2000); 3359 do { 3360 dma_active = dsp_is_dma_active(codec, dma_chan); 3361 if (!dma_active) 3362 break; 3363 msleep(20); 3364 } while (time_before(jiffies, timeout)); 3365 if (dma_active) 3366 break; 3367 3368 codec_dbg(codec, "+++++ DMA complete\n"); 3369 dma_set_state(dma_engine, DMA_STATE_STOP); 3370 status = dma_reset(dma_engine); 3371 3372 if (status < 0) 3373 return status; 3374 3375 data += run_size_words; 3376 chip_addx += run_size_words*sizeof(u32); 3377 words_to_write -= run_size_words; 3378 } 3379 3380 if (remainder_words != 0) { 3381 status = chipio_write_multiple(codec, chip_addx_remainder, 3382 data_remainder, remainder_words); 3383 } 3384 3385 return status; 3386 } 3387 3388 /** 3389 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3390 * 3391 * @codec: the HDA codec 3392 * @fls_data: pointer to a fast load image 3393 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3394 * no relocation 3395 * @sample_rate: sampling rate of the stream used for DSP download 3396 * @channels: channels of the stream used for DSP download 3397 * @ovly: TRUE if overlay format is required 3398 * 3399 * Returns zero or a negative error code. 3400 */ 3401 static int dspxfr_image(struct hda_codec *codec, 3402 const struct dsp_image_seg *fls_data, 3403 unsigned int reloc, 3404 unsigned int sample_rate, 3405 unsigned short channels, 3406 bool ovly) 3407 { 3408 struct ca0132_spec *spec = codec->spec; 3409 int status; 3410 unsigned short hda_format = 0; 3411 unsigned int response; 3412 unsigned char stream_id = 0; 3413 struct dma_engine *dma_engine; 3414 unsigned int dma_chan; 3415 unsigned int port_map_mask; 3416 3417 if (fls_data == NULL) 3418 return -EINVAL; 3419 3420 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3421 if (!dma_engine) 3422 return -ENOMEM; 3423 3424 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3425 if (!dma_engine->dmab) { 3426 kfree(dma_engine); 3427 return -ENOMEM; 3428 } 3429 3430 dma_engine->codec = codec; 3431 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3432 dma_engine->m_converter_format = hda_format; 3433 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3434 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3435 3436 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3437 3438 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3439 hda_format, &response); 3440 3441 if (status < 0) { 3442 codec_dbg(codec, "set converter format fail\n"); 3443 goto exit; 3444 } 3445 3446 status = snd_hda_codec_load_dsp_prepare(codec, 3447 dma_engine->m_converter_format, 3448 dma_engine->buf_size, 3449 dma_engine->dmab); 3450 if (status < 0) 3451 goto exit; 3452 spec->dsp_stream_id = status; 3453 3454 if (ovly) { 3455 status = dspio_alloc_dma_chan(codec, &dma_chan); 3456 if (status < 0) { 3457 codec_dbg(codec, "alloc dmachan fail\n"); 3458 dma_chan = INVALID_DMA_CHANNEL; 3459 goto exit; 3460 } 3461 } 3462 3463 port_map_mask = 0; 3464 status = dsp_allocate_ports_format(codec, hda_format, 3465 &port_map_mask); 3466 if (status < 0) { 3467 codec_dbg(codec, "alloc ports fail\n"); 3468 goto exit; 3469 } 3470 3471 stream_id = dma_get_stream_id(dma_engine); 3472 status = codec_set_converter_stream_channel(codec, 3473 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3474 if (status < 0) { 3475 codec_dbg(codec, "set stream chan fail\n"); 3476 goto exit; 3477 } 3478 3479 while ((fls_data != NULL) && !is_last(fls_data)) { 3480 if (!is_valid(fls_data)) { 3481 codec_dbg(codec, "FLS check fail\n"); 3482 status = -EINVAL; 3483 goto exit; 3484 } 3485 status = dspxfr_one_seg(codec, fls_data, reloc, 3486 dma_engine, dma_chan, 3487 port_map_mask, ovly); 3488 if (status < 0) 3489 break; 3490 3491 if (is_hci_prog_list_seg(fls_data)) 3492 fls_data = get_next_seg_ptr(fls_data); 3493 3494 if ((fls_data != NULL) && !is_last(fls_data)) 3495 fls_data = get_next_seg_ptr(fls_data); 3496 } 3497 3498 if (port_map_mask != 0) 3499 status = dsp_free_ports(codec); 3500 3501 if (status < 0) 3502 goto exit; 3503 3504 status = codec_set_converter_stream_channel(codec, 3505 WIDGET_CHIP_CTRL, 0, 0, &response); 3506 3507 exit: 3508 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3509 dspio_free_dma_chan(codec, dma_chan); 3510 3511 if (dma_engine->dmab->area) 3512 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3513 kfree(dma_engine->dmab); 3514 kfree(dma_engine); 3515 3516 return status; 3517 } 3518 3519 /* 3520 * CA0132 DSP download stuffs. 3521 */ 3522 static void dspload_post_setup(struct hda_codec *codec) 3523 { 3524 struct ca0132_spec *spec = codec->spec; 3525 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3526 if (!ca0132_use_alt_functions(spec)) { 3527 /*set DSP speaker to 2.0 configuration*/ 3528 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3529 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3530 3531 /*update write pointer*/ 3532 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3533 } 3534 } 3535 3536 /** 3537 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3538 * 3539 * @codec: the HDA codec 3540 * @fls: pointer to a fast load image 3541 * @ovly: TRUE if overlay format is required 3542 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3543 * no relocation 3544 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3545 * @router_chans: number of audio router channels to be allocated (0 means use 3546 * internal defaults; max is 32) 3547 * 3548 * Download DSP from a DSP Image Fast Load structure. This structure is a 3549 * linear, non-constant sized element array of structures, each of which 3550 * contain the count of the data to be loaded, the data itself, and the 3551 * corresponding starting chip address of the starting data location. 3552 * Returns zero or a negative error code. 3553 */ 3554 static int dspload_image(struct hda_codec *codec, 3555 const struct dsp_image_seg *fls, 3556 bool ovly, 3557 unsigned int reloc, 3558 bool autostart, 3559 int router_chans) 3560 { 3561 int status = 0; 3562 unsigned int sample_rate; 3563 unsigned short channels; 3564 3565 codec_dbg(codec, "---- dspload_image begin ------\n"); 3566 if (router_chans == 0) { 3567 if (!ovly) 3568 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3569 else 3570 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3571 } 3572 3573 sample_rate = 48000; 3574 channels = (unsigned short)router_chans; 3575 3576 while (channels > 16) { 3577 sample_rate *= 2; 3578 channels /= 2; 3579 } 3580 3581 do { 3582 codec_dbg(codec, "Ready to program DMA\n"); 3583 if (!ovly) 3584 status = dsp_reset(codec); 3585 3586 if (status < 0) 3587 break; 3588 3589 codec_dbg(codec, "dsp_reset() complete\n"); 3590 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3591 ovly); 3592 3593 if (status < 0) 3594 break; 3595 3596 codec_dbg(codec, "dspxfr_image() complete\n"); 3597 if (autostart && !ovly) { 3598 dspload_post_setup(codec); 3599 status = dsp_set_run_state(codec); 3600 } 3601 3602 codec_dbg(codec, "LOAD FINISHED\n"); 3603 } while (0); 3604 3605 return status; 3606 } 3607 3608 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3609 static bool dspload_is_loaded(struct hda_codec *codec) 3610 { 3611 unsigned int data = 0; 3612 int status = 0; 3613 3614 status = chipio_read(codec, 0x40004, &data); 3615 if ((status < 0) || (data != 1)) 3616 return false; 3617 3618 return true; 3619 } 3620 #else 3621 #define dspload_is_loaded(codec) false 3622 #endif 3623 3624 static bool dspload_wait_loaded(struct hda_codec *codec) 3625 { 3626 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3627 3628 do { 3629 if (dspload_is_loaded(codec)) { 3630 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3631 return true; 3632 } 3633 msleep(20); 3634 } while (time_before(jiffies, timeout)); 3635 3636 codec_err(codec, "ca0132 failed to download DSP\n"); 3637 return false; 3638 } 3639 3640 /* 3641 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3642 * based cards, and has a second mmio region, region2, that's used for special 3643 * commands. 3644 */ 3645 3646 /* 3647 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3648 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3649 * The first eight bits are just the number of the pin. So far, I've only seen 3650 * this number go to 7. 3651 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3652 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3653 * then off to send that bit. 3654 */ 3655 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3656 bool enable) 3657 { 3658 struct ca0132_spec *spec = codec->spec; 3659 unsigned short gpio_data; 3660 3661 gpio_data = gpio_pin & 0xF; 3662 gpio_data |= ((enable << 8) & 0x100); 3663 3664 writew(gpio_data, spec->mem_base + 0x320); 3665 } 3666 3667 /* 3668 * Special pci region2 commands that are only used by the AE-5. They follow 3669 * a set format, and require reads at certain points to seemingly 'clear' 3670 * the response data. My first tests didn't do these reads, and would cause 3671 * the card to get locked up until the memory was read. These commands 3672 * seem to work with three distinct values that I've taken to calling group, 3673 * target-id, and value. 3674 */ 3675 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3676 unsigned int target, unsigned int value) 3677 { 3678 struct ca0132_spec *spec = codec->spec; 3679 unsigned int write_val; 3680 3681 writel(0x0000007e, spec->mem_base + 0x210); 3682 readl(spec->mem_base + 0x210); 3683 writel(0x0000005a, spec->mem_base + 0x210); 3684 readl(spec->mem_base + 0x210); 3685 readl(spec->mem_base + 0x210); 3686 3687 writel(0x00800005, spec->mem_base + 0x20c); 3688 writel(group, spec->mem_base + 0x804); 3689 3690 writel(0x00800005, spec->mem_base + 0x20c); 3691 write_val = (target & 0xff); 3692 write_val |= (value << 8); 3693 3694 3695 writel(write_val, spec->mem_base + 0x204); 3696 /* 3697 * Need delay here or else it goes too fast and works inconsistently. 3698 */ 3699 msleep(20); 3700 3701 readl(spec->mem_base + 0x860); 3702 readl(spec->mem_base + 0x854); 3703 readl(spec->mem_base + 0x840); 3704 3705 writel(0x00800004, spec->mem_base + 0x20c); 3706 writel(0x00000000, spec->mem_base + 0x210); 3707 readl(spec->mem_base + 0x210); 3708 readl(spec->mem_base + 0x210); 3709 } 3710 3711 /* 3712 * This second type of command is used for setting the sound filter type. 3713 */ 3714 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3715 unsigned int group, unsigned int target, unsigned int value) 3716 { 3717 struct ca0132_spec *spec = codec->spec; 3718 unsigned int write_val; 3719 3720 writel(0x0000007e, spec->mem_base + 0x210); 3721 readl(spec->mem_base + 0x210); 3722 writel(0x0000005a, spec->mem_base + 0x210); 3723 readl(spec->mem_base + 0x210); 3724 readl(spec->mem_base + 0x210); 3725 3726 writel(0x00800003, spec->mem_base + 0x20c); 3727 writel(group, spec->mem_base + 0x804); 3728 3729 writel(0x00800005, spec->mem_base + 0x20c); 3730 write_val = (target & 0xff); 3731 write_val |= (value << 8); 3732 3733 3734 writel(write_val, spec->mem_base + 0x204); 3735 msleep(20); 3736 readl(spec->mem_base + 0x860); 3737 readl(spec->mem_base + 0x854); 3738 readl(spec->mem_base + 0x840); 3739 3740 writel(0x00800004, spec->mem_base + 0x20c); 3741 writel(0x00000000, spec->mem_base + 0x210); 3742 readl(spec->mem_base + 0x210); 3743 readl(spec->mem_base + 0x210); 3744 } 3745 3746 /* 3747 * Setup GPIO for the other variants of Core3D. 3748 */ 3749 3750 /* 3751 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3752 * the card shows as having no GPIO pins. 3753 */ 3754 static void ca0132_gpio_init(struct hda_codec *codec) 3755 { 3756 struct ca0132_spec *spec = codec->spec; 3757 3758 switch (ca0132_quirk(spec)) { 3759 case QUIRK_SBZ: 3760 case QUIRK_AE5: 3761 case QUIRK_AE7: 3762 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3763 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3764 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3765 break; 3766 case QUIRK_R3DI: 3767 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3768 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3769 break; 3770 default: 3771 break; 3772 } 3773 3774 } 3775 3776 /* Sets the GPIO for audio output. */ 3777 static void ca0132_gpio_setup(struct hda_codec *codec) 3778 { 3779 struct ca0132_spec *spec = codec->spec; 3780 3781 switch (ca0132_quirk(spec)) { 3782 case QUIRK_SBZ: 3783 snd_hda_codec_write(codec, 0x01, 0, 3784 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3785 snd_hda_codec_write(codec, 0x01, 0, 3786 AC_VERB_SET_GPIO_MASK, 0x07); 3787 snd_hda_codec_write(codec, 0x01, 0, 3788 AC_VERB_SET_GPIO_DATA, 0x04); 3789 snd_hda_codec_write(codec, 0x01, 0, 3790 AC_VERB_SET_GPIO_DATA, 0x06); 3791 break; 3792 case QUIRK_R3DI: 3793 snd_hda_codec_write(codec, 0x01, 0, 3794 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3795 snd_hda_codec_write(codec, 0x01, 0, 3796 AC_VERB_SET_GPIO_MASK, 0x1F); 3797 snd_hda_codec_write(codec, 0x01, 0, 3798 AC_VERB_SET_GPIO_DATA, 0x0C); 3799 break; 3800 default: 3801 break; 3802 } 3803 } 3804 3805 /* 3806 * GPIO control functions for the Recon3D integrated. 3807 */ 3808 3809 enum r3di_gpio_bit { 3810 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3811 R3DI_MIC_SELECT_BIT = 1, 3812 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3813 R3DI_OUT_SELECT_BIT = 2, 3814 /* 3815 * I dunno what this actually does, but it stays on until the dsp 3816 * is downloaded. 3817 */ 3818 R3DI_GPIO_DSP_DOWNLOADING = 3, 3819 /* 3820 * Same as above, no clue what it does, but it comes on after the dsp 3821 * is downloaded. 3822 */ 3823 R3DI_GPIO_DSP_DOWNLOADED = 4 3824 }; 3825 3826 enum r3di_mic_select { 3827 /* Set GPIO bit 1 to 0 for rear mic */ 3828 R3DI_REAR_MIC = 0, 3829 /* Set GPIO bit 1 to 1 for front microphone*/ 3830 R3DI_FRONT_MIC = 1 3831 }; 3832 3833 enum r3di_out_select { 3834 /* Set GPIO bit 2 to 0 for headphone */ 3835 R3DI_HEADPHONE_OUT = 0, 3836 /* Set GPIO bit 2 to 1 for speaker */ 3837 R3DI_LINE_OUT = 1 3838 }; 3839 enum r3di_dsp_status { 3840 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3841 R3DI_DSP_DOWNLOADING = 0, 3842 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3843 R3DI_DSP_DOWNLOADED = 1 3844 }; 3845 3846 3847 static void r3di_gpio_mic_set(struct hda_codec *codec, 3848 enum r3di_mic_select cur_mic) 3849 { 3850 unsigned int cur_gpio; 3851 3852 /* Get the current GPIO Data setup */ 3853 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3854 3855 switch (cur_mic) { 3856 case R3DI_REAR_MIC: 3857 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3858 break; 3859 case R3DI_FRONT_MIC: 3860 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3861 break; 3862 } 3863 snd_hda_codec_write(codec, codec->core.afg, 0, 3864 AC_VERB_SET_GPIO_DATA, cur_gpio); 3865 } 3866 3867 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3868 enum r3di_dsp_status dsp_status) 3869 { 3870 unsigned int cur_gpio; 3871 3872 /* Get the current GPIO Data setup */ 3873 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3874 3875 switch (dsp_status) { 3876 case R3DI_DSP_DOWNLOADING: 3877 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3878 snd_hda_codec_write(codec, codec->core.afg, 0, 3879 AC_VERB_SET_GPIO_DATA, cur_gpio); 3880 break; 3881 case R3DI_DSP_DOWNLOADED: 3882 /* Set DOWNLOADING bit to 0. */ 3883 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3884 3885 snd_hda_codec_write(codec, codec->core.afg, 0, 3886 AC_VERB_SET_GPIO_DATA, cur_gpio); 3887 3888 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3889 break; 3890 } 3891 3892 snd_hda_codec_write(codec, codec->core.afg, 0, 3893 AC_VERB_SET_GPIO_DATA, cur_gpio); 3894 } 3895 3896 /* 3897 * PCM callbacks 3898 */ 3899 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3900 struct hda_codec *codec, 3901 unsigned int stream_tag, 3902 unsigned int format, 3903 struct snd_pcm_substream *substream) 3904 { 3905 struct ca0132_spec *spec = codec->spec; 3906 3907 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3908 3909 return 0; 3910 } 3911 3912 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3913 struct hda_codec *codec, 3914 struct snd_pcm_substream *substream) 3915 { 3916 struct ca0132_spec *spec = codec->spec; 3917 3918 if (spec->dsp_state == DSP_DOWNLOADING) 3919 return 0; 3920 3921 /*If Playback effects are on, allow stream some time to flush 3922 *effects tail*/ 3923 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3924 msleep(50); 3925 3926 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3927 3928 return 0; 3929 } 3930 3931 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3932 struct hda_codec *codec, 3933 struct snd_pcm_substream *substream) 3934 { 3935 struct ca0132_spec *spec = codec->spec; 3936 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3937 struct snd_pcm_runtime *runtime = substream->runtime; 3938 3939 if (spec->dsp_state != DSP_DOWNLOADED) 3940 return 0; 3941 3942 /* Add latency if playback enhancement and either effect is enabled. */ 3943 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3944 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3945 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3946 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3947 } 3948 3949 /* Applying Speaker EQ adds latency as well. */ 3950 if (spec->cur_out_type == SPEAKER_OUT) 3951 latency += DSP_SPEAKER_OUT_LATENCY; 3952 3953 return (latency * runtime->rate) / 1000; 3954 } 3955 3956 /* 3957 * Digital out 3958 */ 3959 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3960 struct hda_codec *codec, 3961 struct snd_pcm_substream *substream) 3962 { 3963 struct ca0132_spec *spec = codec->spec; 3964 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3965 } 3966 3967 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3968 struct hda_codec *codec, 3969 unsigned int stream_tag, 3970 unsigned int format, 3971 struct snd_pcm_substream *substream) 3972 { 3973 struct ca0132_spec *spec = codec->spec; 3974 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3975 stream_tag, format, substream); 3976 } 3977 3978 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3979 struct hda_codec *codec, 3980 struct snd_pcm_substream *substream) 3981 { 3982 struct ca0132_spec *spec = codec->spec; 3983 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3984 } 3985 3986 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3987 struct hda_codec *codec, 3988 struct snd_pcm_substream *substream) 3989 { 3990 struct ca0132_spec *spec = codec->spec; 3991 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3992 } 3993 3994 /* 3995 * Analog capture 3996 */ 3997 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3998 struct hda_codec *codec, 3999 unsigned int stream_tag, 4000 unsigned int format, 4001 struct snd_pcm_substream *substream) 4002 { 4003 snd_hda_codec_setup_stream(codec, hinfo->nid, 4004 stream_tag, 0, format); 4005 4006 return 0; 4007 } 4008 4009 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 4010 struct hda_codec *codec, 4011 struct snd_pcm_substream *substream) 4012 { 4013 struct ca0132_spec *spec = codec->spec; 4014 4015 if (spec->dsp_state == DSP_DOWNLOADING) 4016 return 0; 4017 4018 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 4019 return 0; 4020 } 4021 4022 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 4023 struct hda_codec *codec, 4024 struct snd_pcm_substream *substream) 4025 { 4026 struct ca0132_spec *spec = codec->spec; 4027 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 4028 struct snd_pcm_runtime *runtime = substream->runtime; 4029 4030 if (spec->dsp_state != DSP_DOWNLOADED) 4031 return 0; 4032 4033 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4034 latency += DSP_CRYSTAL_VOICE_LATENCY; 4035 4036 return (latency * runtime->rate) / 1000; 4037 } 4038 4039 /* 4040 * Controls stuffs. 4041 */ 4042 4043 /* 4044 * Mixer controls helpers. 4045 */ 4046 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4047 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4048 .name = xname, \ 4049 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4050 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4051 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4052 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4053 .info = ca0132_volume_info, \ 4054 .get = ca0132_volume_get, \ 4055 .put = ca0132_volume_put, \ 4056 .tlv = { .c = ca0132_volume_tlv }, \ 4057 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4058 4059 /* 4060 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4061 * volume put, which is used for setting the DSP volume. This was done because 4062 * the ca0132 functions were taking too much time and causing lag. 4063 */ 4064 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4065 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4066 .name = xname, \ 4067 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4068 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4069 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4070 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4071 .info = snd_hda_mixer_amp_volume_info, \ 4072 .get = snd_hda_mixer_amp_volume_get, \ 4073 .put = ca0132_alt_volume_put, \ 4074 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4075 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4076 4077 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4078 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4079 .name = xname, \ 4080 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4081 .info = snd_hda_mixer_amp_switch_info, \ 4082 .get = ca0132_switch_get, \ 4083 .put = ca0132_switch_put, \ 4084 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4085 4086 /* stereo */ 4087 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4088 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4089 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4090 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4091 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4092 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4093 4094 /* lookup tables */ 4095 /* 4096 * Lookup table with decibel values for the DSP. When volume is changed in 4097 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4098 * these values have decimal points, probably because the Windows driver 4099 * actually uses floating point. We can't here, so I made a lookup table of 4100 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4101 * DAC's, and 9 is the maximum. 4102 */ 4103 static const unsigned int float_vol_db_lookup[] = { 4104 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4105 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4106 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4107 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4108 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4109 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4110 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4111 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4112 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4113 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4114 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4115 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4116 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4117 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4118 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4119 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4120 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4121 }; 4122 4123 /* 4124 * This table counts from float 0 to 1 in increments of .01, which is 4125 * useful for a few different sliders. 4126 */ 4127 static const unsigned int float_zero_to_one_lookup[] = { 4128 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4129 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4130 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4131 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4132 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4133 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4134 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4135 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4136 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4137 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4138 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4139 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4140 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4141 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4142 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4143 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4144 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4145 }; 4146 4147 /* 4148 * This table counts from float 10 to 1000, which is the range of the x-bass 4149 * crossover slider in Windows. 4150 */ 4151 static const unsigned int float_xbass_xover_lookup[] = { 4152 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4153 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4154 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4155 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4156 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4157 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4158 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4159 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4160 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4161 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4162 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4163 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4164 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4165 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4166 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4167 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4168 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4169 }; 4170 4171 /* The following are for tuning of products */ 4172 #ifdef ENABLE_TUNING_CONTROLS 4173 4174 static const unsigned int voice_focus_vals_lookup[] = { 4175 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4176 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4177 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4178 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4179 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4180 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4181 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4182 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4183 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4184 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4185 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4186 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4187 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4188 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4189 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4190 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4191 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4192 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4193 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4194 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4195 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4196 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4197 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4198 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4199 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4200 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4201 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4202 }; 4203 4204 static const unsigned int mic_svm_vals_lookup[] = { 4205 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4206 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4207 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4208 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4209 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4210 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4211 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4212 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4213 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4214 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4215 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4216 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4217 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4218 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4219 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4220 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4221 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4222 }; 4223 4224 static const unsigned int equalizer_vals_lookup[] = { 4225 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4226 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4227 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4228 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4229 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4230 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4231 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4232 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4233 0x41C00000 4234 }; 4235 4236 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4237 const unsigned int *lookup, int idx) 4238 { 4239 int i = 0; 4240 4241 for (i = 0; i < TUNING_CTLS_COUNT; i++) 4242 if (nid == ca0132_tuning_ctls[i].nid) 4243 goto found; 4244 4245 return -EINVAL; 4246 found: 4247 snd_hda_power_up(codec); 4248 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4249 ca0132_tuning_ctls[i].req, 4250 &(lookup[idx]), sizeof(unsigned int)); 4251 snd_hda_power_down(codec); 4252 4253 return 1; 4254 } 4255 4256 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4257 struct snd_ctl_elem_value *ucontrol) 4258 { 4259 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4260 struct ca0132_spec *spec = codec->spec; 4261 hda_nid_t nid = get_amp_nid(kcontrol); 4262 long *valp = ucontrol->value.integer.value; 4263 int idx = nid - TUNING_CTL_START_NID; 4264 4265 *valp = spec->cur_ctl_vals[idx]; 4266 return 0; 4267 } 4268 4269 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4270 struct snd_ctl_elem_info *uinfo) 4271 { 4272 int chs = get_amp_channels(kcontrol); 4273 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4274 uinfo->count = chs == 3 ? 2 : 1; 4275 uinfo->value.integer.min = 20; 4276 uinfo->value.integer.max = 180; 4277 uinfo->value.integer.step = 1; 4278 4279 return 0; 4280 } 4281 4282 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4283 struct snd_ctl_elem_value *ucontrol) 4284 { 4285 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4286 struct ca0132_spec *spec = codec->spec; 4287 hda_nid_t nid = get_amp_nid(kcontrol); 4288 long *valp = ucontrol->value.integer.value; 4289 int idx; 4290 4291 idx = nid - TUNING_CTL_START_NID; 4292 /* any change? */ 4293 if (spec->cur_ctl_vals[idx] == *valp) 4294 return 0; 4295 4296 spec->cur_ctl_vals[idx] = *valp; 4297 4298 idx = *valp - 20; 4299 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4300 4301 return 1; 4302 } 4303 4304 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4305 struct snd_ctl_elem_info *uinfo) 4306 { 4307 int chs = get_amp_channels(kcontrol); 4308 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4309 uinfo->count = chs == 3 ? 2 : 1; 4310 uinfo->value.integer.min = 0; 4311 uinfo->value.integer.max = 100; 4312 uinfo->value.integer.step = 1; 4313 4314 return 0; 4315 } 4316 4317 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4318 struct snd_ctl_elem_value *ucontrol) 4319 { 4320 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4321 struct ca0132_spec *spec = codec->spec; 4322 hda_nid_t nid = get_amp_nid(kcontrol); 4323 long *valp = ucontrol->value.integer.value; 4324 int idx; 4325 4326 idx = nid - TUNING_CTL_START_NID; 4327 /* any change? */ 4328 if (spec->cur_ctl_vals[idx] == *valp) 4329 return 0; 4330 4331 spec->cur_ctl_vals[idx] = *valp; 4332 4333 idx = *valp; 4334 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4335 4336 return 0; 4337 } 4338 4339 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4340 struct snd_ctl_elem_info *uinfo) 4341 { 4342 int chs = get_amp_channels(kcontrol); 4343 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4344 uinfo->count = chs == 3 ? 2 : 1; 4345 uinfo->value.integer.min = 0; 4346 uinfo->value.integer.max = 48; 4347 uinfo->value.integer.step = 1; 4348 4349 return 0; 4350 } 4351 4352 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4353 struct snd_ctl_elem_value *ucontrol) 4354 { 4355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4356 struct ca0132_spec *spec = codec->spec; 4357 hda_nid_t nid = get_amp_nid(kcontrol); 4358 long *valp = ucontrol->value.integer.value; 4359 int idx; 4360 4361 idx = nid - TUNING_CTL_START_NID; 4362 /* any change? */ 4363 if (spec->cur_ctl_vals[idx] == *valp) 4364 return 0; 4365 4366 spec->cur_ctl_vals[idx] = *valp; 4367 4368 idx = *valp; 4369 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4370 4371 return 1; 4372 } 4373 4374 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4375 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4376 4377 static int add_tuning_control(struct hda_codec *codec, 4378 hda_nid_t pnid, hda_nid_t nid, 4379 const char *name, int dir) 4380 { 4381 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4382 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4383 struct snd_kcontrol_new knew = 4384 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4385 4386 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4387 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4388 knew.tlv.c = 0; 4389 knew.tlv.p = 0; 4390 switch (pnid) { 4391 case VOICE_FOCUS: 4392 knew.info = voice_focus_ctl_info; 4393 knew.get = tuning_ctl_get; 4394 knew.put = voice_focus_ctl_put; 4395 knew.tlv.p = voice_focus_db_scale; 4396 break; 4397 case MIC_SVM: 4398 knew.info = mic_svm_ctl_info; 4399 knew.get = tuning_ctl_get; 4400 knew.put = mic_svm_ctl_put; 4401 break; 4402 case EQUALIZER: 4403 knew.info = equalizer_ctl_info; 4404 knew.get = tuning_ctl_get; 4405 knew.put = equalizer_ctl_put; 4406 knew.tlv.p = eq_db_scale; 4407 break; 4408 default: 4409 return 0; 4410 } 4411 knew.private_value = 4412 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4413 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4414 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4415 } 4416 4417 static int add_tuning_ctls(struct hda_codec *codec) 4418 { 4419 int i; 4420 int err; 4421 4422 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4423 err = add_tuning_control(codec, 4424 ca0132_tuning_ctls[i].parent_nid, 4425 ca0132_tuning_ctls[i].nid, 4426 ca0132_tuning_ctls[i].name, 4427 ca0132_tuning_ctls[i].direct); 4428 if (err < 0) 4429 return err; 4430 } 4431 4432 return 0; 4433 } 4434 4435 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4436 { 4437 struct ca0132_spec *spec = codec->spec; 4438 int i; 4439 4440 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4441 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4442 /* SVM level defaults to 0.74. */ 4443 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4444 4445 /* EQ defaults to 0dB. */ 4446 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4447 spec->cur_ctl_vals[i] = 24; 4448 } 4449 #endif /*ENABLE_TUNING_CONTROLS*/ 4450 4451 /* 4452 * Select the active output. 4453 * If autodetect is enabled, output will be selected based on jack detection. 4454 * If jack inserted, headphone will be selected, else built-in speakers 4455 * If autodetect is disabled, output will be selected based on selection. 4456 */ 4457 static int ca0132_select_out(struct hda_codec *codec) 4458 { 4459 struct ca0132_spec *spec = codec->spec; 4460 unsigned int pin_ctl; 4461 int jack_present; 4462 int auto_jack; 4463 unsigned int tmp; 4464 int err; 4465 4466 codec_dbg(codec, "ca0132_select_out\n"); 4467 4468 snd_hda_power_up_pm(codec); 4469 4470 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4471 4472 if (auto_jack) 4473 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4474 else 4475 jack_present = 4476 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4477 4478 if (jack_present) 4479 spec->cur_out_type = HEADPHONE_OUT; 4480 else 4481 spec->cur_out_type = SPEAKER_OUT; 4482 4483 if (spec->cur_out_type == SPEAKER_OUT) { 4484 codec_dbg(codec, "ca0132_select_out speaker\n"); 4485 /*speaker out config*/ 4486 tmp = FLOAT_ONE; 4487 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4488 if (err < 0) 4489 goto exit; 4490 /*enable speaker EQ*/ 4491 tmp = FLOAT_ONE; 4492 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4493 if (err < 0) 4494 goto exit; 4495 4496 /* Setup EAPD */ 4497 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4498 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4499 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4500 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4501 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4502 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4503 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4504 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4505 4506 /* disable headphone node */ 4507 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4508 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4509 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4510 pin_ctl & ~PIN_HP); 4511 /* enable speaker node */ 4512 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4513 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4514 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4515 pin_ctl | PIN_OUT); 4516 } else { 4517 codec_dbg(codec, "ca0132_select_out hp\n"); 4518 /*headphone out config*/ 4519 tmp = FLOAT_ZERO; 4520 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4521 if (err < 0) 4522 goto exit; 4523 /*disable speaker EQ*/ 4524 tmp = FLOAT_ZERO; 4525 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4526 if (err < 0) 4527 goto exit; 4528 4529 /* Setup EAPD */ 4530 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4531 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4532 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4533 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4534 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4535 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4536 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4537 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4538 4539 /* disable speaker*/ 4540 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4541 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4542 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4543 pin_ctl & ~PIN_HP); 4544 /* enable headphone*/ 4545 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4546 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4547 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4548 pin_ctl | PIN_HP); 4549 } 4550 4551 exit: 4552 snd_hda_power_down_pm(codec); 4553 4554 return err < 0 ? err : 0; 4555 } 4556 4557 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4558 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4559 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4560 4561 static void ae5_mmio_select_out(struct hda_codec *codec) 4562 { 4563 struct ca0132_spec *spec = codec->spec; 4564 const struct ae_ca0113_output_set *out_cmds; 4565 unsigned int i; 4566 4567 if (ca0132_quirk(spec) == QUIRK_AE5) 4568 out_cmds = &ae5_ca0113_output_presets; 4569 else 4570 out_cmds = &ae7_ca0113_output_presets; 4571 4572 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4573 ca0113_mmio_command_set(codec, out_cmds->group[i], 4574 out_cmds->target[i], 4575 out_cmds->vals[spec->cur_out_type][i]); 4576 } 4577 4578 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4579 { 4580 struct ca0132_spec *spec = codec->spec; 4581 int quirk = ca0132_quirk(spec); 4582 unsigned int tmp; 4583 int err; 4584 4585 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4586 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4587 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4588 return 0; 4589 4590 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4591 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4592 err = dspio_set_uint_param(codec, 0x96, 4593 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4594 if (err < 0) 4595 return err; 4596 4597 /* When setting full-range rear, both rear and center/lfe are set. */ 4598 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4599 err = dspio_set_uint_param(codec, 0x96, 4600 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4601 if (err < 0) 4602 return err; 4603 4604 err = dspio_set_uint_param(codec, 0x96, 4605 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4606 if (err < 0) 4607 return err; 4608 4609 /* 4610 * Only the AE series cards set this value when setting full-range, 4611 * and it's always 1.0f. 4612 */ 4613 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4614 err = dspio_set_uint_param(codec, 0x96, 4615 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4616 if (err < 0) 4617 return err; 4618 } 4619 4620 return 0; 4621 } 4622 4623 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4624 bool val) 4625 { 4626 struct ca0132_spec *spec = codec->spec; 4627 unsigned int tmp; 4628 int err; 4629 4630 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4631 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4632 tmp = FLOAT_ONE; 4633 else 4634 tmp = FLOAT_ZERO; 4635 4636 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4637 if (err < 0) 4638 return err; 4639 4640 /* If it is enabled, make sure to set the crossover frequency. */ 4641 if (tmp) { 4642 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4643 err = dspio_set_uint_param(codec, 0x96, 4644 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4645 if (err < 0) 4646 return err; 4647 } 4648 4649 return 0; 4650 } 4651 4652 /* 4653 * These are the commands needed to setup output on each of the different card 4654 * types. 4655 */ 4656 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4657 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4658 { 4659 struct ca0132_spec *spec = codec->spec; 4660 int quirk = ca0132_quirk(spec); 4661 unsigned int i; 4662 4663 *quirk_data = NULL; 4664 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4665 if (quirk_out_set_data[i].quirk_id == quirk) { 4666 *quirk_data = &quirk_out_set_data[i]; 4667 return; 4668 } 4669 } 4670 } 4671 4672 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4673 { 4674 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4675 const struct ca0132_alt_out_set_info *out_info; 4676 struct ca0132_spec *spec = codec->spec; 4677 unsigned int i, gpio_data; 4678 int err; 4679 4680 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4681 if (!quirk_data) 4682 return 0; 4683 4684 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4685 if (quirk_data->is_ae_series) 4686 ae5_mmio_select_out(codec); 4687 4688 if (out_info->has_hda_gpio) { 4689 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4690 AC_VERB_GET_GPIO_DATA, 0); 4691 4692 if (out_info->hda_gpio_set) 4693 gpio_data |= (1 << out_info->hda_gpio_pin); 4694 else 4695 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4696 4697 snd_hda_codec_write(codec, codec->core.afg, 0, 4698 AC_VERB_SET_GPIO_DATA, gpio_data); 4699 } 4700 4701 if (out_info->mmio_gpio_count) { 4702 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4703 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4704 out_info->mmio_gpio_set[i]); 4705 } 4706 } 4707 4708 if (out_info->scp_cmds_count) { 4709 for (i = 0; i < out_info->scp_cmds_count; i++) { 4710 err = dspio_set_uint_param(codec, 4711 out_info->scp_cmd_mid[i], 4712 out_info->scp_cmd_req[i], 4713 out_info->scp_cmd_val[i]); 4714 if (err < 0) 4715 return err; 4716 } 4717 } 4718 4719 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4720 4721 if (out_info->has_chipio_write) { 4722 chipio_write(codec, out_info->chipio_write_addr, 4723 out_info->chipio_write_data); 4724 } 4725 4726 if (quirk_data->has_headphone_gain) { 4727 if (spec->cur_out_type != HEADPHONE_OUT) { 4728 if (quirk_data->is_ae_series) 4729 ae5_headphone_gain_set(codec, 2); 4730 else 4731 zxr_headphone_gain_set(codec, 0); 4732 } else { 4733 if (quirk_data->is_ae_series) 4734 ae5_headphone_gain_set(codec, 4735 spec->ae5_headphone_gain_val); 4736 else 4737 zxr_headphone_gain_set(codec, 4738 spec->zxr_gain_set); 4739 } 4740 } 4741 4742 return 0; 4743 } 4744 4745 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4746 bool out_enable, bool hp_enable) 4747 { 4748 unsigned int pin_ctl; 4749 4750 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4751 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4752 4753 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4754 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4755 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4756 } 4757 4758 /* 4759 * This function behaves similarly to the ca0132_select_out funciton above, 4760 * except with a few differences. It adds the ability to select the current 4761 * output with an enumerated control "output source" if the auto detect 4762 * mute switch is set to off. If the auto detect mute switch is enabled, it 4763 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4764 * It also adds the ability to auto-detect the front headphone port. 4765 */ 4766 static int ca0132_alt_select_out(struct hda_codec *codec) 4767 { 4768 struct ca0132_spec *spec = codec->spec; 4769 unsigned int tmp, outfx_set; 4770 int jack_present; 4771 int auto_jack; 4772 int err; 4773 /* Default Headphone is rear headphone */ 4774 hda_nid_t headphone_nid = spec->out_pins[1]; 4775 4776 codec_dbg(codec, "%s\n", __func__); 4777 4778 snd_hda_power_up_pm(codec); 4779 4780 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4781 4782 /* 4783 * If headphone rear or front is plugged in, set to headphone. 4784 * If neither is plugged in, set to rear line out. Only if 4785 * hp/speaker auto detect is enabled. 4786 */ 4787 if (auto_jack) { 4788 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4789 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4790 4791 if (jack_present) 4792 spec->cur_out_type = HEADPHONE_OUT; 4793 else 4794 spec->cur_out_type = SPEAKER_OUT; 4795 } else 4796 spec->cur_out_type = spec->out_enum_val; 4797 4798 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4799 4800 /* Begin DSP output switch, mute DSP volume. */ 4801 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4802 if (err < 0) 4803 goto exit; 4804 4805 if (ca0132_alt_select_out_quirk_set(codec) < 0) 4806 goto exit; 4807 4808 switch (spec->cur_out_type) { 4809 case SPEAKER_OUT: 4810 codec_dbg(codec, "%s speaker\n", __func__); 4811 4812 /* Enable EAPD */ 4813 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4814 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4815 4816 /* Disable headphone node. */ 4817 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4818 /* Set front L-R to output. */ 4819 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4820 /* Set Center/LFE to output. */ 4821 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4822 /* Set rear surround to output. */ 4823 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4824 4825 /* 4826 * Without PlayEnhancement being enabled, if we've got a 2.0 4827 * setup, set it to floating point eight to disable any DSP 4828 * processing effects. 4829 */ 4830 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4831 tmp = FLOAT_EIGHT; 4832 else 4833 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4834 4835 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4836 if (err < 0) 4837 goto exit; 4838 4839 break; 4840 case HEADPHONE_OUT: 4841 codec_dbg(codec, "%s hp\n", __func__); 4842 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4843 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4844 4845 /* Disable all speaker nodes. */ 4846 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4847 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4848 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4849 4850 /* enable headphone, either front or rear */ 4851 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4852 headphone_nid = spec->out_pins[2]; 4853 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4854 headphone_nid = spec->out_pins[1]; 4855 4856 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4857 4858 if (outfx_set) 4859 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4860 else 4861 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4862 4863 if (err < 0) 4864 goto exit; 4865 break; 4866 } 4867 /* 4868 * If output effects are enabled, set the X-Bass effect value again to 4869 * make sure that it's properly enabled/disabled for speaker 4870 * configurations with an LFE channel. 4871 */ 4872 if (outfx_set) 4873 ca0132_effects_set(codec, X_BASS, 4874 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4875 4876 /* Set speaker EQ bypass attenuation to 0. */ 4877 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4878 if (err < 0) 4879 goto exit; 4880 4881 /* 4882 * Although unused on all cards but the AE series, this is always set 4883 * to zero when setting the output. 4884 */ 4885 err = dspio_set_uint_param(codec, 0x96, 4886 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4887 if (err < 0) 4888 goto exit; 4889 4890 if (spec->cur_out_type == SPEAKER_OUT) 4891 err = ca0132_alt_surround_set_bass_redirection(codec, 4892 spec->bass_redirection_val); 4893 else 4894 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4895 4896 /* Unmute DSP now that we're done with output selection. */ 4897 err = dspio_set_uint_param(codec, 0x96, 4898 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4899 if (err < 0) 4900 goto exit; 4901 4902 if (spec->cur_out_type == SPEAKER_OUT) { 4903 err = ca0132_alt_set_full_range_speaker(codec); 4904 if (err < 0) 4905 goto exit; 4906 } 4907 4908 exit: 4909 snd_hda_power_down_pm(codec); 4910 4911 return err < 0 ? err : 0; 4912 } 4913 4914 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4915 { 4916 struct ca0132_spec *spec = container_of( 4917 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4918 struct hda_jack_tbl *jack; 4919 4920 if (ca0132_use_alt_functions(spec)) 4921 ca0132_alt_select_out(spec->codec); 4922 else 4923 ca0132_select_out(spec->codec); 4924 4925 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4926 if (jack) { 4927 jack->block_report = 0; 4928 snd_hda_jack_report_sync(spec->codec); 4929 } 4930 } 4931 4932 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4933 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4934 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4935 static int stop_mic1(struct hda_codec *codec); 4936 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4937 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4938 4939 /* 4940 * Select the active VIP source 4941 */ 4942 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4943 { 4944 struct ca0132_spec *spec = codec->spec; 4945 unsigned int tmp; 4946 4947 if (spec->dsp_state != DSP_DOWNLOADED) 4948 return 0; 4949 4950 /* if CrystalVoice if off, vipsource should be 0 */ 4951 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4952 (val == 0)) { 4953 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4954 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4955 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4956 if (spec->cur_mic_type == DIGITAL_MIC) 4957 tmp = FLOAT_TWO; 4958 else 4959 tmp = FLOAT_ONE; 4960 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4961 tmp = FLOAT_ZERO; 4962 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4963 } else { 4964 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4965 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4966 if (spec->cur_mic_type == DIGITAL_MIC) 4967 tmp = FLOAT_TWO; 4968 else 4969 tmp = FLOAT_ONE; 4970 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4971 tmp = FLOAT_ONE; 4972 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4973 msleep(20); 4974 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4975 } 4976 4977 return 1; 4978 } 4979 4980 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4981 { 4982 struct ca0132_spec *spec = codec->spec; 4983 unsigned int tmp; 4984 4985 if (spec->dsp_state != DSP_DOWNLOADED) 4986 return 0; 4987 4988 codec_dbg(codec, "%s\n", __func__); 4989 4990 chipio_set_stream_control(codec, 0x03, 0); 4991 chipio_set_stream_control(codec, 0x04, 0); 4992 4993 /* if CrystalVoice is off, vipsource should be 0 */ 4994 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4995 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4996 codec_dbg(codec, "%s: off.", __func__); 4997 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4998 4999 tmp = FLOAT_ZERO; 5000 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5001 5002 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5003 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5004 if (ca0132_quirk(spec) == QUIRK_R3DI) 5005 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5006 5007 5008 if (spec->in_enum_val == REAR_LINE_IN) 5009 tmp = FLOAT_ZERO; 5010 else { 5011 if (ca0132_quirk(spec) == QUIRK_SBZ) 5012 tmp = FLOAT_THREE; 5013 else 5014 tmp = FLOAT_ONE; 5015 } 5016 5017 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5018 5019 } else { 5020 codec_dbg(codec, "%s: on.", __func__); 5021 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 5022 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 5023 if (ca0132_quirk(spec) == QUIRK_R3DI) 5024 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 5025 5026 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 5027 tmp = FLOAT_TWO; 5028 else 5029 tmp = FLOAT_ONE; 5030 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5031 5032 tmp = FLOAT_ONE; 5033 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5034 5035 msleep(20); 5036 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 5037 } 5038 5039 chipio_set_stream_control(codec, 0x03, 1); 5040 chipio_set_stream_control(codec, 0x04, 1); 5041 5042 return 1; 5043 } 5044 5045 /* 5046 * Select the active microphone. 5047 * If autodetect is enabled, mic will be selected based on jack detection. 5048 * If jack inserted, ext.mic will be selected, else built-in mic 5049 * If autodetect is disabled, mic will be selected based on selection. 5050 */ 5051 static int ca0132_select_mic(struct hda_codec *codec) 5052 { 5053 struct ca0132_spec *spec = codec->spec; 5054 int jack_present; 5055 int auto_jack; 5056 5057 codec_dbg(codec, "ca0132_select_mic\n"); 5058 5059 snd_hda_power_up_pm(codec); 5060 5061 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5062 5063 if (auto_jack) 5064 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5065 else 5066 jack_present = 5067 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5068 5069 if (jack_present) 5070 spec->cur_mic_type = LINE_MIC_IN; 5071 else 5072 spec->cur_mic_type = DIGITAL_MIC; 5073 5074 if (spec->cur_mic_type == DIGITAL_MIC) { 5075 /* enable digital Mic */ 5076 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5077 ca0132_set_dmic(codec, 1); 5078 ca0132_mic_boost_set(codec, 0); 5079 /* set voice focus */ 5080 ca0132_effects_set(codec, VOICE_FOCUS, 5081 spec->effects_switch 5082 [VOICE_FOCUS - EFFECT_START_NID]); 5083 } else { 5084 /* disable digital Mic */ 5085 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5086 ca0132_set_dmic(codec, 0); 5087 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5088 /* disable voice focus */ 5089 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5090 } 5091 5092 snd_hda_power_down_pm(codec); 5093 5094 return 0; 5095 } 5096 5097 /* 5098 * Select the active input. 5099 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5100 * The front mic has no jack-detection, so the only way to switch to it 5101 * is to do it manually in alsamixer. 5102 */ 5103 static int ca0132_alt_select_in(struct hda_codec *codec) 5104 { 5105 struct ca0132_spec *spec = codec->spec; 5106 unsigned int tmp; 5107 5108 codec_dbg(codec, "%s\n", __func__); 5109 5110 snd_hda_power_up_pm(codec); 5111 5112 chipio_set_stream_control(codec, 0x03, 0); 5113 chipio_set_stream_control(codec, 0x04, 0); 5114 5115 spec->cur_mic_type = spec->in_enum_val; 5116 5117 switch (spec->cur_mic_type) { 5118 case REAR_MIC: 5119 switch (ca0132_quirk(spec)) { 5120 case QUIRK_SBZ: 5121 case QUIRK_R3D: 5122 ca0113_mmio_gpio_set(codec, 0, false); 5123 tmp = FLOAT_THREE; 5124 break; 5125 case QUIRK_ZXR: 5126 tmp = FLOAT_THREE; 5127 break; 5128 case QUIRK_R3DI: 5129 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5130 tmp = FLOAT_ONE; 5131 break; 5132 case QUIRK_AE5: 5133 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5134 tmp = FLOAT_THREE; 5135 break; 5136 case QUIRK_AE7: 5137 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5138 tmp = FLOAT_THREE; 5139 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5140 SR_96_000); 5141 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5142 SR_96_000); 5143 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5144 break; 5145 default: 5146 tmp = FLOAT_ONE; 5147 break; 5148 } 5149 5150 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5151 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5152 if (ca0132_quirk(spec) == QUIRK_R3DI) 5153 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5154 5155 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5156 5157 chipio_set_stream_control(codec, 0x03, 1); 5158 chipio_set_stream_control(codec, 0x04, 1); 5159 switch (ca0132_quirk(spec)) { 5160 case QUIRK_SBZ: 5161 chipio_write(codec, 0x18B098, 0x0000000C); 5162 chipio_write(codec, 0x18B09C, 0x0000000C); 5163 break; 5164 case QUIRK_ZXR: 5165 chipio_write(codec, 0x18B098, 0x0000000C); 5166 chipio_write(codec, 0x18B09C, 0x000000CC); 5167 break; 5168 case QUIRK_AE5: 5169 chipio_write(codec, 0x18B098, 0x0000000C); 5170 chipio_write(codec, 0x18B09C, 0x0000004C); 5171 break; 5172 default: 5173 break; 5174 } 5175 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5176 break; 5177 case REAR_LINE_IN: 5178 ca0132_mic_boost_set(codec, 0); 5179 switch (ca0132_quirk(spec)) { 5180 case QUIRK_SBZ: 5181 case QUIRK_R3D: 5182 ca0113_mmio_gpio_set(codec, 0, false); 5183 break; 5184 case QUIRK_R3DI: 5185 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5186 break; 5187 case QUIRK_AE5: 5188 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5189 break; 5190 case QUIRK_AE7: 5191 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5192 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5193 SR_96_000); 5194 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5195 SR_96_000); 5196 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5197 break; 5198 default: 5199 break; 5200 } 5201 5202 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5203 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5204 if (ca0132_quirk(spec) == QUIRK_R3DI) 5205 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5206 5207 if (ca0132_quirk(spec) == QUIRK_AE7) 5208 tmp = FLOAT_THREE; 5209 else 5210 tmp = FLOAT_ZERO; 5211 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5212 5213 switch (ca0132_quirk(spec)) { 5214 case QUIRK_SBZ: 5215 case QUIRK_AE5: 5216 chipio_write(codec, 0x18B098, 0x00000000); 5217 chipio_write(codec, 0x18B09C, 0x00000000); 5218 break; 5219 default: 5220 break; 5221 } 5222 chipio_set_stream_control(codec, 0x03, 1); 5223 chipio_set_stream_control(codec, 0x04, 1); 5224 break; 5225 case FRONT_MIC: 5226 switch (ca0132_quirk(spec)) { 5227 case QUIRK_SBZ: 5228 case QUIRK_R3D: 5229 ca0113_mmio_gpio_set(codec, 0, true); 5230 ca0113_mmio_gpio_set(codec, 5, false); 5231 tmp = FLOAT_THREE; 5232 break; 5233 case QUIRK_R3DI: 5234 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5235 tmp = FLOAT_ONE; 5236 break; 5237 case QUIRK_AE5: 5238 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5239 tmp = FLOAT_THREE; 5240 break; 5241 default: 5242 tmp = FLOAT_ONE; 5243 break; 5244 } 5245 5246 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5247 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5248 if (ca0132_quirk(spec) == QUIRK_R3DI) 5249 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5250 5251 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5252 5253 chipio_set_stream_control(codec, 0x03, 1); 5254 chipio_set_stream_control(codec, 0x04, 1); 5255 5256 switch (ca0132_quirk(spec)) { 5257 case QUIRK_SBZ: 5258 chipio_write(codec, 0x18B098, 0x0000000C); 5259 chipio_write(codec, 0x18B09C, 0x000000CC); 5260 break; 5261 case QUIRK_AE5: 5262 chipio_write(codec, 0x18B098, 0x0000000C); 5263 chipio_write(codec, 0x18B09C, 0x0000004C); 5264 break; 5265 default: 5266 break; 5267 } 5268 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5269 break; 5270 } 5271 ca0132_cvoice_switch_set(codec); 5272 5273 snd_hda_power_down_pm(codec); 5274 return 0; 5275 } 5276 5277 /* 5278 * Check if VNODE settings take effect immediately. 5279 */ 5280 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5281 hda_nid_t vnid, 5282 hda_nid_t *shared_nid) 5283 { 5284 struct ca0132_spec *spec = codec->spec; 5285 hda_nid_t nid; 5286 5287 switch (vnid) { 5288 case VNID_SPK: 5289 nid = spec->shared_out_nid; 5290 break; 5291 case VNID_MIC: 5292 nid = spec->shared_mic_nid; 5293 break; 5294 default: 5295 return false; 5296 } 5297 5298 if (shared_nid) 5299 *shared_nid = nid; 5300 5301 return true; 5302 } 5303 5304 /* 5305 * The following functions are control change helpers. 5306 * They return 0 if no changed. Return 1 if changed. 5307 */ 5308 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5309 { 5310 struct ca0132_spec *spec = codec->spec; 5311 unsigned int tmp; 5312 5313 /* based on CrystalVoice state to enable VoiceFX. */ 5314 if (enable) { 5315 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5316 FLOAT_ONE : FLOAT_ZERO; 5317 } else { 5318 tmp = FLOAT_ZERO; 5319 } 5320 5321 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5322 ca0132_voicefx.reqs[0], tmp); 5323 5324 return 1; 5325 } 5326 5327 /* 5328 * Set the effects parameters 5329 */ 5330 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5331 { 5332 struct ca0132_spec *spec = codec->spec; 5333 unsigned int on, tmp, channel_cfg; 5334 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5335 int err = 0; 5336 int idx = nid - EFFECT_START_NID; 5337 5338 if ((idx < 0) || (idx >= num_fx)) 5339 return 0; /* no changed */ 5340 5341 /* for out effect, qualify with PE */ 5342 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5343 /* if PE if off, turn off out effects. */ 5344 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5345 val = 0; 5346 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5347 channel_cfg = spec->channel_cfg_val; 5348 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5349 channel_cfg != SPEAKER_CHANNELS_4_0) 5350 val = 0; 5351 } 5352 } 5353 5354 /* for in effect, qualify with CrystalVoice */ 5355 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5356 /* if CrystalVoice if off, turn off in effects. */ 5357 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5358 val = 0; 5359 5360 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5361 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5362 val = 0; 5363 5364 /* If Voice Focus on SBZ, set to two channel. */ 5365 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5366 && (spec->cur_mic_type != REAR_LINE_IN)) { 5367 if (spec->effects_switch[CRYSTAL_VOICE - 5368 EFFECT_START_NID]) { 5369 5370 if (spec->effects_switch[VOICE_FOCUS - 5371 EFFECT_START_NID]) { 5372 tmp = FLOAT_TWO; 5373 val = 1; 5374 } else 5375 tmp = FLOAT_ONE; 5376 5377 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5378 } 5379 } 5380 /* 5381 * For SBZ noise reduction, there's an extra command 5382 * to module ID 0x47. No clue why. 5383 */ 5384 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5385 && (spec->cur_mic_type != REAR_LINE_IN)) { 5386 if (spec->effects_switch[CRYSTAL_VOICE - 5387 EFFECT_START_NID]) { 5388 if (spec->effects_switch[NOISE_REDUCTION - 5389 EFFECT_START_NID]) 5390 tmp = FLOAT_ONE; 5391 else 5392 tmp = FLOAT_ZERO; 5393 } else 5394 tmp = FLOAT_ZERO; 5395 5396 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5397 } 5398 5399 /* If rear line in disable effects. */ 5400 if (ca0132_use_alt_functions(spec) && 5401 spec->in_enum_val == REAR_LINE_IN) 5402 val = 0; 5403 } 5404 5405 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5406 nid, val); 5407 5408 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5409 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5410 ca0132_effects[idx].reqs[0], on); 5411 5412 if (err < 0) 5413 return 0; /* no changed */ 5414 5415 return 1; 5416 } 5417 5418 /* 5419 * Turn on/off Playback Enhancements 5420 */ 5421 static int ca0132_pe_switch_set(struct hda_codec *codec) 5422 { 5423 struct ca0132_spec *spec = codec->spec; 5424 hda_nid_t nid; 5425 int i, ret = 0; 5426 5427 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5428 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5429 5430 if (ca0132_use_alt_functions(spec)) 5431 ca0132_alt_select_out(codec); 5432 5433 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5434 nid = OUT_EFFECT_START_NID; 5435 /* PE affects all out effects */ 5436 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5437 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5438 5439 return ret; 5440 } 5441 5442 /* Check if Mic1 is streaming, if so, stop streaming */ 5443 static int stop_mic1(struct hda_codec *codec) 5444 { 5445 struct ca0132_spec *spec = codec->spec; 5446 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5447 AC_VERB_GET_CONV, 0); 5448 if (oldval != 0) 5449 snd_hda_codec_write(codec, spec->adcs[0], 0, 5450 AC_VERB_SET_CHANNEL_STREAMID, 5451 0); 5452 return oldval; 5453 } 5454 5455 /* Resume Mic1 streaming if it was stopped. */ 5456 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5457 { 5458 struct ca0132_spec *spec = codec->spec; 5459 /* Restore the previous stream and channel */ 5460 if (oldval != 0) 5461 snd_hda_codec_write(codec, spec->adcs[0], 0, 5462 AC_VERB_SET_CHANNEL_STREAMID, 5463 oldval); 5464 } 5465 5466 /* 5467 * Turn on/off CrystalVoice 5468 */ 5469 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5470 { 5471 struct ca0132_spec *spec = codec->spec; 5472 hda_nid_t nid; 5473 int i, ret = 0; 5474 unsigned int oldval; 5475 5476 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5477 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5478 5479 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5480 nid = IN_EFFECT_START_NID; 5481 /* CrystalVoice affects all in effects */ 5482 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5483 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5484 5485 /* including VoiceFX */ 5486 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5487 5488 /* set correct vipsource */ 5489 oldval = stop_mic1(codec); 5490 if (ca0132_use_alt_functions(spec)) 5491 ret |= ca0132_alt_set_vipsource(codec, 1); 5492 else 5493 ret |= ca0132_set_vipsource(codec, 1); 5494 resume_mic1(codec, oldval); 5495 return ret; 5496 } 5497 5498 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5499 { 5500 struct ca0132_spec *spec = codec->spec; 5501 int ret = 0; 5502 5503 if (val) /* on */ 5504 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5505 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5506 else /* off */ 5507 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5508 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5509 5510 return ret; 5511 } 5512 5513 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5514 { 5515 struct ca0132_spec *spec = codec->spec; 5516 int ret = 0; 5517 5518 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5519 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5520 return ret; 5521 } 5522 5523 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5524 { 5525 unsigned int i; 5526 5527 for (i = 0; i < 4; i++) 5528 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5529 ae5_headphone_gain_presets[val].vals[i]); 5530 return 0; 5531 } 5532 5533 /* 5534 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5535 * amplifier to handle a 600 ohm load. 5536 */ 5537 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5538 { 5539 ca0113_mmio_gpio_set(codec, 1, val); 5540 5541 return 0; 5542 } 5543 5544 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5545 struct snd_ctl_elem_value *ucontrol) 5546 { 5547 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5548 hda_nid_t nid = get_amp_nid(kcontrol); 5549 hda_nid_t shared_nid = 0; 5550 bool effective; 5551 int ret = 0; 5552 struct ca0132_spec *spec = codec->spec; 5553 int auto_jack; 5554 5555 if (nid == VNID_HP_SEL) { 5556 auto_jack = 5557 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5558 if (!auto_jack) { 5559 if (ca0132_use_alt_functions(spec)) 5560 ca0132_alt_select_out(codec); 5561 else 5562 ca0132_select_out(codec); 5563 } 5564 return 1; 5565 } 5566 5567 if (nid == VNID_AMIC1_SEL) { 5568 auto_jack = 5569 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5570 if (!auto_jack) 5571 ca0132_select_mic(codec); 5572 return 1; 5573 } 5574 5575 if (nid == VNID_HP_ASEL) { 5576 if (ca0132_use_alt_functions(spec)) 5577 ca0132_alt_select_out(codec); 5578 else 5579 ca0132_select_out(codec); 5580 return 1; 5581 } 5582 5583 if (nid == VNID_AMIC1_ASEL) { 5584 ca0132_select_mic(codec); 5585 return 1; 5586 } 5587 5588 /* if effective conditions, then update hw immediately. */ 5589 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5590 if (effective) { 5591 int dir = get_amp_direction(kcontrol); 5592 int ch = get_amp_channels(kcontrol); 5593 unsigned long pval; 5594 5595 mutex_lock(&codec->control_mutex); 5596 pval = kcontrol->private_value; 5597 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5598 0, dir); 5599 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5600 kcontrol->private_value = pval; 5601 mutex_unlock(&codec->control_mutex); 5602 } 5603 5604 return ret; 5605 } 5606 /* End of control change helpers. */ 5607 5608 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5609 long idx) 5610 { 5611 snd_hda_power_up(codec); 5612 5613 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5614 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5615 5616 snd_hda_power_down(codec); 5617 } 5618 5619 /* 5620 * Below I've added controls to mess with the effect levels, I've only enabled 5621 * them on the Sound Blaster Z, but they would probably also work on the 5622 * Chromebook. I figured they were probably tuned specifically for it, and left 5623 * out for a reason. 5624 */ 5625 5626 /* Sets DSP effect level from the sliders above the controls */ 5627 5628 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5629 const unsigned int *lookup, int idx) 5630 { 5631 int i = 0; 5632 unsigned int y; 5633 /* 5634 * For X_BASS, req 2 is actually crossover freq instead of 5635 * effect level 5636 */ 5637 if (nid == X_BASS) 5638 y = 2; 5639 else 5640 y = 1; 5641 5642 snd_hda_power_up(codec); 5643 if (nid == XBASS_XOVER) { 5644 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5645 if (ca0132_effects[i].nid == X_BASS) 5646 break; 5647 5648 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5649 ca0132_effects[i].reqs[1], 5650 &(lookup[idx - 1]), sizeof(unsigned int)); 5651 } else { 5652 /* Find the actual effect structure */ 5653 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5654 if (nid == ca0132_effects[i].nid) 5655 break; 5656 5657 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5658 ca0132_effects[i].reqs[y], 5659 &(lookup[idx]), sizeof(unsigned int)); 5660 } 5661 5662 snd_hda_power_down(codec); 5663 5664 return 0; 5665 } 5666 5667 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5668 struct snd_ctl_elem_value *ucontrol) 5669 { 5670 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5671 struct ca0132_spec *spec = codec->spec; 5672 long *valp = ucontrol->value.integer.value; 5673 hda_nid_t nid = get_amp_nid(kcontrol); 5674 5675 if (nid == BASS_REDIRECTION_XOVER) 5676 *valp = spec->bass_redirect_xover_freq; 5677 else 5678 *valp = spec->xbass_xover_freq; 5679 5680 return 0; 5681 } 5682 5683 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5684 struct snd_ctl_elem_value *ucontrol) 5685 { 5686 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5687 struct ca0132_spec *spec = codec->spec; 5688 hda_nid_t nid = get_amp_nid(kcontrol); 5689 long *valp = ucontrol->value.integer.value; 5690 int idx = nid - OUT_EFFECT_START_NID; 5691 5692 *valp = spec->fx_ctl_val[idx]; 5693 return 0; 5694 } 5695 5696 /* 5697 * The X-bass crossover starts at 10hz, so the min is 1. The 5698 * frequency is set in multiples of 10. 5699 */ 5700 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5701 struct snd_ctl_elem_info *uinfo) 5702 { 5703 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5704 uinfo->count = 1; 5705 uinfo->value.integer.min = 1; 5706 uinfo->value.integer.max = 100; 5707 uinfo->value.integer.step = 1; 5708 5709 return 0; 5710 } 5711 5712 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5713 struct snd_ctl_elem_info *uinfo) 5714 { 5715 int chs = get_amp_channels(kcontrol); 5716 5717 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5718 uinfo->count = chs == 3 ? 2 : 1; 5719 uinfo->value.integer.min = 0; 5720 uinfo->value.integer.max = 100; 5721 uinfo->value.integer.step = 1; 5722 5723 return 0; 5724 } 5725 5726 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5727 struct snd_ctl_elem_value *ucontrol) 5728 { 5729 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5730 struct ca0132_spec *spec = codec->spec; 5731 hda_nid_t nid = get_amp_nid(kcontrol); 5732 long *valp = ucontrol->value.integer.value; 5733 long *cur_val; 5734 int idx; 5735 5736 if (nid == BASS_REDIRECTION_XOVER) 5737 cur_val = &spec->bass_redirect_xover_freq; 5738 else 5739 cur_val = &spec->xbass_xover_freq; 5740 5741 /* any change? */ 5742 if (*cur_val == *valp) 5743 return 0; 5744 5745 *cur_val = *valp; 5746 5747 idx = *valp; 5748 if (nid == BASS_REDIRECTION_XOVER) 5749 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5750 else 5751 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5752 5753 return 0; 5754 } 5755 5756 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5757 struct snd_ctl_elem_value *ucontrol) 5758 { 5759 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5760 struct ca0132_spec *spec = codec->spec; 5761 hda_nid_t nid = get_amp_nid(kcontrol); 5762 long *valp = ucontrol->value.integer.value; 5763 int idx; 5764 5765 idx = nid - EFFECT_START_NID; 5766 /* any change? */ 5767 if (spec->fx_ctl_val[idx] == *valp) 5768 return 0; 5769 5770 spec->fx_ctl_val[idx] = *valp; 5771 5772 idx = *valp; 5773 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5774 5775 return 0; 5776 } 5777 5778 5779 /* 5780 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5781 * only has off or full 30 dB, and didn't like making a volume slider that has 5782 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5783 */ 5784 #define MIC_BOOST_NUM_OF_STEPS 4 5785 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5786 5787 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5788 struct snd_ctl_elem_info *uinfo) 5789 { 5790 char *sfx = "dB"; 5791 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5792 5793 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5794 uinfo->count = 1; 5795 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5796 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5797 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5798 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5799 strcpy(uinfo->value.enumerated.name, namestr); 5800 return 0; 5801 } 5802 5803 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5804 struct snd_ctl_elem_value *ucontrol) 5805 { 5806 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5807 struct ca0132_spec *spec = codec->spec; 5808 5809 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5810 return 0; 5811 } 5812 5813 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5814 struct snd_ctl_elem_value *ucontrol) 5815 { 5816 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5817 struct ca0132_spec *spec = codec->spec; 5818 int sel = ucontrol->value.enumerated.item[0]; 5819 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5820 5821 if (sel >= items) 5822 return 0; 5823 5824 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5825 sel); 5826 5827 spec->mic_boost_enum_val = sel; 5828 5829 if (spec->in_enum_val != REAR_LINE_IN) 5830 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5831 5832 return 1; 5833 } 5834 5835 /* 5836 * Sound BlasterX AE-5 Headphone Gain Controls. 5837 */ 5838 #define AE5_HEADPHONE_GAIN_MAX 3 5839 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5840 struct snd_ctl_elem_info *uinfo) 5841 { 5842 char *sfx = " Ohms)"; 5843 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5844 5845 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5846 uinfo->count = 1; 5847 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5848 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5849 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5850 sprintf(namestr, "%s %s", 5851 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5852 sfx); 5853 strcpy(uinfo->value.enumerated.name, namestr); 5854 return 0; 5855 } 5856 5857 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5858 struct snd_ctl_elem_value *ucontrol) 5859 { 5860 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5861 struct ca0132_spec *spec = codec->spec; 5862 5863 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5864 return 0; 5865 } 5866 5867 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5868 struct snd_ctl_elem_value *ucontrol) 5869 { 5870 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5871 struct ca0132_spec *spec = codec->spec; 5872 int sel = ucontrol->value.enumerated.item[0]; 5873 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5874 5875 if (sel >= items) 5876 return 0; 5877 5878 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5879 sel); 5880 5881 spec->ae5_headphone_gain_val = sel; 5882 5883 if (spec->out_enum_val == HEADPHONE_OUT) 5884 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5885 5886 return 1; 5887 } 5888 5889 /* 5890 * Sound BlasterX AE-5 sound filter enumerated control. 5891 */ 5892 #define AE5_SOUND_FILTER_MAX 3 5893 5894 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5895 struct snd_ctl_elem_info *uinfo) 5896 { 5897 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5898 5899 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5900 uinfo->count = 1; 5901 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5902 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5903 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5904 sprintf(namestr, "%s", 5905 ae5_filter_presets[uinfo->value.enumerated.item].name); 5906 strcpy(uinfo->value.enumerated.name, namestr); 5907 return 0; 5908 } 5909 5910 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5911 struct snd_ctl_elem_value *ucontrol) 5912 { 5913 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5914 struct ca0132_spec *spec = codec->spec; 5915 5916 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5917 return 0; 5918 } 5919 5920 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5921 struct snd_ctl_elem_value *ucontrol) 5922 { 5923 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5924 struct ca0132_spec *spec = codec->spec; 5925 int sel = ucontrol->value.enumerated.item[0]; 5926 unsigned int items = AE5_SOUND_FILTER_MAX; 5927 5928 if (sel >= items) 5929 return 0; 5930 5931 codec_dbg(codec, "ae5_sound_filter: %s\n", 5932 ae5_filter_presets[sel].name); 5933 5934 spec->ae5_filter_val = sel; 5935 5936 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5937 ae5_filter_presets[sel].val); 5938 5939 return 1; 5940 } 5941 5942 /* 5943 * Input Select Control for alternative ca0132 codecs. This exists because 5944 * front microphone has no auto-detect, and we need a way to set the rear 5945 * as line-in 5946 */ 5947 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5948 struct snd_ctl_elem_info *uinfo) 5949 { 5950 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5951 uinfo->count = 1; 5952 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5953 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5954 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5955 strcpy(uinfo->value.enumerated.name, 5956 in_src_str[uinfo->value.enumerated.item]); 5957 return 0; 5958 } 5959 5960 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5961 struct snd_ctl_elem_value *ucontrol) 5962 { 5963 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5964 struct ca0132_spec *spec = codec->spec; 5965 5966 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5967 return 0; 5968 } 5969 5970 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5971 struct snd_ctl_elem_value *ucontrol) 5972 { 5973 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5974 struct ca0132_spec *spec = codec->spec; 5975 int sel = ucontrol->value.enumerated.item[0]; 5976 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5977 5978 /* 5979 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5980 * line-in. 5981 */ 5982 if (ca0132_quirk(spec) == QUIRK_AE7) 5983 items = 2; 5984 5985 if (sel >= items) 5986 return 0; 5987 5988 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5989 sel, in_src_str[sel]); 5990 5991 spec->in_enum_val = sel; 5992 5993 ca0132_alt_select_in(codec); 5994 5995 return 1; 5996 } 5997 5998 /* Sound Blaster Z Output Select Control */ 5999 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 6000 struct snd_ctl_elem_info *uinfo) 6001 { 6002 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6003 uinfo->count = 1; 6004 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 6005 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 6006 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 6007 strcpy(uinfo->value.enumerated.name, 6008 out_type_str[uinfo->value.enumerated.item]); 6009 return 0; 6010 } 6011 6012 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 6013 struct snd_ctl_elem_value *ucontrol) 6014 { 6015 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6016 struct ca0132_spec *spec = codec->spec; 6017 6018 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 6019 return 0; 6020 } 6021 6022 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 6023 struct snd_ctl_elem_value *ucontrol) 6024 { 6025 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6026 struct ca0132_spec *spec = codec->spec; 6027 int sel = ucontrol->value.enumerated.item[0]; 6028 unsigned int items = NUM_OF_OUTPUTS; 6029 unsigned int auto_jack; 6030 6031 if (sel >= items) 6032 return 0; 6033 6034 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6035 sel, out_type_str[sel]); 6036 6037 spec->out_enum_val = sel; 6038 6039 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 6040 6041 if (!auto_jack) 6042 ca0132_alt_select_out(codec); 6043 6044 return 1; 6045 } 6046 6047 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6048 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6049 struct snd_ctl_elem_info *uinfo) 6050 { 6051 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6052 6053 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6054 uinfo->count = 1; 6055 uinfo->value.enumerated.items = items; 6056 if (uinfo->value.enumerated.item >= items) 6057 uinfo->value.enumerated.item = items - 1; 6058 strcpy(uinfo->value.enumerated.name, 6059 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6060 return 0; 6061 } 6062 6063 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6064 struct snd_ctl_elem_value *ucontrol) 6065 { 6066 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6067 struct ca0132_spec *spec = codec->spec; 6068 6069 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6070 return 0; 6071 } 6072 6073 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6074 struct snd_ctl_elem_value *ucontrol) 6075 { 6076 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6077 struct ca0132_spec *spec = codec->spec; 6078 int sel = ucontrol->value.enumerated.item[0]; 6079 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6080 6081 if (sel >= items) 6082 return 0; 6083 6084 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6085 sel, speaker_channel_cfgs[sel].name); 6086 6087 spec->channel_cfg_val = sel; 6088 6089 if (spec->out_enum_val == SPEAKER_OUT) 6090 ca0132_alt_select_out(codec); 6091 6092 return 1; 6093 } 6094 6095 /* 6096 * Smart Volume output setting control. Three different settings, Normal, 6097 * which takes the value from the smart volume slider. The two others, loud 6098 * and night, disregard the slider value and have uneditable values. 6099 */ 6100 #define NUM_OF_SVM_SETTINGS 3 6101 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6102 6103 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6104 struct snd_ctl_elem_info *uinfo) 6105 { 6106 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6107 uinfo->count = 1; 6108 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6109 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6110 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6111 strcpy(uinfo->value.enumerated.name, 6112 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6113 return 0; 6114 } 6115 6116 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6117 struct snd_ctl_elem_value *ucontrol) 6118 { 6119 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6120 struct ca0132_spec *spec = codec->spec; 6121 6122 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6123 return 0; 6124 } 6125 6126 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6127 struct snd_ctl_elem_value *ucontrol) 6128 { 6129 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6130 struct ca0132_spec *spec = codec->spec; 6131 int sel = ucontrol->value.enumerated.item[0]; 6132 unsigned int items = NUM_OF_SVM_SETTINGS; 6133 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6134 unsigned int tmp; 6135 6136 if (sel >= items) 6137 return 0; 6138 6139 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6140 sel, out_svm_set_enum_str[sel]); 6141 6142 spec->smart_volume_setting = sel; 6143 6144 switch (sel) { 6145 case 0: 6146 tmp = FLOAT_ZERO; 6147 break; 6148 case 1: 6149 tmp = FLOAT_ONE; 6150 break; 6151 case 2: 6152 tmp = FLOAT_TWO; 6153 break; 6154 default: 6155 tmp = FLOAT_ZERO; 6156 break; 6157 } 6158 /* Req 2 is the Smart Volume Setting req. */ 6159 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6160 ca0132_effects[idx].reqs[2], tmp); 6161 return 1; 6162 } 6163 6164 /* Sound Blaster Z EQ preset controls */ 6165 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6166 struct snd_ctl_elem_info *uinfo) 6167 { 6168 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6169 6170 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6171 uinfo->count = 1; 6172 uinfo->value.enumerated.items = items; 6173 if (uinfo->value.enumerated.item >= items) 6174 uinfo->value.enumerated.item = items - 1; 6175 strcpy(uinfo->value.enumerated.name, 6176 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6177 return 0; 6178 } 6179 6180 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6181 struct snd_ctl_elem_value *ucontrol) 6182 { 6183 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6184 struct ca0132_spec *spec = codec->spec; 6185 6186 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6187 return 0; 6188 } 6189 6190 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6191 struct snd_ctl_elem_value *ucontrol) 6192 { 6193 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6194 struct ca0132_spec *spec = codec->spec; 6195 int i, err = 0; 6196 int sel = ucontrol->value.enumerated.item[0]; 6197 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6198 6199 if (sel >= items) 6200 return 0; 6201 6202 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6203 ca0132_alt_eq_presets[sel].name); 6204 /* 6205 * Idx 0 is default. 6206 * Default needs to qualify with CrystalVoice state. 6207 */ 6208 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6209 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6210 ca0132_alt_eq_enum.reqs[i], 6211 ca0132_alt_eq_presets[sel].vals[i]); 6212 if (err < 0) 6213 break; 6214 } 6215 6216 if (err >= 0) 6217 spec->eq_preset_val = sel; 6218 6219 return 1; 6220 } 6221 6222 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6223 struct snd_ctl_elem_info *uinfo) 6224 { 6225 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6226 6227 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6228 uinfo->count = 1; 6229 uinfo->value.enumerated.items = items; 6230 if (uinfo->value.enumerated.item >= items) 6231 uinfo->value.enumerated.item = items - 1; 6232 strcpy(uinfo->value.enumerated.name, 6233 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6234 return 0; 6235 } 6236 6237 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6238 struct snd_ctl_elem_value *ucontrol) 6239 { 6240 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6241 struct ca0132_spec *spec = codec->spec; 6242 6243 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6244 return 0; 6245 } 6246 6247 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6248 struct snd_ctl_elem_value *ucontrol) 6249 { 6250 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6251 struct ca0132_spec *spec = codec->spec; 6252 int i, err = 0; 6253 int sel = ucontrol->value.enumerated.item[0]; 6254 6255 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6256 return 0; 6257 6258 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6259 sel, ca0132_voicefx_presets[sel].name); 6260 6261 /* 6262 * Idx 0 is default. 6263 * Default needs to qualify with CrystalVoice state. 6264 */ 6265 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6266 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6267 ca0132_voicefx.reqs[i], 6268 ca0132_voicefx_presets[sel].vals[i]); 6269 if (err < 0) 6270 break; 6271 } 6272 6273 if (err >= 0) { 6274 spec->voicefx_val = sel; 6275 /* enable voice fx */ 6276 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6277 } 6278 6279 return 1; 6280 } 6281 6282 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6283 struct snd_ctl_elem_value *ucontrol) 6284 { 6285 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6286 struct ca0132_spec *spec = codec->spec; 6287 hda_nid_t nid = get_amp_nid(kcontrol); 6288 int ch = get_amp_channels(kcontrol); 6289 long *valp = ucontrol->value.integer.value; 6290 6291 /* vnode */ 6292 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6293 if (ch & 1) { 6294 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6295 valp++; 6296 } 6297 if (ch & 2) { 6298 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6299 valp++; 6300 } 6301 return 0; 6302 } 6303 6304 /* effects, include PE and CrystalVoice */ 6305 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6306 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6307 return 0; 6308 } 6309 6310 /* mic boost */ 6311 if (nid == spec->input_pins[0]) { 6312 *valp = spec->cur_mic_boost; 6313 return 0; 6314 } 6315 6316 if (nid == ZXR_HEADPHONE_GAIN) { 6317 *valp = spec->zxr_gain_set; 6318 return 0; 6319 } 6320 6321 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6322 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6323 return 0; 6324 } 6325 6326 if (nid == BASS_REDIRECTION) { 6327 *valp = spec->bass_redirection_val; 6328 return 0; 6329 } 6330 6331 return 0; 6332 } 6333 6334 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6335 struct snd_ctl_elem_value *ucontrol) 6336 { 6337 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6338 struct ca0132_spec *spec = codec->spec; 6339 hda_nid_t nid = get_amp_nid(kcontrol); 6340 int ch = get_amp_channels(kcontrol); 6341 long *valp = ucontrol->value.integer.value; 6342 int changed = 1; 6343 6344 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6345 nid, *valp); 6346 6347 snd_hda_power_up(codec); 6348 /* vnode */ 6349 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6350 if (ch & 1) { 6351 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6352 valp++; 6353 } 6354 if (ch & 2) { 6355 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6356 valp++; 6357 } 6358 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 6359 goto exit; 6360 } 6361 6362 /* PE */ 6363 if (nid == PLAY_ENHANCEMENT) { 6364 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6365 changed = ca0132_pe_switch_set(codec); 6366 goto exit; 6367 } 6368 6369 /* CrystalVoice */ 6370 if (nid == CRYSTAL_VOICE) { 6371 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6372 changed = ca0132_cvoice_switch_set(codec); 6373 goto exit; 6374 } 6375 6376 /* out and in effects */ 6377 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6378 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6379 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6380 changed = ca0132_effects_set(codec, nid, *valp); 6381 goto exit; 6382 } 6383 6384 /* mic boost */ 6385 if (nid == spec->input_pins[0]) { 6386 spec->cur_mic_boost = *valp; 6387 if (ca0132_use_alt_functions(spec)) { 6388 if (spec->in_enum_val != REAR_LINE_IN) 6389 changed = ca0132_mic_boost_set(codec, *valp); 6390 } else { 6391 /* Mic boost does not apply to Digital Mic */ 6392 if (spec->cur_mic_type != DIGITAL_MIC) 6393 changed = ca0132_mic_boost_set(codec, *valp); 6394 } 6395 6396 goto exit; 6397 } 6398 6399 if (nid == ZXR_HEADPHONE_GAIN) { 6400 spec->zxr_gain_set = *valp; 6401 if (spec->cur_out_type == HEADPHONE_OUT) 6402 changed = zxr_headphone_gain_set(codec, *valp); 6403 else 6404 changed = 0; 6405 6406 goto exit; 6407 } 6408 6409 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6410 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6411 if (spec->cur_out_type == SPEAKER_OUT) 6412 ca0132_alt_set_full_range_speaker(codec); 6413 6414 changed = 0; 6415 } 6416 6417 if (nid == BASS_REDIRECTION) { 6418 spec->bass_redirection_val = *valp; 6419 if (spec->cur_out_type == SPEAKER_OUT) 6420 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6421 6422 changed = 0; 6423 } 6424 6425 exit: 6426 snd_hda_power_down(codec); 6427 return changed; 6428 } 6429 6430 /* 6431 * Volume related 6432 */ 6433 /* 6434 * Sets the internal DSP decibel level to match the DAC for output, and the 6435 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6436 * all alternative codecs set DSP playback volume. 6437 */ 6438 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6439 { 6440 struct ca0132_spec *spec = codec->spec; 6441 unsigned int dsp_dir; 6442 unsigned int lookup_val; 6443 6444 if (nid == VNID_SPK) 6445 dsp_dir = DSP_VOL_OUT; 6446 else 6447 dsp_dir = DSP_VOL_IN; 6448 6449 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6450 6451 dspio_set_uint_param(codec, 6452 ca0132_alt_vol_ctls[dsp_dir].mid, 6453 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6454 float_vol_db_lookup[lookup_val]); 6455 6456 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6457 6458 dspio_set_uint_param(codec, 6459 ca0132_alt_vol_ctls[dsp_dir].mid, 6460 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6461 float_vol_db_lookup[lookup_val]); 6462 6463 dspio_set_uint_param(codec, 6464 ca0132_alt_vol_ctls[dsp_dir].mid, 6465 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6466 } 6467 6468 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6469 struct snd_ctl_elem_info *uinfo) 6470 { 6471 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6472 struct ca0132_spec *spec = codec->spec; 6473 hda_nid_t nid = get_amp_nid(kcontrol); 6474 int ch = get_amp_channels(kcontrol); 6475 int dir = get_amp_direction(kcontrol); 6476 unsigned long pval; 6477 int err; 6478 6479 switch (nid) { 6480 case VNID_SPK: 6481 /* follow shared_out info */ 6482 nid = spec->shared_out_nid; 6483 mutex_lock(&codec->control_mutex); 6484 pval = kcontrol->private_value; 6485 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6486 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6487 kcontrol->private_value = pval; 6488 mutex_unlock(&codec->control_mutex); 6489 break; 6490 case VNID_MIC: 6491 /* follow shared_mic info */ 6492 nid = spec->shared_mic_nid; 6493 mutex_lock(&codec->control_mutex); 6494 pval = kcontrol->private_value; 6495 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6496 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6497 kcontrol->private_value = pval; 6498 mutex_unlock(&codec->control_mutex); 6499 break; 6500 default: 6501 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6502 } 6503 return err; 6504 } 6505 6506 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6507 struct snd_ctl_elem_value *ucontrol) 6508 { 6509 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6510 struct ca0132_spec *spec = codec->spec; 6511 hda_nid_t nid = get_amp_nid(kcontrol); 6512 int ch = get_amp_channels(kcontrol); 6513 long *valp = ucontrol->value.integer.value; 6514 6515 /* store the left and right volume */ 6516 if (ch & 1) { 6517 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6518 valp++; 6519 } 6520 if (ch & 2) { 6521 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6522 valp++; 6523 } 6524 return 0; 6525 } 6526 6527 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6528 struct snd_ctl_elem_value *ucontrol) 6529 { 6530 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6531 struct ca0132_spec *spec = codec->spec; 6532 hda_nid_t nid = get_amp_nid(kcontrol); 6533 int ch = get_amp_channels(kcontrol); 6534 long *valp = ucontrol->value.integer.value; 6535 hda_nid_t shared_nid = 0; 6536 bool effective; 6537 int changed = 1; 6538 6539 /* store the left and right volume */ 6540 if (ch & 1) { 6541 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6542 valp++; 6543 } 6544 if (ch & 2) { 6545 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6546 valp++; 6547 } 6548 6549 /* if effective conditions, then update hw immediately. */ 6550 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6551 if (effective) { 6552 int dir = get_amp_direction(kcontrol); 6553 unsigned long pval; 6554 6555 snd_hda_power_up(codec); 6556 mutex_lock(&codec->control_mutex); 6557 pval = kcontrol->private_value; 6558 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6559 0, dir); 6560 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6561 kcontrol->private_value = pval; 6562 mutex_unlock(&codec->control_mutex); 6563 snd_hda_power_down(codec); 6564 } 6565 6566 return changed; 6567 } 6568 6569 /* 6570 * This function is the same as the one above, because using an if statement 6571 * inside of the above volume control for the DSP volume would cause too much 6572 * lag. This is a lot more smooth. 6573 */ 6574 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6575 struct snd_ctl_elem_value *ucontrol) 6576 { 6577 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6578 struct ca0132_spec *spec = codec->spec; 6579 hda_nid_t nid = get_amp_nid(kcontrol); 6580 int ch = get_amp_channels(kcontrol); 6581 long *valp = ucontrol->value.integer.value; 6582 hda_nid_t vnid = 0; 6583 int changed; 6584 6585 switch (nid) { 6586 case 0x02: 6587 vnid = VNID_SPK; 6588 break; 6589 case 0x07: 6590 vnid = VNID_MIC; 6591 break; 6592 } 6593 6594 /* store the left and right volume */ 6595 if (ch & 1) { 6596 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6597 valp++; 6598 } 6599 if (ch & 2) { 6600 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6601 valp++; 6602 } 6603 6604 snd_hda_power_up(codec); 6605 ca0132_alt_dsp_volume_put(codec, vnid); 6606 mutex_lock(&codec->control_mutex); 6607 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6608 mutex_unlock(&codec->control_mutex); 6609 snd_hda_power_down(codec); 6610 6611 return changed; 6612 } 6613 6614 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6615 unsigned int size, unsigned int __user *tlv) 6616 { 6617 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6618 struct ca0132_spec *spec = codec->spec; 6619 hda_nid_t nid = get_amp_nid(kcontrol); 6620 int ch = get_amp_channels(kcontrol); 6621 int dir = get_amp_direction(kcontrol); 6622 unsigned long pval; 6623 int err; 6624 6625 switch (nid) { 6626 case VNID_SPK: 6627 /* follow shared_out tlv */ 6628 nid = spec->shared_out_nid; 6629 mutex_lock(&codec->control_mutex); 6630 pval = kcontrol->private_value; 6631 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6632 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6633 kcontrol->private_value = pval; 6634 mutex_unlock(&codec->control_mutex); 6635 break; 6636 case VNID_MIC: 6637 /* follow shared_mic tlv */ 6638 nid = spec->shared_mic_nid; 6639 mutex_lock(&codec->control_mutex); 6640 pval = kcontrol->private_value; 6641 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6642 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6643 kcontrol->private_value = pval; 6644 mutex_unlock(&codec->control_mutex); 6645 break; 6646 default: 6647 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6648 } 6649 return err; 6650 } 6651 6652 /* Add volume slider control for effect level */ 6653 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6654 const char *pfx, int dir) 6655 { 6656 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6657 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6658 struct snd_kcontrol_new knew = 6659 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6660 6661 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6662 6663 knew.tlv.c = NULL; 6664 6665 switch (nid) { 6666 case XBASS_XOVER: 6667 knew.info = ca0132_alt_xbass_xover_slider_info; 6668 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6669 knew.put = ca0132_alt_xbass_xover_slider_put; 6670 break; 6671 default: 6672 knew.info = ca0132_alt_effect_slider_info; 6673 knew.get = ca0132_alt_slider_ctl_get; 6674 knew.put = ca0132_alt_effect_slider_put; 6675 knew.private_value = 6676 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6677 break; 6678 } 6679 6680 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6681 } 6682 6683 /* 6684 * Added FX: prefix for the alternative codecs, because otherwise the surround 6685 * effect would conflict with the Surround sound volume control. Also seems more 6686 * clear as to what the switches do. Left alone for others. 6687 */ 6688 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6689 const char *pfx, int dir) 6690 { 6691 struct ca0132_spec *spec = codec->spec; 6692 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6693 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6694 struct snd_kcontrol_new knew = 6695 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6696 /* If using alt_controls, add FX: prefix. But, don't add FX: 6697 * prefix to OutFX or InFX enable controls. 6698 */ 6699 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6700 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6701 else 6702 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6703 6704 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6705 } 6706 6707 static int add_voicefx(struct hda_codec *codec) 6708 { 6709 struct snd_kcontrol_new knew = 6710 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6711 VOICEFX, 1, 0, HDA_INPUT); 6712 knew.info = ca0132_voicefx_info; 6713 knew.get = ca0132_voicefx_get; 6714 knew.put = ca0132_voicefx_put; 6715 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6716 } 6717 6718 /* Create the EQ Preset control */ 6719 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6720 { 6721 struct snd_kcontrol_new knew = 6722 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6723 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6724 knew.info = ca0132_alt_eq_preset_info; 6725 knew.get = ca0132_alt_eq_preset_get; 6726 knew.put = ca0132_alt_eq_preset_put; 6727 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6728 snd_ctl_new1(&knew, codec)); 6729 } 6730 6731 /* 6732 * Add enumerated control for the three different settings of the smart volume 6733 * output effect. Normal just uses the slider value, and loud and night are 6734 * their own things that ignore that value. 6735 */ 6736 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6737 { 6738 struct snd_kcontrol_new knew = 6739 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6740 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6741 knew.info = ca0132_alt_svm_setting_info; 6742 knew.get = ca0132_alt_svm_setting_get; 6743 knew.put = ca0132_alt_svm_setting_put; 6744 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6745 snd_ctl_new1(&knew, codec)); 6746 6747 } 6748 6749 /* 6750 * Create an Output Select enumerated control for codecs with surround 6751 * out capabilities. 6752 */ 6753 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6754 { 6755 struct snd_kcontrol_new knew = 6756 HDA_CODEC_MUTE_MONO("Output Select", 6757 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6758 knew.info = ca0132_alt_output_select_get_info; 6759 knew.get = ca0132_alt_output_select_get; 6760 knew.put = ca0132_alt_output_select_put; 6761 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6762 snd_ctl_new1(&knew, codec)); 6763 } 6764 6765 /* 6766 * Add a control for selecting channel count on speaker output. Setting this 6767 * allows the DSP to do bass redirection and channel upmixing on surround 6768 * configurations. 6769 */ 6770 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6771 { 6772 struct snd_kcontrol_new knew = 6773 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6774 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6775 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6776 knew.get = ca0132_alt_speaker_channel_cfg_get; 6777 knew.put = ca0132_alt_speaker_channel_cfg_put; 6778 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6779 snd_ctl_new1(&knew, codec)); 6780 } 6781 6782 /* 6783 * Full range front stereo and rear surround switches. When these are set to 6784 * full range, the lower frequencies from these channels are no longer 6785 * redirected to the LFE channel. 6786 */ 6787 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6788 { 6789 struct snd_kcontrol_new knew = 6790 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6791 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6792 6793 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6794 snd_ctl_new1(&knew, codec)); 6795 } 6796 6797 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6798 { 6799 struct snd_kcontrol_new knew = 6800 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6801 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6802 6803 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6804 snd_ctl_new1(&knew, codec)); 6805 } 6806 6807 /* 6808 * Bass redirection redirects audio below the crossover frequency to the LFE 6809 * channel on speakers that are set as not being full-range. On configurations 6810 * without an LFE channel, it does nothing. Bass redirection seems to be the 6811 * replacement for X-Bass on configurations with an LFE channel. 6812 */ 6813 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6814 { 6815 const char *namestr = "Bass Redirection Crossover"; 6816 struct snd_kcontrol_new knew = 6817 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6818 HDA_OUTPUT); 6819 6820 knew.tlv.c = NULL; 6821 knew.info = ca0132_alt_xbass_xover_slider_info; 6822 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6823 knew.put = ca0132_alt_xbass_xover_slider_put; 6824 6825 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6826 snd_ctl_new1(&knew, codec)); 6827 } 6828 6829 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6830 { 6831 const char *namestr = "Bass Redirection"; 6832 struct snd_kcontrol_new knew = 6833 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6834 HDA_OUTPUT); 6835 6836 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6837 snd_ctl_new1(&knew, codec)); 6838 } 6839 6840 /* 6841 * Create an Input Source enumerated control for the alternate ca0132 codecs 6842 * because the front microphone has no auto-detect, and Line-in has to be set 6843 * somehow. 6844 */ 6845 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6846 { 6847 struct snd_kcontrol_new knew = 6848 HDA_CODEC_MUTE_MONO("Input Source", 6849 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6850 knew.info = ca0132_alt_input_source_info; 6851 knew.get = ca0132_alt_input_source_get; 6852 knew.put = ca0132_alt_input_source_put; 6853 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6854 snd_ctl_new1(&knew, codec)); 6855 } 6856 6857 /* 6858 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6859 * more control than the original mic boost, which is either full 30dB or off. 6860 */ 6861 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6862 { 6863 struct snd_kcontrol_new knew = 6864 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6865 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6866 knew.info = ca0132_alt_mic_boost_info; 6867 knew.get = ca0132_alt_mic_boost_get; 6868 knew.put = ca0132_alt_mic_boost_put; 6869 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6870 snd_ctl_new1(&knew, codec)); 6871 6872 } 6873 6874 /* 6875 * Add headphone gain enumerated control for the AE-5. This switches between 6876 * three modes, low, medium, and high. When non-headphone outputs are selected, 6877 * it is automatically set to high. This is the same behavior as Windows. 6878 */ 6879 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6880 { 6881 struct snd_kcontrol_new knew = 6882 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6883 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6884 knew.info = ae5_headphone_gain_info; 6885 knew.get = ae5_headphone_gain_get; 6886 knew.put = ae5_headphone_gain_put; 6887 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6888 snd_ctl_new1(&knew, codec)); 6889 } 6890 6891 /* 6892 * Add sound filter enumerated control for the AE-5. This adds three different 6893 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6894 * read into it, it changes the DAC's interpolation filter. 6895 */ 6896 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6897 { 6898 struct snd_kcontrol_new knew = 6899 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6900 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6901 knew.info = ae5_sound_filter_info; 6902 knew.get = ae5_sound_filter_get; 6903 knew.put = ae5_sound_filter_put; 6904 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6905 snd_ctl_new1(&knew, codec)); 6906 } 6907 6908 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6909 { 6910 struct snd_kcontrol_new knew = 6911 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6912 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6913 6914 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6915 snd_ctl_new1(&knew, codec)); 6916 } 6917 6918 /* 6919 * Need to create follower controls for the alternate codecs that have surround 6920 * capabilities. 6921 */ 6922 static const char * const ca0132_alt_follower_pfxs[] = { 6923 "Front", "Surround", "Center", "LFE", NULL, 6924 }; 6925 6926 /* 6927 * Also need special channel map, because the default one is incorrect. 6928 * I think this has to do with the pin for rear surround being 0x11, 6929 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6930 */ 6931 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6932 { .channels = 2, 6933 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6934 { .channels = 4, 6935 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6936 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6937 { .channels = 6, 6938 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6939 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6940 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6941 { } 6942 }; 6943 6944 /* Add the correct chmap for streams with 6 channels. */ 6945 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6946 { 6947 int err = 0; 6948 struct hda_pcm *pcm; 6949 6950 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6951 struct hda_pcm_stream *hinfo = 6952 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6953 struct snd_pcm_chmap *chmap; 6954 const struct snd_pcm_chmap_elem *elem; 6955 6956 elem = ca0132_alt_chmaps; 6957 if (hinfo->channels_max == 6) { 6958 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6959 SNDRV_PCM_STREAM_PLAYBACK, 6960 elem, hinfo->channels_max, 0, &chmap); 6961 if (err < 0) 6962 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6963 } 6964 } 6965 } 6966 6967 /* 6968 * When changing Node IDs for Mixer Controls below, make sure to update 6969 * Node IDs in ca0132_config() as well. 6970 */ 6971 static const struct snd_kcontrol_new ca0132_mixer[] = { 6972 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6973 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6974 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6975 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6976 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6977 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6978 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6979 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6980 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6981 0x12, 1, HDA_INPUT), 6982 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6983 VNID_HP_SEL, 1, HDA_OUTPUT), 6984 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6985 VNID_AMIC1_SEL, 1, HDA_INPUT), 6986 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6987 VNID_HP_ASEL, 1, HDA_OUTPUT), 6988 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6989 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6990 { } /* end */ 6991 }; 6992 6993 /* 6994 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6995 * surround controls. Also sets both the Front Playback and Capture Volume 6996 * controls to alt so they set the DSP's decibel level. 6997 */ 6998 static const struct snd_kcontrol_new desktop_mixer[] = { 6999 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7000 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7001 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7002 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7003 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7004 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7005 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7006 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7007 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 7008 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7009 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7010 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7011 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7012 VNID_HP_ASEL, 1, HDA_OUTPUT), 7013 { } /* end */ 7014 }; 7015 7016 /* 7017 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 7018 * because it doesn't set decibel levels for the DSP for capture. 7019 */ 7020 static const struct snd_kcontrol_new r3di_mixer[] = { 7021 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7022 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7023 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7024 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7025 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7026 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7027 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7028 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7029 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 7030 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7031 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7032 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7033 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7034 VNID_HP_ASEL, 1, HDA_OUTPUT), 7035 { } /* end */ 7036 }; 7037 7038 static int ca0132_build_controls(struct hda_codec *codec) 7039 { 7040 struct ca0132_spec *spec = codec->spec; 7041 int i, num_fx, num_sliders; 7042 int err = 0; 7043 7044 /* Add Mixer controls */ 7045 for (i = 0; i < spec->num_mixers; i++) { 7046 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7047 if (err < 0) 7048 return err; 7049 } 7050 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7051 if (ca0132_use_alt_functions(spec)) { 7052 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7053 spec->tlv); 7054 snd_hda_add_vmaster(codec, "Master Playback Volume", 7055 spec->tlv, ca0132_alt_follower_pfxs, 7056 "Playback Volume", 0); 7057 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7058 NULL, ca0132_alt_follower_pfxs, 7059 "Playback Switch", 7060 true, 0, &spec->vmaster_mute.sw_kctl); 7061 if (err < 0) 7062 return err; 7063 } 7064 7065 /* Add in and out effects controls. 7066 * VoiceFX, PE and CrystalVoice are added separately. 7067 */ 7068 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7069 for (i = 0; i < num_fx; i++) { 7070 /* Desktop cards break if Echo Cancellation is used. */ 7071 if (ca0132_use_pci_mmio(spec)) { 7072 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7073 OUT_EFFECTS_COUNT)) 7074 continue; 7075 } 7076 7077 err = add_fx_switch(codec, ca0132_effects[i].nid, 7078 ca0132_effects[i].name, 7079 ca0132_effects[i].direct); 7080 if (err < 0) 7081 return err; 7082 } 7083 /* 7084 * If codec has use_alt_controls set to true, add effect level sliders, 7085 * EQ presets, and Smart Volume presets. Also, change names to add FX 7086 * prefix, and change PlayEnhancement and CrystalVoice to match. 7087 */ 7088 if (ca0132_use_alt_controls(spec)) { 7089 err = ca0132_alt_add_svm_enum(codec); 7090 if (err < 0) 7091 return err; 7092 7093 err = add_ca0132_alt_eq_presets(codec); 7094 if (err < 0) 7095 return err; 7096 7097 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7098 "Enable OutFX", 0); 7099 if (err < 0) 7100 return err; 7101 7102 err = add_fx_switch(codec, CRYSTAL_VOICE, 7103 "Enable InFX", 1); 7104 if (err < 0) 7105 return err; 7106 7107 num_sliders = OUT_EFFECTS_COUNT - 1; 7108 for (i = 0; i < num_sliders; i++) { 7109 err = ca0132_alt_add_effect_slider(codec, 7110 ca0132_effects[i].nid, 7111 ca0132_effects[i].name, 7112 ca0132_effects[i].direct); 7113 if (err < 0) 7114 return err; 7115 } 7116 7117 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7118 "X-Bass Crossover", EFX_DIR_OUT); 7119 7120 if (err < 0) 7121 return err; 7122 } else { 7123 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7124 "PlayEnhancement", 0); 7125 if (err < 0) 7126 return err; 7127 7128 err = add_fx_switch(codec, CRYSTAL_VOICE, 7129 "CrystalVoice", 1); 7130 if (err < 0) 7131 return err; 7132 } 7133 err = add_voicefx(codec); 7134 if (err < 0) 7135 return err; 7136 7137 /* 7138 * If the codec uses alt_functions, you need the enumerated controls 7139 * to select the new outputs and inputs, plus add the new mic boost 7140 * setting control. 7141 */ 7142 if (ca0132_use_alt_functions(spec)) { 7143 err = ca0132_alt_add_output_enum(codec); 7144 if (err < 0) 7145 return err; 7146 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7147 if (err < 0) 7148 return err; 7149 err = ca0132_alt_add_front_full_range_switch(codec); 7150 if (err < 0) 7151 return err; 7152 err = ca0132_alt_add_rear_full_range_switch(codec); 7153 if (err < 0) 7154 return err; 7155 err = ca0132_alt_add_bass_redirection_crossover(codec); 7156 if (err < 0) 7157 return err; 7158 err = ca0132_alt_add_bass_redirection_switch(codec); 7159 if (err < 0) 7160 return err; 7161 err = ca0132_alt_add_mic_boost_enum(codec); 7162 if (err < 0) 7163 return err; 7164 /* 7165 * ZxR only has microphone input, there is no front panel 7166 * header on the card, and aux-in is handled by the DBPro board. 7167 */ 7168 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7169 err = ca0132_alt_add_input_enum(codec); 7170 if (err < 0) 7171 return err; 7172 } 7173 } 7174 7175 switch (ca0132_quirk(spec)) { 7176 case QUIRK_AE5: 7177 case QUIRK_AE7: 7178 err = ae5_add_headphone_gain_enum(codec); 7179 if (err < 0) 7180 return err; 7181 err = ae5_add_sound_filter_enum(codec); 7182 if (err < 0) 7183 return err; 7184 break; 7185 case QUIRK_ZXR: 7186 err = zxr_add_headphone_gain_switch(codec); 7187 if (err < 0) 7188 return err; 7189 break; 7190 default: 7191 break; 7192 } 7193 7194 #ifdef ENABLE_TUNING_CONTROLS 7195 add_tuning_ctls(codec); 7196 #endif 7197 7198 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7199 if (err < 0) 7200 return err; 7201 7202 if (spec->dig_out) { 7203 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7204 spec->dig_out); 7205 if (err < 0) 7206 return err; 7207 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7208 if (err < 0) 7209 return err; 7210 /* spec->multiout.share_spdif = 1; */ 7211 } 7212 7213 if (spec->dig_in) { 7214 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7215 if (err < 0) 7216 return err; 7217 } 7218 7219 if (ca0132_use_alt_functions(spec)) 7220 ca0132_alt_add_chmap_ctls(codec); 7221 7222 return 0; 7223 } 7224 7225 static int dbpro_build_controls(struct hda_codec *codec) 7226 { 7227 struct ca0132_spec *spec = codec->spec; 7228 int err = 0; 7229 7230 if (spec->dig_out) { 7231 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7232 spec->dig_out); 7233 if (err < 0) 7234 return err; 7235 } 7236 7237 if (spec->dig_in) { 7238 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7239 if (err < 0) 7240 return err; 7241 } 7242 7243 return 0; 7244 } 7245 7246 /* 7247 * PCM 7248 */ 7249 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7250 .substreams = 1, 7251 .channels_min = 2, 7252 .channels_max = 6, 7253 .ops = { 7254 .prepare = ca0132_playback_pcm_prepare, 7255 .cleanup = ca0132_playback_pcm_cleanup, 7256 .get_delay = ca0132_playback_pcm_delay, 7257 }, 7258 }; 7259 7260 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7261 .substreams = 1, 7262 .channels_min = 2, 7263 .channels_max = 2, 7264 .ops = { 7265 .prepare = ca0132_capture_pcm_prepare, 7266 .cleanup = ca0132_capture_pcm_cleanup, 7267 .get_delay = ca0132_capture_pcm_delay, 7268 }, 7269 }; 7270 7271 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7272 .substreams = 1, 7273 .channels_min = 2, 7274 .channels_max = 2, 7275 .ops = { 7276 .open = ca0132_dig_playback_pcm_open, 7277 .close = ca0132_dig_playback_pcm_close, 7278 .prepare = ca0132_dig_playback_pcm_prepare, 7279 .cleanup = ca0132_dig_playback_pcm_cleanup 7280 }, 7281 }; 7282 7283 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7284 .substreams = 1, 7285 .channels_min = 2, 7286 .channels_max = 2, 7287 }; 7288 7289 static int ca0132_build_pcms(struct hda_codec *codec) 7290 { 7291 struct ca0132_spec *spec = codec->spec; 7292 struct hda_pcm *info; 7293 7294 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7295 if (!info) 7296 return -ENOMEM; 7297 if (ca0132_use_alt_functions(spec)) { 7298 info->own_chmap = true; 7299 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7300 = ca0132_alt_chmaps; 7301 } 7302 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7303 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7304 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7305 spec->multiout.max_channels; 7306 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7307 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7308 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7309 7310 /* With the DSP enabled, desktops don't use this ADC. */ 7311 if (!ca0132_use_alt_functions(spec)) { 7312 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7313 if (!info) 7314 return -ENOMEM; 7315 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7316 ca0132_pcm_analog_capture; 7317 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7318 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7319 } 7320 7321 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7322 if (!info) 7323 return -ENOMEM; 7324 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7325 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7326 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7327 7328 if (!spec->dig_out && !spec->dig_in) 7329 return 0; 7330 7331 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7332 if (!info) 7333 return -ENOMEM; 7334 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7335 if (spec->dig_out) { 7336 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7337 ca0132_pcm_digital_playback; 7338 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7339 } 7340 if (spec->dig_in) { 7341 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7342 ca0132_pcm_digital_capture; 7343 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7344 } 7345 7346 return 0; 7347 } 7348 7349 static int dbpro_build_pcms(struct hda_codec *codec) 7350 { 7351 struct ca0132_spec *spec = codec->spec; 7352 struct hda_pcm *info; 7353 7354 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7355 if (!info) 7356 return -ENOMEM; 7357 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7358 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7359 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7360 7361 7362 if (!spec->dig_out && !spec->dig_in) 7363 return 0; 7364 7365 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7366 if (!info) 7367 return -ENOMEM; 7368 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7369 if (spec->dig_out) { 7370 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7371 ca0132_pcm_digital_playback; 7372 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7373 } 7374 if (spec->dig_in) { 7375 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7376 ca0132_pcm_digital_capture; 7377 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7378 } 7379 7380 return 0; 7381 } 7382 7383 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7384 { 7385 if (pin) { 7386 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7387 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7388 snd_hda_codec_write(codec, pin, 0, 7389 AC_VERB_SET_AMP_GAIN_MUTE, 7390 AMP_OUT_UNMUTE); 7391 } 7392 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7393 snd_hda_codec_write(codec, dac, 0, 7394 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7395 } 7396 7397 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7398 { 7399 if (pin) { 7400 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7401 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7402 snd_hda_codec_write(codec, pin, 0, 7403 AC_VERB_SET_AMP_GAIN_MUTE, 7404 AMP_IN_UNMUTE(0)); 7405 } 7406 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7407 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7408 AMP_IN_UNMUTE(0)); 7409 7410 /* init to 0 dB and unmute. */ 7411 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7412 HDA_AMP_VOLMASK, 0x5a); 7413 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7414 HDA_AMP_MUTE, 0); 7415 } 7416 } 7417 7418 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7419 { 7420 unsigned int caps; 7421 7422 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7423 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7424 snd_hda_override_amp_caps(codec, nid, dir, caps); 7425 } 7426 7427 /* 7428 * Switch between Digital built-in mic and analog mic. 7429 */ 7430 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7431 { 7432 struct ca0132_spec *spec = codec->spec; 7433 unsigned int tmp; 7434 u8 val; 7435 unsigned int oldval; 7436 7437 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7438 7439 oldval = stop_mic1(codec); 7440 ca0132_set_vipsource(codec, 0); 7441 if (enable) { 7442 /* set DMic input as 2-ch */ 7443 tmp = FLOAT_TWO; 7444 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7445 7446 val = spec->dmic_ctl; 7447 val |= 0x80; 7448 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7449 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7450 7451 if (!(spec->dmic_ctl & 0x20)) 7452 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7453 } else { 7454 /* set AMic input as mono */ 7455 tmp = FLOAT_ONE; 7456 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7457 7458 val = spec->dmic_ctl; 7459 /* clear bit7 and bit5 to disable dmic */ 7460 val &= 0x5f; 7461 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7462 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7463 7464 if (!(spec->dmic_ctl & 0x20)) 7465 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7466 } 7467 ca0132_set_vipsource(codec, 1); 7468 resume_mic1(codec, oldval); 7469 } 7470 7471 /* 7472 * Initialization for Digital Mic. 7473 */ 7474 static void ca0132_init_dmic(struct hda_codec *codec) 7475 { 7476 struct ca0132_spec *spec = codec->spec; 7477 u8 val; 7478 7479 /* Setup Digital Mic here, but don't enable. 7480 * Enable based on jack detect. 7481 */ 7482 7483 /* MCLK uses MPIO1, set to enable. 7484 * Bit 2-0: MPIO select 7485 * Bit 3: set to disable 7486 * Bit 7-4: reserved 7487 */ 7488 val = 0x01; 7489 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7490 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7491 7492 /* Data1 uses MPIO3. Data2 not use 7493 * Bit 2-0: Data1 MPIO select 7494 * Bit 3: set disable Data1 7495 * Bit 6-4: Data2 MPIO select 7496 * Bit 7: set disable Data2 7497 */ 7498 val = 0x83; 7499 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7500 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7501 7502 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7503 * Bit 3-0: Channel mask 7504 * Bit 4: set for 48KHz, clear for 32KHz 7505 * Bit 5: mode 7506 * Bit 6: set to select Data2, clear for Data1 7507 * Bit 7: set to enable DMic, clear for AMic 7508 */ 7509 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7510 val = 0x33; 7511 else 7512 val = 0x23; 7513 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7514 spec->dmic_ctl = val; 7515 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7516 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7517 } 7518 7519 /* 7520 * Initialization for Analog Mic 2 7521 */ 7522 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7523 { 7524 struct ca0132_spec *spec = codec->spec; 7525 7526 mutex_lock(&spec->chipio_mutex); 7527 7528 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7529 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7530 7531 mutex_unlock(&spec->chipio_mutex); 7532 } 7533 7534 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7535 { 7536 struct ca0132_spec *spec = codec->spec; 7537 int i; 7538 7539 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7540 snd_hda_codec_update_widgets(codec); 7541 7542 for (i = 0; i < spec->multiout.num_dacs; i++) 7543 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7544 7545 for (i = 0; i < spec->num_outputs; i++) 7546 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7547 7548 for (i = 0; i < spec->num_inputs; i++) { 7549 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7550 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7551 } 7552 } 7553 7554 7555 /* If there is an active channel for some reason, find it and free it. */ 7556 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7557 { 7558 unsigned int i, tmp; 7559 int status; 7560 7561 /* Read active DSPDMAC channel register. */ 7562 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7563 if (status >= 0) { 7564 /* AND against 0xfff to get the active channel bits. */ 7565 tmp = tmp & 0xfff; 7566 7567 /* If there are no active channels, nothing to free. */ 7568 if (!tmp) 7569 return; 7570 } else { 7571 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7572 __func__); 7573 return; 7574 } 7575 7576 /* 7577 * Check each DSP DMA channel for activity, and if the channel is 7578 * active, free it. 7579 */ 7580 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7581 if (dsp_is_dma_active(codec, i)) { 7582 status = dspio_free_dma_chan(codec, i); 7583 if (status < 0) 7584 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7585 __func__, i); 7586 } 7587 } 7588 } 7589 7590 /* 7591 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7592 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7593 * Instead, audio is now routed through the DSP's DMA controllers, which 7594 * the DSP is tasked with setting up itself. Through debugging, it seems the 7595 * cause of most of the no-audio on startup issues were due to improperly 7596 * configured DSP DMA channels. 7597 * 7598 * Normally, the DSP configures these the first time an HDA audio stream is 7599 * started post DSP firmware download. That is why creating a 'dummy' stream 7600 * worked in fixing the audio in some cases. This works most of the time, but 7601 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7602 * configuration registers, it ends up in a broken state. Issues can also 7603 * arise if streams are started in an unusual order, i.e the audio output dma 7604 * channel being sandwiched between the mic1 and mic2 dma channels. 7605 * 7606 * The solution to this is to make sure that the DSP has no DMA channels 7607 * in use post DSP firmware download, and then to manually start each default 7608 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7609 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7610 */ 7611 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7612 { 7613 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7614 struct ca0132_spec *spec = codec->spec; 7615 unsigned int i, tmp; 7616 7617 /* 7618 * Check if any of the default streams are active, and if they are, 7619 * stop them. 7620 */ 7621 mutex_lock(&spec->chipio_mutex); 7622 7623 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7624 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7625 7626 if (tmp) { 7627 chipio_set_stream_control(codec, 7628 dsp_dma_stream_ids[i], 0); 7629 } 7630 } 7631 7632 mutex_unlock(&spec->chipio_mutex); 7633 7634 /* 7635 * If all DSP streams are inactive, there should be no active DSP DMA 7636 * channels. Check and make sure this is the case, and if it isn't, 7637 * free any active channels. 7638 */ 7639 ca0132_alt_free_active_dma_channels(codec); 7640 7641 mutex_lock(&spec->chipio_mutex); 7642 7643 /* Make sure stream 0x0c is six channels. */ 7644 chipio_set_stream_channels(codec, 0x0c, 6); 7645 7646 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7647 chipio_set_stream_control(codec, 7648 dsp_dma_stream_ids[i], 1); 7649 7650 /* Give the DSP some time to setup the DMA channel. */ 7651 msleep(75); 7652 } 7653 7654 mutex_unlock(&spec->chipio_mutex); 7655 } 7656 7657 /* 7658 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7659 * router', where each entry represents a 48khz audio channel, with a format 7660 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7661 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7662 * and 3 if it's using Sample Rate Converter ports. 7663 * An example is: 7664 * 0x0001f8c0 7665 * In this case, f8 is the destination, and c0 is the source. The number value 7666 * is 1. 7667 * This region of memory is normally managed internally by the 8051, where 7668 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7669 * entry within the 0x190000 range, and when a range of entries is in use, the 7670 * ending value is overwritten with 0xff. 7671 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7672 * streamID's, where each entry is a starting 0x190000 port offset. 7673 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7674 * offset for the corresponding streamID. 7675 * 7676 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7677 * the 8051, then manually overwritten to remap the ports to work with the 7678 * new DACs. 7679 * 7680 * Currently known portID's: 7681 * 0x00-0x1f: HDA audio stream input/output ports. 7682 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7683 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7684 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7685 * 0xe0-0xff: DAC/ADC audio input/output ports. 7686 * 7687 * Currently known streamID's: 7688 * 0x03: Mic1 ADC to DSP. 7689 * 0x04: Mic2 ADC to DSP. 7690 * 0x05: HDA node 0x02 audio stream to DSP. 7691 * 0x0f: DSP Mic exit to HDA node 0x07. 7692 * 0x0c: DSP processed audio to DACs. 7693 * 0x14: DAC0, front L/R. 7694 * 7695 * It is possible to route the HDA audio streams directly to the DAC and 7696 * bypass the DSP entirely, with the only downside being that since the DSP 7697 * does volume control, the only volume control you'll get is through PCM on 7698 * the PC side, in the same way volume is handled for optical out. This may be 7699 * useful for debugging. 7700 */ 7701 static void chipio_remap_stream(struct hda_codec *codec, 7702 const struct chipio_stream_remap_data *remap_data) 7703 { 7704 unsigned int i, stream_offset; 7705 7706 /* Get the starting port for the stream to be remapped. */ 7707 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7708 &stream_offset); 7709 7710 /* 7711 * Check if the stream's port value is 0xff, because the 8051 may not 7712 * have gotten around to setting up the stream yet. Wait until it's 7713 * setup to remap it's ports. 7714 */ 7715 if (stream_offset == 0xff) { 7716 for (i = 0; i < 5; i++) { 7717 msleep(25); 7718 7719 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7720 &stream_offset); 7721 7722 if (stream_offset != 0xff) 7723 break; 7724 } 7725 } 7726 7727 if (stream_offset == 0xff) { 7728 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7729 __func__, remap_data->stream_id); 7730 return; 7731 } 7732 7733 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7734 stream_offset *= 0x04; 7735 stream_offset += 0x190000; 7736 7737 for (i = 0; i < remap_data->count; i++) { 7738 chipio_write_no_mutex(codec, 7739 stream_offset + remap_data->offset[i], 7740 remap_data->value[i]); 7741 } 7742 7743 /* Update stream map configuration. */ 7744 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7745 } 7746 7747 /* 7748 * Default speaker tuning values setup for alternative codecs. 7749 */ 7750 static const unsigned int sbz_default_delay_values[] = { 7751 /* Non-zero values are floating point 0.000198. */ 7752 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7753 }; 7754 7755 static const unsigned int zxr_default_delay_values[] = { 7756 /* Non-zero values are floating point 0.000220. */ 7757 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7758 }; 7759 7760 static const unsigned int ae5_default_delay_values[] = { 7761 /* Non-zero values are floating point 0.000100. */ 7762 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7763 }; 7764 7765 /* 7766 * If we never change these, probably only need them on initialization. 7767 */ 7768 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7769 { 7770 struct ca0132_spec *spec = codec->spec; 7771 unsigned int i, tmp, start_req, end_req; 7772 const unsigned int *values; 7773 7774 switch (ca0132_quirk(spec)) { 7775 case QUIRK_SBZ: 7776 values = sbz_default_delay_values; 7777 break; 7778 case QUIRK_ZXR: 7779 values = zxr_default_delay_values; 7780 break; 7781 case QUIRK_AE5: 7782 case QUIRK_AE7: 7783 values = ae5_default_delay_values; 7784 break; 7785 default: 7786 values = sbz_default_delay_values; 7787 break; 7788 } 7789 7790 tmp = FLOAT_ZERO; 7791 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7792 7793 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7794 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7795 for (i = start_req; i < end_req + 1; i++) 7796 dspio_set_uint_param(codec, 0x96, i, tmp); 7797 7798 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7799 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7800 for (i = start_req; i < end_req + 1; i++) 7801 dspio_set_uint_param(codec, 0x96, i, tmp); 7802 7803 7804 for (i = 0; i < 6; i++) 7805 dspio_set_uint_param(codec, 0x96, 7806 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7807 } 7808 7809 /* 7810 * Initialize mic for non-chromebook ca0132 implementations. 7811 */ 7812 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7813 { 7814 struct ca0132_spec *spec = codec->spec; 7815 unsigned int tmp; 7816 7817 /* Mic 1 Setup */ 7818 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7819 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7820 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7821 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7822 tmp = FLOAT_ONE; 7823 } else 7824 tmp = FLOAT_THREE; 7825 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7826 7827 /* Mic 2 setup (not present on desktop cards) */ 7828 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7829 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7830 if (ca0132_quirk(spec) == QUIRK_R3DI) 7831 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7832 tmp = FLOAT_ZERO; 7833 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7834 } 7835 7836 /* 7837 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7838 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7839 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7840 * having an updated DAC, which changes the destination to that DAC. 7841 */ 7842 static void sbz_connect_streams(struct hda_codec *codec) 7843 { 7844 struct ca0132_spec *spec = codec->spec; 7845 7846 mutex_lock(&spec->chipio_mutex); 7847 7848 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7849 7850 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7851 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7852 7853 /* Setup stream 0x14 with it's source and destination points */ 7854 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7855 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7856 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7857 chipio_set_stream_channels(codec, 0x14, 2); 7858 chipio_set_stream_control(codec, 0x14, 1); 7859 7860 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7861 7862 mutex_unlock(&spec->chipio_mutex); 7863 } 7864 7865 /* 7866 * Write data through ChipIO to setup proper stream destinations. 7867 * Not sure how it exactly works, but it seems to direct data 7868 * to different destinations. Example is f8 to c0, e0 to c0. 7869 * All I know is, if you don't set these, you get no sound. 7870 */ 7871 static void sbz_chipio_startup_data(struct hda_codec *codec) 7872 { 7873 const struct chipio_stream_remap_data *dsp_out_remap_data; 7874 struct ca0132_spec *spec = codec->spec; 7875 7876 mutex_lock(&spec->chipio_mutex); 7877 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7878 7879 /* Remap DAC0's output ports. */ 7880 chipio_remap_stream(codec, &stream_remap_data[0]); 7881 7882 /* Remap DSP audio output stream ports. */ 7883 switch (ca0132_quirk(spec)) { 7884 case QUIRK_SBZ: 7885 dsp_out_remap_data = &stream_remap_data[1]; 7886 break; 7887 7888 case QUIRK_ZXR: 7889 dsp_out_remap_data = &stream_remap_data[2]; 7890 break; 7891 7892 default: 7893 dsp_out_remap_data = NULL; 7894 break; 7895 } 7896 7897 if (dsp_out_remap_data) 7898 chipio_remap_stream(codec, dsp_out_remap_data); 7899 7900 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7901 mutex_unlock(&spec->chipio_mutex); 7902 } 7903 7904 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7905 { 7906 struct ca0132_spec *spec = codec->spec; 7907 unsigned int tmp; 7908 7909 chipio_set_stream_control(codec, 0x03, 0); 7910 chipio_set_stream_control(codec, 0x04, 0); 7911 7912 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7913 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7914 7915 tmp = FLOAT_THREE; 7916 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7917 7918 chipio_set_stream_control(codec, 0x03, 1); 7919 chipio_set_stream_control(codec, 0x04, 1); 7920 7921 switch (ca0132_quirk(spec)) { 7922 case QUIRK_SBZ: 7923 chipio_write(codec, 0x18b098, 0x0000000c); 7924 chipio_write(codec, 0x18b09C, 0x0000000c); 7925 break; 7926 case QUIRK_AE5: 7927 chipio_write(codec, 0x18b098, 0x0000000c); 7928 chipio_write(codec, 0x18b09c, 0x0000004c); 7929 break; 7930 default: 7931 break; 7932 } 7933 } 7934 7935 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7936 { 7937 struct ca0132_spec *spec = codec->spec; 7938 7939 chipio_8051_write_direct(codec, 0x93, 0x10); 7940 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7941 7942 writeb(0xff, spec->mem_base + 0x304); 7943 writeb(0xff, spec->mem_base + 0x304); 7944 writeb(0xff, spec->mem_base + 0x304); 7945 writeb(0xff, spec->mem_base + 0x304); 7946 writeb(0x00, spec->mem_base + 0x100); 7947 writeb(0xff, spec->mem_base + 0x304); 7948 writeb(0x00, spec->mem_base + 0x100); 7949 writeb(0xff, spec->mem_base + 0x304); 7950 writeb(0x00, spec->mem_base + 0x100); 7951 writeb(0xff, spec->mem_base + 0x304); 7952 writeb(0x00, spec->mem_base + 0x100); 7953 writeb(0xff, spec->mem_base + 0x304); 7954 7955 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7956 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7957 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7958 } 7959 7960 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7961 { 7962 /* 7963 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7964 * which seems to be 'multichannel'. This is also mentioned in the 7965 * AE-5's registry values in Windows. 7966 */ 7967 chipio_set_control_param(codec, 3, 0); 7968 /* 7969 * I believe ASI is 'audio serial interface' and that it's used to 7970 * change colors on the external LED strip connected to the AE-5. 7971 */ 7972 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7973 7974 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7975 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7976 7977 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7978 } 7979 7980 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7981 { 7982 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7983 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7984 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7985 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7986 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7987 } 7988 7989 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7990 { 7991 struct ca0132_spec *spec = codec->spec; 7992 7993 mutex_lock(&spec->chipio_mutex); 7994 7995 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7996 7997 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7998 7999 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 8000 8001 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 8002 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8003 chipio_set_stream_channels(codec, 0x18, 6); 8004 chipio_set_stream_control(codec, 0x18, 1); 8005 8006 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8007 8008 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8009 8010 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 8011 8012 mutex_unlock(&spec->chipio_mutex); 8013 } 8014 8015 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 8016 { 8017 struct ca0132_spec *spec = codec->spec; 8018 8019 mutex_lock(&spec->chipio_mutex); 8020 8021 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8022 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8023 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8024 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8025 8026 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8027 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8028 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 8029 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 8030 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 8031 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8032 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8033 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8034 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8035 ca0113_mmio_gpio_set(codec, 0, true); 8036 ca0113_mmio_gpio_set(codec, 1, true); 8037 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 8038 8039 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 8040 8041 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8042 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8043 8044 mutex_unlock(&spec->chipio_mutex); 8045 } 8046 8047 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 8048 { 8049 struct ca0132_spec *spec = codec->spec; 8050 8051 mutex_lock(&spec->chipio_mutex); 8052 8053 /* Seems to share the same port remapping as the SBZ. */ 8054 chipio_remap_stream(codec, &stream_remap_data[1]); 8055 8056 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8057 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 8058 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8059 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8060 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8061 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8062 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8063 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8064 8065 mutex_unlock(&spec->chipio_mutex); 8066 } 8067 8068 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8069 { 8070 struct ca0132_spec *spec = codec->spec; 8071 8072 mutex_lock(&spec->chipio_mutex); 8073 8074 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8075 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8076 8077 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8078 8079 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8080 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8081 8082 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8083 chipio_set_stream_channels(codec, 0x18, 6); 8084 chipio_set_stream_control(codec, 0x18, 1); 8085 8086 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8087 8088 mutex_unlock(&spec->chipio_mutex); 8089 } 8090 8091 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8092 { 8093 static const unsigned int addr[] = { 8094 0x41, 0x45, 0x40, 0x43, 0x51 8095 }; 8096 static const unsigned int data[] = { 8097 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8098 }; 8099 unsigned int i; 8100 8101 for (i = 0; i < ARRAY_SIZE(addr); i++) 8102 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8103 } 8104 8105 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8106 { 8107 struct ca0132_spec *spec = codec->spec; 8108 static const unsigned int target[] = { 8109 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8110 }; 8111 static const unsigned int data[] = { 8112 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8113 }; 8114 unsigned int i; 8115 8116 mutex_lock(&spec->chipio_mutex); 8117 8118 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8119 8120 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8121 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8122 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8123 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8124 8125 ae7_post_dsp_pll_setup(codec); 8126 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8127 8128 for (i = 0; i < ARRAY_SIZE(target); i++) 8129 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8130 8131 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8132 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8133 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8134 8135 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8136 chipio_set_stream_channels(codec, 0x21, 2); 8137 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8138 8139 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8140 /* 8141 * In the 8051's memory, this param is referred to as 'n2sid', which I 8142 * believe is 'node to streamID'. It seems to be a way to assign a 8143 * stream to a given HDA node. 8144 */ 8145 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8146 8147 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8148 8149 /* 8150 * Now, at this point on Windows, an actual stream is setup and 8151 * seemingly sends data to the HDA node 0x09, which is the digital 8152 * audio input node. This is left out here, because obviously I don't 8153 * know what data is being sent. Interestingly, the AE-5 seems to go 8154 * through the motions of getting here and never actually takes this 8155 * step, but the AE-7 does. 8156 */ 8157 8158 ca0113_mmio_gpio_set(codec, 0, 1); 8159 ca0113_mmio_gpio_set(codec, 1, 1); 8160 8161 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8162 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8163 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8164 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8165 8166 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8167 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8168 8169 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8170 chipio_set_stream_channels(codec, 0x18, 6); 8171 8172 /* 8173 * Runs again, this has been repeated a few times, but I'm just 8174 * following what the Windows driver does. 8175 */ 8176 ae7_post_dsp_pll_setup(codec); 8177 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8178 8179 mutex_unlock(&spec->chipio_mutex); 8180 } 8181 8182 /* 8183 * The Windows driver has commands that seem to setup ASI, which I believe to 8184 * be some sort of audio serial interface. My current speculation is that it's 8185 * related to communicating with the new DAC. 8186 */ 8187 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8188 { 8189 chipio_8051_write_direct(codec, 0x93, 0x10); 8190 8191 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8192 8193 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8194 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8195 8196 chipio_set_control_param(codec, 3, 3); 8197 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8198 8199 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8200 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8201 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8202 8203 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8204 8205 ae7_post_dsp_pll_setup(codec); 8206 ae7_post_dsp_asi_stream_setup(codec); 8207 8208 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8209 8210 ae7_post_dsp_asi_setup_ports(codec); 8211 } 8212 8213 /* 8214 * Setup default parameters for DSP 8215 */ 8216 static void ca0132_setup_defaults(struct hda_codec *codec) 8217 { 8218 struct ca0132_spec *spec = codec->spec; 8219 unsigned int tmp; 8220 int num_fx; 8221 int idx, i; 8222 8223 if (spec->dsp_state != DSP_DOWNLOADED) 8224 return; 8225 8226 /* out, in effects + voicefx */ 8227 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8228 for (idx = 0; idx < num_fx; idx++) { 8229 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8230 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8231 ca0132_effects[idx].reqs[i], 8232 ca0132_effects[idx].def_vals[i]); 8233 } 8234 } 8235 8236 /*remove DSP headroom*/ 8237 tmp = FLOAT_ZERO; 8238 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8239 8240 /*set speaker EQ bypass attenuation*/ 8241 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8242 8243 /* set AMic1 and AMic2 as mono mic */ 8244 tmp = FLOAT_ONE; 8245 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8246 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8247 8248 /* set AMic1 as CrystalVoice input */ 8249 tmp = FLOAT_ONE; 8250 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8251 8252 /* set WUH source */ 8253 tmp = FLOAT_TWO; 8254 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8255 } 8256 8257 /* 8258 * Setup default parameters for Recon3D/Recon3Di DSP. 8259 */ 8260 8261 static void r3d_setup_defaults(struct hda_codec *codec) 8262 { 8263 struct ca0132_spec *spec = codec->spec; 8264 unsigned int tmp; 8265 int num_fx; 8266 int idx, i; 8267 8268 if (spec->dsp_state != DSP_DOWNLOADED) 8269 return; 8270 8271 ca0132_alt_init_analog_mics(codec); 8272 ca0132_alt_start_dsp_audio_streams(codec); 8273 8274 /*remove DSP headroom*/ 8275 tmp = FLOAT_ZERO; 8276 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8277 8278 /* set WUH source */ 8279 tmp = FLOAT_TWO; 8280 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8281 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8282 8283 /* Set speaker source? */ 8284 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8285 8286 if (ca0132_quirk(spec) == QUIRK_R3DI) 8287 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8288 8289 /* Disable mute on Center/LFE. */ 8290 if (ca0132_quirk(spec) == QUIRK_R3D) { 8291 ca0113_mmio_gpio_set(codec, 2, false); 8292 ca0113_mmio_gpio_set(codec, 4, true); 8293 } 8294 8295 /* Setup effect defaults */ 8296 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8297 for (idx = 0; idx < num_fx; idx++) { 8298 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8299 dspio_set_uint_param(codec, 8300 ca0132_effects[idx].mid, 8301 ca0132_effects[idx].reqs[i], 8302 ca0132_effects[idx].def_vals[i]); 8303 } 8304 } 8305 } 8306 8307 /* 8308 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8309 * than the Chromebook setup. 8310 */ 8311 static void sbz_setup_defaults(struct hda_codec *codec) 8312 { 8313 struct ca0132_spec *spec = codec->spec; 8314 unsigned int tmp; 8315 int num_fx; 8316 int idx, i; 8317 8318 if (spec->dsp_state != DSP_DOWNLOADED) 8319 return; 8320 8321 ca0132_alt_init_analog_mics(codec); 8322 ca0132_alt_start_dsp_audio_streams(codec); 8323 sbz_connect_streams(codec); 8324 sbz_chipio_startup_data(codec); 8325 8326 /* 8327 * Sets internal input loopback to off, used to have a switch to 8328 * enable input loopback, but turned out to be way too buggy. 8329 */ 8330 tmp = FLOAT_ONE; 8331 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8332 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8333 8334 /*remove DSP headroom*/ 8335 tmp = FLOAT_ZERO; 8336 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8337 8338 /* set WUH source */ 8339 tmp = FLOAT_TWO; 8340 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8341 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8342 8343 /* Set speaker source? */ 8344 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8345 8346 ca0132_alt_dsp_initial_mic_setup(codec); 8347 8348 /* out, in effects + voicefx */ 8349 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8350 for (idx = 0; idx < num_fx; idx++) { 8351 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8352 dspio_set_uint_param(codec, 8353 ca0132_effects[idx].mid, 8354 ca0132_effects[idx].reqs[i], 8355 ca0132_effects[idx].def_vals[i]); 8356 } 8357 } 8358 8359 ca0132_alt_init_speaker_tuning(codec); 8360 } 8361 8362 /* 8363 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8364 */ 8365 static void ae5_setup_defaults(struct hda_codec *codec) 8366 { 8367 struct ca0132_spec *spec = codec->spec; 8368 unsigned int tmp; 8369 int num_fx; 8370 int idx, i; 8371 8372 if (spec->dsp_state != DSP_DOWNLOADED) 8373 return; 8374 8375 ca0132_alt_init_analog_mics(codec); 8376 ca0132_alt_start_dsp_audio_streams(codec); 8377 8378 /* New, unknown SCP req's */ 8379 tmp = FLOAT_ZERO; 8380 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8381 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8382 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8383 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8384 8385 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8386 ca0113_mmio_gpio_set(codec, 0, false); 8387 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8388 8389 /* Internal loopback off */ 8390 tmp = FLOAT_ONE; 8391 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8392 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8393 8394 /*remove DSP headroom*/ 8395 tmp = FLOAT_ZERO; 8396 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8397 8398 /* set WUH source */ 8399 tmp = FLOAT_TWO; 8400 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8401 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8402 8403 /* Set speaker source? */ 8404 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8405 8406 ca0132_alt_dsp_initial_mic_setup(codec); 8407 ae5_post_dsp_register_set(codec); 8408 ae5_post_dsp_param_setup(codec); 8409 ae5_post_dsp_pll_setup(codec); 8410 ae5_post_dsp_stream_setup(codec); 8411 ae5_post_dsp_startup_data(codec); 8412 8413 /* out, in effects + voicefx */ 8414 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8415 for (idx = 0; idx < num_fx; idx++) { 8416 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8417 dspio_set_uint_param(codec, 8418 ca0132_effects[idx].mid, 8419 ca0132_effects[idx].reqs[i], 8420 ca0132_effects[idx].def_vals[i]); 8421 } 8422 } 8423 8424 ca0132_alt_init_speaker_tuning(codec); 8425 } 8426 8427 /* 8428 * Setup default parameters for the Sound Blaster AE-7 DSP. 8429 */ 8430 static void ae7_setup_defaults(struct hda_codec *codec) 8431 { 8432 struct ca0132_spec *spec = codec->spec; 8433 unsigned int tmp; 8434 int num_fx; 8435 int idx, i; 8436 8437 if (spec->dsp_state != DSP_DOWNLOADED) 8438 return; 8439 8440 ca0132_alt_init_analog_mics(codec); 8441 ca0132_alt_start_dsp_audio_streams(codec); 8442 ae7_post_dsp_setup_ports(codec); 8443 8444 tmp = FLOAT_ZERO; 8445 dspio_set_uint_param(codec, 0x96, 8446 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8447 dspio_set_uint_param(codec, 0x96, 8448 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8449 8450 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8451 8452 /* New, unknown SCP req's */ 8453 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8454 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8455 8456 ca0113_mmio_gpio_set(codec, 0, false); 8457 8458 /* Internal loopback off */ 8459 tmp = FLOAT_ONE; 8460 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8461 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8462 8463 /*remove DSP headroom*/ 8464 tmp = FLOAT_ZERO; 8465 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8466 8467 /* set WUH source */ 8468 tmp = FLOAT_TWO; 8469 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8470 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8471 8472 /* Set speaker source? */ 8473 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8474 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8475 8476 /* 8477 * This is the second time we've called this, but this is seemingly 8478 * what Windows does. 8479 */ 8480 ca0132_alt_init_analog_mics(codec); 8481 8482 ae7_post_dsp_asi_setup(codec); 8483 8484 /* 8485 * Not sure why, but these are both set to 1. They're only set to 0 8486 * upon shutdown. 8487 */ 8488 ca0113_mmio_gpio_set(codec, 0, true); 8489 ca0113_mmio_gpio_set(codec, 1, true); 8490 8491 /* Volume control related. */ 8492 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8493 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8494 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8495 8496 /* out, in effects + voicefx */ 8497 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8498 for (idx = 0; idx < num_fx; idx++) { 8499 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8500 dspio_set_uint_param(codec, 8501 ca0132_effects[idx].mid, 8502 ca0132_effects[idx].reqs[i], 8503 ca0132_effects[idx].def_vals[i]); 8504 } 8505 } 8506 8507 ca0132_alt_init_speaker_tuning(codec); 8508 } 8509 8510 /* 8511 * Initialization of flags in chip 8512 */ 8513 static void ca0132_init_flags(struct hda_codec *codec) 8514 { 8515 struct ca0132_spec *spec = codec->spec; 8516 8517 if (ca0132_use_alt_functions(spec)) { 8518 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8519 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8520 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8521 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8522 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8523 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8524 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8525 chipio_set_control_flag(codec, 8526 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8527 chipio_set_control_flag(codec, 8528 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8529 } else { 8530 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8531 chipio_set_control_flag(codec, 8532 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8533 chipio_set_control_flag(codec, 8534 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8535 chipio_set_control_flag(codec, 8536 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8537 chipio_set_control_flag(codec, 8538 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8539 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8540 } 8541 } 8542 8543 /* 8544 * Initialization of parameters in chip 8545 */ 8546 static void ca0132_init_params(struct hda_codec *codec) 8547 { 8548 struct ca0132_spec *spec = codec->spec; 8549 8550 if (ca0132_use_alt_functions(spec)) { 8551 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8552 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8553 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8554 chipio_set_control_param(codec, 0, 0); 8555 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8556 } 8557 8558 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8559 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8560 } 8561 8562 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8563 { 8564 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8565 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8566 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8567 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8568 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8569 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8570 8571 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8572 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8573 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8574 } 8575 8576 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8577 { 8578 bool dsp_loaded = false; 8579 struct ca0132_spec *spec = codec->spec; 8580 const struct dsp_image_seg *dsp_os_image; 8581 const struct firmware *fw_entry = NULL; 8582 /* 8583 * Alternate firmwares for different variants. The Recon3Di apparently 8584 * can use the default firmware, but I'll leave the option in case 8585 * it needs it again. 8586 */ 8587 switch (ca0132_quirk(spec)) { 8588 case QUIRK_SBZ: 8589 case QUIRK_R3D: 8590 case QUIRK_AE5: 8591 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8592 codec->card->dev) != 0) 8593 codec_dbg(codec, "Desktop firmware not found."); 8594 else 8595 codec_dbg(codec, "Desktop firmware selected."); 8596 break; 8597 case QUIRK_R3DI: 8598 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8599 codec->card->dev) != 0) 8600 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8601 else 8602 codec_dbg(codec, "Recon3Di firmware selected."); 8603 break; 8604 default: 8605 break; 8606 } 8607 /* 8608 * Use default ctefx.bin if no alt firmware is detected, or if none 8609 * exists for your particular codec. 8610 */ 8611 if (!fw_entry) { 8612 codec_dbg(codec, "Default firmware selected."); 8613 if (request_firmware(&fw_entry, EFX_FILE, 8614 codec->card->dev) != 0) 8615 return false; 8616 } 8617 8618 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8619 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8620 codec_err(codec, "ca0132 DSP load image failed\n"); 8621 goto exit_download; 8622 } 8623 8624 dsp_loaded = dspload_wait_loaded(codec); 8625 8626 exit_download: 8627 release_firmware(fw_entry); 8628 8629 return dsp_loaded; 8630 } 8631 8632 static void ca0132_download_dsp(struct hda_codec *codec) 8633 { 8634 struct ca0132_spec *spec = codec->spec; 8635 8636 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8637 return; /* NOP */ 8638 #endif 8639 8640 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8641 return; /* don't retry failures */ 8642 8643 chipio_enable_clocks(codec); 8644 if (spec->dsp_state != DSP_DOWNLOADED) { 8645 spec->dsp_state = DSP_DOWNLOADING; 8646 8647 if (!ca0132_download_dsp_images(codec)) 8648 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8649 else 8650 spec->dsp_state = DSP_DOWNLOADED; 8651 } 8652 8653 /* For codecs using alt functions, this is already done earlier */ 8654 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8655 ca0132_set_dsp_msr(codec, true); 8656 } 8657 8658 static void ca0132_process_dsp_response(struct hda_codec *codec, 8659 struct hda_jack_callback *callback) 8660 { 8661 struct ca0132_spec *spec = codec->spec; 8662 8663 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8664 snd_hda_power_up_pm(codec); 8665 if (spec->wait_scp) { 8666 if (dspio_get_response_data(codec) >= 0) 8667 spec->wait_scp = 0; 8668 } 8669 8670 dspio_clear_response_queue(codec); 8671 snd_hda_power_down_pm(codec); 8672 } 8673 8674 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8675 { 8676 struct ca0132_spec *spec = codec->spec; 8677 struct hda_jack_tbl *tbl; 8678 8679 /* Delay enabling the HP amp, to let the mic-detection 8680 * state machine run. 8681 */ 8682 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8683 if (tbl) 8684 tbl->block_report = 1; 8685 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8686 } 8687 8688 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8689 { 8690 struct ca0132_spec *spec = codec->spec; 8691 8692 if (ca0132_use_alt_functions(spec)) 8693 ca0132_alt_select_in(codec); 8694 else 8695 ca0132_select_mic(codec); 8696 } 8697 8698 static void ca0132_setup_unsol(struct hda_codec *codec) 8699 { 8700 struct ca0132_spec *spec = codec->spec; 8701 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8702 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8703 amic_callback); 8704 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8705 ca0132_process_dsp_response); 8706 /* Front headphone jack detection */ 8707 if (ca0132_use_alt_functions(spec)) 8708 snd_hda_jack_detect_enable_callback(codec, 8709 spec->unsol_tag_front_hp, hp_callback); 8710 } 8711 8712 /* 8713 * Verbs tables. 8714 */ 8715 8716 /* Sends before DSP download. */ 8717 static const struct hda_verb ca0132_base_init_verbs[] = { 8718 /*enable ct extension*/ 8719 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8720 {} 8721 }; 8722 8723 /* Send at exit. */ 8724 static const struct hda_verb ca0132_base_exit_verbs[] = { 8725 /*set afg to D3*/ 8726 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8727 /*disable ct extension*/ 8728 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8729 {} 8730 }; 8731 8732 /* Other verbs tables. Sends after DSP download. */ 8733 8734 static const struct hda_verb ca0132_init_verbs0[] = { 8735 /* chip init verbs */ 8736 {0x15, 0x70D, 0xF0}, 8737 {0x15, 0x70E, 0xFE}, 8738 {0x15, 0x707, 0x75}, 8739 {0x15, 0x707, 0xD3}, 8740 {0x15, 0x707, 0x09}, 8741 {0x15, 0x707, 0x53}, 8742 {0x15, 0x707, 0xD4}, 8743 {0x15, 0x707, 0xEF}, 8744 {0x15, 0x707, 0x75}, 8745 {0x15, 0x707, 0xD3}, 8746 {0x15, 0x707, 0x09}, 8747 {0x15, 0x707, 0x02}, 8748 {0x15, 0x707, 0x37}, 8749 {0x15, 0x707, 0x78}, 8750 {0x15, 0x53C, 0xCE}, 8751 {0x15, 0x575, 0xC9}, 8752 {0x15, 0x53D, 0xCE}, 8753 {0x15, 0x5B7, 0xC9}, 8754 {0x15, 0x70D, 0xE8}, 8755 {0x15, 0x70E, 0xFE}, 8756 {0x15, 0x707, 0x02}, 8757 {0x15, 0x707, 0x68}, 8758 {0x15, 0x707, 0x62}, 8759 {0x15, 0x53A, 0xCE}, 8760 {0x15, 0x546, 0xC9}, 8761 {0x15, 0x53B, 0xCE}, 8762 {0x15, 0x5E8, 0xC9}, 8763 {} 8764 }; 8765 8766 /* Extra init verbs for desktop cards. */ 8767 static const struct hda_verb ca0132_init_verbs1[] = { 8768 {0x15, 0x70D, 0x20}, 8769 {0x15, 0x70E, 0x19}, 8770 {0x15, 0x707, 0x00}, 8771 {0x15, 0x539, 0xCE}, 8772 {0x15, 0x546, 0xC9}, 8773 {0x15, 0x70D, 0xB7}, 8774 {0x15, 0x70E, 0x09}, 8775 {0x15, 0x707, 0x10}, 8776 {0x15, 0x70D, 0xAF}, 8777 {0x15, 0x70E, 0x09}, 8778 {0x15, 0x707, 0x01}, 8779 {0x15, 0x707, 0x05}, 8780 {0x15, 0x70D, 0x73}, 8781 {0x15, 0x70E, 0x09}, 8782 {0x15, 0x707, 0x14}, 8783 {0x15, 0x6FF, 0xC4}, 8784 {} 8785 }; 8786 8787 static void ca0132_init_chip(struct hda_codec *codec) 8788 { 8789 struct ca0132_spec *spec = codec->spec; 8790 int num_fx; 8791 int i; 8792 unsigned int on; 8793 8794 mutex_init(&spec->chipio_mutex); 8795 8796 /* 8797 * The Windows driver always does this upon startup, which seems to 8798 * clear out any previous configuration. This should help issues where 8799 * a boot into Windows prior to a boot into Linux breaks things. Also, 8800 * Windows always sends the reset twice. 8801 */ 8802 if (ca0132_use_alt_functions(spec)) { 8803 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8804 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 8805 8806 snd_hda_codec_write(codec, codec->core.afg, 0, 8807 AC_VERB_SET_CODEC_RESET, 0); 8808 snd_hda_codec_write(codec, codec->core.afg, 0, 8809 AC_VERB_SET_CODEC_RESET, 0); 8810 } 8811 8812 spec->cur_out_type = SPEAKER_OUT; 8813 if (!ca0132_use_alt_functions(spec)) 8814 spec->cur_mic_type = DIGITAL_MIC; 8815 else 8816 spec->cur_mic_type = REAR_MIC; 8817 8818 spec->cur_mic_boost = 0; 8819 8820 for (i = 0; i < VNODES_COUNT; i++) { 8821 spec->vnode_lvol[i] = 0x5a; 8822 spec->vnode_rvol[i] = 0x5a; 8823 spec->vnode_lswitch[i] = 0; 8824 spec->vnode_rswitch[i] = 0; 8825 } 8826 8827 /* 8828 * Default states for effects are in ca0132_effects[]. 8829 */ 8830 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8831 for (i = 0; i < num_fx; i++) { 8832 on = (unsigned int)ca0132_effects[i].reqs[0]; 8833 spec->effects_switch[i] = on ? 1 : 0; 8834 } 8835 /* 8836 * Sets defaults for the effect slider controls, only for alternative 8837 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8838 */ 8839 if (ca0132_use_alt_controls(spec)) { 8840 /* Set speakers to default to full range. */ 8841 spec->speaker_range_val[0] = 1; 8842 spec->speaker_range_val[1] = 1; 8843 8844 spec->xbass_xover_freq = 8; 8845 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8846 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8847 8848 spec->bass_redirect_xover_freq = 8; 8849 } 8850 8851 spec->voicefx_val = 0; 8852 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8853 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8854 8855 /* 8856 * The ZxR doesn't have a front panel header, and it's line-in is on 8857 * the daughter board. So, there is no input enum control, and we need 8858 * to make sure that spec->in_enum_val is set properly. 8859 */ 8860 if (ca0132_quirk(spec) == QUIRK_ZXR) 8861 spec->in_enum_val = REAR_MIC; 8862 8863 #ifdef ENABLE_TUNING_CONTROLS 8864 ca0132_init_tuning_defaults(codec); 8865 #endif 8866 } 8867 8868 /* 8869 * Recon3Di exit specific commands. 8870 */ 8871 /* prevents popping noise on shutdown */ 8872 static void r3di_gpio_shutdown(struct hda_codec *codec) 8873 { 8874 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8875 } 8876 8877 /* 8878 * Sound Blaster Z exit specific commands. 8879 */ 8880 static void sbz_region2_exit(struct hda_codec *codec) 8881 { 8882 struct ca0132_spec *spec = codec->spec; 8883 unsigned int i; 8884 8885 for (i = 0; i < 4; i++) 8886 writeb(0x0, spec->mem_base + 0x100); 8887 for (i = 0; i < 8; i++) 8888 writeb(0xb3, spec->mem_base + 0x304); 8889 8890 ca0113_mmio_gpio_set(codec, 0, false); 8891 ca0113_mmio_gpio_set(codec, 1, false); 8892 ca0113_mmio_gpio_set(codec, 4, true); 8893 ca0113_mmio_gpio_set(codec, 5, false); 8894 ca0113_mmio_gpio_set(codec, 7, false); 8895 } 8896 8897 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8898 { 8899 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8900 unsigned int i; 8901 8902 snd_hda_codec_write(codec, 0x11, 0, 8903 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8904 8905 for (i = 0; i < ARRAY_SIZE(pins); i++) 8906 snd_hda_codec_write(codec, pins[i], 0, 8907 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8908 } 8909 8910 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8911 { 8912 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8913 unsigned int i; 8914 8915 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8916 snd_hda_codec_write(codec, pins[i], 0, 8917 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8918 } 8919 } 8920 8921 /* On shutdown, sends commands in sets of three */ 8922 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8923 int mask, int data) 8924 { 8925 if (dir >= 0) 8926 snd_hda_codec_write(codec, 0x01, 0, 8927 AC_VERB_SET_GPIO_DIRECTION, dir); 8928 if (mask >= 0) 8929 snd_hda_codec_write(codec, 0x01, 0, 8930 AC_VERB_SET_GPIO_MASK, mask); 8931 8932 if (data >= 0) 8933 snd_hda_codec_write(codec, 0x01, 0, 8934 AC_VERB_SET_GPIO_DATA, data); 8935 } 8936 8937 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8938 { 8939 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8940 unsigned int i; 8941 8942 for (i = 0; i < ARRAY_SIZE(pins); i++) 8943 snd_hda_codec_write(codec, pins[i], 0, 8944 AC_VERB_SET_POWER_STATE, 0x03); 8945 } 8946 8947 static void sbz_exit_chip(struct hda_codec *codec) 8948 { 8949 chipio_set_stream_control(codec, 0x03, 0); 8950 chipio_set_stream_control(codec, 0x04, 0); 8951 8952 /* Mess with GPIO */ 8953 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8954 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8955 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8956 8957 chipio_set_stream_control(codec, 0x14, 0); 8958 chipio_set_stream_control(codec, 0x0C, 0); 8959 8960 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8961 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8962 8963 chipio_write(codec, 0x18a020, 0x00000083); 8964 8965 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8966 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8967 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8968 8969 chipio_set_stream_control(codec, 0x0C, 0); 8970 8971 chipio_set_control_param(codec, 0x0D, 0x24); 8972 8973 ca0132_clear_unsolicited(codec); 8974 sbz_set_pin_ctl_default(codec); 8975 8976 snd_hda_codec_write(codec, 0x0B, 0, 8977 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8978 8979 sbz_region2_exit(codec); 8980 } 8981 8982 static void r3d_exit_chip(struct hda_codec *codec) 8983 { 8984 ca0132_clear_unsolicited(codec); 8985 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8986 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8987 } 8988 8989 static void ae5_exit_chip(struct hda_codec *codec) 8990 { 8991 chipio_set_stream_control(codec, 0x03, 0); 8992 chipio_set_stream_control(codec, 0x04, 0); 8993 8994 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8995 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8996 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8997 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8998 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8999 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 9000 ca0113_mmio_gpio_set(codec, 0, false); 9001 ca0113_mmio_gpio_set(codec, 1, false); 9002 9003 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9004 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9005 9006 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9007 9008 chipio_set_stream_control(codec, 0x18, 0); 9009 chipio_set_stream_control(codec, 0x0c, 0); 9010 9011 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 9012 } 9013 9014 static void ae7_exit_chip(struct hda_codec *codec) 9015 { 9016 chipio_set_stream_control(codec, 0x18, 0); 9017 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 9018 chipio_set_stream_channels(codec, 0x21, 0); 9019 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 9020 chipio_set_control_param(codec, 0x20, 0x01); 9021 9022 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9023 9024 chipio_set_stream_control(codec, 0x18, 0); 9025 chipio_set_stream_control(codec, 0x0c, 0); 9026 9027 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9028 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 9029 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9030 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 9031 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 9032 ca0113_mmio_gpio_set(codec, 0, false); 9033 ca0113_mmio_gpio_set(codec, 1, false); 9034 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9035 9036 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9037 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9038 } 9039 9040 static void zxr_exit_chip(struct hda_codec *codec) 9041 { 9042 chipio_set_stream_control(codec, 0x03, 0); 9043 chipio_set_stream_control(codec, 0x04, 0); 9044 chipio_set_stream_control(codec, 0x14, 0); 9045 chipio_set_stream_control(codec, 0x0C, 0); 9046 9047 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9048 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9049 9050 chipio_write(codec, 0x18a020, 0x00000083); 9051 9052 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9053 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9054 9055 ca0132_clear_unsolicited(codec); 9056 sbz_set_pin_ctl_default(codec); 9057 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9058 9059 ca0113_mmio_gpio_set(codec, 5, false); 9060 ca0113_mmio_gpio_set(codec, 2, false); 9061 ca0113_mmio_gpio_set(codec, 3, false); 9062 ca0113_mmio_gpio_set(codec, 0, false); 9063 ca0113_mmio_gpio_set(codec, 4, true); 9064 ca0113_mmio_gpio_set(codec, 0, true); 9065 ca0113_mmio_gpio_set(codec, 5, true); 9066 ca0113_mmio_gpio_set(codec, 2, false); 9067 ca0113_mmio_gpio_set(codec, 3, false); 9068 } 9069 9070 static void ca0132_exit_chip(struct hda_codec *codec) 9071 { 9072 /* put any chip cleanup stuffs here. */ 9073 9074 if (dspload_is_loaded(codec)) 9075 dsp_reset(codec); 9076 } 9077 9078 /* 9079 * This fixes a problem that was hard to reproduce. Very rarely, I would 9080 * boot up, and there would be no sound, but the DSP indicated it had loaded 9081 * properly. I did a few memory dumps to see if anything was different, and 9082 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9083 * checks if those areas are uninitialized, and if they are, it'll attempt to 9084 * reload the card 3 times. Usually it fixes by the second. 9085 */ 9086 static void sbz_dsp_startup_check(struct hda_codec *codec) 9087 { 9088 struct ca0132_spec *spec = codec->spec; 9089 unsigned int dsp_data_check[4]; 9090 unsigned int cur_address = 0x390; 9091 unsigned int i; 9092 unsigned int failure = 0; 9093 unsigned int reload = 3; 9094 9095 if (spec->startup_check_entered) 9096 return; 9097 9098 spec->startup_check_entered = true; 9099 9100 for (i = 0; i < 4; i++) { 9101 chipio_read(codec, cur_address, &dsp_data_check[i]); 9102 cur_address += 0x4; 9103 } 9104 for (i = 0; i < 4; i++) { 9105 if (dsp_data_check[i] == 0xa1a2a3a4) 9106 failure = 1; 9107 } 9108 9109 codec_dbg(codec, "Startup Check: %d ", failure); 9110 if (failure) 9111 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9112 /* 9113 * While the failure condition is true, and we haven't reached our 9114 * three reload limit, continue trying to reload the driver and 9115 * fix the issue. 9116 */ 9117 while (failure && (reload != 0)) { 9118 codec_info(codec, "Reloading... Tries left: %d", reload); 9119 sbz_exit_chip(codec); 9120 spec->dsp_state = DSP_DOWNLOAD_INIT; 9121 codec->patch_ops.init(codec); 9122 failure = 0; 9123 for (i = 0; i < 4; i++) { 9124 chipio_read(codec, cur_address, &dsp_data_check[i]); 9125 cur_address += 0x4; 9126 } 9127 for (i = 0; i < 4; i++) { 9128 if (dsp_data_check[i] == 0xa1a2a3a4) 9129 failure = 1; 9130 } 9131 reload--; 9132 } 9133 9134 if (!failure && reload < 3) 9135 codec_info(codec, "DSP fixed."); 9136 9137 if (!failure) 9138 return; 9139 9140 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9141 } 9142 9143 /* 9144 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9145 * extra precision for decibel values. If you had the dB value in floating point 9146 * you would take the value after the decimal point, multiply by 64, and divide 9147 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9148 * implement fixed point or floating point dB volumes. For now, I'll set them 9149 * to 0 just incase a value has lingered from a boot into Windows. 9150 */ 9151 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9152 { 9153 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9154 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9155 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9156 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9157 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9158 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9159 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9160 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9161 } 9162 9163 /* 9164 * Extra commands that don't really fit anywhere else. 9165 */ 9166 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9167 { 9168 struct ca0132_spec *spec = codec->spec; 9169 9170 writel(0x00820680, spec->mem_base + 0x01C); 9171 writel(0x00820680, spec->mem_base + 0x01C); 9172 9173 chipio_write(codec, 0x18b0a4, 0x000000c2); 9174 9175 snd_hda_codec_write(codec, 0x11, 0, 9176 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9177 } 9178 9179 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9180 { 9181 chipio_write(codec, 0x18b0a4, 0x000000c2); 9182 9183 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9184 9185 snd_hda_codec_write(codec, 0x11, 0, 9186 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9187 } 9188 9189 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9190 { 9191 chipio_write(codec, 0x18b0a4, 0x000000c2); 9192 9193 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9194 chipio_8051_write_exram(codec, 0x1920, 0x00); 9195 chipio_8051_write_exram(codec, 0x1921, 0x40); 9196 9197 snd_hda_codec_write(codec, 0x11, 0, 9198 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9199 } 9200 9201 /* 9202 * The ZxR seems to use alternative DAC's for the surround channels, which 9203 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9204 * this up, we get no audio out of the surround jacks. 9205 */ 9206 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9207 { 9208 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9209 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9210 unsigned int i; 9211 9212 chipio_write(codec, 0x189000, 0x0001f100); 9213 msleep(50); 9214 chipio_write(codec, 0x18900c, 0x0001f100); 9215 msleep(50); 9216 9217 /* 9218 * This writes a RET instruction at the entry point of the function at 9219 * 0xfa92 in exram. This function seems to have something to do with 9220 * ASI. Might be some way to prevent the card from reconfiguring the 9221 * ASI stuff itself. 9222 */ 9223 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9224 9225 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9226 9227 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9228 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9229 9230 chipio_write(codec, 0x18902c, 0x00000000); 9231 msleep(50); 9232 chipio_write(codec, 0x18902c, 0x00000003); 9233 msleep(50); 9234 9235 for (i = 0; i < ARRAY_SIZE(addr); i++) 9236 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9237 } 9238 9239 /* 9240 * These are sent before the DSP is downloaded. Not sure 9241 * what they do, or if they're necessary. Could possibly 9242 * be removed. Figure they're better to leave in. 9243 */ 9244 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9245 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9246 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9247 }; 9248 9249 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9250 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9251 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9252 0x000000c1, 0x00000080 9253 }; 9254 9255 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9256 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9257 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9258 0x000000c1, 0x00000080 9259 }; 9260 9261 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9262 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9263 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9264 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9265 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9266 }; 9267 9268 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9269 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9270 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9271 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9272 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9273 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9274 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9275 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9276 0x00000080, 0x00880680 9277 }; 9278 9279 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9280 { 9281 struct ca0132_spec *spec = codec->spec; 9282 unsigned int tmp[2], i, count, cur_addr; 9283 const unsigned int *addr, *data; 9284 9285 addr = ca0113_mmio_init_address_sbz; 9286 for (i = 0; i < 3; i++) 9287 writel(0x00000000, spec->mem_base + addr[i]); 9288 9289 cur_addr = i; 9290 switch (ca0132_quirk(spec)) { 9291 case QUIRK_ZXR: 9292 tmp[0] = 0x00880480; 9293 tmp[1] = 0x00000080; 9294 break; 9295 case QUIRK_SBZ: 9296 tmp[0] = 0x00820680; 9297 tmp[1] = 0x00000083; 9298 break; 9299 case QUIRK_R3D: 9300 tmp[0] = 0x00880680; 9301 tmp[1] = 0x00000083; 9302 break; 9303 default: 9304 tmp[0] = 0x00000000; 9305 tmp[1] = 0x00000000; 9306 break; 9307 } 9308 9309 for (i = 0; i < 2; i++) 9310 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9311 9312 cur_addr += i; 9313 9314 switch (ca0132_quirk(spec)) { 9315 case QUIRK_ZXR: 9316 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9317 data = ca0113_mmio_init_data_zxr; 9318 break; 9319 default: 9320 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9321 data = ca0113_mmio_init_data_sbz; 9322 break; 9323 } 9324 9325 for (i = 0; i < count; i++) 9326 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9327 } 9328 9329 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9330 { 9331 struct ca0132_spec *spec = codec->spec; 9332 const unsigned int *addr, *data; 9333 unsigned int i, count; 9334 9335 addr = ca0113_mmio_init_address_ae5; 9336 data = ca0113_mmio_init_data_ae5; 9337 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9338 9339 if (ca0132_quirk(spec) == QUIRK_AE7) { 9340 writel(0x00000680, spec->mem_base + 0x1c); 9341 writel(0x00880680, spec->mem_base + 0x1c); 9342 } 9343 9344 for (i = 0; i < count; i++) { 9345 /* 9346 * AE-7 shares all writes with the AE-5, except that it writes 9347 * a different value to 0x20c. 9348 */ 9349 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9350 writel(0x00800001, spec->mem_base + addr[i]); 9351 continue; 9352 } 9353 9354 writel(data[i], spec->mem_base + addr[i]); 9355 } 9356 9357 if (ca0132_quirk(spec) == QUIRK_AE5) 9358 writel(0x00880680, spec->mem_base + 0x1c); 9359 } 9360 9361 static void ca0132_mmio_init(struct hda_codec *codec) 9362 { 9363 struct ca0132_spec *spec = codec->spec; 9364 9365 switch (ca0132_quirk(spec)) { 9366 case QUIRK_R3D: 9367 case QUIRK_SBZ: 9368 case QUIRK_ZXR: 9369 ca0132_mmio_init_sbz(codec); 9370 break; 9371 case QUIRK_AE5: 9372 ca0132_mmio_init_ae5(codec); 9373 break; 9374 default: 9375 break; 9376 } 9377 } 9378 9379 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9380 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9381 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9382 }; 9383 9384 static const unsigned char ca0132_ae5_register_set_data[] = { 9385 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9386 0x01, 0x6b, 0x57 9387 }; 9388 9389 /* 9390 * This function writes to some SFR's, does some region2 writes, and then 9391 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9392 * what it does. 9393 */ 9394 static void ae5_register_set(struct hda_codec *codec) 9395 { 9396 struct ca0132_spec *spec = codec->spec; 9397 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9398 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9399 const unsigned char *data = ca0132_ae5_register_set_data; 9400 unsigned int i, cur_addr; 9401 unsigned char tmp[3]; 9402 9403 if (ca0132_quirk(spec) == QUIRK_AE7) 9404 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9405 9406 chipio_8051_write_direct(codec, 0x93, 0x10); 9407 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9408 9409 if (ca0132_quirk(spec) == QUIRK_AE7) { 9410 tmp[0] = 0x03; 9411 tmp[1] = 0x03; 9412 tmp[2] = 0x07; 9413 } else { 9414 tmp[0] = 0x0f; 9415 tmp[1] = 0x0f; 9416 tmp[2] = 0x0f; 9417 } 9418 9419 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9420 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9421 9422 /* 9423 * First writes are in single bytes, final are in 4 bytes. So, we use 9424 * writeb, then writel. 9425 */ 9426 for (i = 0; cur_addr < 12; i++, cur_addr++) 9427 writeb(data[i], spec->mem_base + addr[cur_addr]); 9428 9429 for (; cur_addr < count; i++, cur_addr++) 9430 writel(data[i], spec->mem_base + addr[cur_addr]); 9431 9432 writel(0x00800001, spec->mem_base + 0x20c); 9433 9434 if (ca0132_quirk(spec) == QUIRK_AE7) { 9435 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9436 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9437 } else { 9438 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9439 } 9440 9441 chipio_8051_write_direct(codec, 0x90, 0x00); 9442 chipio_8051_write_direct(codec, 0x90, 0x10); 9443 9444 if (ca0132_quirk(spec) == QUIRK_AE5) 9445 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9446 } 9447 9448 /* 9449 * Extra init functions for alternative ca0132 codecs. Done 9450 * here so they don't clutter up the main ca0132_init function 9451 * anymore than they have to. 9452 */ 9453 static void ca0132_alt_init(struct hda_codec *codec) 9454 { 9455 struct ca0132_spec *spec = codec->spec; 9456 9457 ca0132_alt_vol_setup(codec); 9458 9459 switch (ca0132_quirk(spec)) { 9460 case QUIRK_SBZ: 9461 codec_dbg(codec, "SBZ alt_init"); 9462 ca0132_gpio_init(codec); 9463 sbz_pre_dsp_setup(codec); 9464 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9465 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9466 break; 9467 case QUIRK_R3DI: 9468 codec_dbg(codec, "R3DI alt_init"); 9469 ca0132_gpio_init(codec); 9470 ca0132_gpio_setup(codec); 9471 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9472 r3di_pre_dsp_setup(codec); 9473 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9474 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9475 break; 9476 case QUIRK_R3D: 9477 r3d_pre_dsp_setup(codec); 9478 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9479 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9480 break; 9481 case QUIRK_AE5: 9482 ca0132_gpio_init(codec); 9483 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9484 chipio_write(codec, 0x18b030, 0x00000020); 9485 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9486 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9487 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9488 break; 9489 case QUIRK_AE7: 9490 ca0132_gpio_init(codec); 9491 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9492 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9493 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9494 chipio_write(codec, 0x18b008, 0x000000f8); 9495 chipio_write(codec, 0x18b008, 0x000000f0); 9496 chipio_write(codec, 0x18b030, 0x00000020); 9497 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9498 break; 9499 case QUIRK_ZXR: 9500 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9501 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9502 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9503 zxr_pre_dsp_setup(codec); 9504 break; 9505 default: 9506 break; 9507 } 9508 } 9509 9510 static int ca0132_init(struct hda_codec *codec) 9511 { 9512 struct ca0132_spec *spec = codec->spec; 9513 struct auto_pin_cfg *cfg = &spec->autocfg; 9514 int i; 9515 bool dsp_loaded; 9516 9517 /* 9518 * If the DSP is already downloaded, and init has been entered again, 9519 * there's only two reasons for it. One, the codec has awaken from a 9520 * suspended state, and in that case dspload_is_loaded will return 9521 * false, and the init will be ran again. The other reason it gets 9522 * re entered is on startup for some reason it triggers a suspend and 9523 * resume state. In this case, it will check if the DSP is downloaded, 9524 * and not run the init function again. For codecs using alt_functions, 9525 * it will check if the DSP is loaded properly. 9526 */ 9527 if (spec->dsp_state == DSP_DOWNLOADED) { 9528 dsp_loaded = dspload_is_loaded(codec); 9529 if (!dsp_loaded) { 9530 spec->dsp_reload = true; 9531 spec->dsp_state = DSP_DOWNLOAD_INIT; 9532 } else { 9533 if (ca0132_quirk(spec) == QUIRK_SBZ) 9534 sbz_dsp_startup_check(codec); 9535 return 0; 9536 } 9537 } 9538 9539 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9540 spec->dsp_state = DSP_DOWNLOAD_INIT; 9541 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9542 9543 if (ca0132_use_pci_mmio(spec)) 9544 ca0132_mmio_init(codec); 9545 9546 snd_hda_power_up_pm(codec); 9547 9548 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9549 ae5_register_set(codec); 9550 9551 ca0132_init_params(codec); 9552 ca0132_init_flags(codec); 9553 9554 snd_hda_sequence_write(codec, spec->base_init_verbs); 9555 9556 if (ca0132_use_alt_functions(spec)) 9557 ca0132_alt_init(codec); 9558 9559 ca0132_download_dsp(codec); 9560 9561 ca0132_refresh_widget_caps(codec); 9562 9563 switch (ca0132_quirk(spec)) { 9564 case QUIRK_R3DI: 9565 case QUIRK_R3D: 9566 r3d_setup_defaults(codec); 9567 break; 9568 case QUIRK_SBZ: 9569 case QUIRK_ZXR: 9570 sbz_setup_defaults(codec); 9571 break; 9572 case QUIRK_AE5: 9573 ae5_setup_defaults(codec); 9574 break; 9575 case QUIRK_AE7: 9576 ae7_setup_defaults(codec); 9577 break; 9578 default: 9579 ca0132_setup_defaults(codec); 9580 ca0132_init_analog_mic2(codec); 9581 ca0132_init_dmic(codec); 9582 break; 9583 } 9584 9585 for (i = 0; i < spec->num_outputs; i++) 9586 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9587 9588 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9589 9590 for (i = 0; i < spec->num_inputs; i++) 9591 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9592 9593 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9594 9595 if (!ca0132_use_alt_functions(spec)) { 9596 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9597 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9598 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9599 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9600 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9601 } 9602 9603 if (ca0132_quirk(spec) == QUIRK_SBZ) 9604 ca0132_gpio_setup(codec); 9605 9606 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9607 if (ca0132_use_alt_functions(spec)) { 9608 ca0132_alt_select_out(codec); 9609 ca0132_alt_select_in(codec); 9610 } else { 9611 ca0132_select_out(codec); 9612 ca0132_select_mic(codec); 9613 } 9614 9615 snd_hda_jack_report_sync(codec); 9616 9617 /* 9618 * Re set the PlayEnhancement switch on a resume event, because the 9619 * controls will not be reloaded. 9620 */ 9621 if (spec->dsp_reload) { 9622 spec->dsp_reload = false; 9623 ca0132_pe_switch_set(codec); 9624 } 9625 9626 snd_hda_power_down_pm(codec); 9627 9628 return 0; 9629 } 9630 9631 static int dbpro_init(struct hda_codec *codec) 9632 { 9633 struct ca0132_spec *spec = codec->spec; 9634 struct auto_pin_cfg *cfg = &spec->autocfg; 9635 unsigned int i; 9636 9637 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9638 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9639 9640 for (i = 0; i < spec->num_inputs; i++) 9641 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9642 9643 return 0; 9644 } 9645 9646 static void ca0132_free(struct hda_codec *codec) 9647 { 9648 struct ca0132_spec *spec = codec->spec; 9649 9650 cancel_delayed_work_sync(&spec->unsol_hp_work); 9651 snd_hda_power_up(codec); 9652 switch (ca0132_quirk(spec)) { 9653 case QUIRK_SBZ: 9654 sbz_exit_chip(codec); 9655 break; 9656 case QUIRK_ZXR: 9657 zxr_exit_chip(codec); 9658 break; 9659 case QUIRK_R3D: 9660 r3d_exit_chip(codec); 9661 break; 9662 case QUIRK_AE5: 9663 ae5_exit_chip(codec); 9664 break; 9665 case QUIRK_AE7: 9666 ae7_exit_chip(codec); 9667 break; 9668 case QUIRK_R3DI: 9669 r3di_gpio_shutdown(codec); 9670 break; 9671 default: 9672 break; 9673 } 9674 9675 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9676 ca0132_exit_chip(codec); 9677 9678 snd_hda_power_down(codec); 9679 #ifdef CONFIG_PCI 9680 if (spec->mem_base) 9681 pci_iounmap(codec->bus->pci, spec->mem_base); 9682 #endif 9683 kfree(spec->spec_init_verbs); 9684 kfree(codec->spec); 9685 } 9686 9687 static void dbpro_free(struct hda_codec *codec) 9688 { 9689 struct ca0132_spec *spec = codec->spec; 9690 9691 zxr_dbpro_power_state_shutdown(codec); 9692 9693 kfree(spec->spec_init_verbs); 9694 kfree(codec->spec); 9695 } 9696 9697 static int ca0132_suspend(struct hda_codec *codec) 9698 { 9699 struct ca0132_spec *spec = codec->spec; 9700 9701 cancel_delayed_work_sync(&spec->unsol_hp_work); 9702 return 0; 9703 } 9704 9705 static const struct hda_codec_ops ca0132_patch_ops = { 9706 .build_controls = ca0132_build_controls, 9707 .build_pcms = ca0132_build_pcms, 9708 .init = ca0132_init, 9709 .free = ca0132_free, 9710 .unsol_event = snd_hda_jack_unsol_event, 9711 .suspend = ca0132_suspend, 9712 }; 9713 9714 static const struct hda_codec_ops dbpro_patch_ops = { 9715 .build_controls = dbpro_build_controls, 9716 .build_pcms = dbpro_build_pcms, 9717 .init = dbpro_init, 9718 .free = dbpro_free, 9719 }; 9720 9721 static void ca0132_config(struct hda_codec *codec) 9722 { 9723 struct ca0132_spec *spec = codec->spec; 9724 9725 spec->dacs[0] = 0x2; 9726 spec->dacs[1] = 0x3; 9727 spec->dacs[2] = 0x4; 9728 9729 spec->multiout.dac_nids = spec->dacs; 9730 spec->multiout.num_dacs = 3; 9731 9732 if (!ca0132_use_alt_functions(spec)) 9733 spec->multiout.max_channels = 2; 9734 else 9735 spec->multiout.max_channels = 6; 9736 9737 switch (ca0132_quirk(spec)) { 9738 case QUIRK_ALIENWARE: 9739 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9740 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9741 break; 9742 case QUIRK_SBZ: 9743 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9744 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9745 break; 9746 case QUIRK_ZXR: 9747 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9748 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9749 break; 9750 case QUIRK_R3D: 9751 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9752 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9753 break; 9754 case QUIRK_R3DI: 9755 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9756 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9757 break; 9758 case QUIRK_AE5: 9759 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9760 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9761 break; 9762 case QUIRK_AE7: 9763 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9764 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9765 break; 9766 default: 9767 break; 9768 } 9769 9770 switch (ca0132_quirk(spec)) { 9771 case QUIRK_ALIENWARE: 9772 spec->num_outputs = 2; 9773 spec->out_pins[0] = 0x0b; /* speaker out */ 9774 spec->out_pins[1] = 0x0f; 9775 spec->shared_out_nid = 0x2; 9776 spec->unsol_tag_hp = 0x0f; 9777 9778 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9779 spec->adcs[1] = 0x8; /* analog mic2 */ 9780 spec->adcs[2] = 0xa; /* what u hear */ 9781 9782 spec->num_inputs = 3; 9783 spec->input_pins[0] = 0x12; 9784 spec->input_pins[1] = 0x11; 9785 spec->input_pins[2] = 0x13; 9786 spec->shared_mic_nid = 0x7; 9787 spec->unsol_tag_amic1 = 0x11; 9788 break; 9789 case QUIRK_SBZ: 9790 case QUIRK_R3D: 9791 spec->num_outputs = 2; 9792 spec->out_pins[0] = 0x0B; /* Line out */ 9793 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9794 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9795 spec->out_pins[3] = 0x11; /* Rear surround */ 9796 spec->shared_out_nid = 0x2; 9797 spec->unsol_tag_hp = spec->out_pins[1]; 9798 spec->unsol_tag_front_hp = spec->out_pins[2]; 9799 9800 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9801 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9802 spec->adcs[2] = 0xa; /* what u hear */ 9803 9804 spec->num_inputs = 2; 9805 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9806 spec->input_pins[1] = 0x13; /* What U Hear */ 9807 spec->shared_mic_nid = 0x7; 9808 spec->unsol_tag_amic1 = spec->input_pins[0]; 9809 9810 /* SPDIF I/O */ 9811 spec->dig_out = 0x05; 9812 spec->multiout.dig_out_nid = spec->dig_out; 9813 spec->dig_in = 0x09; 9814 break; 9815 case QUIRK_ZXR: 9816 spec->num_outputs = 2; 9817 spec->out_pins[0] = 0x0B; /* Line out */ 9818 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9819 spec->out_pins[2] = 0x10; /* Center/LFE */ 9820 spec->out_pins[3] = 0x11; /* Rear surround */ 9821 spec->shared_out_nid = 0x2; 9822 spec->unsol_tag_hp = spec->out_pins[1]; 9823 spec->unsol_tag_front_hp = spec->out_pins[2]; 9824 9825 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9826 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9827 spec->adcs[2] = 0xa; /* what u hear */ 9828 9829 spec->num_inputs = 2; 9830 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9831 spec->input_pins[1] = 0x13; /* What U Hear */ 9832 spec->shared_mic_nid = 0x7; 9833 spec->unsol_tag_amic1 = spec->input_pins[0]; 9834 break; 9835 case QUIRK_ZXR_DBPRO: 9836 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9837 9838 spec->num_inputs = 1; 9839 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9840 9841 spec->dig_out = 0x05; 9842 spec->multiout.dig_out_nid = spec->dig_out; 9843 9844 spec->dig_in = 0x09; 9845 break; 9846 case QUIRK_AE5: 9847 case QUIRK_AE7: 9848 spec->num_outputs = 2; 9849 spec->out_pins[0] = 0x0B; /* Line out */ 9850 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9851 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9852 spec->out_pins[3] = 0x0F; /* Rear surround */ 9853 spec->shared_out_nid = 0x2; 9854 spec->unsol_tag_hp = spec->out_pins[1]; 9855 spec->unsol_tag_front_hp = spec->out_pins[2]; 9856 9857 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9858 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9859 spec->adcs[2] = 0xa; /* what u hear */ 9860 9861 spec->num_inputs = 2; 9862 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9863 spec->input_pins[1] = 0x13; /* What U Hear */ 9864 spec->shared_mic_nid = 0x7; 9865 spec->unsol_tag_amic1 = spec->input_pins[0]; 9866 9867 /* SPDIF I/O */ 9868 spec->dig_out = 0x05; 9869 spec->multiout.dig_out_nid = spec->dig_out; 9870 break; 9871 case QUIRK_R3DI: 9872 spec->num_outputs = 2; 9873 spec->out_pins[0] = 0x0B; /* Line out */ 9874 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9875 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9876 spec->out_pins[3] = 0x11; /* Rear surround */ 9877 spec->shared_out_nid = 0x2; 9878 spec->unsol_tag_hp = spec->out_pins[1]; 9879 spec->unsol_tag_front_hp = spec->out_pins[2]; 9880 9881 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9882 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9883 spec->adcs[2] = 0x0a; /* what u hear */ 9884 9885 spec->num_inputs = 2; 9886 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9887 spec->input_pins[1] = 0x13; /* What U Hear */ 9888 spec->shared_mic_nid = 0x7; 9889 spec->unsol_tag_amic1 = spec->input_pins[0]; 9890 9891 /* SPDIF I/O */ 9892 spec->dig_out = 0x05; 9893 spec->multiout.dig_out_nid = spec->dig_out; 9894 break; 9895 default: 9896 spec->num_outputs = 2; 9897 spec->out_pins[0] = 0x0b; /* speaker out */ 9898 spec->out_pins[1] = 0x10; /* headphone out */ 9899 spec->shared_out_nid = 0x2; 9900 spec->unsol_tag_hp = spec->out_pins[1]; 9901 9902 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9903 spec->adcs[1] = 0x8; /* analog mic2 */ 9904 spec->adcs[2] = 0xa; /* what u hear */ 9905 9906 spec->num_inputs = 3; 9907 spec->input_pins[0] = 0x12; 9908 spec->input_pins[1] = 0x11; 9909 spec->input_pins[2] = 0x13; 9910 spec->shared_mic_nid = 0x7; 9911 spec->unsol_tag_amic1 = spec->input_pins[0]; 9912 9913 /* SPDIF I/O */ 9914 spec->dig_out = 0x05; 9915 spec->multiout.dig_out_nid = spec->dig_out; 9916 spec->dig_in = 0x09; 9917 break; 9918 } 9919 } 9920 9921 static int ca0132_prepare_verbs(struct hda_codec *codec) 9922 { 9923 /* Verbs + terminator (an empty element) */ 9924 #define NUM_SPEC_VERBS 2 9925 struct ca0132_spec *spec = codec->spec; 9926 9927 spec->chip_init_verbs = ca0132_init_verbs0; 9928 /* 9929 * Since desktop cards use pci_mmio, this can be used to determine 9930 * whether or not to use these verbs instead of a separate bool. 9931 */ 9932 if (ca0132_use_pci_mmio(spec)) 9933 spec->desktop_init_verbs = ca0132_init_verbs1; 9934 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 9935 sizeof(struct hda_verb), 9936 GFP_KERNEL); 9937 if (!spec->spec_init_verbs) 9938 return -ENOMEM; 9939 9940 /* config EAPD */ 9941 spec->spec_init_verbs[0].nid = 0x0b; 9942 spec->spec_init_verbs[0].param = 0x78D; 9943 spec->spec_init_verbs[0].verb = 0x00; 9944 9945 /* Previously commented configuration */ 9946 /* 9947 spec->spec_init_verbs[2].nid = 0x0b; 9948 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9949 spec->spec_init_verbs[2].verb = 0x02; 9950 9951 spec->spec_init_verbs[3].nid = 0x10; 9952 spec->spec_init_verbs[3].param = 0x78D; 9953 spec->spec_init_verbs[3].verb = 0x02; 9954 9955 spec->spec_init_verbs[4].nid = 0x10; 9956 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9957 spec->spec_init_verbs[4].verb = 0x02; 9958 */ 9959 9960 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9961 return 0; 9962 } 9963 9964 /* 9965 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9966 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9967 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9968 * daughter boards ID. 9969 */ 9970 static void sbz_detect_quirk(struct hda_codec *codec) 9971 { 9972 switch (codec->core.subsystem_id) { 9973 case 0x11020033: 9974 codec->fixup_id = QUIRK_ZXR; 9975 break; 9976 case 0x1102003f: 9977 codec->fixup_id = QUIRK_ZXR_DBPRO; 9978 break; 9979 default: 9980 codec->fixup_id = QUIRK_SBZ; 9981 break; 9982 } 9983 } 9984 9985 static int patch_ca0132(struct hda_codec *codec) 9986 { 9987 struct ca0132_spec *spec; 9988 int err; 9989 9990 codec_dbg(codec, "patch_ca0132\n"); 9991 9992 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 9993 if (!spec) 9994 return -ENOMEM; 9995 codec->spec = spec; 9996 spec->codec = codec; 9997 9998 /* Detect codec quirk */ 9999 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL); 10000 if (ca0132_quirk(spec) == QUIRK_SBZ) 10001 sbz_detect_quirk(codec); 10002 10003 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10004 codec->patch_ops = dbpro_patch_ops; 10005 else 10006 codec->patch_ops = ca0132_patch_ops; 10007 10008 codec->pcm_format_first = 1; 10009 codec->no_sticky_stream = 1; 10010 10011 10012 spec->dsp_state = DSP_DOWNLOAD_INIT; 10013 spec->num_mixers = 1; 10014 10015 /* Set which mixers each quirk uses. */ 10016 switch (ca0132_quirk(spec)) { 10017 case QUIRK_SBZ: 10018 spec->mixers[0] = desktop_mixer; 10019 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 10020 break; 10021 case QUIRK_ZXR: 10022 spec->mixers[0] = desktop_mixer; 10023 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 10024 break; 10025 case QUIRK_ZXR_DBPRO: 10026 break; 10027 case QUIRK_R3D: 10028 spec->mixers[0] = desktop_mixer; 10029 snd_hda_codec_set_name(codec, "Recon3D"); 10030 break; 10031 case QUIRK_R3DI: 10032 spec->mixers[0] = r3di_mixer; 10033 snd_hda_codec_set_name(codec, "Recon3Di"); 10034 break; 10035 case QUIRK_AE5: 10036 spec->mixers[0] = desktop_mixer; 10037 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 10038 break; 10039 case QUIRK_AE7: 10040 spec->mixers[0] = desktop_mixer; 10041 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 10042 break; 10043 default: 10044 spec->mixers[0] = ca0132_mixer; 10045 break; 10046 } 10047 10048 /* Setup whether or not to use alt functions/controls/pci_mmio */ 10049 switch (ca0132_quirk(spec)) { 10050 case QUIRK_SBZ: 10051 case QUIRK_R3D: 10052 case QUIRK_AE5: 10053 case QUIRK_AE7: 10054 case QUIRK_ZXR: 10055 spec->use_alt_controls = true; 10056 spec->use_alt_functions = true; 10057 spec->use_pci_mmio = true; 10058 break; 10059 case QUIRK_R3DI: 10060 spec->use_alt_controls = true; 10061 spec->use_alt_functions = true; 10062 spec->use_pci_mmio = false; 10063 break; 10064 default: 10065 spec->use_alt_controls = false; 10066 spec->use_alt_functions = false; 10067 spec->use_pci_mmio = false; 10068 break; 10069 } 10070 10071 #ifdef CONFIG_PCI 10072 if (spec->use_pci_mmio) { 10073 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 10074 if (spec->mem_base == NULL) { 10075 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 10076 codec->fixup_id = QUIRK_NONE; 10077 } 10078 } 10079 #endif 10080 10081 spec->base_init_verbs = ca0132_base_init_verbs; 10082 spec->base_exit_verbs = ca0132_base_exit_verbs; 10083 10084 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10085 10086 ca0132_init_chip(codec); 10087 10088 ca0132_config(codec); 10089 10090 err = ca0132_prepare_verbs(codec); 10091 if (err < 0) 10092 goto error; 10093 10094 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10095 if (err < 0) 10096 goto error; 10097 10098 ca0132_setup_unsol(codec); 10099 10100 return 0; 10101 10102 error: 10103 ca0132_free(codec); 10104 return err; 10105 } 10106 10107 /* 10108 * patch entries 10109 */ 10110 static const struct hda_device_id snd_hda_id_ca0132[] = { 10111 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 10112 {} /* terminator */ 10113 }; 10114 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10115 10116 MODULE_LICENSE("GPL"); 10117 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10118 10119 static struct hda_codec_driver ca0132_driver = { 10120 .id = snd_hda_id_ca0132, 10121 }; 10122 10123 module_hda_codec_driver(ca0132_driver); 10124