1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 MaxLinear, Inc.
4 *
5 * This driver is a hardware monitoring driver for PVT controller
6 * (MR75203) which is used to configure & control Moortec embedded
7 * analog IP to enable multiple embedded temperature sensor(TS),
8 * voltage monitor(VM) & process detector(PD) modules.
9 */
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/hwmon.h>
14 #include <linux/kstrtox.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21 #include <linux/units.h>
22
23 /* PVT Common register */
24 #define PVT_IP_CONFIG 0x04
25 #define TS_NUM_MSK GENMASK(4, 0)
26 #define TS_NUM_SFT 0
27 #define PD_NUM_MSK GENMASK(12, 8)
28 #define PD_NUM_SFT 8
29 #define VM_NUM_MSK GENMASK(20, 16)
30 #define VM_NUM_SFT 16
31 #define CH_NUM_MSK GENMASK(31, 24)
32 #define CH_NUM_SFT 24
33
34 #define VM_NUM_MAX (VM_NUM_MSK >> VM_NUM_SFT)
35
36 /* Macro Common Register */
37 #define CLK_SYNTH 0x00
38 #define CLK_SYNTH_LO_SFT 0
39 #define CLK_SYNTH_HI_SFT 8
40 #define CLK_SYNTH_HOLD_SFT 16
41 #define CLK_SYNTH_EN BIT(24)
42 #define CLK_SYS_CYCLES_MAX 514
43 #define CLK_SYS_CYCLES_MIN 2
44
45 #define SDIF_DISABLE 0x04
46
47 #define SDIF_STAT 0x08
48 #define SDIF_BUSY BIT(0)
49 #define SDIF_LOCK BIT(1)
50
51 #define SDIF_W 0x0c
52 #define SDIF_PROG BIT(31)
53 #define SDIF_WRN_W BIT(27)
54 #define SDIF_WRN_R 0x00
55 #define SDIF_ADDR_SFT 24
56
57 #define SDIF_HALT 0x10
58 #define SDIF_CTRL 0x14
59 #define SDIF_SMPL_CTRL 0x20
60
61 /* TS & PD Individual Macro Register */
62 #define COM_REG_SIZE 0x40
63
64 #define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n))
65 #define SDIF_SMPL_DONE BIT(0)
66
67 #define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n))
68 #define SAMPLE_DATA_MSK GENMASK(15, 0)
69
70 #define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n))
71
72 /* VM Individual Macro Register */
73 #define VM_COM_REG_SIZE 0x200
74 #define VM_SDIF_DONE(vm) (VM_COM_REG_SIZE + 0x34 + 0x200 * (vm))
75 #define VM_SDIF_DATA(vm, ch) \
76 (VM_COM_REG_SIZE + 0x40 + 0x200 * (vm) + 0x4 * (ch))
77
78 /* SDA Slave Register */
79 #define IP_CTRL 0x00
80 #define IP_RST_REL BIT(1)
81 #define IP_RUN_CONT BIT(3)
82 #define IP_AUTO BIT(8)
83 #define IP_VM_MODE BIT(10)
84
85 #define IP_CFG 0x01
86 #define CFG0_MODE_2 BIT(0)
87 #define CFG0_PARALLEL_OUT 0
88 #define CFG0_12_BIT 0
89 #define CFG1_VOL_MEAS_MODE 0
90 #define CFG1_PARALLEL_OUT 0
91 #define CFG1_14_BIT 0
92
93 #define IP_DATA 0x03
94
95 #define IP_POLL 0x04
96 #define VM_CH_INIT BIT(20)
97 #define VM_CH_REQ BIT(21)
98
99 #define IP_TMR 0x05
100 #define POWER_DELAY_CYCLE_256 0x100
101 #define POWER_DELAY_CYCLE_64 0x40
102
103 #define PVT_POLL_DELAY_US 20
104 #define PVT_POLL_TIMEOUT_US 20000
105 #define PVT_CONV_BITS 10
106 #define PVT_N_CONST 90
107 #define PVT_R_CONST 245805
108
109 #define PVT_TEMP_MIN_mC -40000
110 #define PVT_TEMP_MAX_mC 125000
111
112 /* Temperature coefficients for series 5 */
113 #define PVT_SERIES5_H_CONST 200000
114 #define PVT_SERIES5_G_CONST 60000
115 #define PVT_SERIES5_J_CONST -100
116 #define PVT_SERIES5_CAL5_CONST 4094
117
118 /* Temperature coefficients for series 6 */
119 #define PVT_SERIES6_H_CONST 249400
120 #define PVT_SERIES6_G_CONST 57400
121 #define PVT_SERIES6_J_CONST 0
122 #define PVT_SERIES6_CAL5_CONST 4096
123
124 #define TEMPERATURE_SENSOR_SERIES_5 5
125 #define TEMPERATURE_SENSOR_SERIES_6 6
126
127 #define PRE_SCALER_X1 1
128 #define PRE_SCALER_X2 2
129
130 /**
131 * struct voltage_device - VM single input parameters.
132 * @vm_map: Map channel number to VM index.
133 * @ch_map: Map channel number to channel index.
134 * @pre_scaler: Pre scaler value (1 or 2) used to normalize the voltage output
135 * result.
136 *
137 * The structure provides mapping between channel-number (0..N-1) to VM-index
138 * (0..num_vm-1) and channel-index (0..ch_num-1) where N = num_vm * ch_num.
139 * It also provides normalization factor for the VM equation.
140 */
141 struct voltage_device {
142 u32 vm_map;
143 u32 ch_map;
144 u32 pre_scaler;
145 };
146
147 /**
148 * struct voltage_channels - VM channel count.
149 * @total: Total number of channels in all VMs.
150 * @max: Maximum number of channels among all VMs.
151 *
152 * The structure provides channel count information across all VMs.
153 */
154 struct voltage_channels {
155 u32 total;
156 u8 max;
157 };
158
159 struct temp_coeff {
160 u32 h;
161 u32 g;
162 u32 cal5;
163 s32 j;
164 };
165
166 struct pvt_device {
167 struct regmap *c_map;
168 struct regmap *t_map;
169 struct regmap *p_map;
170 struct regmap *v_map;
171 struct clk *clk;
172 struct reset_control *rst;
173 struct dentry *dbgfs_dir;
174 struct voltage_device *vd;
175 struct voltage_channels vm_channels;
176 struct temp_coeff ts_coeff;
177 u32 t_num;
178 u32 p_num;
179 u32 v_num;
180 u32 ip_freq;
181 };
182
pvt_ts_coeff_j_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)183 static ssize_t pvt_ts_coeff_j_read(struct file *file, char __user *user_buf,
184 size_t count, loff_t *ppos)
185 {
186 struct pvt_device *pvt = file->private_data;
187 unsigned int len;
188 char buf[13];
189
190 len = scnprintf(buf, sizeof(buf), "%d\n", pvt->ts_coeff.j);
191
192 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
193 }
194
pvt_ts_coeff_j_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)195 static ssize_t pvt_ts_coeff_j_write(struct file *file,
196 const char __user *user_buf,
197 size_t count, loff_t *ppos)
198 {
199 struct pvt_device *pvt = file->private_data;
200 int ret;
201
202 ret = kstrtos32_from_user(user_buf, count, 0, &pvt->ts_coeff.j);
203 if (ret)
204 return ret;
205
206 return count;
207 }
208
209 static const struct file_operations pvt_ts_coeff_j_fops = {
210 .read = pvt_ts_coeff_j_read,
211 .write = pvt_ts_coeff_j_write,
212 .open = simple_open,
213 .owner = THIS_MODULE,
214 .llseek = default_llseek,
215 };
216
devm_pvt_ts_dbgfs_remove(void * data)217 static void devm_pvt_ts_dbgfs_remove(void *data)
218 {
219 struct pvt_device *pvt = (struct pvt_device *)data;
220
221 debugfs_remove_recursive(pvt->dbgfs_dir);
222 pvt->dbgfs_dir = NULL;
223 }
224
pvt_ts_dbgfs_create(struct pvt_device * pvt,struct device * dev)225 static int pvt_ts_dbgfs_create(struct pvt_device *pvt, struct device *dev)
226 {
227 pvt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
228
229 debugfs_create_u32("ts_coeff_h", 0644, pvt->dbgfs_dir,
230 &pvt->ts_coeff.h);
231 debugfs_create_u32("ts_coeff_g", 0644, pvt->dbgfs_dir,
232 &pvt->ts_coeff.g);
233 debugfs_create_u32("ts_coeff_cal5", 0644, pvt->dbgfs_dir,
234 &pvt->ts_coeff.cal5);
235 debugfs_create_file("ts_coeff_j", 0644, pvt->dbgfs_dir, pvt,
236 &pvt_ts_coeff_j_fops);
237
238 return devm_add_action_or_reset(dev, devm_pvt_ts_dbgfs_remove, pvt);
239 }
240
pvt_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)241 static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type,
242 u32 attr, int channel)
243 {
244 switch (type) {
245 case hwmon_temp:
246 if (attr == hwmon_temp_input)
247 return 0444;
248 break;
249 case hwmon_in:
250 if (attr == hwmon_in_input)
251 return 0444;
252 break;
253 default:
254 break;
255 }
256 return 0;
257 }
258
pvt_calc_temp(struct pvt_device * pvt,u32 nbs)259 static long pvt_calc_temp(struct pvt_device *pvt, u32 nbs)
260 {
261 /*
262 * Convert the register value to degrees centigrade temperature:
263 * T = G + H * (n / cal5 - 0.5) + J * F
264 */
265 struct temp_coeff *ts_coeff = &pvt->ts_coeff;
266
267 s64 tmp = ts_coeff->g +
268 div_s64(ts_coeff->h * (s64)nbs, ts_coeff->cal5) -
269 ts_coeff->h / 2 +
270 div_s64(ts_coeff->j * (s64)pvt->ip_freq, HZ_PER_MHZ);
271
272 return clamp_val(tmp, PVT_TEMP_MIN_mC, PVT_TEMP_MAX_mC);
273 }
274
pvt_read_temp(struct device * dev,u32 attr,int channel,long * val)275 static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val)
276 {
277 struct pvt_device *pvt = dev_get_drvdata(dev);
278 struct regmap *t_map = pvt->t_map;
279 u32 stat, nbs;
280 int ret;
281
282 switch (attr) {
283 case hwmon_temp_input:
284 ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel),
285 stat, stat & SDIF_SMPL_DONE,
286 PVT_POLL_DELAY_US,
287 PVT_POLL_TIMEOUT_US);
288 if (ret)
289 return ret;
290
291 ret = regmap_read(t_map, SDIF_DATA(channel), &nbs);
292 if (ret < 0)
293 return ret;
294
295 nbs &= SAMPLE_DATA_MSK;
296
297 /*
298 * Convert the register value to
299 * degrees centigrade temperature
300 */
301 *val = pvt_calc_temp(pvt, nbs);
302
303 return 0;
304 default:
305 return -EOPNOTSUPP;
306 }
307 }
308
pvt_read_in(struct device * dev,u32 attr,int channel,long * val)309 static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val)
310 {
311 struct pvt_device *pvt = dev_get_drvdata(dev);
312 struct regmap *v_map = pvt->v_map;
313 u32 n, stat, pre_scaler;
314 u8 vm_idx, ch_idx;
315 int ret;
316
317 if (channel >= pvt->vm_channels.total)
318 return -EINVAL;
319
320 vm_idx = pvt->vd[channel].vm_map;
321 ch_idx = pvt->vd[channel].ch_map;
322
323 switch (attr) {
324 case hwmon_in_input:
325 ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx),
326 stat, stat & SDIF_SMPL_DONE,
327 PVT_POLL_DELAY_US,
328 PVT_POLL_TIMEOUT_US);
329 if (ret)
330 return ret;
331
332 ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx, ch_idx), &n);
333 if (ret < 0)
334 return ret;
335
336 n &= SAMPLE_DATA_MSK;
337 pre_scaler = pvt->vd[channel].pre_scaler;
338 /*
339 * Convert the N bitstream count into voltage.
340 * To support negative voltage calculation for 64bit machines
341 * n must be cast to long, since n and *val differ both in
342 * signedness and in size.
343 * Division is used instead of right shift, because for signed
344 * numbers, the sign bit is used to fill the vacated bit
345 * positions, and if the number is negative, 1 is used.
346 * BIT(x) may not be used instead of (1 << x) because it's
347 * unsigned.
348 */
349 *val = pre_scaler * (PVT_N_CONST * (long)n - PVT_R_CONST) /
350 (1 << PVT_CONV_BITS);
351
352 return 0;
353 default:
354 return -EOPNOTSUPP;
355 }
356 }
357
pvt_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)358 static int pvt_read(struct device *dev, enum hwmon_sensor_types type,
359 u32 attr, int channel, long *val)
360 {
361 switch (type) {
362 case hwmon_temp:
363 return pvt_read_temp(dev, attr, channel, val);
364 case hwmon_in:
365 return pvt_read_in(dev, attr, channel, val);
366 default:
367 return -EOPNOTSUPP;
368 }
369 }
370
371 static struct hwmon_channel_info pvt_temp = {
372 .type = hwmon_temp,
373 };
374
375 static struct hwmon_channel_info pvt_in = {
376 .type = hwmon_in,
377 };
378
379 static const struct hwmon_ops pvt_hwmon_ops = {
380 .is_visible = pvt_is_visible,
381 .read = pvt_read,
382 };
383
384 static struct hwmon_chip_info pvt_chip_info = {
385 .ops = &pvt_hwmon_ops,
386 };
387
pvt_init(struct pvt_device * pvt)388 static int pvt_init(struct pvt_device *pvt)
389 {
390 u16 sys_freq, key, middle, low = 4, high = 8;
391 struct regmap *t_map = pvt->t_map;
392 struct regmap *p_map = pvt->p_map;
393 struct regmap *v_map = pvt->v_map;
394 u32 t_num = pvt->t_num;
395 u32 p_num = pvt->p_num;
396 u32 v_num = pvt->v_num;
397 u32 clk_synth, val;
398 int ret;
399
400 sys_freq = clk_get_rate(pvt->clk) / HZ_PER_MHZ;
401 while (high >= low) {
402 middle = (low + high + 1) / 2;
403 key = DIV_ROUND_CLOSEST(sys_freq, middle);
404 if (key > CLK_SYS_CYCLES_MAX) {
405 low = middle + 1;
406 continue;
407 } else if (key < CLK_SYS_CYCLES_MIN) {
408 high = middle - 1;
409 continue;
410 } else {
411 break;
412 }
413 }
414
415 /*
416 * The system supports 'clk_sys' to 'clk_ip' frequency ratios
417 * from 2:1 to 512:1
418 */
419 key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2;
420
421 clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT |
422 (key >> 1) << CLK_SYNTH_HI_SFT |
423 (key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN;
424
425 pvt->ip_freq = clk_get_rate(pvt->clk) / (key + 2);
426
427 if (t_num) {
428 ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0);
429 if (ret < 0)
430 return ret;
431
432 ret = regmap_write(t_map, SDIF_HALT, 0x0);
433 if (ret < 0)
434 return ret;
435
436 ret = regmap_write(t_map, CLK_SYNTH, clk_synth);
437 if (ret < 0)
438 return ret;
439
440 ret = regmap_write(t_map, SDIF_DISABLE, 0x0);
441 if (ret < 0)
442 return ret;
443
444 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
445 val, !(val & SDIF_BUSY),
446 PVT_POLL_DELAY_US,
447 PVT_POLL_TIMEOUT_US);
448 if (ret)
449 return ret;
450
451 val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT |
452 IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
453 ret = regmap_write(t_map, SDIF_W, val);
454 if (ret < 0)
455 return ret;
456
457 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
458 val, !(val & SDIF_BUSY),
459 PVT_POLL_DELAY_US,
460 PVT_POLL_TIMEOUT_US);
461 if (ret)
462 return ret;
463
464 val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT |
465 SDIF_WRN_W | SDIF_PROG;
466 ret = regmap_write(t_map, SDIF_W, val);
467 if (ret < 0)
468 return ret;
469
470 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
471 val, !(val & SDIF_BUSY),
472 PVT_POLL_DELAY_US,
473 PVT_POLL_TIMEOUT_US);
474 if (ret)
475 return ret;
476
477 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO |
478 IP_CTRL << SDIF_ADDR_SFT |
479 SDIF_WRN_W | SDIF_PROG;
480 ret = regmap_write(t_map, SDIF_W, val);
481 if (ret < 0)
482 return ret;
483 }
484
485 if (p_num) {
486 ret = regmap_write(p_map, SDIF_HALT, 0x0);
487 if (ret < 0)
488 return ret;
489
490 ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1);
491 if (ret < 0)
492 return ret;
493
494 ret = regmap_write(p_map, CLK_SYNTH, clk_synth);
495 if (ret < 0)
496 return ret;
497 }
498
499 if (v_num) {
500 ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0);
501 if (ret < 0)
502 return ret;
503
504 ret = regmap_write(v_map, SDIF_HALT, 0x0);
505 if (ret < 0)
506 return ret;
507
508 ret = regmap_write(v_map, CLK_SYNTH, clk_synth);
509 if (ret < 0)
510 return ret;
511
512 ret = regmap_write(v_map, SDIF_DISABLE, 0x0);
513 if (ret < 0)
514 return ret;
515
516 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
517 val, !(val & SDIF_BUSY),
518 PVT_POLL_DELAY_US,
519 PVT_POLL_TIMEOUT_US);
520 if (ret)
521 return ret;
522
523 val = (BIT(pvt->vm_channels.max) - 1) | VM_CH_INIT |
524 IP_POLL << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
525 ret = regmap_write(v_map, SDIF_W, val);
526 if (ret < 0)
527 return ret;
528
529 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
530 val, !(val & SDIF_BUSY),
531 PVT_POLL_DELAY_US,
532 PVT_POLL_TIMEOUT_US);
533 if (ret)
534 return ret;
535
536 val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT |
537 CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT |
538 SDIF_WRN_W | SDIF_PROG;
539 ret = regmap_write(v_map, SDIF_W, val);
540 if (ret < 0)
541 return ret;
542
543 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
544 val, !(val & SDIF_BUSY),
545 PVT_POLL_DELAY_US,
546 PVT_POLL_TIMEOUT_US);
547 if (ret)
548 return ret;
549
550 val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT |
551 SDIF_WRN_W | SDIF_PROG;
552 ret = regmap_write(v_map, SDIF_W, val);
553 if (ret < 0)
554 return ret;
555
556 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
557 val, !(val & SDIF_BUSY),
558 PVT_POLL_DELAY_US,
559 PVT_POLL_TIMEOUT_US);
560 if (ret)
561 return ret;
562
563 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE |
564 IP_CTRL << SDIF_ADDR_SFT |
565 SDIF_WRN_W | SDIF_PROG;
566 ret = regmap_write(v_map, SDIF_W, val);
567 if (ret < 0)
568 return ret;
569 }
570
571 return 0;
572 }
573
574 static struct regmap_config pvt_regmap_config = {
575 .reg_bits = 32,
576 .reg_stride = 4,
577 .val_bits = 32,
578 };
579
pvt_get_regmap(struct platform_device * pdev,char * reg_name,struct pvt_device * pvt)580 static int pvt_get_regmap(struct platform_device *pdev, char *reg_name,
581 struct pvt_device *pvt)
582 {
583 struct device *dev = &pdev->dev;
584 struct regmap **reg_map;
585 void __iomem *io_base;
586
587 if (!strcmp(reg_name, "common"))
588 reg_map = &pvt->c_map;
589 else if (!strcmp(reg_name, "ts"))
590 reg_map = &pvt->t_map;
591 else if (!strcmp(reg_name, "pd"))
592 reg_map = &pvt->p_map;
593 else if (!strcmp(reg_name, "vm"))
594 reg_map = &pvt->v_map;
595 else
596 return -EINVAL;
597
598 io_base = devm_platform_ioremap_resource_byname(pdev, reg_name);
599 if (IS_ERR(io_base))
600 return PTR_ERR(io_base);
601
602 pvt_regmap_config.name = reg_name;
603 *reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config);
604 if (IS_ERR(*reg_map)) {
605 dev_err(dev, "failed to init register map\n");
606 return PTR_ERR(*reg_map);
607 }
608
609 return 0;
610 }
611
pvt_reset_control_assert(void * data)612 static void pvt_reset_control_assert(void *data)
613 {
614 struct pvt_device *pvt = data;
615
616 reset_control_assert(pvt->rst);
617 }
618
pvt_reset_control_deassert(struct device * dev,struct pvt_device * pvt)619 static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt)
620 {
621 int ret;
622
623 ret = reset_control_deassert(pvt->rst);
624 if (ret)
625 return ret;
626
627 return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt);
628 }
629
pvt_get_active_channel(struct device * dev,struct pvt_device * pvt,u32 vm_num,u32 ch_num,u8 * vm_idx)630 static int pvt_get_active_channel(struct device *dev, struct pvt_device *pvt,
631 u32 vm_num, u32 ch_num, u8 *vm_idx)
632 {
633 u8 vm_active_ch[VM_NUM_MAX];
634 int ret, i, j, k;
635
636 ret = device_property_read_u8_array(dev, "moortec,vm-active-channels",
637 vm_active_ch, vm_num);
638 if (ret) {
639 /*
640 * Incase "moortec,vm-active-channels" property is not defined,
641 * we assume each VM sensor has all of its channels active.
642 */
643 memset(vm_active_ch, ch_num, vm_num);
644 pvt->vm_channels.max = ch_num;
645 pvt->vm_channels.total = ch_num * vm_num;
646 } else {
647 for (i = 0; i < vm_num; i++) {
648 if (vm_active_ch[i] > ch_num) {
649 dev_err(dev, "invalid active channels: %u\n",
650 vm_active_ch[i]);
651 return -EINVAL;
652 }
653
654 pvt->vm_channels.total += vm_active_ch[i];
655
656 if (vm_active_ch[i] > pvt->vm_channels.max)
657 pvt->vm_channels.max = vm_active_ch[i];
658 }
659 }
660
661 /*
662 * Map between the channel-number to VM-index and channel-index.
663 * Example - 3 VMs, "moortec,vm_active_ch" = <5 2 4>:
664 * vm_map = [0 0 0 0 0 1 1 2 2 2 2]
665 * ch_map = [0 1 2 3 4 0 1 0 1 2 3]
666 */
667 pvt->vd = devm_kcalloc(dev, pvt->vm_channels.total, sizeof(*pvt->vd),
668 GFP_KERNEL);
669 if (!pvt->vd)
670 return -ENOMEM;
671
672 k = 0;
673 for (i = 0; i < vm_num; i++) {
674 for (j = 0; j < vm_active_ch[i]; j++) {
675 pvt->vd[k].vm_map = vm_idx[i];
676 pvt->vd[k].ch_map = j;
677 k++;
678 }
679 }
680
681 return 0;
682 }
683
pvt_get_pre_scaler(struct device * dev,struct pvt_device * pvt)684 static int pvt_get_pre_scaler(struct device *dev, struct pvt_device *pvt)
685 {
686 u8 *pre_scaler_ch_list;
687 int i, ret, num_ch;
688 u32 channel;
689
690 /* Set default pre-scaler value to be 1. */
691 for (i = 0; i < pvt->vm_channels.total; i++)
692 pvt->vd[i].pre_scaler = PRE_SCALER_X1;
693
694 /* Get number of channels configured in "moortec,vm-pre-scaler-x2". */
695 num_ch = device_property_count_u8(dev, "moortec,vm-pre-scaler-x2");
696 if (num_ch <= 0)
697 return 0;
698
699 pre_scaler_ch_list = kcalloc(num_ch, sizeof(*pre_scaler_ch_list),
700 GFP_KERNEL);
701 if (!pre_scaler_ch_list)
702 return -ENOMEM;
703
704 /* Get list of all channels that have pre-scaler of 2. */
705 ret = device_property_read_u8_array(dev, "moortec,vm-pre-scaler-x2",
706 pre_scaler_ch_list, num_ch);
707 if (ret)
708 goto out;
709
710 for (i = 0; i < num_ch; i++) {
711 channel = pre_scaler_ch_list[i];
712 pvt->vd[channel].pre_scaler = PRE_SCALER_X2;
713 }
714
715 out:
716 kfree(pre_scaler_ch_list);
717
718 return ret;
719 }
720
pvt_set_temp_coeff(struct device * dev,struct pvt_device * pvt)721 static int pvt_set_temp_coeff(struct device *dev, struct pvt_device *pvt)
722 {
723 struct temp_coeff *ts_coeff = &pvt->ts_coeff;
724 u32 series;
725 int ret;
726
727 /* Incase ts-series property is not defined, use default 5. */
728 ret = device_property_read_u32(dev, "moortec,ts-series", &series);
729 if (ret)
730 series = TEMPERATURE_SENSOR_SERIES_5;
731
732 switch (series) {
733 case TEMPERATURE_SENSOR_SERIES_5:
734 ts_coeff->h = PVT_SERIES5_H_CONST;
735 ts_coeff->g = PVT_SERIES5_G_CONST;
736 ts_coeff->j = PVT_SERIES5_J_CONST;
737 ts_coeff->cal5 = PVT_SERIES5_CAL5_CONST;
738 break;
739 case TEMPERATURE_SENSOR_SERIES_6:
740 ts_coeff->h = PVT_SERIES6_H_CONST;
741 ts_coeff->g = PVT_SERIES6_G_CONST;
742 ts_coeff->j = PVT_SERIES6_J_CONST;
743 ts_coeff->cal5 = PVT_SERIES6_CAL5_CONST;
744 break;
745 default:
746 dev_err(dev, "invalid temperature sensor series (%u)\n",
747 series);
748 return -EINVAL;
749 }
750
751 dev_dbg(dev, "temperature sensor series = %u\n", series);
752
753 /* Override ts-coeff-h/g/j/cal5 if they are defined. */
754 device_property_read_u32(dev, "moortec,ts-coeff-h", &ts_coeff->h);
755 device_property_read_u32(dev, "moortec,ts-coeff-g", &ts_coeff->g);
756 device_property_read_u32(dev, "moortec,ts-coeff-j", &ts_coeff->j);
757 device_property_read_u32(dev, "moortec,ts-coeff-cal5", &ts_coeff->cal5);
758
759 dev_dbg(dev, "ts-coeff: h = %u, g = %u, j = %d, cal5 = %u\n",
760 ts_coeff->h, ts_coeff->g, ts_coeff->j, ts_coeff->cal5);
761
762 return 0;
763 }
764
mr75203_probe(struct platform_device * pdev)765 static int mr75203_probe(struct platform_device *pdev)
766 {
767 u32 ts_num, vm_num, pd_num, ch_num, val, index, i;
768 const struct hwmon_channel_info **pvt_info;
769 struct device *dev = &pdev->dev;
770 u32 *temp_config, *in_config;
771 struct device *hwmon_dev;
772 struct pvt_device *pvt;
773 int ret;
774
775 pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL);
776 if (!pvt)
777 return -ENOMEM;
778
779 ret = pvt_get_regmap(pdev, "common", pvt);
780 if (ret)
781 return ret;
782
783 pvt->clk = devm_clk_get_enabled(dev, NULL);
784 if (IS_ERR(pvt->clk))
785 return dev_err_probe(dev, PTR_ERR(pvt->clk), "failed to get clock\n");
786
787 pvt->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
788 if (IS_ERR(pvt->rst))
789 return dev_err_probe(dev, PTR_ERR(pvt->rst),
790 "failed to get reset control\n");
791
792 if (pvt->rst) {
793 ret = pvt_reset_control_deassert(dev, pvt);
794 if (ret)
795 return dev_err_probe(dev, ret,
796 "cannot deassert reset control\n");
797 }
798
799 ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val);
800 if (ret < 0)
801 return ret;
802
803 ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT;
804 pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT;
805 vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT;
806 ch_num = (val & CH_NUM_MSK) >> CH_NUM_SFT;
807 pvt->t_num = ts_num;
808 pvt->p_num = pd_num;
809 pvt->v_num = vm_num;
810 val = 0;
811 if (ts_num)
812 val++;
813 if (vm_num)
814 val++;
815 if (!val)
816 return -ENODEV;
817
818 pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL);
819 if (!pvt_info)
820 return -ENOMEM;
821 pvt_info[0] = HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ);
822 index = 1;
823
824 if (ts_num) {
825 ret = pvt_get_regmap(pdev, "ts", pvt);
826 if (ret)
827 return ret;
828
829 ret = pvt_set_temp_coeff(dev, pvt);
830 if (ret)
831 return ret;
832
833 temp_config = devm_kcalloc(dev, ts_num + 1,
834 sizeof(*temp_config), GFP_KERNEL);
835 if (!temp_config)
836 return -ENOMEM;
837
838 memset32(temp_config, HWMON_T_INPUT, ts_num);
839 pvt_temp.config = temp_config;
840 pvt_info[index++] = &pvt_temp;
841
842 pvt_ts_dbgfs_create(pvt, dev);
843 }
844
845 if (pd_num) {
846 ret = pvt_get_regmap(pdev, "pd", pvt);
847 if (ret)
848 return ret;
849 }
850
851 if (vm_num) {
852 u8 vm_idx[VM_NUM_MAX];
853
854 ret = pvt_get_regmap(pdev, "vm", pvt);
855 if (ret)
856 return ret;
857
858 ret = device_property_read_u8_array(dev, "intel,vm-map", vm_idx,
859 vm_num);
860 if (ret) {
861 /*
862 * Incase intel,vm-map property is not defined, we
863 * assume incremental channel numbers.
864 */
865 for (i = 0; i < vm_num; i++)
866 vm_idx[i] = i;
867 } else {
868 for (i = 0; i < vm_num; i++)
869 if (vm_idx[i] >= vm_num || vm_idx[i] == 0xff) {
870 pvt->v_num = i;
871 vm_num = i;
872 break;
873 }
874 }
875
876 ret = pvt_get_active_channel(dev, pvt, vm_num, ch_num, vm_idx);
877 if (ret)
878 return ret;
879
880 ret = pvt_get_pre_scaler(dev, pvt);
881 if (ret)
882 return ret;
883
884 in_config = devm_kcalloc(dev, pvt->vm_channels.total + 1,
885 sizeof(*in_config), GFP_KERNEL);
886 if (!in_config)
887 return -ENOMEM;
888
889 memset32(in_config, HWMON_I_INPUT, pvt->vm_channels.total);
890 in_config[pvt->vm_channels.total] = 0;
891 pvt_in.config = in_config;
892
893 pvt_info[index++] = &pvt_in;
894 }
895
896 ret = pvt_init(pvt);
897 if (ret) {
898 dev_err(dev, "failed to init pvt: %d\n", ret);
899 return ret;
900 }
901
902 pvt_chip_info.info = pvt_info;
903 hwmon_dev = devm_hwmon_device_register_with_info(dev, "pvt",
904 pvt,
905 &pvt_chip_info,
906 NULL);
907
908 return PTR_ERR_OR_ZERO(hwmon_dev);
909 }
910
911 static const struct of_device_id moortec_pvt_of_match[] = {
912 { .compatible = "moortec,mr75203" },
913 { }
914 };
915 MODULE_DEVICE_TABLE(of, moortec_pvt_of_match);
916
917 static struct platform_driver moortec_pvt_driver = {
918 .driver = {
919 .name = "moortec-pvt",
920 .of_match_table = moortec_pvt_of_match,
921 },
922 .probe = mr75203_probe,
923 };
924 module_platform_driver(moortec_pvt_driver);
925
926 MODULE_DESCRIPTION("Moortec Semiconductor MR75203 PVT Controller driver");
927 MODULE_LICENSE("GPL v2");
928