1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the J722S MAIN domain peripherals 4 * 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clk-0 { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 serdes_wiz0: phy@f000000 { 21 compatible = "ti,am64-wiz-10g"; 22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; 27 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 28 num-lanes = <1>; 29 #reset-cells = <1>; 30 #clock-cells = <1>; 31 32 assigned-clocks = <&k3_clks 279 1>; 33 assigned-clock-parents = <&k3_clks 279 5>; 34 35 status = "disabled"; 36 37 serdes0: serdes@f000000 { 38 compatible = "ti,j721e-serdes-10g"; 39 reg = <0x0f000000 0x00010000>; 40 reg-names = "torrent_phy"; 41 resets = <&serdes_wiz0 0>; 42 reset-names = "torrent_reset"; 43 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 44 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 45 clock-names = "refclk", "phy_en_refclk"; 46 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 47 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 48 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 49 assigned-clock-parents = <&k3_clks 279 1>, 50 <&k3_clks 279 1>, 51 <&k3_clks 279 1>; 52 #address-cells = <1>; 53 #size-cells = <0>; 54 #clock-cells = <1>; 55 }; 56 }; 57 58 serdes_wiz1: phy@f010000 { 59 compatible = "ti,am64-wiz-10g"; 60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; 65 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 66 num-lanes = <1>; 67 #reset-cells = <1>; 68 #clock-cells = <1>; 69 70 assigned-clocks = <&k3_clks 280 1>; 71 assigned-clock-parents = <&k3_clks 280 5>; 72 73 status = "disabled"; 74 75 serdes1: serdes@f010000 { 76 compatible = "ti,j721e-serdes-10g"; 77 reg = <0x0f010000 0x00010000>; 78 reg-names = "torrent_phy"; 79 resets = <&serdes_wiz1 0>; 80 reset-names = "torrent_reset"; 81 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 82 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 83 clock-names = "refclk", "phy_en_refclk"; 84 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 85 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 86 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 87 assigned-clock-parents = <&k3_clks 280 1>, 88 <&k3_clks 280 1>, 89 <&k3_clks 280 1>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 #clock-cells = <1>; 93 }; 94 }; 95 96 pcie0_rc: pcie@f102000 { 97 compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host"; 98 reg = <0x00 0x0f102000 0x00 0x1000>, 99 <0x00 0x0f100000 0x00 0x400>, 100 <0x00 0x0d000000 0x00 0x00800000>, 101 <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 102 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 103 ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 104 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 106 interrupt-names = "link_state"; 107 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>; 108 device_type = "pci"; 109 max-link-speed = <3>; 110 num-lanes = <1>; 111 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 112 clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; 113 clock-names = "fck", "pcie_refclk"; 114 #address-cells = <3>; 115 #size-cells = <2>; 116 bus-range = <0x0 0xff>; 117 vendor-id = <0x104c>; 118 device-id = <0xb010>; 119 cdns,no-bar-match-nbits = <64>; 120 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 121 msi-map = <0x0 &gic_its 0x0 0x10000>; 122 status = "disabled"; 123 }; 124 125 usbss1: usb@f920000 { 126 compatible = "ti,j721e-usb"; 127 reg = <0x00 0x0f920000 0x00 0x100>; 128 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 129 clocks = <&k3_clks 278 3>, <&k3_clks 278 1>; 130 clock-names = "ref", "lpm"; 131 assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */ 132 assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */ 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 status = "disabled"; 137 138 usb1: usb@31200000 { 139 compatible = "cdns,usb3"; 140 reg = <0x00 0x31200000 0x00 0x10000>, 141 <0x00 0x31210000 0x00 0x10000>, 142 <0x00 0x31220000 0x00 0x10000>; 143 reg-names = "otg", 144 "xhci", 145 "dev"; 146 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 147 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 148 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 149 interrupt-names = "host", 150 "peripheral", 151 "otg"; 152 maximum-speed = "super-speed"; 153 dr_mode = "otg"; 154 }; 155 }; 156 157 ti_csi2rx1: ticsi2rx@30122000 { 158 compatible = "ti,j721e-csi2rx-shim"; 159 reg = <0x00 0x30122000 0x00 0x1000>; 160 ranges; 161 #address-cells = <2>; 162 #size-cells = <2>; 163 dmas = <&main_bcdma_csi 0 0x5100 0>; 164 dma-names = "rx0"; 165 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 166 status = "disabled"; 167 168 cdns_csi2rx1: csi-bridge@30121000 { 169 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 170 reg = <0x00 0x30121000 0x00 0x1000>; 171 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 173 interrupt-names = "error_irq", "irq"; 174 clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, 175 <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; 176 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 177 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 178 phys = <&dphy1>; 179 phy-names = "dphy"; 180 181 ports { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 csi1_port0: port@0 { 186 reg = <0>; 187 status = "disabled"; 188 }; 189 190 csi1_port1: port@1 { 191 reg = <1>; 192 status = "disabled"; 193 }; 194 195 csi1_port2: port@2 { 196 reg = <2>; 197 status = "disabled"; 198 }; 199 200 csi1_port3: port@3 { 201 reg = <3>; 202 status = "disabled"; 203 }; 204 205 csi1_port4: port@4 { 206 reg = <4>; 207 status = "disabled"; 208 }; 209 }; 210 }; 211 }; 212 213 ti_csi2rx2: ticsi2rx@30142000 { 214 compatible = "ti,j721e-csi2rx-shim"; 215 reg = <0x00 0x30142000 0x00 0x1000>; 216 ranges; 217 #address-cells = <2>; 218 #size-cells = <2>; 219 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 220 dmas = <&main_bcdma_csi 0 0x5200 0>; 221 dma-names = "rx0"; 222 status = "disabled"; 223 224 cdns_csi2rx2: csi-bridge@30141000 { 225 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 226 reg = <0x00 0x30141000 0x00 0x1000>; 227 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 229 interrupt-names = "error_irq", "irq"; 230 clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, 231 <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; 232 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 233 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 234 phys = <&dphy2>; 235 phy-names = "dphy"; 236 237 ports { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 csi2_port0: port@0 { 242 reg = <0>; 243 status = "disabled"; 244 }; 245 246 csi2_port1: port@1 { 247 reg = <1>; 248 status = "disabled"; 249 }; 250 251 csi2_port2: port@2 { 252 reg = <2>; 253 status = "disabled"; 254 }; 255 256 csi2_port3: port@3 { 257 reg = <3>; 258 status = "disabled"; 259 }; 260 261 csi2_port4: port@4 { 262 reg = <4>; 263 status = "disabled"; 264 }; 265 }; 266 }; 267 }; 268 269 ti_csi2rx3: ticsi2rx@30162000 { 270 compatible = "ti,j721e-csi2rx-shim"; 271 reg = <0x00 0x30162000 0x00 0x1000>; 272 ranges; 273 #address-cells = <2>; 274 #size-cells = <2>; 275 dmas = <&main_bcdma_csi 0 0x5300 0>; 276 dma-names = "rx0"; 277 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 278 status = "disabled"; 279 280 cdns_csi2rx3: csi-bridge@30161000 { 281 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 282 reg = <0x00 0x30161000 0x00 0x1000>; 283 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-names = "error_irq", "irq"; 286 clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, 287 <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; 288 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 289 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 290 phys = <&dphy3>; 291 phy-names = "dphy"; 292 293 ports { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 csi3_port0: port@0 { 298 reg = <0>; 299 status = "disabled"; 300 }; 301 302 csi3_port1: port@1 { 303 reg = <1>; 304 status = "disabled"; 305 }; 306 307 csi3_port2: port@2 { 308 reg = <2>; 309 status = "disabled"; 310 }; 311 312 csi3_port3: port@3 { 313 reg = <3>; 314 status = "disabled"; 315 }; 316 317 csi3_port4: port@4 { 318 reg = <4>; 319 status = "disabled"; 320 }; 321 }; 322 }; 323 }; 324 325 dphy1: phy@30130000 { 326 compatible = "cdns,dphy-rx"; 327 reg = <0x00 0x30130000 0x00 0x1100>; 328 #phy-cells = <0>; 329 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 330 status = "disabled"; 331 }; 332 333 dphy2: phy@30150000 { 334 compatible = "cdns,dphy-rx"; 335 reg = <0x00 0x30150000 0x00 0x1100>; 336 #phy-cells = <0>; 337 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 338 status = "disabled"; 339 }; 340 341 dphy3: phy@30170000 { 342 compatible = "cdns,dphy-rx"; 343 reg = <0x00 0x30170000 0x00 0x1100>; 344 #phy-cells = <0>; 345 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 346 status = "disabled"; 347 }; 348 349 main_r5fss0: r5fss@78400000 { 350 compatible = "ti,am62-r5fss"; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges = <0x78400000 0x00 0x78400000 0x8000>, 354 <0x78500000 0x00 0x78500000 0x8000>; 355 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 356 status = "disabled"; 357 358 main_r5fss0_core0: r5f@78400000 { 359 compatible = "ti,am62-r5f"; 360 reg = <0x78400000 0x00008000>, 361 <0x78500000 0x00008000>; 362 reg-names = "atcm", "btcm"; 363 resets = <&k3_reset 262 1>; 364 firmware-name = "j722s-main-r5f0_0-fw"; 365 ti,sci = <&dmsc>; 366 ti,sci-dev-id = <262>; 367 ti,sci-proc-ids = <0x04 0xff>; 368 ti,atcm-enable = <1>; 369 ti,btcm-enable = <1>; 370 ti,loczrama = <1>; 371 status = "disabled"; 372 }; 373 }; 374 375 c7x_0: dsp@7e000000 { 376 compatible = "ti,am62a-c7xv-dsp"; 377 reg = <0x00 0x7e000000 0x00 0x00200000>; 378 reg-names = "l2sram"; 379 resets = <&k3_reset 208 1>; 380 firmware-name = "j722s-c71_0-fw"; 381 ti,sci = <&dmsc>; 382 ti,sci-dev-id = <208>; 383 ti,sci-proc-ids = <0x30 0xff>; 384 status = "disabled"; 385 }; 386 387 c7x_1: dsp@7e200000 { 388 compatible = "ti,am62a-c7xv-dsp"; 389 reg = <0x00 0x7e200000 0x00 0x00200000>; 390 reg-names = "l2sram"; 391 resets = <&k3_reset 268 1>; 392 firmware-name = "j722s-c71_1-fw"; 393 ti,sci = <&dmsc>; 394 ti,sci-dev-id = <268>; 395 ti,sci-proc-ids = <0x31 0xff>; 396 status = "disabled"; 397 }; 398 399 e5010: jpeg-encoder@fd20000 { 400 compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; 401 reg = <0x00 0xfd20000 0x00 0x100>, 402 <0x00 0xfd20200 0x00 0x200>; 403 reg-names = "core", "mmu"; 404 clocks = <&k3_clks 201 0>; 405 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 406 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 407 }; 408}; 409 410&main_bcdma_csi { 411 compatible = "ti,j722s-dmss-bcdma-csi"; 412 reg = <0x00 0x4e230000 0x00 0x100>, 413 <0x00 0x4e180000 0x00 0x20000>, 414 <0x00 0x4e300000 0x00 0x10000>, 415 <0x00 0x4e100000 0x00 0x80000>; 416 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 417 ti,sci-rm-range-tchan = <0x22>; 418}; 419 420/* MCU domain overrides */ 421 422&mcu_r5fss0_core0 { 423 firmware-name = "j722s-mcu-r5f0_0-fw"; 424}; 425 426/* Wakeup domain overrides */ 427 428&wkup_r5fss0_core0 { 429 firmware-name = "j722s-wkup-r5f0_0-fw"; 430}; 431 432&main_conf { 433 serdes_ln_ctrl: mux-controller@4080 { 434 compatible = "reg-mux"; 435 reg = <0x4080 0x14>; 436 #mux-control-cells = <1>; 437 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */ 438 <0x10 0x3>; /* SERDES1 lane0 select */ 439 }; 440}; 441 442&wkup_conf { 443 pcie0_ctrl: pcie0-ctrl@4070 { 444 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 445 reg = <0x4070 0x4>; 446 }; 447}; 448 449&oc_sram { 450 reg = <0x00 0x70000000 0x00 0x40000>; 451 ranges = <0x00 0x00 0x70000000 0x40000>; 452}; 453 454&inta_main_dmss { 455 ti,interrupt-ranges = <7 71 21>; 456}; 457 458&main_gpio0 { 459 gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, 460 <&main_pmx0 70 72 17>; 461 ti,ngpio = <87>; 462}; 463 464&main_gpio1 { 465 gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>, 466 <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>; 467 gpio-reserved-ranges = <0 7>, <32 10>; 468 ti,ngpio = <73>; 469}; 470