1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Realtek switches of the Otto series (RTL838x, RTL839x, RTL930x and RTL931x SoCs) have multiple
4 * integrated MDIO controllers. This driver targets the ethernet MDIO controller. It serves only
5 * 1G/2.5G/10G ethernet PHYs attached to up to 4 individual buses.
6 *
7 * The controller is programmed through MMIO. The MDIO communication is abstracted by the hardware
8 * and uses the switch port number for its addressing. For this to work, mapping registers need to
9 * be setup in advance. With that the controller translates each port based I/O operation into the
10 * physical bus and address. This gives the following end-to-end communication
11 *
12 * +----------+ +----------+ +----------+ +----------+
13 * | phydev | ... | phydev | | phydev | ... | phydev |
14 * +----------+ +----------+ +----------+ +----------+
15 * | | | |
16 * mii_bus 0 +------------------+ +------------------+ mii_bus 1
17 * | |
18 * +-----------------------------------------------------+
19 * | MDIO driver |
20 * | translate bus/address -> port |
21 * +-----------------------------------------------------+
22 * | Software
23 * - - - - - - - - - - - - - - - - - - - - - - - - -
24 * | Hardware
25 * +-----------------------------------------------------+
26 * | MDIO controller |
27 * | translate port -> bus/address |
28 * +-----------------------------------------------------+
29 * | |
30 * bus 0 +------------------+ +------------------+ bus 1
31 * | | | |
32 * +----------+ +----------+ +----------+ +----------+
33 * | PHY 0/1 | ... | PHY 0/31 | | PHY 1/1 | ... | PHY 1/31 |
34 * +----------+ +----------+ +----------+ +----------+
35 *
36 * The driver works out the mapping based on the MDIO bus described in device tree and phandles on
37 * the ethernet-ports property.
38 */
39
40 #include <linux/bitfield.h>
41 #include <linux/bitmap.h>
42 #include <linux/bits.h>
43 #include <linux/find.h>
44 #include <linux/mdio.h>
45 #include <linux/mfd/syscon.h>
46 #include <linux/mutex.h>
47 #include <linux/of_mdio.h>
48 #include <linux/phy.h>
49 #include <linux/platform_device.h>
50 #include <linux/property.h>
51 #include <linux/regmap.h>
52
53 #define RTL9300_NUM_BUSES 4
54 #define RTL9300_NUM_PAGES 4096
55 #define RTL9300_NUM_PORTS 28
56 #define RTL9300_SMI_GLB_CTRL 0xca00
57 #define RTL9300_GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf))
58 #define RTL9300_SMI_PORT0_15_POLLING_SEL 0xca08
59 #define RTL9300_SMI_ACCESS_PHY_CTRL_0 0xcb70
60 #define RTL9300_SMI_ACCESS_PHY_CTRL_1 0xcb74
61 #define RTL9300_PHY_CTRL_REG_ADDR GENMASK(24, 20)
62 #define RTL9300_PHY_CTRL_PARK_PAGE GENMASK(19, 15)
63 #define RTL9300_PHY_CTRL_MAIN_PAGE GENMASK(14, 3)
64 #define RTL9300_PHY_CTRL_WRITE BIT(2)
65 #define RTL9300_PHY_CTRL_READ 0
66 #define RTL9300_PHY_CTRL_TYPE_C45 BIT(1)
67 #define RTL9300_PHY_CTRL_TYPE_C22 0
68 #define RTL9300_PHY_CTRL_FAIL BIT(25)
69 #define RTL9300_SMI_ACCESS_PHY_CTRL_2 0xcb78
70 #define RTL9300_PHY_CTRL_INDATA GENMASK(31, 16)
71 #define RTL9300_PHY_CTRL_DATA GENMASK(15, 0)
72 #define RTL9300_SMI_ACCESS_PHY_CTRL_3 0xcb7c
73 #define RTL9300_SMI_PORT0_5_ADDR_CTRL 0xcb80
74
75 #define RTL9310_NUM_BUSES 4
76 #define RTL9310_NUM_PAGES 8192
77 #define RTL9310_NUM_PORTS 56
78 #define RTL9310_SMI_GLB_CTRL1 0x0cbc
79 #define RTL9310_SMI_GLB_FMT_SEL_C45(intf) BIT((intf) * 2 + 1)
80 #define RTL9310_SMI_INDRT_ACCESS_CTRL_0 0x0c00
81 #define RTL9310_PHY_CTRL_REG_ADDR GENMASK(10, 6)
82 #define RTL9310_PHY_CTRL_MAIN_PAGE GENMASK(23, 11)
83 #define RTL9310_PHY_CTRL_READ 0
84 #define RTL9310_PHY_CTRL_WRITE BIT(4)
85 #define RTL9310_PHY_CTRL_TYPE_C45 BIT(3)
86 #define RTL9310_PHY_CTRL_TYPE_C22 0
87 #define RTL9310_PHY_CTRL_FAIL BIT(1)
88 #define RTL9310_SMI_INDRT_ACCESS_BC_PHYID_CTRL 0x0c14
89 #define RTL9310_BC_PORT_ID GENMASK(10, 5)
90 #define RTL9310_SMI_INDRT_ACCESS_CTRL_1 0x0c04
91 #define RTL9310_SMI_INDRT_ACCESS_CTRL_2_LOW 0x0c08
92 #define RTL9310_SMI_INDRT_ACCESS_CTRL_2_HIGH 0x0c0c
93 #define RTL9310_SMI_INDRT_ACCESS_CTRL_3 0x0c10 /* I/O fields flipped */
94 #define RTL9310_PHY_CTRL_DATA GENMASK(31, 16)
95 #define RTL9310_PHY_CTRL_INDATA GENMASK(15, 0)
96 #define RTL9310_SMI_INDRT_ACCESS_MMD_CTRL 0x0c18
97 #define RTL9310_SMI_PORT_ADDR_CTRL 0x0c74
98 #define RTL9310_SMI_PORT_POLLING_SEL 0x0c9c
99
100 #define PHY_CTRL_CMD BIT(0)
101 #define PHY_CTRL_MMD_DEVAD GENMASK(20, 16)
102 #define PHY_CTRL_MMD_REG GENMASK(15, 0)
103
104 #define MAP_ADDRS_PER_REG 6
105 #define MAP_BITS_PER_ADDR 5
106 #define MAP_BITS_PER_BUS 2
107 #define MAP_BUSES_PER_REG 16
108 #define MAX_PORTS 56
109 #define MAX_SMI_BUSSES 4
110 #define RAW_PAGE(priv) ((priv)->info->num_pages - 1)
111
112
113 struct otto_emdio_cmd_regs {
114 u32 c22_data;
115 u32 c45_data;
116 u32 io_data;
117 u32 port_mask_low;
118 /* additional registers for high port count models RTL839x/RTL931x */
119 u32 port_mask_high;
120 u32 broadcast;
121 u32 ext_page;
122 };
123
124 struct otto_emdio_priv {
125 const struct otto_emdio_info *info;
126 struct regmap *regmap;
127 struct mutex lock; /* protect HW access */
128 DECLARE_BITMAP(valid_ports, MAX_PORTS);
129 u8 smi_bus[MAX_PORTS];
130 u8 smi_addr[MAX_PORTS];
131 bool smi_bus_is_c45[MAX_SMI_BUSSES];
132 struct mii_bus *bus[MAX_SMI_BUSSES];
133 };
134
135 struct otto_emdio_info {
136 u32 addr_map_base;
137 u32 bus_map_base;
138 u32 cmd_fail;
139 u32 cmd_read;
140 u32 cmd_write;
141 struct otto_emdio_cmd_regs cmd_regs;
142 u8 num_buses;
143 u8 num_ports;
144 u16 num_pages;
145 int (*setup_controller)(struct otto_emdio_priv *priv);
146 int (*read_c22)(struct mii_bus *bus, int port, int regnum, u32 *value);
147 int (*read_c45)(struct mii_bus *bus, int port, int dev_addr, int regnum, u32 *value);
148 int (*write_c22)(struct mii_bus *bus, int port, int regnum, u16 value);
149 int (*write_c45)(struct mii_bus *bus, int port, int dev_addr, int regnum, u16 value);
150 };
151
152 struct otto_emdio_chan {
153 struct otto_emdio_priv *priv;
154 u8 mdio_bus;
155 };
156
otto_emdio_phy_to_port(struct mii_bus * bus,int phy_id)157 static int otto_emdio_phy_to_port(struct mii_bus *bus, int phy_id)
158 {
159 struct otto_emdio_chan *chan = bus->priv;
160 struct otto_emdio_priv *priv;
161 int i;
162
163 priv = chan->priv;
164
165 for_each_set_bit(i, priv->valid_ports, priv->info->num_ports)
166 if (priv->smi_bus[i] == chan->mdio_bus &&
167 priv->smi_addr[i] == phy_id)
168 return i;
169
170 return -ENOENT;
171 }
172
otto_emdio_bus_to_priv(struct mii_bus * bus)173 static struct otto_emdio_priv *otto_emdio_bus_to_priv(struct mii_bus *bus)
174 {
175 struct otto_emdio_chan *chan = bus->priv;
176
177 return chan->priv;
178 }
179
otto_emdio_run_cmd(struct mii_bus * bus,u32 cmd,struct otto_emdio_cmd_regs * cmd_data)180 static int otto_emdio_run_cmd(struct mii_bus *bus, u32 cmd,
181 struct otto_emdio_cmd_regs *cmd_data)
182 {
183 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
184 const struct otto_emdio_info *info = priv->info;
185 u32 cmdstate;
186 int ret;
187
188 /* Defensive pre check just in case something goes horrible wrong */
189 ret = regmap_read_poll_timeout(priv->regmap, info->cmd_regs.c22_data,
190 cmdstate, !(cmdstate & PHY_CTRL_CMD), 10, 1000);
191 if (ret)
192 return ret;
193
194 /* Fill all registers. Hardware will read only the needed bits depending on command */
195 if (info->cmd_regs.port_mask_high) {
196 /* Fill extra registers for high port count models */
197 ret = regmap_write(priv->regmap, info->cmd_regs.broadcast, cmd_data->broadcast);
198 if (ret)
199 return ret;
200
201 ret = regmap_write(priv->regmap, info->cmd_regs.ext_page, cmd_data->ext_page);
202 if (ret)
203 return ret;
204
205 ret = regmap_write(priv->regmap,
206 info->cmd_regs.port_mask_high, cmd_data->port_mask_high);
207 if (ret)
208 return ret;
209 }
210
211 ret = regmap_write(priv->regmap, info->cmd_regs.port_mask_low, cmd_data->port_mask_low);
212 if (ret)
213 return ret;
214
215 ret = regmap_write(priv->regmap, info->cmd_regs.io_data, cmd_data->io_data);
216 if (ret)
217 return ret;
218
219 ret = regmap_write(priv->regmap, info->cmd_regs.c45_data, cmd_data->c45_data);
220 if (ret)
221 return ret;
222
223 /* C22 data and command bits share the same register. */
224 ret = regmap_write(priv->regmap, info->cmd_regs.c22_data,
225 cmd_data->c22_data | cmd | PHY_CTRL_CMD);
226 if (ret)
227 return ret;
228
229 ret = regmap_read_poll_timeout(priv->regmap, info->cmd_regs.c22_data,
230 cmdstate, !(cmdstate & PHY_CTRL_CMD), 10, 1000);
231 if (ret)
232 return ret;
233
234 return cmdstate & info->cmd_fail ? -ENXIO : 0;
235 }
236
otto_emdio_read_cmd(struct mii_bus * bus,u32 cmd,struct otto_emdio_cmd_regs * cmd_data,u32 mask,u32 * value)237 static int otto_emdio_read_cmd(struct mii_bus *bus, u32 cmd,
238 struct otto_emdio_cmd_regs *cmd_data, u32 mask, u32 *value)
239 {
240 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
241 int ret;
242
243 lockdep_assert_held(&priv->lock);
244 ret = otto_emdio_run_cmd(bus, cmd | priv->info->cmd_read, cmd_data);
245 if (ret)
246 return ret;
247
248 ret = regmap_read(priv->regmap, priv->info->cmd_regs.io_data, value);
249 if (ret)
250 return ret;
251
252 *value = field_get(mask, *value);
253
254 return 0;
255 }
256
otto_emdio_write_cmd(struct mii_bus * bus,u32 cmd,struct otto_emdio_cmd_regs * cmd_data)257 static int otto_emdio_write_cmd(struct mii_bus *bus, u32 cmd,
258 struct otto_emdio_cmd_regs *cmd_data)
259 {
260 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
261
262 lockdep_assert_held(&priv->lock);
263
264 return otto_emdio_run_cmd(bus, cmd | priv->info->cmd_write, cmd_data);
265 }
266
otto_emdio_9300_read_c22(struct mii_bus * bus,int port,int regnum,u32 * value)267 static int otto_emdio_9300_read_c22(struct mii_bus *bus, int port, int regnum, u32 *value)
268 {
269 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
270 struct otto_emdio_cmd_regs cmd_data = {
271 .c22_data = FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |
272 FIELD_PREP(RTL9300_PHY_CTRL_PARK_PAGE, 0x1f) |
273 FIELD_PREP(RTL9300_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
274 .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
275 };
276
277 return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data,
278 RTL9300_PHY_CTRL_DATA, value);
279 }
280
otto_emdio_9300_write_c22(struct mii_bus * bus,int port,int regnum,u16 value)281 static int otto_emdio_9300_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)
282 {
283 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
284 struct otto_emdio_cmd_regs cmd_data = {
285 .c22_data = FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |
286 FIELD_PREP(RTL9300_PHY_CTRL_PARK_PAGE, 0x1f) |
287 FIELD_PREP(RTL9300_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
288 .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, value),
289 .port_mask_low = BIT(port),
290 };
291
292 return otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data);
293 }
294
otto_emdio_9300_read_c45(struct mii_bus * bus,int port,int dev_addr,int regnum,u32 * value)295 static int otto_emdio_9300_read_c45(struct mii_bus *bus, int port,
296 int dev_addr, int regnum, u32 *value)
297 {
298 struct otto_emdio_cmd_regs cmd_data = {
299 .c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
300 FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
301 .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
302 };
303
304 return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data,
305 RTL9300_PHY_CTRL_DATA, value);
306 }
307
otto_emdio_9300_write_c45(struct mii_bus * bus,int port,int dev_addr,int regnum,u16 value)308 static int otto_emdio_9300_write_c45(struct mii_bus *bus, int port,
309 int dev_addr, int regnum, u16 value)
310 {
311 struct otto_emdio_cmd_regs cmd_data = {
312 .c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
313 FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
314 .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, value),
315 .port_mask_low = BIT(port),
316 };
317
318 return otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data);
319 }
320
otto_emdio_9310_read_c22(struct mii_bus * bus,int port,int regnum,u32 * value)321 static int otto_emdio_9310_read_c22(struct mii_bus *bus, int port, int regnum, u32 *value)
322 {
323 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
324 struct otto_emdio_cmd_regs cmd_data = {
325 .broadcast = FIELD_PREP(RTL9310_BC_PORT_ID, port),
326 .c22_data = FIELD_PREP(RTL9310_PHY_CTRL_REG_ADDR, regnum) |
327 FIELD_PREP(RTL9310_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
328 };
329
330 return otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, &cmd_data,
331 RTL9310_PHY_CTRL_DATA, value);
332 }
333
otto_emdio_9310_write_c22(struct mii_bus * bus,int port,int regnum,u16 value)334 static int otto_emdio_9310_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)
335 {
336 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
337 struct otto_emdio_cmd_regs cmd_data = {
338 .c22_data = FIELD_PREP(RTL9310_PHY_CTRL_REG_ADDR, regnum) |
339 FIELD_PREP(RTL9310_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
340 .io_data = FIELD_PREP(RTL9310_PHY_CTRL_INDATA, value),
341 .port_mask_high = (u32)(BIT_ULL(port) >> 32),
342 .port_mask_low = (u32)(BIT_ULL(port)),
343 };
344
345 return otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, &cmd_data);
346 }
347
otto_emdio_9310_read_c45(struct mii_bus * bus,int port,int dev_addr,int regnum,u32 * value)348 static int otto_emdio_9310_read_c45(struct mii_bus *bus, int port,
349 int dev_addr, int regnum, u32 *value)
350 {
351 struct otto_emdio_cmd_regs cmd_data = {
352 .broadcast = FIELD_PREP(RTL9310_BC_PORT_ID, port),
353 .c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
354 FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
355 };
356
357 return otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, &cmd_data,
358 RTL9310_PHY_CTRL_DATA, value);
359 }
360
otto_emdio_9310_write_c45(struct mii_bus * bus,int port,int dev_addr,int regnum,u16 value)361 static int otto_emdio_9310_write_c45(struct mii_bus *bus, int port,
362 int dev_addr, int regnum, u16 value)
363 {
364 struct otto_emdio_cmd_regs cmd_data = {
365 .c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
366 FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
367 .io_data = FIELD_PREP(RTL9310_PHY_CTRL_INDATA, value),
368 .port_mask_high = (u32)(BIT_ULL(port) >> 32),
369 .port_mask_low = (u32)(BIT_ULL(port)),
370 };
371
372 return otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, &cmd_data);
373 }
374
otto_emdio_read_c22(struct mii_bus * bus,int phy_id,int regnum)375 static int otto_emdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)
376 {
377 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
378 int ret, port;
379 u32 value;
380
381 port = otto_emdio_phy_to_port(bus, phy_id);
382 if (port < 0)
383 return port;
384
385 scoped_guard(mutex, &priv->lock)
386 ret = priv->info->read_c22(bus, port, regnum, &value);
387
388 return ret ? ret : value;
389 }
390
otto_emdio_write_c22(struct mii_bus * bus,int phy_id,int regnum,u16 value)391 static int otto_emdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 value)
392 {
393 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
394 int ret, port;
395
396 port = otto_emdio_phy_to_port(bus, phy_id);
397 if (port < 0)
398 return port;
399
400 scoped_guard(mutex, &priv->lock)
401 ret = priv->info->write_c22(bus, port, regnum, value);
402
403 return ret;
404 }
405
otto_emdio_read_c45(struct mii_bus * bus,int phy_id,int dev_addr,int regnum)406 static int otto_emdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum)
407 {
408 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
409 int ret, port;
410 u32 value;
411
412 port = otto_emdio_phy_to_port(bus, phy_id);
413 if (port < 0)
414 return port;
415
416 scoped_guard(mutex, &priv->lock)
417 ret = priv->info->read_c45(bus, port, dev_addr, regnum, &value);
418
419 return ret ? ret : value;
420 }
421
otto_emdio_write_c45(struct mii_bus * bus,int phy_id,int dev_addr,int regnum,u16 value)422 static int otto_emdio_write_c45(struct mii_bus *bus, int phy_id,
423 int dev_addr, int regnum, u16 value)
424 {
425 struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
426 int ret, port;
427
428 port = otto_emdio_phy_to_port(bus, phy_id);
429 if (port < 0)
430 return port;
431
432 scoped_guard(mutex, &priv->lock)
433 ret = priv->info->write_c45(bus, port, dev_addr, regnum, value);
434
435 return ret;
436 }
437
otto_emdio_write_mapping(struct otto_emdio_priv * priv,u32 base,u32 port,u32 vals_per_reg,u32 bits_per_val,u32 value)438 static int otto_emdio_write_mapping(struct otto_emdio_priv *priv, u32 base, u32 port,
439 u32 vals_per_reg, u32 bits_per_val, u32 value)
440 {
441 u32 shift = (port % vals_per_reg) * bits_per_val;
442 u32 reg = base + (port / vals_per_reg) * 4;
443 u32 mask = GENMASK(bits_per_val - 1, 0);
444
445 return regmap_update_bits(priv->regmap, reg, mask << shift, value << shift);
446 }
447
otto_emdio_setup_topology(struct otto_emdio_priv * priv)448 static int otto_emdio_setup_topology(struct otto_emdio_priv *priv)
449 {
450 const struct otto_emdio_info *info = priv->info;
451 u32 port;
452 int ret;
453
454 for_each_set_bit(port, priv->valid_ports, info->num_ports) {
455 if (info->bus_map_base) {
456 ret = otto_emdio_write_mapping(priv, info->bus_map_base, port,
457 MAP_BUSES_PER_REG, MAP_BITS_PER_BUS,
458 priv->smi_bus[port]);
459 if (ret)
460 return ret;
461 }
462 if (info->addr_map_base) {
463 ret = otto_emdio_write_mapping(priv, info->addr_map_base, port,
464 MAP_ADDRS_PER_REG, MAP_BITS_PER_ADDR,
465 priv->smi_addr[port]);
466 if (ret)
467 return ret;
468 }
469 }
470
471 return 0;
472 }
473
otto_emdio_9300_setup_controller(struct otto_emdio_priv * priv)474 static int otto_emdio_9300_setup_controller(struct otto_emdio_priv *priv)
475 {
476 u32 glb_ctrl_mask = 0, glb_ctrl_val = 0;
477 struct regmap *regmap = priv->regmap;
478 int i, err;
479
480 /* Put the interfaces into C45 mode if required */
481 glb_ctrl_mask = GENMASK(19, 16);
482 for (i = 0; i < priv->info->num_buses; i++)
483 if (priv->smi_bus_is_c45[i])
484 glb_ctrl_val |= RTL9300_GLB_CTRL_INTF_SEL(i);
485
486 err = regmap_update_bits(regmap, RTL9300_SMI_GLB_CTRL,
487 glb_ctrl_mask, glb_ctrl_val);
488 if (err)
489 return err;
490
491 return 0;
492 }
493
otto_emdio_9310_setup_controller(struct otto_emdio_priv * priv)494 static int otto_emdio_9310_setup_controller(struct otto_emdio_priv *priv)
495 {
496 int i, err;
497
498 /* Put the interfaces into C45 mode if required */
499 for (i = 0; i < priv->info->num_buses; i++) {
500 err = regmap_assign_bits(priv->regmap, RTL9310_SMI_GLB_CTRL1,
501 RTL9310_SMI_GLB_FMT_SEL_C45(i),
502 priv->smi_bus_is_c45[i]);
503 if (err)
504 return err;
505 }
506
507 return 0;
508 }
509
otto_emdio_probe_one(struct device * dev,struct otto_emdio_priv * priv,struct fwnode_handle * node)510 static int otto_emdio_probe_one(struct device *dev, struct otto_emdio_priv *priv,
511 struct fwnode_handle *node)
512 {
513 struct otto_emdio_chan *chan;
514 struct mii_bus *bus;
515 u32 mdio_bus;
516 int err;
517
518 err = fwnode_property_read_u32(node, "reg", &mdio_bus);
519 if (err)
520 return dev_err_probe(dev, err, "undefined smi bus number\n");
521
522 if (mdio_bus >= priv->info->num_buses)
523 return dev_err_probe(dev, -EINVAL,
524 "illegal (dangling) smi bus number %d\n", mdio_bus);
525
526 bus = devm_mdiobus_alloc_size(dev, sizeof(*chan));
527 if (!bus)
528 return -ENOMEM;
529
530 bus->name = "Realtek Switch MDIO Bus";
531 if (priv->smi_bus_is_c45[mdio_bus]) {
532 bus->read_c45 = otto_emdio_read_c45;
533 bus->write_c45 = otto_emdio_write_c45;
534 } else {
535 bus->read = otto_emdio_read_c22;
536 bus->write = otto_emdio_write_c22;
537 }
538 bus->parent = dev;
539 chan = bus->priv;
540 chan->mdio_bus = mdio_bus;
541 chan->priv = priv;
542
543 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", dev_name(dev), mdio_bus);
544
545 err = devm_of_mdiobus_register(dev, bus, to_of_node(node));
546 if (err)
547 return dev_err_probe(dev, err, "cannot register MDIO bus\n");
548
549 return 0;
550 }
551
otto_emdio_get_bus_node(struct device_node * dn)552 static struct device_node *otto_emdio_get_bus_node(struct device_node *dn)
553 {
554 struct device_node *parent = of_get_parent(dn);
555 struct device_node *grandparent;
556
557 if (parent && of_node_name_eq(parent, "ethernet-phy-package")) {
558 grandparent = of_get_parent(parent);
559 of_node_put(parent);
560
561 return grandparent;
562 }
563
564 return parent;
565 }
566
567 /* The mdio-controller is part of a switch block so we parse the sibling
568 * ethernet-ports node and build a mapping of the switch port to MDIO bus/addr
569 * based on the phy-handle.
570 */
otto_emdio_map_ports(struct device * dev)571 static int otto_emdio_map_ports(struct device *dev)
572 {
573 struct device_node *ports_dn, *phy_dn, *bus_dn, *ctrl_dn;
574 struct otto_emdio_priv *priv = dev_get_drvdata(dev);
575 struct device *parent = dev->parent;
576 int addr, err = 0;
577 u32 bus, pn;
578
579 ports_dn = of_get_child_by_name(parent->of_node, "ethernet-ports");
580 if (!ports_dn)
581 return dev_err_probe(dev, -EINVAL, "%pfwP missing ethernet-ports\n",
582 dev_fwnode(parent));
583
584 for_each_available_child_of_node_scoped(ports_dn, port_dn) {
585 ctrl_dn = NULL;
586 bus_dn = NULL;
587 phy_dn = of_parse_phandle(port_dn, "phy-handle", 0);
588 /* skip ports without phys */
589 if (!phy_dn)
590 continue;
591
592 bus_dn = otto_emdio_get_bus_node(phy_dn);
593 if (!bus_dn)
594 goto put_nodes;
595
596 ctrl_dn = of_get_parent(bus_dn);
597 /* only map ports that are connected to this mdio-controller */
598 if (ctrl_dn != dev->of_node)
599 goto put_nodes;
600
601 err = of_property_read_u32(port_dn, "reg", &pn);
602 if (err)
603 goto put_nodes;
604
605 if (pn >= priv->info->num_ports) {
606 err = dev_err_probe(dev, -EINVAL, "illegal port number %d\n", pn);
607 goto put_nodes;
608 }
609
610 if (test_bit(pn, priv->valid_ports)) {
611 err = dev_err_probe(dev, -EINVAL, "duplicated port number %d\n", pn);
612 goto put_nodes;
613 }
614
615 err = of_property_read_u32(bus_dn, "reg", &bus);
616 if (err)
617 goto put_nodes;
618
619 if (bus >= priv->info->num_buses) {
620 err = dev_err_probe(dev, -EINVAL, "illegal smi bus number %d\n", bus);
621 goto put_nodes;
622 }
623
624 addr = of_mdio_parse_addr(dev, phy_dn);
625 if (addr < 0) {
626 err = addr;
627 goto put_nodes;
628 }
629
630 /*
631 * The MDIO accesses from the kernel work with the PHY polling unit in the
632 * switch. The PPU either operates in GPHY (i.e. clause 22) or 10GPHY mode
633 * (i.e. clause 45). Select 10GPHY mode if there is at least one PHY that
634 * declares compatible = "ethernet-phy-ieee802.3-c45".
635 */
636 if (of_device_is_compatible(phy_dn, "ethernet-phy-ieee802.3-c45"))
637 priv->smi_bus_is_c45[bus] = true;
638
639 __set_bit(pn, priv->valid_ports);
640 priv->smi_bus[pn] = bus;
641 priv->smi_addr[pn] = addr;
642 put_nodes:
643 of_node_put(bus_dn);
644 of_node_put(phy_dn);
645 of_node_put(ctrl_dn);
646 if (err)
647 break;
648 }
649
650 of_node_put(ports_dn);
651
652 return err;
653 }
654
otto_emdio_probe(struct platform_device * pdev)655 static int otto_emdio_probe(struct platform_device *pdev)
656 {
657 struct device *dev = &pdev->dev;
658 struct otto_emdio_priv *priv;
659 int err;
660
661 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
662 if (!priv)
663 return -ENOMEM;
664
665 err = devm_mutex_init(dev, &priv->lock);
666 if (err)
667 return err;
668
669 priv->info = device_get_match_data(dev);
670 priv->regmap = syscon_node_to_regmap(dev->parent->of_node);
671 if (IS_ERR(priv->regmap))
672 return PTR_ERR(priv->regmap);
673
674 platform_set_drvdata(pdev, priv);
675
676 err = otto_emdio_map_ports(dev);
677 if (err)
678 return err;
679
680 err = otto_emdio_setup_topology(priv);
681 if (err)
682 return err;
683
684 if (priv->info->setup_controller) {
685 err = priv->info->setup_controller(priv);
686 if (err)
687 return dev_err_probe(dev, err, "failed to setup MDIO bus controller\n");
688 }
689
690 device_for_each_child_node_scoped(dev, child) {
691 err = otto_emdio_probe_one(dev, priv, child);
692 if (err)
693 return err;
694 }
695
696 return 0;
697 }
698
699 static const struct otto_emdio_info otto_emdio_9300_info = {
700 .addr_map_base = RTL9300_SMI_PORT0_5_ADDR_CTRL,
701 .bus_map_base = RTL9300_SMI_PORT0_15_POLLING_SEL,
702 .cmd_fail = RTL9300_PHY_CTRL_FAIL,
703 .cmd_read = RTL9300_PHY_CTRL_READ,
704 .cmd_write = RTL9300_PHY_CTRL_WRITE,
705 .cmd_regs = {
706 .c22_data = RTL9300_SMI_ACCESS_PHY_CTRL_1,
707 .c45_data = RTL9300_SMI_ACCESS_PHY_CTRL_3,
708 .io_data = RTL9300_SMI_ACCESS_PHY_CTRL_2,
709 .port_mask_low = RTL9300_SMI_ACCESS_PHY_CTRL_0,
710 },
711 .num_buses = RTL9300_NUM_BUSES,
712 .num_ports = RTL9300_NUM_PORTS,
713 .num_pages = RTL9300_NUM_PAGES,
714 .setup_controller = otto_emdio_9300_setup_controller,
715 .read_c22 = otto_emdio_9300_read_c22,
716 .read_c45 = otto_emdio_9300_read_c45,
717 .write_c22 = otto_emdio_9300_write_c22,
718 .write_c45 = otto_emdio_9300_write_c45,
719 };
720
721 static const struct otto_emdio_info otto_emdio_9310_info = {
722 .addr_map_base = RTL9310_SMI_PORT_ADDR_CTRL,
723 .bus_map_base = RTL9310_SMI_PORT_POLLING_SEL,
724 .cmd_fail = RTL9310_PHY_CTRL_FAIL,
725 .cmd_read = RTL9310_PHY_CTRL_READ,
726 .cmd_write = RTL9310_PHY_CTRL_WRITE,
727 .cmd_regs = {
728 .broadcast = RTL9310_SMI_INDRT_ACCESS_BC_PHYID_CTRL,
729 .c22_data = RTL9310_SMI_INDRT_ACCESS_CTRL_0,
730 .c45_data = RTL9310_SMI_INDRT_ACCESS_MMD_CTRL,
731 .ext_page = RTL9310_SMI_INDRT_ACCESS_CTRL_1,
732 .io_data = RTL9310_SMI_INDRT_ACCESS_CTRL_3,
733 .port_mask_low = RTL9310_SMI_INDRT_ACCESS_CTRL_2_LOW,
734 .port_mask_high = RTL9310_SMI_INDRT_ACCESS_CTRL_2_HIGH,
735 },
736 .num_buses = RTL9310_NUM_BUSES,
737 .num_pages = RTL9310_NUM_PAGES,
738 .num_ports = RTL9310_NUM_PORTS,
739 .setup_controller = otto_emdio_9310_setup_controller,
740 .read_c22 = otto_emdio_9310_read_c22,
741 .read_c45 = otto_emdio_9310_read_c45,
742 .write_c22 = otto_emdio_9310_write_c22,
743 .write_c45 = otto_emdio_9310_write_c45,
744 };
745
746 static const struct of_device_id otto_emdio_ids[] = {
747 { .compatible = "realtek,rtl9301-mdio", .data = &otto_emdio_9300_info },
748 { .compatible = "realtek,rtl9311-mdio", .data = &otto_emdio_9310_info },
749 {}
750 };
751 MODULE_DEVICE_TABLE(of, otto_emdio_ids);
752
753 static struct platform_driver otto_emdio_driver = {
754 .probe = otto_emdio_probe,
755 .driver = {
756 .name = "mdio-rtl9300",
757 .of_match_table = otto_emdio_ids,
758 },
759 };
760
761 module_platform_driver(otto_emdio_driver);
762
763 MODULE_DESCRIPTION("RTL9300 MDIO driver");
764 MODULE_LICENSE("GPL");
765