1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012, 2016, 2025 Chelsio Communications.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_inet.h"
30
31 #include <sys/param.h>
32 #include <sys/eventhandler.h>
33
34 #include "common.h"
35 #include "t4_regs.h"
36 #include "t4_regs_values.h"
37 #include "firmware/t4fw_interface.h"
38
39 #undef msleep
40 #define msleep(x) do { \
41 if (cold) \
42 DELAY((x) * 1000); \
43 else \
44 pause("t4hw", (x) * hz / 1000); \
45 } while (0)
46
47 /**
48 * t4_wait_op_done_val - wait until an operation is completed
49 * @adapter: the adapter performing the operation
50 * @reg: the register to check for completion
51 * @mask: a single-bit field within @reg that indicates completion
52 * @polarity: the value of the field when the operation is completed
53 * @attempts: number of check iterations
54 * @delay: delay in usecs between iterations
55 * @valp: where to store the value of the register at completion time
56 *
57 * Wait until an operation is completed by checking a bit in a register
58 * up to @attempts times. If @valp is not NULL the value of the register
59 * at the time it indicated completion is stored there. Returns 0 if the
60 * operation completes and -EAGAIN otherwise.
61 */
t4_wait_op_done_val(struct adapter * adapter,int reg,u32 mask,int polarity,int attempts,int delay,u32 * valp)62 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
63 int polarity, int attempts, int delay, u32 *valp)
64 {
65 while (1) {
66 u32 val = t4_read_reg(adapter, reg);
67
68 if (!!(val & mask) == polarity) {
69 if (valp)
70 *valp = val;
71 return 0;
72 }
73 if (--attempts == 0)
74 return -EAGAIN;
75 if (delay)
76 udelay(delay);
77 }
78 }
79
t4_wait_op_done(struct adapter * adapter,int reg,u32 mask,int polarity,int attempts,int delay)80 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
81 int polarity, int attempts, int delay)
82 {
83 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
84 delay, NULL);
85 }
86
87 /**
88 * t7_wait_sram_done - wait until an operation is completed
89 * @adapter: the adapter performing the operation
90 * @reg: the register to check for completion
91 * @result_reg: register that holds the result value
92 * @attempts: number of check iterations
93 * @delay: delay in usecs between iterations
94 * @valp: where to store the value of the result register at completion time
95 *
96 * Waits until a specific bit in @reg is cleared, checking up to
97 * @attempts times.Once the bit is cleared, reads from @result_reg
98 * and stores the value in @valp if it is not NULL. Returns 0 if the
99 * operation completes successfully and -EAGAIN if it times out.
100 */
t7_wait_sram_done(struct adapter * adap,int reg,int result_reg,int attempts,int delay,u32 * valp)101 static int t7_wait_sram_done(struct adapter *adap, int reg, int result_reg,
102 int attempts, int delay, u32 *valp)
103 {
104 while (1) {
105 u32 val = t4_read_reg(adap, reg);
106
107 /* Check if SramStart (bit 19) is cleared */
108 if (!(val & (1 << 19))) {
109 if (valp)
110 *valp = t4_read_reg(adap, result_reg);
111 return 0;
112 }
113
114 if (--attempts == 0)
115 return -EAGAIN;
116
117 if (delay)
118 udelay(delay);
119 }
120 }
121
122 /**
123 * t4_set_reg_field - set a register field to a value
124 * @adapter: the adapter to program
125 * @addr: the register address
126 * @mask: specifies the portion of the register to modify
127 * @val: the new value for the register field
128 *
129 * Sets a register field specified by the supplied mask to the
130 * given value.
131 */
t4_set_reg_field(struct adapter * adapter,unsigned int addr,u32 mask,u32 val)132 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
133 u32 val)
134 {
135 u32 v = t4_read_reg(adapter, addr) & ~mask;
136
137 t4_write_reg(adapter, addr, v | val);
138 (void) t4_read_reg(adapter, addr); /* flush */
139 }
140
141 /**
142 * t4_read_indirect - read indirectly addressed registers
143 * @adap: the adapter
144 * @addr_reg: register holding the indirect address
145 * @data_reg: register holding the value of the indirect register
146 * @vals: where the read register values are stored
147 * @nregs: how many indirect registers to read
148 * @start_idx: index of first indirect register to read
149 *
150 * Reads registers that are accessed indirectly through an address/data
151 * register pair.
152 */
t4_read_indirect(struct adapter * adap,unsigned int addr_reg,unsigned int data_reg,u32 * vals,unsigned int nregs,unsigned int start_idx)153 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
154 unsigned int data_reg, u32 *vals,
155 unsigned int nregs, unsigned int start_idx)
156 {
157 while (nregs--) {
158 t4_write_reg(adap, addr_reg, start_idx);
159 *vals++ = t4_read_reg(adap, data_reg);
160 start_idx++;
161 }
162 }
163
164 /**
165 * t4_write_indirect - write indirectly addressed registers
166 * @adap: the adapter
167 * @addr_reg: register holding the indirect addresses
168 * @data_reg: register holding the value for the indirect registers
169 * @vals: values to write
170 * @nregs: how many indirect registers to write
171 * @start_idx: address of first indirect register to write
172 *
173 * Writes a sequential block of registers that are accessed indirectly
174 * through an address/data register pair.
175 */
t4_write_indirect(struct adapter * adap,unsigned int addr_reg,unsigned int data_reg,const u32 * vals,unsigned int nregs,unsigned int start_idx)176 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
177 unsigned int data_reg, const u32 *vals,
178 unsigned int nregs, unsigned int start_idx)
179 {
180 while (nregs--) {
181 t4_write_reg(adap, addr_reg, start_idx++);
182 t4_write_reg(adap, data_reg, *vals++);
183 }
184 }
185
186 /*
187 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
188 * mechanism. This guarantees that we get the real value even if we're
189 * operating within a Virtual Machine and the Hypervisor is trapping our
190 * Configuration Space accesses.
191 *
192 * N.B. This routine should only be used as a last resort: the firmware uses
193 * the backdoor registers on a regular basis and we can end up
194 * conflicting with it's uses!
195 */
t4_hw_pci_read_cfg4(adapter_t * adap,int reg)196 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
197 {
198 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
199 u32 val;
200
201 if (chip_id(adap) <= CHELSIO_T5)
202 req |= F_ENABLE;
203 else
204 req |= F_T6_ENABLE;
205
206 if (is_t4(adap))
207 req |= F_LOCALCFG;
208
209 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
210 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
211
212 /*
213 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
214 * Configuration Space read. (None of the other fields matter when
215 * F_ENABLE is 0 so a simple register write is easier than a
216 * read-modify-write via t4_set_reg_field().)
217 */
218 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
219
220 return val;
221 }
222
223 /*
224 * t4_report_fw_error - report firmware error
225 * @adap: the adapter
226 *
227 * The adapter firmware can indicate error conditions to the host.
228 * If the firmware has indicated an error, print out the reason for
229 * the firmware error.
230 */
t4_report_fw_error(struct adapter * adap)231 void t4_report_fw_error(struct adapter *adap)
232 {
233 static const char *const reason[] = {
234 "Crash", /* PCIE_FW_EVAL_CRASH */
235 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
236 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
237 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
238 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
239 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
240 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
241 "Reserved", /* reserved */
242 };
243 u32 pcie_fw;
244
245 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
246 if (pcie_fw & F_PCIE_FW_ERR) {
247 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n",
248 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw);
249 }
250 }
251
252 /*
253 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
254 */
get_mbox_rpl(struct adapter * adap,__be64 * rpl,int nflit,u32 mbox_addr)255 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
256 u32 mbox_addr)
257 {
258 for ( ; nflit; nflit--, mbox_addr += 8)
259 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
260 }
261
262 /*
263 * Handle a FW assertion reported in a mailbox.
264 */
fw_asrt(struct adapter * adap,struct fw_debug_cmd * asrt)265 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
266 {
267 CH_ALERT(adap,
268 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
269 asrt->u.assert.filename_0_7,
270 be32_to_cpu(asrt->u.assert.line),
271 be32_to_cpu(asrt->u.assert.x),
272 be32_to_cpu(asrt->u.assert.y));
273 }
274
275 struct port_tx_state {
276 uint64_t rx_pause;
277 uint64_t tx_frames;
278 };
279
280 u32
t4_port_reg(struct adapter * adap,u8 port,u32 reg)281 t4_port_reg(struct adapter *adap, u8 port, u32 reg)
282 {
283 if (chip_id(adap) > CHELSIO_T6)
284 return T7_PORT_REG(port, reg);
285 if (chip_id(adap) > CHELSIO_T4)
286 return T5_PORT_REG(port, reg);
287 return PORT_REG(port, reg);
288 }
289
290 static void
read_tx_state_one(struct adapter * sc,int i,struct port_tx_state * tx_state)291 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
292 {
293 uint32_t rx_pause_reg, tx_frames_reg;
294
295 rx_pause_reg = t4_port_reg(sc, i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
296 tx_frames_reg = t4_port_reg(sc, i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
297
298 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
299 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
300 }
301
302 static void
read_tx_state(struct adapter * sc,struct port_tx_state * tx_state)303 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
304 {
305 int i;
306
307 for (i = 0; i < MAX_NCHAN; i++) {
308 if (sc->chan_map[i] != 0xff)
309 read_tx_state_one(sc, i, &tx_state[i]);
310 }
311 }
312
313 static void
check_tx_state(struct adapter * sc,struct port_tx_state * tx_state)314 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
315 {
316 uint32_t port_ctl_reg;
317 uint64_t tx_frames, rx_pause;
318 int i;
319
320 for (i = 0; i < MAX_NCHAN; i++) {
321 if (sc->chan_map[i] == 0xff)
322 continue;
323 rx_pause = tx_state[i].rx_pause;
324 tx_frames = tx_state[i].tx_frames;
325 read_tx_state_one(sc, i, &tx_state[i]); /* update */
326
327 port_ctl_reg = t4_port_reg(sc, i, A_MPS_PORT_CTL);
328 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN &&
329 rx_pause != tx_state[i].rx_pause &&
330 tx_frames == tx_state[i].tx_frames) {
331 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
332 mdelay(1);
333 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
334 }
335 }
336 }
337
338 #define X_CIM_PF_NOACCESS 0xeeeeeeee
339 /**
340 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
341 * @adap: the adapter
342 * @mbox: index of the mailbox to use
343 * @cmd: the command to write
344 * @size: command length in bytes
345 * @rpl: where to optionally store the reply
346 * @sleep_ok: if true we may sleep while awaiting command completion
347 * @timeout: time to wait for command to finish before timing out
348 * (negative implies @sleep_ok=false)
349 *
350 * Sends the given command to FW through the selected mailbox and waits
351 * for the FW to execute the command. If @rpl is not %NULL it is used to
352 * store the FW's reply to the command. The command and its optional
353 * reply are of the same length. Some FW commands like RESET and
354 * INITIALIZE can take a considerable amount of time to execute.
355 * @sleep_ok determines whether we may sleep while awaiting the response.
356 * If sleeping is allowed we use progressive backoff otherwise we spin.
357 * Note that passing in a negative @timeout is an alternate mechanism
358 * for specifying @sleep_ok=false. This is useful when a higher level
359 * interface allows for specification of @timeout but not @sleep_ok ...
360 *
361 * The return value is 0 on success or a negative errno on failure. A
362 * failure can happen either because we are not able to execute the
363 * command or FW executes it but signals an error. In the latter case
364 * the return value is the error code indicated by FW (negated).
365 */
t4_wr_mbox_meat_timeout(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,bool sleep_ok,int timeout)366 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
367 int size, void *rpl, bool sleep_ok, int timeout)
368 {
369 /*
370 * We delay in small increments at first in an effort to maintain
371 * responsiveness for simple, fast executing commands but then back
372 * off to larger delays to a maximum retry delay.
373 */
374 static const int delay[] = {
375 1, 1, 3, 5, 10, 10, 20, 50, 100
376 };
377 u32 v;
378 u64 res;
379 int i, ms, delay_idx, ret, next_tx_check;
380 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
381 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
382 u32 ctl;
383 __be64 cmd_rpl[MBOX_LEN/8];
384 u32 pcie_fw;
385 struct port_tx_state tx_state[MAX_NPORTS];
386
387 if (adap->flags & CHK_MBOX_ACCESS)
388 ASSERT_SYNCHRONIZED_OP(adap);
389
390 if (size <= 0 || (size & 15) || size > MBOX_LEN)
391 return -EINVAL;
392
393 if (adap->flags & IS_VF) {
394 if (chip_id(adap) >= CHELSIO_T6)
395 data_reg = FW_T6VF_MBDATA_BASE_ADDR;
396 else
397 data_reg = FW_T4VF_MBDATA_BASE_ADDR;
398 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
399 }
400
401 /*
402 * If we have a negative timeout, that implies that we can't sleep.
403 */
404 if (timeout < 0) {
405 sleep_ok = false;
406 timeout = -timeout;
407 }
408
409 /*
410 * Attempt to gain access to the mailbox.
411 */
412 pcie_fw = 0;
413 if (!(adap->flags & IS_VF)) {
414 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
415 if (pcie_fw & F_PCIE_FW_ERR)
416 goto failed;
417 }
418 for (i = 0; i < 4; i++) {
419 ctl = t4_read_reg(adap, ctl_reg);
420 v = G_MBOWNER(ctl);
421 if (v != X_MBOWNER_NONE)
422 break;
423 }
424
425 /*
426 * If we were unable to gain access, report the error to our caller.
427 */
428 if (v != X_MBOWNER_PL) {
429 if (!(adap->flags & IS_VF)) {
430 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
431 if (pcie_fw & F_PCIE_FW_ERR)
432 goto failed;
433 }
434 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
435 return ret;
436 }
437
438 /*
439 * If we gain ownership of the mailbox and there's a "valid" message
440 * in it, this is likely an asynchronous error message from the
441 * firmware. So we'll report that and then proceed on with attempting
442 * to issue our own command ... which may well fail if the error
443 * presaged the firmware crashing ...
444 */
445 if (ctl & F_MBMSGVALID) {
446 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true);
447 }
448
449 /*
450 * Copy in the new mailbox command and send it on its way ...
451 */
452 memset(cmd_rpl, 0, sizeof(cmd_rpl));
453 memcpy(cmd_rpl, cmd, size);
454 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false);
455 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++)
456 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i]));
457
458 if (adap->flags & IS_VF) {
459 /*
460 * For the VFs, the Mailbox Data "registers" are
461 * actually backed by T4's "MA" interface rather than
462 * PL Registers (as is the case for the PFs). Because
463 * these are in different coherency domains, the write
464 * to the VF's PL-register-backed Mailbox Control can
465 * race in front of the writes to the MA-backed VF
466 * Mailbox Data "registers". So we need to do a
467 * read-back on at least one byte of the VF Mailbox
468 * Data registers before doing the write to the VF
469 * Mailbox Control register.
470 */
471 t4_read_reg(adap, data_reg);
472 }
473
474 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
475 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */
476 next_tx_check = 1000;
477 delay_idx = 0;
478 ms = delay[0];
479
480 /*
481 * Loop waiting for the reply; bail out if we time out or the firmware
482 * reports an error.
483 */
484 for (i = 0; i < timeout; i += ms) {
485 if (!(adap->flags & IS_VF)) {
486 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
487 if (pcie_fw & F_PCIE_FW_ERR)
488 break;
489 }
490
491 if (i >= next_tx_check) {
492 check_tx_state(adap, &tx_state[0]);
493 next_tx_check = i + 1000;
494 }
495
496 if (sleep_ok) {
497 ms = delay[delay_idx]; /* last element may repeat */
498 if (delay_idx < ARRAY_SIZE(delay) - 1)
499 delay_idx++;
500 msleep(ms);
501 } else {
502 mdelay(ms);
503 }
504
505 v = t4_read_reg(adap, ctl_reg);
506 if (v == X_CIM_PF_NOACCESS)
507 continue;
508 if (G_MBOWNER(v) == X_MBOWNER_PL) {
509 if (!(v & F_MBMSGVALID)) {
510 t4_write_reg(adap, ctl_reg,
511 V_MBOWNER(X_MBOWNER_NONE));
512 continue;
513 }
514
515 /*
516 * Retrieve the command reply and release the mailbox.
517 */
518 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
519 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false);
520 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
521
522 res = be64_to_cpu(cmd_rpl[0]);
523 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
524 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
525 res = V_FW_CMD_RETVAL(EIO);
526 } else if (rpl)
527 memcpy(rpl, cmd_rpl, size);
528 return -G_FW_CMD_RETVAL((int)res);
529 }
530 }
531
532 /*
533 * We timed out waiting for a reply to our mailbox command. Report
534 * the error and also check to see if the firmware reported any
535 * errors ...
536 */
537 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n",
538 *(const u8 *)cmd, mbox, pcie_fw);
539 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true);
540 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true);
541 failed:
542 adap->flags &= ~FW_OK;
543 ret = pcie_fw & F_PCIE_FW_ERR ? -ENXIO : -ETIMEDOUT;
544 t4_fatal_err(adap, true);
545 return ret;
546 }
547
t4_wr_mbox_meat(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,bool sleep_ok)548 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
549 void *rpl, bool sleep_ok)
550 {
551 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
552 sleep_ok, FW_CMD_MAX_TIMEOUT);
553 }
554
t4_edc_err_read(struct adapter * adap,int idx)555 static int t4_edc_err_read(struct adapter *adap, int idx)
556 {
557 u32 edc_ecc_err_addr_reg;
558 u32 edc_bist_status_rdata_reg;
559
560 if (is_t4(adap)) {
561 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
562 return 0;
563 }
564 if (idx != MEM_EDC0 && idx != MEM_EDC1) {
565 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
566 return 0;
567 }
568
569 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
570 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
571
572 CH_WARN(adap,
573 " edc%d err addr 0x%x: 0x%x.\n",
574 idx, edc_ecc_err_addr_reg,
575 t4_read_reg(adap, edc_ecc_err_addr_reg));
576 CH_WARN(adap,
577 " bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
578 edc_bist_status_rdata_reg,
579 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
580 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
581 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
582 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
583 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
584 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
585 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
586 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
587 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
588
589 return 0;
590 }
591
592 /**
593 * t4_mc_read - read from MC through backdoor accesses
594 * @adap: the adapter
595 * @idx: which MC to access
596 * @addr: address of first byte requested
597 * @data: 64 bytes of data containing the requested address
598 * @ecc: where to store the corresponding 64-bit ECC word
599 *
600 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
601 * that covers the requested address @addr. If @parity is not %NULL it
602 * is assigned the 64-bit ECC word for the read data.
603 */
t4_mc_read(struct adapter * adap,int idx,u32 addr,__be32 * data,u64 * ecc)604 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
605 {
606 int i;
607 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
608 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
609
610 if (is_t4(adap)) {
611 mc_bist_cmd_reg = A_MC_BIST_CMD;
612 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
613 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
614 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
615 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
616 } else if (chip_id(adap) < CHELSIO_T7) {
617 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
618 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
619 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
620 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, idx);
621 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, idx);
622 } else {
623 /* Need to figure out split mode and the rest. */
624 return (-ENOTSUP);
625 }
626
627 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
628 return -EBUSY;
629 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
630 t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
631 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
632 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
633 F_START_BIST | V_BIST_CMD_GAP(1));
634 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
635 if (i)
636 return i;
637
638 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
639
640 for (i = 15; i >= 0; i--)
641 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
642 if (ecc)
643 *ecc = t4_read_reg64(adap, MC_DATA(16));
644 #undef MC_DATA
645 return 0;
646 }
647
648 /**
649 * t4_edc_read - read from EDC through backdoor accesses
650 * @adap: the adapter
651 * @idx: which EDC to access
652 * @addr: address of first byte requested
653 * @data: 64 bytes of data containing the requested address
654 * @ecc: where to store the corresponding 64-bit ECC word
655 *
656 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
657 * that covers the requested address @addr. If @parity is not %NULL it
658 * is assigned the 64-bit ECC word for the read data.
659 */
t4_edc_read(struct adapter * adap,int idx,u32 addr,__be32 * data,u64 * ecc)660 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
661 {
662 int i;
663 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
664 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
665
666 if (is_t4(adap)) {
667 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
668 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
669 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
670 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
671 idx);
672 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
673 idx);
674 } else {
675 edc_bist_cmd_reg = EDC_T5_REG(A_EDC_H_BIST_CMD, idx);
676 edc_bist_cmd_addr_reg = EDC_T5_REG(A_EDC_H_BIST_CMD_ADDR, idx);
677 edc_bist_cmd_len_reg = EDC_T5_REG(A_EDC_H_BIST_CMD_LEN, idx);
678 edc_bist_cmd_data_pattern = EDC_T5_REG(A_EDC_H_BIST_DATA_PATTERN,
679 idx);
680 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA,
681 idx);
682 }
683
684 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
685 return -EBUSY;
686 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
687 t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
688 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
689 t4_write_reg(adap, edc_bist_cmd_reg,
690 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
691 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
692 if (i)
693 return i;
694
695 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
696
697 for (i = 15; i >= 0; i--)
698 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
699 if (ecc)
700 *ecc = t4_read_reg64(adap, EDC_DATA(16));
701 #undef EDC_DATA
702 return 0;
703 }
704
705 /**
706 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer
707 * @adap: the adapter
708 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
709 * @addr: address within indicated memory type
710 * @len: amount of memory to read
711 * @buf: host memory buffer
712 *
713 * Reads an [almost] arbitrary memory region in the firmware: the
714 * firmware memory address, length and host buffer must be aligned on
715 * 32-bit boudaries. The memory is returned as a raw byte sequence from
716 * the firmware's memory. If this memory contains data structures which
717 * contain multi-byte integers, it's the callers responsibility to
718 * perform appropriate byte order conversions.
719 */
t4_mem_read(struct adapter * adap,int mtype,u32 addr,u32 len,__be32 * buf)720 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
721 __be32 *buf)
722 {
723 u32 pos, start, end, offset;
724 int ret;
725
726 /*
727 * Argument sanity checks ...
728 */
729 if ((addr & 0x3) || (len & 0x3))
730 return -EINVAL;
731
732 /*
733 * The underlaying EDC/MC read routines read 64 bytes at a time so we
734 * need to round down the start and round up the end. We'll start
735 * copying out of the first line at (addr - start) a word at a time.
736 */
737 start = rounddown2(addr, 64);
738 end = roundup2(addr + len, 64);
739 offset = (addr - start)/sizeof(__be32);
740
741 for (pos = start; pos < end; pos += 64, offset = 0) {
742 __be32 data[16];
743
744 /*
745 * Read the chip's memory block and bail if there's an error.
746 */
747 if ((mtype == MEM_MC) || (mtype == MEM_MC1))
748 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
749 else
750 ret = t4_edc_read(adap, mtype, pos, data, NULL);
751 if (ret)
752 return ret;
753
754 /*
755 * Copy the data into the caller's memory buffer.
756 */
757 while (offset < 16 && len > 0) {
758 *buf++ = data[offset++];
759 len -= sizeof(__be32);
760 }
761 }
762
763 return 0;
764 }
765
766 /*
767 * Return the specified PCI-E Configuration Space register from our Physical
768 * Function. We try first via a Firmware LDST Command (if fw_attach != 0)
769 * since we prefer to let the firmware own all of these registers, but if that
770 * fails we go for it directly ourselves.
771 */
t4_read_pcie_cfg4(struct adapter * adap,int reg,int drv_fw_attach)772 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
773 {
774
775 /*
776 * If fw_attach != 0, construct and send the Firmware LDST Command to
777 * retrieve the specified PCI-E Configuration Space register.
778 */
779 if (drv_fw_attach != 0) {
780 struct fw_ldst_cmd ldst_cmd;
781 int ret;
782
783 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
784 ldst_cmd.op_to_addrspace =
785 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
786 F_FW_CMD_REQUEST |
787 F_FW_CMD_READ |
788 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
789 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
790 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
791 ldst_cmd.u.pcie.ctrl_to_fn =
792 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
793 ldst_cmd.u.pcie.r = reg;
794
795 /*
796 * If the LDST Command succeeds, return the result, otherwise
797 * fall through to reading it directly ourselves ...
798 */
799 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
800 &ldst_cmd);
801 if (ret == 0)
802 return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
803
804 CH_WARN(adap, "Firmware failed to return "
805 "Configuration Space register %d, err = %d\n",
806 reg, -ret);
807 }
808
809 /*
810 * Read the desired Configuration Space register via the PCI-E
811 * Backdoor mechanism.
812 */
813 return t4_hw_pci_read_cfg4(adap, reg);
814 }
815
816 /**
817 * t4_get_regs_len - return the size of the chips register set
818 * @adapter: the adapter
819 *
820 * Returns the size of the chip's BAR0 register space.
821 */
t4_get_regs_len(struct adapter * adapter)822 unsigned int t4_get_regs_len(struct adapter *adapter)
823 {
824 unsigned int chip_version = chip_id(adapter);
825
826 switch (chip_version) {
827 case CHELSIO_T4:
828 if (adapter->flags & IS_VF)
829 return FW_T4VF_REGMAP_SIZE;
830 return T4_REGMAP_SIZE;
831
832 case CHELSIO_T5:
833 case CHELSIO_T6:
834 case CHELSIO_T7:
835 if (adapter->flags & IS_VF)
836 return FW_T4VF_REGMAP_SIZE;
837 return T5_REGMAP_SIZE;
838 }
839
840 CH_ERR(adapter,
841 "Unsupported chip version %d\n", chip_version);
842 return 0;
843 }
844
845 /**
846 * t4_get_regs - read chip registers into provided buffer
847 * @adap: the adapter
848 * @buf: register buffer
849 * @buf_size: size (in bytes) of register buffer
850 *
851 * If the provided register buffer isn't large enough for the chip's
852 * full register range, the register dump will be truncated to the
853 * register buffer's size.
854 */
t4_get_regs(struct adapter * adap,u8 * buf,size_t buf_size)855 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
856 {
857 static const unsigned int t4_reg_ranges[] = {
858 0x1008, 0x1108,
859 0x1180, 0x1184,
860 0x1190, 0x1194,
861 0x11a0, 0x11a4,
862 0x11b0, 0x11b4,
863 0x11fc, 0x123c,
864 0x1300, 0x173c,
865 0x1800, 0x18fc,
866 0x3000, 0x30d8,
867 0x30e0, 0x30e4,
868 0x30ec, 0x5910,
869 0x5920, 0x5924,
870 0x5960, 0x5960,
871 0x5968, 0x5968,
872 0x5970, 0x5970,
873 0x5978, 0x5978,
874 0x5980, 0x5980,
875 0x5988, 0x5988,
876 0x5990, 0x5990,
877 0x5998, 0x5998,
878 0x59a0, 0x59d4,
879 0x5a00, 0x5ae0,
880 0x5ae8, 0x5ae8,
881 0x5af0, 0x5af0,
882 0x5af8, 0x5af8,
883 0x6000, 0x6098,
884 0x6100, 0x6150,
885 0x6200, 0x6208,
886 0x6240, 0x6248,
887 0x6280, 0x62b0,
888 0x62c0, 0x6338,
889 0x6370, 0x638c,
890 0x6400, 0x643c,
891 0x6500, 0x6524,
892 0x6a00, 0x6a04,
893 0x6a14, 0x6a38,
894 0x6a60, 0x6a70,
895 0x6a78, 0x6a78,
896 0x6b00, 0x6b0c,
897 0x6b1c, 0x6b84,
898 0x6bf0, 0x6bf8,
899 0x6c00, 0x6c0c,
900 0x6c1c, 0x6c84,
901 0x6cf0, 0x6cf8,
902 0x6d00, 0x6d0c,
903 0x6d1c, 0x6d84,
904 0x6df0, 0x6df8,
905 0x6e00, 0x6e0c,
906 0x6e1c, 0x6e84,
907 0x6ef0, 0x6ef8,
908 0x6f00, 0x6f0c,
909 0x6f1c, 0x6f84,
910 0x6ff0, 0x6ff8,
911 0x7000, 0x700c,
912 0x701c, 0x7084,
913 0x70f0, 0x70f8,
914 0x7100, 0x710c,
915 0x711c, 0x7184,
916 0x71f0, 0x71f8,
917 0x7200, 0x720c,
918 0x721c, 0x7284,
919 0x72f0, 0x72f8,
920 0x7300, 0x730c,
921 0x731c, 0x7384,
922 0x73f0, 0x73f8,
923 0x7400, 0x7450,
924 0x7500, 0x7530,
925 0x7600, 0x760c,
926 0x7614, 0x761c,
927 0x7680, 0x76cc,
928 0x7700, 0x7798,
929 0x77c0, 0x77fc,
930 0x7900, 0x79fc,
931 0x7b00, 0x7b58,
932 0x7b60, 0x7b84,
933 0x7b8c, 0x7c38,
934 0x7d00, 0x7d38,
935 0x7d40, 0x7d80,
936 0x7d8c, 0x7ddc,
937 0x7de4, 0x7e04,
938 0x7e10, 0x7e1c,
939 0x7e24, 0x7e38,
940 0x7e40, 0x7e44,
941 0x7e4c, 0x7e78,
942 0x7e80, 0x7ea4,
943 0x7eac, 0x7edc,
944 0x7ee8, 0x7efc,
945 0x8dc0, 0x8e04,
946 0x8e10, 0x8e1c,
947 0x8e30, 0x8e78,
948 0x8ea0, 0x8eb8,
949 0x8ec0, 0x8f6c,
950 0x8fc0, 0x9008,
951 0x9010, 0x9058,
952 0x9060, 0x9060,
953 0x9068, 0x9074,
954 0x90fc, 0x90fc,
955 0x9400, 0x9408,
956 0x9410, 0x9458,
957 0x9600, 0x9600,
958 0x9608, 0x9638,
959 0x9640, 0x96bc,
960 0x9800, 0x9808,
961 0x9820, 0x983c,
962 0x9850, 0x9864,
963 0x9c00, 0x9c6c,
964 0x9c80, 0x9cec,
965 0x9d00, 0x9d6c,
966 0x9d80, 0x9dec,
967 0x9e00, 0x9e6c,
968 0x9e80, 0x9eec,
969 0x9f00, 0x9f6c,
970 0x9f80, 0x9fec,
971 0xd004, 0xd004,
972 0xd010, 0xd03c,
973 0xdfc0, 0xdfe0,
974 0xe000, 0xea7c,
975 0xf000, 0x11110,
976 0x11118, 0x11190,
977 0x19040, 0x1906c,
978 0x19078, 0x19080,
979 0x1908c, 0x190e4,
980 0x190f0, 0x190f8,
981 0x19100, 0x19110,
982 0x19120, 0x19124,
983 0x19150, 0x19194,
984 0x1919c, 0x191b0,
985 0x191d0, 0x191e8,
986 0x19238, 0x1924c,
987 0x193f8, 0x1943c,
988 0x1944c, 0x19474,
989 0x19490, 0x194e0,
990 0x194f0, 0x194f8,
991 0x19800, 0x19c08,
992 0x19c10, 0x19c90,
993 0x19ca0, 0x19ce4,
994 0x19cf0, 0x19d40,
995 0x19d50, 0x19d94,
996 0x19da0, 0x19de8,
997 0x19df0, 0x19e40,
998 0x19e50, 0x19e90,
999 0x19ea0, 0x19f4c,
1000 0x1a000, 0x1a004,
1001 0x1a010, 0x1a06c,
1002 0x1a0b0, 0x1a0e4,
1003 0x1a0ec, 0x1a0f4,
1004 0x1a100, 0x1a108,
1005 0x1a114, 0x1a120,
1006 0x1a128, 0x1a130,
1007 0x1a138, 0x1a138,
1008 0x1a190, 0x1a1c4,
1009 0x1a1fc, 0x1a1fc,
1010 0x1e040, 0x1e04c,
1011 0x1e284, 0x1e28c,
1012 0x1e2c0, 0x1e2c0,
1013 0x1e2e0, 0x1e2e0,
1014 0x1e300, 0x1e384,
1015 0x1e3c0, 0x1e3c8,
1016 0x1e440, 0x1e44c,
1017 0x1e684, 0x1e68c,
1018 0x1e6c0, 0x1e6c0,
1019 0x1e6e0, 0x1e6e0,
1020 0x1e700, 0x1e784,
1021 0x1e7c0, 0x1e7c8,
1022 0x1e840, 0x1e84c,
1023 0x1ea84, 0x1ea8c,
1024 0x1eac0, 0x1eac0,
1025 0x1eae0, 0x1eae0,
1026 0x1eb00, 0x1eb84,
1027 0x1ebc0, 0x1ebc8,
1028 0x1ec40, 0x1ec4c,
1029 0x1ee84, 0x1ee8c,
1030 0x1eec0, 0x1eec0,
1031 0x1eee0, 0x1eee0,
1032 0x1ef00, 0x1ef84,
1033 0x1efc0, 0x1efc8,
1034 0x1f040, 0x1f04c,
1035 0x1f284, 0x1f28c,
1036 0x1f2c0, 0x1f2c0,
1037 0x1f2e0, 0x1f2e0,
1038 0x1f300, 0x1f384,
1039 0x1f3c0, 0x1f3c8,
1040 0x1f440, 0x1f44c,
1041 0x1f684, 0x1f68c,
1042 0x1f6c0, 0x1f6c0,
1043 0x1f6e0, 0x1f6e0,
1044 0x1f700, 0x1f784,
1045 0x1f7c0, 0x1f7c8,
1046 0x1f840, 0x1f84c,
1047 0x1fa84, 0x1fa8c,
1048 0x1fac0, 0x1fac0,
1049 0x1fae0, 0x1fae0,
1050 0x1fb00, 0x1fb84,
1051 0x1fbc0, 0x1fbc8,
1052 0x1fc40, 0x1fc4c,
1053 0x1fe84, 0x1fe8c,
1054 0x1fec0, 0x1fec0,
1055 0x1fee0, 0x1fee0,
1056 0x1ff00, 0x1ff84,
1057 0x1ffc0, 0x1ffc8,
1058 0x20000, 0x2002c,
1059 0x20100, 0x2013c,
1060 0x20190, 0x201a0,
1061 0x201a8, 0x201b8,
1062 0x201c4, 0x201c8,
1063 0x20200, 0x20318,
1064 0x20400, 0x204b4,
1065 0x204c0, 0x20528,
1066 0x20540, 0x20614,
1067 0x21000, 0x21040,
1068 0x2104c, 0x21060,
1069 0x210c0, 0x210ec,
1070 0x21200, 0x21268,
1071 0x21270, 0x21284,
1072 0x212fc, 0x21388,
1073 0x21400, 0x21404,
1074 0x21500, 0x21500,
1075 0x21510, 0x21518,
1076 0x2152c, 0x21530,
1077 0x2153c, 0x2153c,
1078 0x21550, 0x21554,
1079 0x21600, 0x21600,
1080 0x21608, 0x2161c,
1081 0x21624, 0x21628,
1082 0x21630, 0x21634,
1083 0x2163c, 0x2163c,
1084 0x21700, 0x2171c,
1085 0x21780, 0x2178c,
1086 0x21800, 0x21818,
1087 0x21820, 0x21828,
1088 0x21830, 0x21848,
1089 0x21850, 0x21854,
1090 0x21860, 0x21868,
1091 0x21870, 0x21870,
1092 0x21878, 0x21898,
1093 0x218a0, 0x218a8,
1094 0x218b0, 0x218c8,
1095 0x218d0, 0x218d4,
1096 0x218e0, 0x218e8,
1097 0x218f0, 0x218f0,
1098 0x218f8, 0x21a18,
1099 0x21a20, 0x21a28,
1100 0x21a30, 0x21a48,
1101 0x21a50, 0x21a54,
1102 0x21a60, 0x21a68,
1103 0x21a70, 0x21a70,
1104 0x21a78, 0x21a98,
1105 0x21aa0, 0x21aa8,
1106 0x21ab0, 0x21ac8,
1107 0x21ad0, 0x21ad4,
1108 0x21ae0, 0x21ae8,
1109 0x21af0, 0x21af0,
1110 0x21af8, 0x21c18,
1111 0x21c20, 0x21c20,
1112 0x21c28, 0x21c30,
1113 0x21c38, 0x21c38,
1114 0x21c80, 0x21c98,
1115 0x21ca0, 0x21ca8,
1116 0x21cb0, 0x21cc8,
1117 0x21cd0, 0x21cd4,
1118 0x21ce0, 0x21ce8,
1119 0x21cf0, 0x21cf0,
1120 0x21cf8, 0x21d7c,
1121 0x21e00, 0x21e04,
1122 0x22000, 0x2202c,
1123 0x22100, 0x2213c,
1124 0x22190, 0x221a0,
1125 0x221a8, 0x221b8,
1126 0x221c4, 0x221c8,
1127 0x22200, 0x22318,
1128 0x22400, 0x224b4,
1129 0x224c0, 0x22528,
1130 0x22540, 0x22614,
1131 0x23000, 0x23040,
1132 0x2304c, 0x23060,
1133 0x230c0, 0x230ec,
1134 0x23200, 0x23268,
1135 0x23270, 0x23284,
1136 0x232fc, 0x23388,
1137 0x23400, 0x23404,
1138 0x23500, 0x23500,
1139 0x23510, 0x23518,
1140 0x2352c, 0x23530,
1141 0x2353c, 0x2353c,
1142 0x23550, 0x23554,
1143 0x23600, 0x23600,
1144 0x23608, 0x2361c,
1145 0x23624, 0x23628,
1146 0x23630, 0x23634,
1147 0x2363c, 0x2363c,
1148 0x23700, 0x2371c,
1149 0x23780, 0x2378c,
1150 0x23800, 0x23818,
1151 0x23820, 0x23828,
1152 0x23830, 0x23848,
1153 0x23850, 0x23854,
1154 0x23860, 0x23868,
1155 0x23870, 0x23870,
1156 0x23878, 0x23898,
1157 0x238a0, 0x238a8,
1158 0x238b0, 0x238c8,
1159 0x238d0, 0x238d4,
1160 0x238e0, 0x238e8,
1161 0x238f0, 0x238f0,
1162 0x238f8, 0x23a18,
1163 0x23a20, 0x23a28,
1164 0x23a30, 0x23a48,
1165 0x23a50, 0x23a54,
1166 0x23a60, 0x23a68,
1167 0x23a70, 0x23a70,
1168 0x23a78, 0x23a98,
1169 0x23aa0, 0x23aa8,
1170 0x23ab0, 0x23ac8,
1171 0x23ad0, 0x23ad4,
1172 0x23ae0, 0x23ae8,
1173 0x23af0, 0x23af0,
1174 0x23af8, 0x23c18,
1175 0x23c20, 0x23c20,
1176 0x23c28, 0x23c30,
1177 0x23c38, 0x23c38,
1178 0x23c80, 0x23c98,
1179 0x23ca0, 0x23ca8,
1180 0x23cb0, 0x23cc8,
1181 0x23cd0, 0x23cd4,
1182 0x23ce0, 0x23ce8,
1183 0x23cf0, 0x23cf0,
1184 0x23cf8, 0x23d7c,
1185 0x23e00, 0x23e04,
1186 0x24000, 0x2402c,
1187 0x24100, 0x2413c,
1188 0x24190, 0x241a0,
1189 0x241a8, 0x241b8,
1190 0x241c4, 0x241c8,
1191 0x24200, 0x24318,
1192 0x24400, 0x244b4,
1193 0x244c0, 0x24528,
1194 0x24540, 0x24614,
1195 0x25000, 0x25040,
1196 0x2504c, 0x25060,
1197 0x250c0, 0x250ec,
1198 0x25200, 0x25268,
1199 0x25270, 0x25284,
1200 0x252fc, 0x25388,
1201 0x25400, 0x25404,
1202 0x25500, 0x25500,
1203 0x25510, 0x25518,
1204 0x2552c, 0x25530,
1205 0x2553c, 0x2553c,
1206 0x25550, 0x25554,
1207 0x25600, 0x25600,
1208 0x25608, 0x2561c,
1209 0x25624, 0x25628,
1210 0x25630, 0x25634,
1211 0x2563c, 0x2563c,
1212 0x25700, 0x2571c,
1213 0x25780, 0x2578c,
1214 0x25800, 0x25818,
1215 0x25820, 0x25828,
1216 0x25830, 0x25848,
1217 0x25850, 0x25854,
1218 0x25860, 0x25868,
1219 0x25870, 0x25870,
1220 0x25878, 0x25898,
1221 0x258a0, 0x258a8,
1222 0x258b0, 0x258c8,
1223 0x258d0, 0x258d4,
1224 0x258e0, 0x258e8,
1225 0x258f0, 0x258f0,
1226 0x258f8, 0x25a18,
1227 0x25a20, 0x25a28,
1228 0x25a30, 0x25a48,
1229 0x25a50, 0x25a54,
1230 0x25a60, 0x25a68,
1231 0x25a70, 0x25a70,
1232 0x25a78, 0x25a98,
1233 0x25aa0, 0x25aa8,
1234 0x25ab0, 0x25ac8,
1235 0x25ad0, 0x25ad4,
1236 0x25ae0, 0x25ae8,
1237 0x25af0, 0x25af0,
1238 0x25af8, 0x25c18,
1239 0x25c20, 0x25c20,
1240 0x25c28, 0x25c30,
1241 0x25c38, 0x25c38,
1242 0x25c80, 0x25c98,
1243 0x25ca0, 0x25ca8,
1244 0x25cb0, 0x25cc8,
1245 0x25cd0, 0x25cd4,
1246 0x25ce0, 0x25ce8,
1247 0x25cf0, 0x25cf0,
1248 0x25cf8, 0x25d7c,
1249 0x25e00, 0x25e04,
1250 0x26000, 0x2602c,
1251 0x26100, 0x2613c,
1252 0x26190, 0x261a0,
1253 0x261a8, 0x261b8,
1254 0x261c4, 0x261c8,
1255 0x26200, 0x26318,
1256 0x26400, 0x264b4,
1257 0x264c0, 0x26528,
1258 0x26540, 0x26614,
1259 0x27000, 0x27040,
1260 0x2704c, 0x27060,
1261 0x270c0, 0x270ec,
1262 0x27200, 0x27268,
1263 0x27270, 0x27284,
1264 0x272fc, 0x27388,
1265 0x27400, 0x27404,
1266 0x27500, 0x27500,
1267 0x27510, 0x27518,
1268 0x2752c, 0x27530,
1269 0x2753c, 0x2753c,
1270 0x27550, 0x27554,
1271 0x27600, 0x27600,
1272 0x27608, 0x2761c,
1273 0x27624, 0x27628,
1274 0x27630, 0x27634,
1275 0x2763c, 0x2763c,
1276 0x27700, 0x2771c,
1277 0x27780, 0x2778c,
1278 0x27800, 0x27818,
1279 0x27820, 0x27828,
1280 0x27830, 0x27848,
1281 0x27850, 0x27854,
1282 0x27860, 0x27868,
1283 0x27870, 0x27870,
1284 0x27878, 0x27898,
1285 0x278a0, 0x278a8,
1286 0x278b0, 0x278c8,
1287 0x278d0, 0x278d4,
1288 0x278e0, 0x278e8,
1289 0x278f0, 0x278f0,
1290 0x278f8, 0x27a18,
1291 0x27a20, 0x27a28,
1292 0x27a30, 0x27a48,
1293 0x27a50, 0x27a54,
1294 0x27a60, 0x27a68,
1295 0x27a70, 0x27a70,
1296 0x27a78, 0x27a98,
1297 0x27aa0, 0x27aa8,
1298 0x27ab0, 0x27ac8,
1299 0x27ad0, 0x27ad4,
1300 0x27ae0, 0x27ae8,
1301 0x27af0, 0x27af0,
1302 0x27af8, 0x27c18,
1303 0x27c20, 0x27c20,
1304 0x27c28, 0x27c30,
1305 0x27c38, 0x27c38,
1306 0x27c80, 0x27c98,
1307 0x27ca0, 0x27ca8,
1308 0x27cb0, 0x27cc8,
1309 0x27cd0, 0x27cd4,
1310 0x27ce0, 0x27ce8,
1311 0x27cf0, 0x27cf0,
1312 0x27cf8, 0x27d7c,
1313 0x27e00, 0x27e04,
1314 };
1315
1316 static const unsigned int t4vf_reg_ranges[] = {
1317 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1318 VF_MPS_REG(A_MPS_VF_CTL),
1319 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1320 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1321 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1322 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1323 FW_T4VF_MBDATA_BASE_ADDR,
1324 FW_T4VF_MBDATA_BASE_ADDR +
1325 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1326 };
1327
1328 static const unsigned int t5_reg_ranges[] = {
1329 0x1008, 0x10c0,
1330 0x10cc, 0x10f8,
1331 0x1100, 0x1100,
1332 0x110c, 0x1148,
1333 0x1180, 0x1184,
1334 0x1190, 0x1194,
1335 0x11a0, 0x11a4,
1336 0x11b0, 0x11b4,
1337 0x11fc, 0x123c,
1338 0x1280, 0x173c,
1339 0x1800, 0x18fc,
1340 0x3000, 0x3028,
1341 0x3060, 0x30b0,
1342 0x30b8, 0x30d8,
1343 0x30e0, 0x30fc,
1344 0x3140, 0x357c,
1345 0x35a8, 0x35cc,
1346 0x35ec, 0x35ec,
1347 0x3600, 0x5624,
1348 0x56cc, 0x56ec,
1349 0x56f4, 0x5720,
1350 0x5728, 0x575c,
1351 0x580c, 0x5814,
1352 0x5890, 0x589c,
1353 0x58a4, 0x58ac,
1354 0x58b8, 0x58bc,
1355 0x5940, 0x59c8,
1356 0x59d0, 0x59dc,
1357 0x59fc, 0x5a18,
1358 0x5a60, 0x5a70,
1359 0x5a80, 0x5a9c,
1360 0x5b94, 0x5bfc,
1361 0x6000, 0x6020,
1362 0x6028, 0x6040,
1363 0x6058, 0x609c,
1364 0x60a8, 0x614c,
1365 0x7700, 0x7798,
1366 0x77c0, 0x78fc,
1367 0x7b00, 0x7b58,
1368 0x7b60, 0x7b84,
1369 0x7b8c, 0x7c54,
1370 0x7d00, 0x7d38,
1371 0x7d40, 0x7d80,
1372 0x7d8c, 0x7ddc,
1373 0x7de4, 0x7e04,
1374 0x7e10, 0x7e1c,
1375 0x7e24, 0x7e38,
1376 0x7e40, 0x7e44,
1377 0x7e4c, 0x7e78,
1378 0x7e80, 0x7edc,
1379 0x7ee8, 0x7efc,
1380 0x8dc0, 0x8de0,
1381 0x8df8, 0x8e04,
1382 0x8e10, 0x8e84,
1383 0x8ea0, 0x8f84,
1384 0x8fc0, 0x9058,
1385 0x9060, 0x9060,
1386 0x9068, 0x90f8,
1387 0x9400, 0x9408,
1388 0x9410, 0x9470,
1389 0x9600, 0x9600,
1390 0x9608, 0x9638,
1391 0x9640, 0x96f4,
1392 0x9800, 0x9808,
1393 0x9810, 0x9864,
1394 0x9c00, 0x9c6c,
1395 0x9c80, 0x9cec,
1396 0x9d00, 0x9d6c,
1397 0x9d80, 0x9dec,
1398 0x9e00, 0x9e6c,
1399 0x9e80, 0x9eec,
1400 0x9f00, 0x9f6c,
1401 0x9f80, 0xa020,
1402 0xd000, 0xd004,
1403 0xd010, 0xd03c,
1404 0xdfc0, 0xdfe0,
1405 0xe000, 0x1106c,
1406 0x11074, 0x11088,
1407 0x1109c, 0x11110,
1408 0x11118, 0x1117c,
1409 0x11190, 0x11204,
1410 0x19040, 0x1906c,
1411 0x19078, 0x19080,
1412 0x1908c, 0x190e8,
1413 0x190f0, 0x190f8,
1414 0x19100, 0x19110,
1415 0x19120, 0x19124,
1416 0x19150, 0x19194,
1417 0x1919c, 0x191b0,
1418 0x191d0, 0x191e8,
1419 0x19238, 0x19290,
1420 0x193f8, 0x19428,
1421 0x19430, 0x19444,
1422 0x1944c, 0x1946c,
1423 0x19474, 0x19474,
1424 0x19490, 0x194cc,
1425 0x194f0, 0x194f8,
1426 0x19c00, 0x19c08,
1427 0x19c10, 0x19c60,
1428 0x19c94, 0x19ce4,
1429 0x19cf0, 0x19d40,
1430 0x19d50, 0x19d94,
1431 0x19da0, 0x19de8,
1432 0x19df0, 0x19e10,
1433 0x19e50, 0x19e90,
1434 0x19ea0, 0x19f24,
1435 0x19f34, 0x19f34,
1436 0x19f40, 0x19f50,
1437 0x19f90, 0x19fb4,
1438 0x19fc4, 0x19fe4,
1439 0x1a000, 0x1a004,
1440 0x1a010, 0x1a06c,
1441 0x1a0b0, 0x1a0e4,
1442 0x1a0ec, 0x1a0f8,
1443 0x1a100, 0x1a108,
1444 0x1a114, 0x1a130,
1445 0x1a138, 0x1a1c4,
1446 0x1a1fc, 0x1a1fc,
1447 0x1e008, 0x1e00c,
1448 0x1e040, 0x1e044,
1449 0x1e04c, 0x1e04c,
1450 0x1e284, 0x1e290,
1451 0x1e2c0, 0x1e2c0,
1452 0x1e2e0, 0x1e2e0,
1453 0x1e300, 0x1e384,
1454 0x1e3c0, 0x1e3c8,
1455 0x1e408, 0x1e40c,
1456 0x1e440, 0x1e444,
1457 0x1e44c, 0x1e44c,
1458 0x1e684, 0x1e690,
1459 0x1e6c0, 0x1e6c0,
1460 0x1e6e0, 0x1e6e0,
1461 0x1e700, 0x1e784,
1462 0x1e7c0, 0x1e7c8,
1463 0x1e808, 0x1e80c,
1464 0x1e840, 0x1e844,
1465 0x1e84c, 0x1e84c,
1466 0x1ea84, 0x1ea90,
1467 0x1eac0, 0x1eac0,
1468 0x1eae0, 0x1eae0,
1469 0x1eb00, 0x1eb84,
1470 0x1ebc0, 0x1ebc8,
1471 0x1ec08, 0x1ec0c,
1472 0x1ec40, 0x1ec44,
1473 0x1ec4c, 0x1ec4c,
1474 0x1ee84, 0x1ee90,
1475 0x1eec0, 0x1eec0,
1476 0x1eee0, 0x1eee0,
1477 0x1ef00, 0x1ef84,
1478 0x1efc0, 0x1efc8,
1479 0x1f008, 0x1f00c,
1480 0x1f040, 0x1f044,
1481 0x1f04c, 0x1f04c,
1482 0x1f284, 0x1f290,
1483 0x1f2c0, 0x1f2c0,
1484 0x1f2e0, 0x1f2e0,
1485 0x1f300, 0x1f384,
1486 0x1f3c0, 0x1f3c8,
1487 0x1f408, 0x1f40c,
1488 0x1f440, 0x1f444,
1489 0x1f44c, 0x1f44c,
1490 0x1f684, 0x1f690,
1491 0x1f6c0, 0x1f6c0,
1492 0x1f6e0, 0x1f6e0,
1493 0x1f700, 0x1f784,
1494 0x1f7c0, 0x1f7c8,
1495 0x1f808, 0x1f80c,
1496 0x1f840, 0x1f844,
1497 0x1f84c, 0x1f84c,
1498 0x1fa84, 0x1fa90,
1499 0x1fac0, 0x1fac0,
1500 0x1fae0, 0x1fae0,
1501 0x1fb00, 0x1fb84,
1502 0x1fbc0, 0x1fbc8,
1503 0x1fc08, 0x1fc0c,
1504 0x1fc40, 0x1fc44,
1505 0x1fc4c, 0x1fc4c,
1506 0x1fe84, 0x1fe90,
1507 0x1fec0, 0x1fec0,
1508 0x1fee0, 0x1fee0,
1509 0x1ff00, 0x1ff84,
1510 0x1ffc0, 0x1ffc8,
1511 0x30000, 0x30030,
1512 0x30100, 0x30144,
1513 0x30190, 0x301a0,
1514 0x301a8, 0x301b8,
1515 0x301c4, 0x301c8,
1516 0x301d0, 0x301d0,
1517 0x30200, 0x30318,
1518 0x30400, 0x304b4,
1519 0x304c0, 0x3052c,
1520 0x30540, 0x3061c,
1521 0x30800, 0x30828,
1522 0x30834, 0x30834,
1523 0x308c0, 0x30908,
1524 0x30910, 0x309ac,
1525 0x30a00, 0x30a14,
1526 0x30a1c, 0x30a2c,
1527 0x30a44, 0x30a50,
1528 0x30a74, 0x30a74,
1529 0x30a7c, 0x30afc,
1530 0x30b08, 0x30c24,
1531 0x30d00, 0x30d00,
1532 0x30d08, 0x30d14,
1533 0x30d1c, 0x30d20,
1534 0x30d3c, 0x30d3c,
1535 0x30d48, 0x30d50,
1536 0x31200, 0x3120c,
1537 0x31220, 0x31220,
1538 0x31240, 0x31240,
1539 0x31600, 0x3160c,
1540 0x31a00, 0x31a1c,
1541 0x31e00, 0x31e20,
1542 0x31e38, 0x31e3c,
1543 0x31e80, 0x31e80,
1544 0x31e88, 0x31ea8,
1545 0x31eb0, 0x31eb4,
1546 0x31ec8, 0x31ed4,
1547 0x31fb8, 0x32004,
1548 0x32200, 0x32200,
1549 0x32208, 0x32240,
1550 0x32248, 0x32280,
1551 0x32288, 0x322c0,
1552 0x322c8, 0x322fc,
1553 0x32600, 0x32630,
1554 0x32a00, 0x32abc,
1555 0x32b00, 0x32b10,
1556 0x32b20, 0x32b30,
1557 0x32b40, 0x32b50,
1558 0x32b60, 0x32b70,
1559 0x33000, 0x33028,
1560 0x33030, 0x33048,
1561 0x33060, 0x33068,
1562 0x33070, 0x3309c,
1563 0x330f0, 0x33128,
1564 0x33130, 0x33148,
1565 0x33160, 0x33168,
1566 0x33170, 0x3319c,
1567 0x331f0, 0x33238,
1568 0x33240, 0x33240,
1569 0x33248, 0x33250,
1570 0x3325c, 0x33264,
1571 0x33270, 0x332b8,
1572 0x332c0, 0x332e4,
1573 0x332f8, 0x33338,
1574 0x33340, 0x33340,
1575 0x33348, 0x33350,
1576 0x3335c, 0x33364,
1577 0x33370, 0x333b8,
1578 0x333c0, 0x333e4,
1579 0x333f8, 0x33428,
1580 0x33430, 0x33448,
1581 0x33460, 0x33468,
1582 0x33470, 0x3349c,
1583 0x334f0, 0x33528,
1584 0x33530, 0x33548,
1585 0x33560, 0x33568,
1586 0x33570, 0x3359c,
1587 0x335f0, 0x33638,
1588 0x33640, 0x33640,
1589 0x33648, 0x33650,
1590 0x3365c, 0x33664,
1591 0x33670, 0x336b8,
1592 0x336c0, 0x336e4,
1593 0x336f8, 0x33738,
1594 0x33740, 0x33740,
1595 0x33748, 0x33750,
1596 0x3375c, 0x33764,
1597 0x33770, 0x337b8,
1598 0x337c0, 0x337e4,
1599 0x337f8, 0x337fc,
1600 0x33814, 0x33814,
1601 0x3382c, 0x3382c,
1602 0x33880, 0x3388c,
1603 0x338e8, 0x338ec,
1604 0x33900, 0x33928,
1605 0x33930, 0x33948,
1606 0x33960, 0x33968,
1607 0x33970, 0x3399c,
1608 0x339f0, 0x33a38,
1609 0x33a40, 0x33a40,
1610 0x33a48, 0x33a50,
1611 0x33a5c, 0x33a64,
1612 0x33a70, 0x33ab8,
1613 0x33ac0, 0x33ae4,
1614 0x33af8, 0x33b10,
1615 0x33b28, 0x33b28,
1616 0x33b3c, 0x33b50,
1617 0x33bf0, 0x33c10,
1618 0x33c28, 0x33c28,
1619 0x33c3c, 0x33c50,
1620 0x33cf0, 0x33cfc,
1621 0x34000, 0x34030,
1622 0x34100, 0x34144,
1623 0x34190, 0x341a0,
1624 0x341a8, 0x341b8,
1625 0x341c4, 0x341c8,
1626 0x341d0, 0x341d0,
1627 0x34200, 0x34318,
1628 0x34400, 0x344b4,
1629 0x344c0, 0x3452c,
1630 0x34540, 0x3461c,
1631 0x34800, 0x34828,
1632 0x34834, 0x34834,
1633 0x348c0, 0x34908,
1634 0x34910, 0x349ac,
1635 0x34a00, 0x34a14,
1636 0x34a1c, 0x34a2c,
1637 0x34a44, 0x34a50,
1638 0x34a74, 0x34a74,
1639 0x34a7c, 0x34afc,
1640 0x34b08, 0x34c24,
1641 0x34d00, 0x34d00,
1642 0x34d08, 0x34d14,
1643 0x34d1c, 0x34d20,
1644 0x34d3c, 0x34d3c,
1645 0x34d48, 0x34d50,
1646 0x35200, 0x3520c,
1647 0x35220, 0x35220,
1648 0x35240, 0x35240,
1649 0x35600, 0x3560c,
1650 0x35a00, 0x35a1c,
1651 0x35e00, 0x35e20,
1652 0x35e38, 0x35e3c,
1653 0x35e80, 0x35e80,
1654 0x35e88, 0x35ea8,
1655 0x35eb0, 0x35eb4,
1656 0x35ec8, 0x35ed4,
1657 0x35fb8, 0x36004,
1658 0x36200, 0x36200,
1659 0x36208, 0x36240,
1660 0x36248, 0x36280,
1661 0x36288, 0x362c0,
1662 0x362c8, 0x362fc,
1663 0x36600, 0x36630,
1664 0x36a00, 0x36abc,
1665 0x36b00, 0x36b10,
1666 0x36b20, 0x36b30,
1667 0x36b40, 0x36b50,
1668 0x36b60, 0x36b70,
1669 0x37000, 0x37028,
1670 0x37030, 0x37048,
1671 0x37060, 0x37068,
1672 0x37070, 0x3709c,
1673 0x370f0, 0x37128,
1674 0x37130, 0x37148,
1675 0x37160, 0x37168,
1676 0x37170, 0x3719c,
1677 0x371f0, 0x37238,
1678 0x37240, 0x37240,
1679 0x37248, 0x37250,
1680 0x3725c, 0x37264,
1681 0x37270, 0x372b8,
1682 0x372c0, 0x372e4,
1683 0x372f8, 0x37338,
1684 0x37340, 0x37340,
1685 0x37348, 0x37350,
1686 0x3735c, 0x37364,
1687 0x37370, 0x373b8,
1688 0x373c0, 0x373e4,
1689 0x373f8, 0x37428,
1690 0x37430, 0x37448,
1691 0x37460, 0x37468,
1692 0x37470, 0x3749c,
1693 0x374f0, 0x37528,
1694 0x37530, 0x37548,
1695 0x37560, 0x37568,
1696 0x37570, 0x3759c,
1697 0x375f0, 0x37638,
1698 0x37640, 0x37640,
1699 0x37648, 0x37650,
1700 0x3765c, 0x37664,
1701 0x37670, 0x376b8,
1702 0x376c0, 0x376e4,
1703 0x376f8, 0x37738,
1704 0x37740, 0x37740,
1705 0x37748, 0x37750,
1706 0x3775c, 0x37764,
1707 0x37770, 0x377b8,
1708 0x377c0, 0x377e4,
1709 0x377f8, 0x377fc,
1710 0x37814, 0x37814,
1711 0x3782c, 0x3782c,
1712 0x37880, 0x3788c,
1713 0x378e8, 0x378ec,
1714 0x37900, 0x37928,
1715 0x37930, 0x37948,
1716 0x37960, 0x37968,
1717 0x37970, 0x3799c,
1718 0x379f0, 0x37a38,
1719 0x37a40, 0x37a40,
1720 0x37a48, 0x37a50,
1721 0x37a5c, 0x37a64,
1722 0x37a70, 0x37ab8,
1723 0x37ac0, 0x37ae4,
1724 0x37af8, 0x37b10,
1725 0x37b28, 0x37b28,
1726 0x37b3c, 0x37b50,
1727 0x37bf0, 0x37c10,
1728 0x37c28, 0x37c28,
1729 0x37c3c, 0x37c50,
1730 0x37cf0, 0x37cfc,
1731 0x38000, 0x38030,
1732 0x38100, 0x38144,
1733 0x38190, 0x381a0,
1734 0x381a8, 0x381b8,
1735 0x381c4, 0x381c8,
1736 0x381d0, 0x381d0,
1737 0x38200, 0x38318,
1738 0x38400, 0x384b4,
1739 0x384c0, 0x3852c,
1740 0x38540, 0x3861c,
1741 0x38800, 0x38828,
1742 0x38834, 0x38834,
1743 0x388c0, 0x38908,
1744 0x38910, 0x389ac,
1745 0x38a00, 0x38a14,
1746 0x38a1c, 0x38a2c,
1747 0x38a44, 0x38a50,
1748 0x38a74, 0x38a74,
1749 0x38a7c, 0x38afc,
1750 0x38b08, 0x38c24,
1751 0x38d00, 0x38d00,
1752 0x38d08, 0x38d14,
1753 0x38d1c, 0x38d20,
1754 0x38d3c, 0x38d3c,
1755 0x38d48, 0x38d50,
1756 0x39200, 0x3920c,
1757 0x39220, 0x39220,
1758 0x39240, 0x39240,
1759 0x39600, 0x3960c,
1760 0x39a00, 0x39a1c,
1761 0x39e00, 0x39e20,
1762 0x39e38, 0x39e3c,
1763 0x39e80, 0x39e80,
1764 0x39e88, 0x39ea8,
1765 0x39eb0, 0x39eb4,
1766 0x39ec8, 0x39ed4,
1767 0x39fb8, 0x3a004,
1768 0x3a200, 0x3a200,
1769 0x3a208, 0x3a240,
1770 0x3a248, 0x3a280,
1771 0x3a288, 0x3a2c0,
1772 0x3a2c8, 0x3a2fc,
1773 0x3a600, 0x3a630,
1774 0x3aa00, 0x3aabc,
1775 0x3ab00, 0x3ab10,
1776 0x3ab20, 0x3ab30,
1777 0x3ab40, 0x3ab50,
1778 0x3ab60, 0x3ab70,
1779 0x3b000, 0x3b028,
1780 0x3b030, 0x3b048,
1781 0x3b060, 0x3b068,
1782 0x3b070, 0x3b09c,
1783 0x3b0f0, 0x3b128,
1784 0x3b130, 0x3b148,
1785 0x3b160, 0x3b168,
1786 0x3b170, 0x3b19c,
1787 0x3b1f0, 0x3b238,
1788 0x3b240, 0x3b240,
1789 0x3b248, 0x3b250,
1790 0x3b25c, 0x3b264,
1791 0x3b270, 0x3b2b8,
1792 0x3b2c0, 0x3b2e4,
1793 0x3b2f8, 0x3b338,
1794 0x3b340, 0x3b340,
1795 0x3b348, 0x3b350,
1796 0x3b35c, 0x3b364,
1797 0x3b370, 0x3b3b8,
1798 0x3b3c0, 0x3b3e4,
1799 0x3b3f8, 0x3b428,
1800 0x3b430, 0x3b448,
1801 0x3b460, 0x3b468,
1802 0x3b470, 0x3b49c,
1803 0x3b4f0, 0x3b528,
1804 0x3b530, 0x3b548,
1805 0x3b560, 0x3b568,
1806 0x3b570, 0x3b59c,
1807 0x3b5f0, 0x3b638,
1808 0x3b640, 0x3b640,
1809 0x3b648, 0x3b650,
1810 0x3b65c, 0x3b664,
1811 0x3b670, 0x3b6b8,
1812 0x3b6c0, 0x3b6e4,
1813 0x3b6f8, 0x3b738,
1814 0x3b740, 0x3b740,
1815 0x3b748, 0x3b750,
1816 0x3b75c, 0x3b764,
1817 0x3b770, 0x3b7b8,
1818 0x3b7c0, 0x3b7e4,
1819 0x3b7f8, 0x3b7fc,
1820 0x3b814, 0x3b814,
1821 0x3b82c, 0x3b82c,
1822 0x3b880, 0x3b88c,
1823 0x3b8e8, 0x3b8ec,
1824 0x3b900, 0x3b928,
1825 0x3b930, 0x3b948,
1826 0x3b960, 0x3b968,
1827 0x3b970, 0x3b99c,
1828 0x3b9f0, 0x3ba38,
1829 0x3ba40, 0x3ba40,
1830 0x3ba48, 0x3ba50,
1831 0x3ba5c, 0x3ba64,
1832 0x3ba70, 0x3bab8,
1833 0x3bac0, 0x3bae4,
1834 0x3baf8, 0x3bb10,
1835 0x3bb28, 0x3bb28,
1836 0x3bb3c, 0x3bb50,
1837 0x3bbf0, 0x3bc10,
1838 0x3bc28, 0x3bc28,
1839 0x3bc3c, 0x3bc50,
1840 0x3bcf0, 0x3bcfc,
1841 0x3c000, 0x3c030,
1842 0x3c100, 0x3c144,
1843 0x3c190, 0x3c1a0,
1844 0x3c1a8, 0x3c1b8,
1845 0x3c1c4, 0x3c1c8,
1846 0x3c1d0, 0x3c1d0,
1847 0x3c200, 0x3c318,
1848 0x3c400, 0x3c4b4,
1849 0x3c4c0, 0x3c52c,
1850 0x3c540, 0x3c61c,
1851 0x3c800, 0x3c828,
1852 0x3c834, 0x3c834,
1853 0x3c8c0, 0x3c908,
1854 0x3c910, 0x3c9ac,
1855 0x3ca00, 0x3ca14,
1856 0x3ca1c, 0x3ca2c,
1857 0x3ca44, 0x3ca50,
1858 0x3ca74, 0x3ca74,
1859 0x3ca7c, 0x3cafc,
1860 0x3cb08, 0x3cc24,
1861 0x3cd00, 0x3cd00,
1862 0x3cd08, 0x3cd14,
1863 0x3cd1c, 0x3cd20,
1864 0x3cd3c, 0x3cd3c,
1865 0x3cd48, 0x3cd50,
1866 0x3d200, 0x3d20c,
1867 0x3d220, 0x3d220,
1868 0x3d240, 0x3d240,
1869 0x3d600, 0x3d60c,
1870 0x3da00, 0x3da1c,
1871 0x3de00, 0x3de20,
1872 0x3de38, 0x3de3c,
1873 0x3de80, 0x3de80,
1874 0x3de88, 0x3dea8,
1875 0x3deb0, 0x3deb4,
1876 0x3dec8, 0x3ded4,
1877 0x3dfb8, 0x3e004,
1878 0x3e200, 0x3e200,
1879 0x3e208, 0x3e240,
1880 0x3e248, 0x3e280,
1881 0x3e288, 0x3e2c0,
1882 0x3e2c8, 0x3e2fc,
1883 0x3e600, 0x3e630,
1884 0x3ea00, 0x3eabc,
1885 0x3eb00, 0x3eb10,
1886 0x3eb20, 0x3eb30,
1887 0x3eb40, 0x3eb50,
1888 0x3eb60, 0x3eb70,
1889 0x3f000, 0x3f028,
1890 0x3f030, 0x3f048,
1891 0x3f060, 0x3f068,
1892 0x3f070, 0x3f09c,
1893 0x3f0f0, 0x3f128,
1894 0x3f130, 0x3f148,
1895 0x3f160, 0x3f168,
1896 0x3f170, 0x3f19c,
1897 0x3f1f0, 0x3f238,
1898 0x3f240, 0x3f240,
1899 0x3f248, 0x3f250,
1900 0x3f25c, 0x3f264,
1901 0x3f270, 0x3f2b8,
1902 0x3f2c0, 0x3f2e4,
1903 0x3f2f8, 0x3f338,
1904 0x3f340, 0x3f340,
1905 0x3f348, 0x3f350,
1906 0x3f35c, 0x3f364,
1907 0x3f370, 0x3f3b8,
1908 0x3f3c0, 0x3f3e4,
1909 0x3f3f8, 0x3f428,
1910 0x3f430, 0x3f448,
1911 0x3f460, 0x3f468,
1912 0x3f470, 0x3f49c,
1913 0x3f4f0, 0x3f528,
1914 0x3f530, 0x3f548,
1915 0x3f560, 0x3f568,
1916 0x3f570, 0x3f59c,
1917 0x3f5f0, 0x3f638,
1918 0x3f640, 0x3f640,
1919 0x3f648, 0x3f650,
1920 0x3f65c, 0x3f664,
1921 0x3f670, 0x3f6b8,
1922 0x3f6c0, 0x3f6e4,
1923 0x3f6f8, 0x3f738,
1924 0x3f740, 0x3f740,
1925 0x3f748, 0x3f750,
1926 0x3f75c, 0x3f764,
1927 0x3f770, 0x3f7b8,
1928 0x3f7c0, 0x3f7e4,
1929 0x3f7f8, 0x3f7fc,
1930 0x3f814, 0x3f814,
1931 0x3f82c, 0x3f82c,
1932 0x3f880, 0x3f88c,
1933 0x3f8e8, 0x3f8ec,
1934 0x3f900, 0x3f928,
1935 0x3f930, 0x3f948,
1936 0x3f960, 0x3f968,
1937 0x3f970, 0x3f99c,
1938 0x3f9f0, 0x3fa38,
1939 0x3fa40, 0x3fa40,
1940 0x3fa48, 0x3fa50,
1941 0x3fa5c, 0x3fa64,
1942 0x3fa70, 0x3fab8,
1943 0x3fac0, 0x3fae4,
1944 0x3faf8, 0x3fb10,
1945 0x3fb28, 0x3fb28,
1946 0x3fb3c, 0x3fb50,
1947 0x3fbf0, 0x3fc10,
1948 0x3fc28, 0x3fc28,
1949 0x3fc3c, 0x3fc50,
1950 0x3fcf0, 0x3fcfc,
1951 0x40000, 0x4000c,
1952 0x40040, 0x40050,
1953 0x40060, 0x40068,
1954 0x4007c, 0x4008c,
1955 0x40094, 0x400b0,
1956 0x400c0, 0x40144,
1957 0x40180, 0x4018c,
1958 0x40200, 0x40254,
1959 0x40260, 0x40264,
1960 0x40270, 0x40288,
1961 0x40290, 0x40298,
1962 0x402ac, 0x402c8,
1963 0x402d0, 0x402e0,
1964 0x402f0, 0x402f0,
1965 0x40300, 0x4033c,
1966 0x403f8, 0x403fc,
1967 0x41304, 0x413c4,
1968 0x41400, 0x4140c,
1969 0x41414, 0x4141c,
1970 0x41480, 0x414d0,
1971 0x44000, 0x44054,
1972 0x4405c, 0x44078,
1973 0x440c0, 0x44174,
1974 0x44180, 0x441ac,
1975 0x441b4, 0x441b8,
1976 0x441c0, 0x44254,
1977 0x4425c, 0x44278,
1978 0x442c0, 0x44374,
1979 0x44380, 0x443ac,
1980 0x443b4, 0x443b8,
1981 0x443c0, 0x44454,
1982 0x4445c, 0x44478,
1983 0x444c0, 0x44574,
1984 0x44580, 0x445ac,
1985 0x445b4, 0x445b8,
1986 0x445c0, 0x44654,
1987 0x4465c, 0x44678,
1988 0x446c0, 0x44774,
1989 0x44780, 0x447ac,
1990 0x447b4, 0x447b8,
1991 0x447c0, 0x44854,
1992 0x4485c, 0x44878,
1993 0x448c0, 0x44974,
1994 0x44980, 0x449ac,
1995 0x449b4, 0x449b8,
1996 0x449c0, 0x449fc,
1997 0x45000, 0x45004,
1998 0x45010, 0x45030,
1999 0x45040, 0x45060,
2000 0x45068, 0x45068,
2001 0x45080, 0x45084,
2002 0x450a0, 0x450b0,
2003 0x45200, 0x45204,
2004 0x45210, 0x45230,
2005 0x45240, 0x45260,
2006 0x45268, 0x45268,
2007 0x45280, 0x45284,
2008 0x452a0, 0x452b0,
2009 0x460c0, 0x460e4,
2010 0x47000, 0x4703c,
2011 0x47044, 0x4708c,
2012 0x47200, 0x47250,
2013 0x47400, 0x47408,
2014 0x47414, 0x47420,
2015 0x47600, 0x47618,
2016 0x47800, 0x47814,
2017 0x48000, 0x4800c,
2018 0x48040, 0x48050,
2019 0x48060, 0x48068,
2020 0x4807c, 0x4808c,
2021 0x48094, 0x480b0,
2022 0x480c0, 0x48144,
2023 0x48180, 0x4818c,
2024 0x48200, 0x48254,
2025 0x48260, 0x48264,
2026 0x48270, 0x48288,
2027 0x48290, 0x48298,
2028 0x482ac, 0x482c8,
2029 0x482d0, 0x482e0,
2030 0x482f0, 0x482f0,
2031 0x48300, 0x4833c,
2032 0x483f8, 0x483fc,
2033 0x49304, 0x493c4,
2034 0x49400, 0x4940c,
2035 0x49414, 0x4941c,
2036 0x49480, 0x494d0,
2037 0x4c000, 0x4c054,
2038 0x4c05c, 0x4c078,
2039 0x4c0c0, 0x4c174,
2040 0x4c180, 0x4c1ac,
2041 0x4c1b4, 0x4c1b8,
2042 0x4c1c0, 0x4c254,
2043 0x4c25c, 0x4c278,
2044 0x4c2c0, 0x4c374,
2045 0x4c380, 0x4c3ac,
2046 0x4c3b4, 0x4c3b8,
2047 0x4c3c0, 0x4c454,
2048 0x4c45c, 0x4c478,
2049 0x4c4c0, 0x4c574,
2050 0x4c580, 0x4c5ac,
2051 0x4c5b4, 0x4c5b8,
2052 0x4c5c0, 0x4c654,
2053 0x4c65c, 0x4c678,
2054 0x4c6c0, 0x4c774,
2055 0x4c780, 0x4c7ac,
2056 0x4c7b4, 0x4c7b8,
2057 0x4c7c0, 0x4c854,
2058 0x4c85c, 0x4c878,
2059 0x4c8c0, 0x4c974,
2060 0x4c980, 0x4c9ac,
2061 0x4c9b4, 0x4c9b8,
2062 0x4c9c0, 0x4c9fc,
2063 0x4d000, 0x4d004,
2064 0x4d010, 0x4d030,
2065 0x4d040, 0x4d060,
2066 0x4d068, 0x4d068,
2067 0x4d080, 0x4d084,
2068 0x4d0a0, 0x4d0b0,
2069 0x4d200, 0x4d204,
2070 0x4d210, 0x4d230,
2071 0x4d240, 0x4d260,
2072 0x4d268, 0x4d268,
2073 0x4d280, 0x4d284,
2074 0x4d2a0, 0x4d2b0,
2075 0x4e0c0, 0x4e0e4,
2076 0x4f000, 0x4f03c,
2077 0x4f044, 0x4f08c,
2078 0x4f200, 0x4f250,
2079 0x4f400, 0x4f408,
2080 0x4f414, 0x4f420,
2081 0x4f600, 0x4f618,
2082 0x4f800, 0x4f814,
2083 0x50000, 0x50084,
2084 0x50090, 0x500cc,
2085 0x50400, 0x50400,
2086 0x50800, 0x50884,
2087 0x50890, 0x508cc,
2088 0x50c00, 0x50c00,
2089 0x51000, 0x5101c,
2090 0x51300, 0x51308,
2091 };
2092
2093 static const unsigned int t5vf_reg_ranges[] = {
2094 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2095 VF_MPS_REG(A_MPS_VF_CTL),
2096 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2097 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2098 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2099 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2100 FW_T4VF_MBDATA_BASE_ADDR,
2101 FW_T4VF_MBDATA_BASE_ADDR +
2102 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2103 };
2104
2105 static const unsigned int t6_reg_ranges[] = {
2106 0x1008, 0x101c,
2107 0x1024, 0x10a8,
2108 0x10b4, 0x10f8,
2109 0x1100, 0x1114,
2110 0x111c, 0x112c,
2111 0x1138, 0x113c,
2112 0x1144, 0x114c,
2113 0x1180, 0x1184,
2114 0x1190, 0x1194,
2115 0x11a0, 0x11a4,
2116 0x11b0, 0x11c4,
2117 0x11fc, 0x123c,
2118 0x1254, 0x1274,
2119 0x1280, 0x133c,
2120 0x1800, 0x18fc,
2121 0x3000, 0x302c,
2122 0x3060, 0x30b0,
2123 0x30b8, 0x30d8,
2124 0x30e0, 0x30fc,
2125 0x3140, 0x357c,
2126 0x35a8, 0x35cc,
2127 0x35ec, 0x35ec,
2128 0x3600, 0x5624,
2129 0x56cc, 0x56ec,
2130 0x56f4, 0x5720,
2131 0x5728, 0x575c,
2132 0x580c, 0x5814,
2133 0x5890, 0x589c,
2134 0x58a4, 0x58ac,
2135 0x58b8, 0x58bc,
2136 0x5940, 0x595c,
2137 0x5980, 0x598c,
2138 0x59b0, 0x59c8,
2139 0x59d0, 0x59dc,
2140 0x59fc, 0x5a18,
2141 0x5a60, 0x5a6c,
2142 0x5a80, 0x5a8c,
2143 0x5a94, 0x5a9c,
2144 0x5b94, 0x5bfc,
2145 0x5c10, 0x5e48,
2146 0x5e50, 0x5e94,
2147 0x5ea0, 0x5eb0,
2148 0x5ec0, 0x5ec0,
2149 0x5ec8, 0x5ed0,
2150 0x5ee0, 0x5ee0,
2151 0x5ef0, 0x5ef0,
2152 0x5f00, 0x5f00,
2153 0x6000, 0x6020,
2154 0x6028, 0x6040,
2155 0x6058, 0x609c,
2156 0x60a8, 0x619c,
2157 0x7700, 0x7798,
2158 0x77c0, 0x7880,
2159 0x78cc, 0x78fc,
2160 0x7b00, 0x7b58,
2161 0x7b60, 0x7b84,
2162 0x7b8c, 0x7c54,
2163 0x7d00, 0x7d38,
2164 0x7d40, 0x7d84,
2165 0x7d8c, 0x7ddc,
2166 0x7de4, 0x7e04,
2167 0x7e10, 0x7e1c,
2168 0x7e24, 0x7e38,
2169 0x7e40, 0x7e44,
2170 0x7e4c, 0x7e78,
2171 0x7e80, 0x7edc,
2172 0x7ee8, 0x7efc,
2173 0x8dc0, 0x8de0,
2174 0x8df8, 0x8e04,
2175 0x8e10, 0x8e84,
2176 0x8ea0, 0x8f88,
2177 0x8fb8, 0x9058,
2178 0x9060, 0x9060,
2179 0x9068, 0x90f8,
2180 0x9100, 0x9124,
2181 0x9400, 0x9470,
2182 0x9600, 0x9600,
2183 0x9608, 0x9638,
2184 0x9640, 0x9704,
2185 0x9710, 0x971c,
2186 0x9800, 0x9808,
2187 0x9810, 0x9864,
2188 0x9c00, 0x9c6c,
2189 0x9c80, 0x9cec,
2190 0x9d00, 0x9d6c,
2191 0x9d80, 0x9dec,
2192 0x9e00, 0x9e6c,
2193 0x9e80, 0x9eec,
2194 0x9f00, 0x9f6c,
2195 0x9f80, 0xa020,
2196 0xd000, 0xd03c,
2197 0xd100, 0xd118,
2198 0xd200, 0xd214,
2199 0xd220, 0xd234,
2200 0xd240, 0xd254,
2201 0xd260, 0xd274,
2202 0xd280, 0xd294,
2203 0xd2a0, 0xd2b4,
2204 0xd2c0, 0xd2d4,
2205 0xd2e0, 0xd2f4,
2206 0xd300, 0xd31c,
2207 0xdfc0, 0xdfe0,
2208 0xe000, 0xf008,
2209 0xf010, 0xf018,
2210 0xf020, 0xf028,
2211 0x11000, 0x11014,
2212 0x11048, 0x1106c,
2213 0x11074, 0x11088,
2214 0x11098, 0x11120,
2215 0x1112c, 0x1117c,
2216 0x11190, 0x112e0,
2217 0x11300, 0x1130c,
2218 0x12000, 0x1206c,
2219 0x19040, 0x1906c,
2220 0x19078, 0x19080,
2221 0x1908c, 0x190e8,
2222 0x190f0, 0x190f8,
2223 0x19100, 0x19110,
2224 0x19120, 0x19124,
2225 0x19150, 0x19194,
2226 0x1919c, 0x191b0,
2227 0x191d0, 0x191e8,
2228 0x19238, 0x19290,
2229 0x192a4, 0x192b0,
2230 0x19348, 0x1934c,
2231 0x193f8, 0x19418,
2232 0x19420, 0x19428,
2233 0x19430, 0x19444,
2234 0x1944c, 0x1946c,
2235 0x19474, 0x19474,
2236 0x19490, 0x194cc,
2237 0x194f0, 0x194f8,
2238 0x19c00, 0x19c48,
2239 0x19c50, 0x19c80,
2240 0x19c94, 0x19c98,
2241 0x19ca0, 0x19cbc,
2242 0x19ce4, 0x19ce4,
2243 0x19cf0, 0x19cf8,
2244 0x19d00, 0x19d28,
2245 0x19d50, 0x19d78,
2246 0x19d94, 0x19d98,
2247 0x19da0, 0x19de0,
2248 0x19df0, 0x19e10,
2249 0x19e50, 0x19e6c,
2250 0x19ea0, 0x19ebc,
2251 0x19ec4, 0x19ef4,
2252 0x19f04, 0x19f2c,
2253 0x19f34, 0x19f34,
2254 0x19f40, 0x19f50,
2255 0x19f90, 0x19fac,
2256 0x19fc4, 0x19fc8,
2257 0x19fd0, 0x19fe4,
2258 0x1a000, 0x1a004,
2259 0x1a010, 0x1a06c,
2260 0x1a0b0, 0x1a0e4,
2261 0x1a0ec, 0x1a0f8,
2262 0x1a100, 0x1a108,
2263 0x1a114, 0x1a130,
2264 0x1a138, 0x1a1c4,
2265 0x1a1fc, 0x1a1fc,
2266 0x1e008, 0x1e00c,
2267 0x1e040, 0x1e044,
2268 0x1e04c, 0x1e04c,
2269 0x1e284, 0x1e290,
2270 0x1e2c0, 0x1e2c0,
2271 0x1e2e0, 0x1e2e0,
2272 0x1e300, 0x1e384,
2273 0x1e3c0, 0x1e3c8,
2274 0x1e408, 0x1e40c,
2275 0x1e440, 0x1e444,
2276 0x1e44c, 0x1e44c,
2277 0x1e684, 0x1e690,
2278 0x1e6c0, 0x1e6c0,
2279 0x1e6e0, 0x1e6e0,
2280 0x1e700, 0x1e784,
2281 0x1e7c0, 0x1e7c8,
2282 0x1e808, 0x1e80c,
2283 0x1e840, 0x1e844,
2284 0x1e84c, 0x1e84c,
2285 0x1ea84, 0x1ea90,
2286 0x1eac0, 0x1eac0,
2287 0x1eae0, 0x1eae0,
2288 0x1eb00, 0x1eb84,
2289 0x1ebc0, 0x1ebc8,
2290 0x1ec08, 0x1ec0c,
2291 0x1ec40, 0x1ec44,
2292 0x1ec4c, 0x1ec4c,
2293 0x1ee84, 0x1ee90,
2294 0x1eec0, 0x1eec0,
2295 0x1eee0, 0x1eee0,
2296 0x1ef00, 0x1ef84,
2297 0x1efc0, 0x1efc8,
2298 0x1f008, 0x1f00c,
2299 0x1f040, 0x1f044,
2300 0x1f04c, 0x1f04c,
2301 0x1f284, 0x1f290,
2302 0x1f2c0, 0x1f2c0,
2303 0x1f2e0, 0x1f2e0,
2304 0x1f300, 0x1f384,
2305 0x1f3c0, 0x1f3c8,
2306 0x1f408, 0x1f40c,
2307 0x1f440, 0x1f444,
2308 0x1f44c, 0x1f44c,
2309 0x1f684, 0x1f690,
2310 0x1f6c0, 0x1f6c0,
2311 0x1f6e0, 0x1f6e0,
2312 0x1f700, 0x1f784,
2313 0x1f7c0, 0x1f7c8,
2314 0x1f808, 0x1f80c,
2315 0x1f840, 0x1f844,
2316 0x1f84c, 0x1f84c,
2317 0x1fa84, 0x1fa90,
2318 0x1fac0, 0x1fac0,
2319 0x1fae0, 0x1fae0,
2320 0x1fb00, 0x1fb84,
2321 0x1fbc0, 0x1fbc8,
2322 0x1fc08, 0x1fc0c,
2323 0x1fc40, 0x1fc44,
2324 0x1fc4c, 0x1fc4c,
2325 0x1fe84, 0x1fe90,
2326 0x1fec0, 0x1fec0,
2327 0x1fee0, 0x1fee0,
2328 0x1ff00, 0x1ff84,
2329 0x1ffc0, 0x1ffc8,
2330 0x30000, 0x30030,
2331 0x30100, 0x30168,
2332 0x30190, 0x301a0,
2333 0x301a8, 0x301b8,
2334 0x301c4, 0x301c8,
2335 0x301d0, 0x301d0,
2336 0x30200, 0x30320,
2337 0x30400, 0x304b4,
2338 0x304c0, 0x3052c,
2339 0x30540, 0x3061c,
2340 0x30800, 0x308a0,
2341 0x308c0, 0x30908,
2342 0x30910, 0x309b8,
2343 0x30a00, 0x30a04,
2344 0x30a0c, 0x30a14,
2345 0x30a1c, 0x30a2c,
2346 0x30a44, 0x30a50,
2347 0x30a74, 0x30a74,
2348 0x30a7c, 0x30afc,
2349 0x30b08, 0x30c24,
2350 0x30d00, 0x30d14,
2351 0x30d1c, 0x30d3c,
2352 0x30d44, 0x30d4c,
2353 0x30d54, 0x30d74,
2354 0x30d7c, 0x30d7c,
2355 0x30de0, 0x30de0,
2356 0x30e00, 0x30ed4,
2357 0x30f00, 0x30fa4,
2358 0x30fc0, 0x30fc4,
2359 0x31000, 0x31004,
2360 0x31080, 0x310fc,
2361 0x31208, 0x31220,
2362 0x3123c, 0x31254,
2363 0x31300, 0x31300,
2364 0x31308, 0x3131c,
2365 0x31338, 0x3133c,
2366 0x31380, 0x31380,
2367 0x31388, 0x313a8,
2368 0x313b4, 0x313b4,
2369 0x31400, 0x31420,
2370 0x31438, 0x3143c,
2371 0x31480, 0x31480,
2372 0x314a8, 0x314a8,
2373 0x314b0, 0x314b4,
2374 0x314c8, 0x314d4,
2375 0x31a40, 0x31a4c,
2376 0x31af0, 0x31b20,
2377 0x31b38, 0x31b3c,
2378 0x31b80, 0x31b80,
2379 0x31ba8, 0x31ba8,
2380 0x31bb0, 0x31bb4,
2381 0x31bc8, 0x31bd4,
2382 0x32140, 0x3218c,
2383 0x321f0, 0x321f4,
2384 0x32200, 0x32200,
2385 0x32218, 0x32218,
2386 0x32400, 0x32400,
2387 0x32408, 0x3241c,
2388 0x32618, 0x32620,
2389 0x32664, 0x32664,
2390 0x326a8, 0x326a8,
2391 0x326ec, 0x326ec,
2392 0x32a00, 0x32abc,
2393 0x32b00, 0x32b18,
2394 0x32b20, 0x32b38,
2395 0x32b40, 0x32b58,
2396 0x32b60, 0x32b78,
2397 0x32c00, 0x32c00,
2398 0x32c08, 0x32c3c,
2399 0x33000, 0x3302c,
2400 0x33034, 0x33050,
2401 0x33058, 0x33058,
2402 0x33060, 0x3308c,
2403 0x3309c, 0x330ac,
2404 0x330c0, 0x330c0,
2405 0x330c8, 0x330d0,
2406 0x330d8, 0x330e0,
2407 0x330ec, 0x3312c,
2408 0x33134, 0x33150,
2409 0x33158, 0x33158,
2410 0x33160, 0x3318c,
2411 0x3319c, 0x331ac,
2412 0x331c0, 0x331c0,
2413 0x331c8, 0x331d0,
2414 0x331d8, 0x331e0,
2415 0x331ec, 0x33290,
2416 0x33298, 0x332c4,
2417 0x332e4, 0x33390,
2418 0x33398, 0x333c4,
2419 0x333e4, 0x3342c,
2420 0x33434, 0x33450,
2421 0x33458, 0x33458,
2422 0x33460, 0x3348c,
2423 0x3349c, 0x334ac,
2424 0x334c0, 0x334c0,
2425 0x334c8, 0x334d0,
2426 0x334d8, 0x334e0,
2427 0x334ec, 0x3352c,
2428 0x33534, 0x33550,
2429 0x33558, 0x33558,
2430 0x33560, 0x3358c,
2431 0x3359c, 0x335ac,
2432 0x335c0, 0x335c0,
2433 0x335c8, 0x335d0,
2434 0x335d8, 0x335e0,
2435 0x335ec, 0x33690,
2436 0x33698, 0x336c4,
2437 0x336e4, 0x33790,
2438 0x33798, 0x337c4,
2439 0x337e4, 0x337fc,
2440 0x33814, 0x33814,
2441 0x33854, 0x33868,
2442 0x33880, 0x3388c,
2443 0x338c0, 0x338d0,
2444 0x338e8, 0x338ec,
2445 0x33900, 0x3392c,
2446 0x33934, 0x33950,
2447 0x33958, 0x33958,
2448 0x33960, 0x3398c,
2449 0x3399c, 0x339ac,
2450 0x339c0, 0x339c0,
2451 0x339c8, 0x339d0,
2452 0x339d8, 0x339e0,
2453 0x339ec, 0x33a90,
2454 0x33a98, 0x33ac4,
2455 0x33ae4, 0x33b10,
2456 0x33b24, 0x33b28,
2457 0x33b38, 0x33b50,
2458 0x33bf0, 0x33c10,
2459 0x33c24, 0x33c28,
2460 0x33c38, 0x33c50,
2461 0x33cf0, 0x33cfc,
2462 0x34000, 0x34030,
2463 0x34100, 0x34168,
2464 0x34190, 0x341a0,
2465 0x341a8, 0x341b8,
2466 0x341c4, 0x341c8,
2467 0x341d0, 0x341d0,
2468 0x34200, 0x34320,
2469 0x34400, 0x344b4,
2470 0x344c0, 0x3452c,
2471 0x34540, 0x3461c,
2472 0x34800, 0x348a0,
2473 0x348c0, 0x34908,
2474 0x34910, 0x349b8,
2475 0x34a00, 0x34a04,
2476 0x34a0c, 0x34a14,
2477 0x34a1c, 0x34a2c,
2478 0x34a44, 0x34a50,
2479 0x34a74, 0x34a74,
2480 0x34a7c, 0x34afc,
2481 0x34b08, 0x34c24,
2482 0x34d00, 0x34d14,
2483 0x34d1c, 0x34d3c,
2484 0x34d44, 0x34d4c,
2485 0x34d54, 0x34d74,
2486 0x34d7c, 0x34d7c,
2487 0x34de0, 0x34de0,
2488 0x34e00, 0x34ed4,
2489 0x34f00, 0x34fa4,
2490 0x34fc0, 0x34fc4,
2491 0x35000, 0x35004,
2492 0x35080, 0x350fc,
2493 0x35208, 0x35220,
2494 0x3523c, 0x35254,
2495 0x35300, 0x35300,
2496 0x35308, 0x3531c,
2497 0x35338, 0x3533c,
2498 0x35380, 0x35380,
2499 0x35388, 0x353a8,
2500 0x353b4, 0x353b4,
2501 0x35400, 0x35420,
2502 0x35438, 0x3543c,
2503 0x35480, 0x35480,
2504 0x354a8, 0x354a8,
2505 0x354b0, 0x354b4,
2506 0x354c8, 0x354d4,
2507 0x35a40, 0x35a4c,
2508 0x35af0, 0x35b20,
2509 0x35b38, 0x35b3c,
2510 0x35b80, 0x35b80,
2511 0x35ba8, 0x35ba8,
2512 0x35bb0, 0x35bb4,
2513 0x35bc8, 0x35bd4,
2514 0x36140, 0x3618c,
2515 0x361f0, 0x361f4,
2516 0x36200, 0x36200,
2517 0x36218, 0x36218,
2518 0x36400, 0x36400,
2519 0x36408, 0x3641c,
2520 0x36618, 0x36620,
2521 0x36664, 0x36664,
2522 0x366a8, 0x366a8,
2523 0x366ec, 0x366ec,
2524 0x36a00, 0x36abc,
2525 0x36b00, 0x36b18,
2526 0x36b20, 0x36b38,
2527 0x36b40, 0x36b58,
2528 0x36b60, 0x36b78,
2529 0x36c00, 0x36c00,
2530 0x36c08, 0x36c3c,
2531 0x37000, 0x3702c,
2532 0x37034, 0x37050,
2533 0x37058, 0x37058,
2534 0x37060, 0x3708c,
2535 0x3709c, 0x370ac,
2536 0x370c0, 0x370c0,
2537 0x370c8, 0x370d0,
2538 0x370d8, 0x370e0,
2539 0x370ec, 0x3712c,
2540 0x37134, 0x37150,
2541 0x37158, 0x37158,
2542 0x37160, 0x3718c,
2543 0x3719c, 0x371ac,
2544 0x371c0, 0x371c0,
2545 0x371c8, 0x371d0,
2546 0x371d8, 0x371e0,
2547 0x371ec, 0x37290,
2548 0x37298, 0x372c4,
2549 0x372e4, 0x37390,
2550 0x37398, 0x373c4,
2551 0x373e4, 0x3742c,
2552 0x37434, 0x37450,
2553 0x37458, 0x37458,
2554 0x37460, 0x3748c,
2555 0x3749c, 0x374ac,
2556 0x374c0, 0x374c0,
2557 0x374c8, 0x374d0,
2558 0x374d8, 0x374e0,
2559 0x374ec, 0x3752c,
2560 0x37534, 0x37550,
2561 0x37558, 0x37558,
2562 0x37560, 0x3758c,
2563 0x3759c, 0x375ac,
2564 0x375c0, 0x375c0,
2565 0x375c8, 0x375d0,
2566 0x375d8, 0x375e0,
2567 0x375ec, 0x37690,
2568 0x37698, 0x376c4,
2569 0x376e4, 0x37790,
2570 0x37798, 0x377c4,
2571 0x377e4, 0x377fc,
2572 0x37814, 0x37814,
2573 0x37854, 0x37868,
2574 0x37880, 0x3788c,
2575 0x378c0, 0x378d0,
2576 0x378e8, 0x378ec,
2577 0x37900, 0x3792c,
2578 0x37934, 0x37950,
2579 0x37958, 0x37958,
2580 0x37960, 0x3798c,
2581 0x3799c, 0x379ac,
2582 0x379c0, 0x379c0,
2583 0x379c8, 0x379d0,
2584 0x379d8, 0x379e0,
2585 0x379ec, 0x37a90,
2586 0x37a98, 0x37ac4,
2587 0x37ae4, 0x37b10,
2588 0x37b24, 0x37b28,
2589 0x37b38, 0x37b50,
2590 0x37bf0, 0x37c10,
2591 0x37c24, 0x37c28,
2592 0x37c38, 0x37c50,
2593 0x37cf0, 0x37cfc,
2594 0x40040, 0x40040,
2595 0x40080, 0x40084,
2596 0x40100, 0x40100,
2597 0x40140, 0x401bc,
2598 0x40200, 0x40214,
2599 0x40228, 0x40228,
2600 0x40240, 0x40258,
2601 0x40280, 0x40280,
2602 0x40304, 0x40304,
2603 0x40330, 0x4033c,
2604 0x41304, 0x413c8,
2605 0x413d0, 0x413dc,
2606 0x413f0, 0x413f0,
2607 0x41400, 0x4140c,
2608 0x41414, 0x4141c,
2609 0x41480, 0x414d0,
2610 0x44000, 0x4407c,
2611 0x440c0, 0x441ac,
2612 0x441b4, 0x4427c,
2613 0x442c0, 0x443ac,
2614 0x443b4, 0x4447c,
2615 0x444c0, 0x445ac,
2616 0x445b4, 0x4467c,
2617 0x446c0, 0x447ac,
2618 0x447b4, 0x4487c,
2619 0x448c0, 0x449ac,
2620 0x449b4, 0x44a7c,
2621 0x44ac0, 0x44bac,
2622 0x44bb4, 0x44c7c,
2623 0x44cc0, 0x44dac,
2624 0x44db4, 0x44e7c,
2625 0x44ec0, 0x44fac,
2626 0x44fb4, 0x4507c,
2627 0x450c0, 0x451ac,
2628 0x451b4, 0x451fc,
2629 0x45800, 0x45804,
2630 0x45810, 0x45830,
2631 0x45840, 0x45860,
2632 0x45868, 0x45868,
2633 0x45880, 0x45884,
2634 0x458a0, 0x458b0,
2635 0x45a00, 0x45a04,
2636 0x45a10, 0x45a30,
2637 0x45a40, 0x45a60,
2638 0x45a68, 0x45a68,
2639 0x45a80, 0x45a84,
2640 0x45aa0, 0x45ab0,
2641 0x460c0, 0x460e4,
2642 0x47000, 0x4703c,
2643 0x47044, 0x4708c,
2644 0x47200, 0x47250,
2645 0x47400, 0x47408,
2646 0x47414, 0x47420,
2647 0x47600, 0x47618,
2648 0x47800, 0x47814,
2649 0x47820, 0x4782c,
2650 0x50000, 0x50084,
2651 0x50090, 0x500cc,
2652 0x50300, 0x50384,
2653 0x50400, 0x50400,
2654 0x50800, 0x50884,
2655 0x50890, 0x508cc,
2656 0x50b00, 0x50b84,
2657 0x50c00, 0x50c00,
2658 0x51000, 0x51020,
2659 0x51028, 0x510b0,
2660 0x51300, 0x51324,
2661 };
2662
2663 static const unsigned int t6vf_reg_ranges[] = {
2664 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2665 VF_MPS_REG(A_MPS_VF_CTL),
2666 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2667 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2668 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2669 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2670 FW_T6VF_MBDATA_BASE_ADDR,
2671 FW_T6VF_MBDATA_BASE_ADDR +
2672 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2673 };
2674
2675 static const unsigned int t7_reg_ranges[] = {
2676 0x1008, 0x101c,
2677 0x1024, 0x10a8,
2678 0x10b4, 0x10f8,
2679 0x1100, 0x1114,
2680 0x111c, 0x112c,
2681 0x1138, 0x113c,
2682 0x1144, 0x115c,
2683 0x1180, 0x1184,
2684 0x1190, 0x1194,
2685 0x11a0, 0x11a4,
2686 0x11b0, 0x11d0,
2687 0x11fc, 0x1278,
2688 0x1280, 0x1368,
2689 0x1700, 0x172c,
2690 0x173c, 0x1760,
2691 0x1800, 0x18fc,
2692 0x3000, 0x3044,
2693 0x30a4, 0x30b0,
2694 0x30b8, 0x30d8,
2695 0x30e0, 0x30e8,
2696 0x3140, 0x357c,
2697 0x35a8, 0x35cc,
2698 0x35e0, 0x35ec,
2699 0x3600, 0x37fc,
2700 0x3804, 0x3818,
2701 0x3880, 0x388c,
2702 0x3900, 0x3904,
2703 0x3910, 0x3978,
2704 0x3980, 0x399c,
2705 0x4700, 0x4720,
2706 0x4728, 0x475c,
2707 0x480c, 0x4814,
2708 0x4890, 0x489c,
2709 0x48a4, 0x48ac,
2710 0x48b8, 0x48bc,
2711 0x4900, 0x4924,
2712 0x4ffc, 0x4ffc,
2713 0x5500, 0x5624,
2714 0x56c4, 0x56ec,
2715 0x56f4, 0x5720,
2716 0x5728, 0x575c,
2717 0x580c, 0x5814,
2718 0x5890, 0x589c,
2719 0x58a4, 0x58ac,
2720 0x58b8, 0x58bc,
2721 0x5940, 0x598c,
2722 0x59b0, 0x59c8,
2723 0x59d0, 0x59dc,
2724 0x59fc, 0x5a18,
2725 0x5a60, 0x5a6c,
2726 0x5a80, 0x5a8c,
2727 0x5a94, 0x5a9c,
2728 0x5b94, 0x5bec,
2729 0x5bf8, 0x5bfc,
2730 0x5c10, 0x5c40,
2731 0x5c4c, 0x5e48,
2732 0x5e50, 0x5e94,
2733 0x5ea0, 0x5eb0,
2734 0x5ec0, 0x5ec0,
2735 0x5ec8, 0x5ed0,
2736 0x5ee0, 0x5ee0,
2737 0x5ef0, 0x5ef0,
2738 0x5f00, 0x5f04,
2739 0x5f0c, 0x5f10,
2740 0x5f20, 0x5f78,
2741 0x5f84, 0x5f88,
2742 0x5f90, 0x5fd8,
2743 0x6000, 0x6020,
2744 0x6028, 0x6030,
2745 0x6044, 0x609c,
2746 0x60a8, 0x60ac,
2747 0x60b8, 0x60ec,
2748 0x6100, 0x6104,
2749 0x6118, 0x611c,
2750 0x6150, 0x6150,
2751 0x6180, 0x61b8,
2752 0x7700, 0x77a8,
2753 0x77b0, 0x7888,
2754 0x78cc, 0x7970,
2755 0x7b00, 0x7b00,
2756 0x7b08, 0x7b0c,
2757 0x7b24, 0x7b84,
2758 0x7b8c, 0x7c2c,
2759 0x7c34, 0x7c40,
2760 0x7c48, 0x7c68,
2761 0x7c70, 0x7c7c,
2762 0x7d00, 0x7ddc,
2763 0x7de4, 0x7e38,
2764 0x7e40, 0x7e44,
2765 0x7e4c, 0x7e74,
2766 0x7e80, 0x7ee0,
2767 0x7ee8, 0x7f0c,
2768 0x7f20, 0x7f5c,
2769 0x8dc0, 0x8de8,
2770 0x8df8, 0x8e04,
2771 0x8e10, 0x8e30,
2772 0x8e7c, 0x8ee8,
2773 0x8f88, 0x8f88,
2774 0x8f90, 0x8fb0,
2775 0x8fb8, 0x9058,
2776 0x9074, 0x90f8,
2777 0x9100, 0x912c,
2778 0x9138, 0x9188,
2779 0x9400, 0x9414,
2780 0x9430, 0x9440,
2781 0x9454, 0x9454,
2782 0x945c, 0x947c,
2783 0x9498, 0x94b8,
2784 0x9600, 0x9600,
2785 0x9608, 0x9638,
2786 0x9640, 0x9704,
2787 0x9710, 0x971c,
2788 0x9800, 0x9804,
2789 0x9854, 0x9854,
2790 0x9c00, 0x9c6c,
2791 0x9c80, 0x9cec,
2792 0x9d00, 0x9d6c,
2793 0x9d80, 0x9dec,
2794 0x9e00, 0x9e6c,
2795 0x9e80, 0x9eec,
2796 0x9f00, 0x9f6c,
2797 0x9f80, 0x9fec,
2798 0xa000, 0xa06c,
2799 0xa080, 0xa0ec,
2800 0xa100, 0xa16c,
2801 0xa180, 0xa1ec,
2802 0xa200, 0xa26c,
2803 0xa280, 0xa2ec,
2804 0xa300, 0xa36c,
2805 0xa380, 0xa458,
2806 0xa460, 0xa4f8,
2807 0xd000, 0xd03c,
2808 0xd100, 0xd134,
2809 0xd200, 0xd214,
2810 0xd220, 0xd234,
2811 0xd240, 0xd254,
2812 0xd260, 0xd274,
2813 0xd280, 0xd294,
2814 0xd2a0, 0xd2b4,
2815 0xd2c0, 0xd2d4,
2816 0xd2e0, 0xd2f4,
2817 0xd300, 0xd31c,
2818 0xdfc0, 0xdfe0,
2819 0xe000, 0xe00c,
2820 0xf000, 0xf008,
2821 0xf010, 0xf06c,
2822 0x11000, 0x11014,
2823 0x11048, 0x11120,
2824 0x11130, 0x11144,
2825 0x11174, 0x11178,
2826 0x11190, 0x111a0,
2827 0x111e4, 0x112f0,
2828 0x11300, 0x1133c,
2829 0x11408, 0x1146c,
2830 0x12000, 0x12004,
2831 0x12060, 0x122c4,
2832 0x19040, 0x1906c,
2833 0x19078, 0x19080,
2834 0x1908c, 0x190e8,
2835 0x190f0, 0x190f8,
2836 0x19100, 0x19110,
2837 0x19120, 0x19124,
2838 0x19150, 0x19194,
2839 0x1919c, 0x191a0,
2840 0x191ac, 0x191c8,
2841 0x191d0, 0x191e4,
2842 0x19250, 0x19250,
2843 0x19258, 0x19268,
2844 0x19278, 0x19278,
2845 0x19280, 0x192b0,
2846 0x192bc, 0x192f0,
2847 0x19300, 0x19308,
2848 0x19310, 0x19318,
2849 0x19320, 0x19328,
2850 0x19330, 0x19330,
2851 0x19348, 0x1934c,
2852 0x193f8, 0x19428,
2853 0x19430, 0x19444,
2854 0x1944c, 0x1946c,
2855 0x19474, 0x1947c,
2856 0x19488, 0x194cc,
2857 0x194f0, 0x194f8,
2858 0x19c00, 0x19c48,
2859 0x19c50, 0x19c80,
2860 0x19c94, 0x19c98,
2861 0x19ca0, 0x19cdc,
2862 0x19ce4, 0x19cf8,
2863 0x19d00, 0x19d30,
2864 0x19d50, 0x19d80,
2865 0x19d94, 0x19d98,
2866 0x19da0, 0x19de0,
2867 0x19df0, 0x19e10,
2868 0x19e50, 0x19e6c,
2869 0x19ea0, 0x19ebc,
2870 0x19ec4, 0x19ef4,
2871 0x19f04, 0x19f2c,
2872 0x19f34, 0x19f34,
2873 0x19f40, 0x19f50,
2874 0x19f90, 0x19fb4,
2875 0x19fbc, 0x19fbc,
2876 0x19fc4, 0x19fc8,
2877 0x19fd0, 0x19fe4,
2878 0x1a000, 0x1a004,
2879 0x1a010, 0x1a06c,
2880 0x1a0b0, 0x1a0e4,
2881 0x1a0ec, 0x1a108,
2882 0x1a114, 0x1a130,
2883 0x1a138, 0x1a1c4,
2884 0x1a1fc, 0x1a29c,
2885 0x1a2a8, 0x1a2b8,
2886 0x1a2c0, 0x1a388,
2887 0x1a398, 0x1a3ac,
2888 0x1e008, 0x1e00c,
2889 0x1e040, 0x1e044,
2890 0x1e04c, 0x1e04c,
2891 0x1e284, 0x1e290,
2892 0x1e2c0, 0x1e2c0,
2893 0x1e2e0, 0x1e2e4,
2894 0x1e300, 0x1e384,
2895 0x1e3c0, 0x1e3c8,
2896 0x1e408, 0x1e40c,
2897 0x1e440, 0x1e444,
2898 0x1e44c, 0x1e44c,
2899 0x1e684, 0x1e690,
2900 0x1e6c0, 0x1e6c0,
2901 0x1e6e0, 0x1e6e4,
2902 0x1e700, 0x1e784,
2903 0x1e7c0, 0x1e7c8,
2904 0x1e808, 0x1e80c,
2905 0x1e840, 0x1e844,
2906 0x1e84c, 0x1e84c,
2907 0x1ea84, 0x1ea90,
2908 0x1eac0, 0x1eac0,
2909 0x1eae0, 0x1eae4,
2910 0x1eb00, 0x1eb84,
2911 0x1ebc0, 0x1ebc8,
2912 0x1ec08, 0x1ec0c,
2913 0x1ec40, 0x1ec44,
2914 0x1ec4c, 0x1ec4c,
2915 0x1ee84, 0x1ee90,
2916 0x1eec0, 0x1eec0,
2917 0x1eee0, 0x1eee4,
2918 0x1ef00, 0x1ef84,
2919 0x1efc0, 0x1efc8,
2920 0x1f008, 0x1f00c,
2921 0x1f040, 0x1f044,
2922 0x1f04c, 0x1f04c,
2923 0x1f284, 0x1f290,
2924 0x1f2c0, 0x1f2c0,
2925 0x1f2e0, 0x1f2e4,
2926 0x1f300, 0x1f384,
2927 0x1f3c0, 0x1f3c8,
2928 0x1f408, 0x1f40c,
2929 0x1f440, 0x1f444,
2930 0x1f44c, 0x1f44c,
2931 0x1f684, 0x1f690,
2932 0x1f6c0, 0x1f6c0,
2933 0x1f6e0, 0x1f6e4,
2934 0x1f700, 0x1f784,
2935 0x1f7c0, 0x1f7c8,
2936 0x1f808, 0x1f80c,
2937 0x1f840, 0x1f844,
2938 0x1f84c, 0x1f84c,
2939 0x1fa84, 0x1fa90,
2940 0x1fac0, 0x1fac0,
2941 0x1fae0, 0x1fae4,
2942 0x1fb00, 0x1fb84,
2943 0x1fbc0, 0x1fbc8,
2944 0x1fc08, 0x1fc0c,
2945 0x1fc40, 0x1fc44,
2946 0x1fc4c, 0x1fc4c,
2947 0x1fe84, 0x1fe90,
2948 0x1fec0, 0x1fec0,
2949 0x1fee0, 0x1fee4,
2950 0x1ff00, 0x1ff84,
2951 0x1ffc0, 0x1ffc8,
2952 0x30000, 0x30038,
2953 0x30100, 0x3017c,
2954 0x30190, 0x301a0,
2955 0x301a8, 0x301b8,
2956 0x301c4, 0x301c8,
2957 0x301d0, 0x301e0,
2958 0x30200, 0x30344,
2959 0x30400, 0x304b4,
2960 0x304c0, 0x3052c,
2961 0x30540, 0x3065c,
2962 0x30800, 0x30848,
2963 0x30850, 0x308a8,
2964 0x308b8, 0x308c0,
2965 0x308cc, 0x308dc,
2966 0x30900, 0x30904,
2967 0x3090c, 0x30914,
2968 0x3091c, 0x30928,
2969 0x30930, 0x3093c,
2970 0x30944, 0x30948,
2971 0x30954, 0x30974,
2972 0x3097c, 0x30980,
2973 0x30a00, 0x30a20,
2974 0x30a38, 0x30a3c,
2975 0x30a50, 0x30a50,
2976 0x30a80, 0x30a80,
2977 0x30a88, 0x30aa8,
2978 0x30ab0, 0x30ab4,
2979 0x30ac8, 0x30ad4,
2980 0x30b28, 0x30b84,
2981 0x30b98, 0x30bb8,
2982 0x30c98, 0x30d14,
2983 0x31000, 0x31020,
2984 0x31038, 0x3103c,
2985 0x31050, 0x31050,
2986 0x31080, 0x31080,
2987 0x31088, 0x310a8,
2988 0x310b0, 0x310b4,
2989 0x310c8, 0x310d4,
2990 0x31128, 0x31184,
2991 0x31198, 0x311b8,
2992 0x32000, 0x32038,
2993 0x32100, 0x3217c,
2994 0x32190, 0x321a0,
2995 0x321a8, 0x321b8,
2996 0x321c4, 0x321c8,
2997 0x321d0, 0x321e0,
2998 0x32200, 0x32344,
2999 0x32400, 0x324b4,
3000 0x324c0, 0x3252c,
3001 0x32540, 0x3265c,
3002 0x32800, 0x32848,
3003 0x32850, 0x328a8,
3004 0x328b8, 0x328c0,
3005 0x328cc, 0x328dc,
3006 0x32900, 0x32904,
3007 0x3290c, 0x32914,
3008 0x3291c, 0x32928,
3009 0x32930, 0x3293c,
3010 0x32944, 0x32948,
3011 0x32954, 0x32974,
3012 0x3297c, 0x32980,
3013 0x32a00, 0x32a20,
3014 0x32a38, 0x32a3c,
3015 0x32a50, 0x32a50,
3016 0x32a80, 0x32a80,
3017 0x32a88, 0x32aa8,
3018 0x32ab0, 0x32ab4,
3019 0x32ac8, 0x32ad4,
3020 0x32b28, 0x32b84,
3021 0x32b98, 0x32bb8,
3022 0x32c98, 0x32d14,
3023 0x33000, 0x33020,
3024 0x33038, 0x3303c,
3025 0x33050, 0x33050,
3026 0x33080, 0x33080,
3027 0x33088, 0x330a8,
3028 0x330b0, 0x330b4,
3029 0x330c8, 0x330d4,
3030 0x33128, 0x33184,
3031 0x33198, 0x331b8,
3032 0x34000, 0x34038,
3033 0x34100, 0x3417c,
3034 0x34190, 0x341a0,
3035 0x341a8, 0x341b8,
3036 0x341c4, 0x341c8,
3037 0x341d0, 0x341e0,
3038 0x34200, 0x34344,
3039 0x34400, 0x344b4,
3040 0x344c0, 0x3452c,
3041 0x34540, 0x3465c,
3042 0x34800, 0x34848,
3043 0x34850, 0x348a8,
3044 0x348b8, 0x348c0,
3045 0x348cc, 0x348dc,
3046 0x34900, 0x34904,
3047 0x3490c, 0x34914,
3048 0x3491c, 0x34928,
3049 0x34930, 0x3493c,
3050 0x34944, 0x34948,
3051 0x34954, 0x34974,
3052 0x3497c, 0x34980,
3053 0x34a00, 0x34a20,
3054 0x34a38, 0x34a3c,
3055 0x34a50, 0x34a50,
3056 0x34a80, 0x34a80,
3057 0x34a88, 0x34aa8,
3058 0x34ab0, 0x34ab4,
3059 0x34ac8, 0x34ad4,
3060 0x34b28, 0x34b84,
3061 0x34b98, 0x34bb8,
3062 0x34c98, 0x34d14,
3063 0x35000, 0x35020,
3064 0x35038, 0x3503c,
3065 0x35050, 0x35050,
3066 0x35080, 0x35080,
3067 0x35088, 0x350a8,
3068 0x350b0, 0x350b4,
3069 0x350c8, 0x350d4,
3070 0x35128, 0x35184,
3071 0x35198, 0x351b8,
3072 0x36000, 0x36038,
3073 0x36100, 0x3617c,
3074 0x36190, 0x361a0,
3075 0x361a8, 0x361b8,
3076 0x361c4, 0x361c8,
3077 0x361d0, 0x361e0,
3078 0x36200, 0x36344,
3079 0x36400, 0x364b4,
3080 0x364c0, 0x3652c,
3081 0x36540, 0x3665c,
3082 0x36800, 0x36848,
3083 0x36850, 0x368a8,
3084 0x368b8, 0x368c0,
3085 0x368cc, 0x368dc,
3086 0x36900, 0x36904,
3087 0x3690c, 0x36914,
3088 0x3691c, 0x36928,
3089 0x36930, 0x3693c,
3090 0x36944, 0x36948,
3091 0x36954, 0x36974,
3092 0x3697c, 0x36980,
3093 0x36a00, 0x36a20,
3094 0x36a38, 0x36a3c,
3095 0x36a50, 0x36a50,
3096 0x36a80, 0x36a80,
3097 0x36a88, 0x36aa8,
3098 0x36ab0, 0x36ab4,
3099 0x36ac8, 0x36ad4,
3100 0x36b28, 0x36b84,
3101 0x36b98, 0x36bb8,
3102 0x36c98, 0x36d14,
3103 0x37000, 0x37020,
3104 0x37038, 0x3703c,
3105 0x37050, 0x37050,
3106 0x37080, 0x37080,
3107 0x37088, 0x370a8,
3108 0x370b0, 0x370b4,
3109 0x370c8, 0x370d4,
3110 0x37128, 0x37184,
3111 0x37198, 0x371b8,
3112 0x38000, 0x380b0,
3113 0x380b8, 0x38130,
3114 0x38140, 0x38140,
3115 0x38150, 0x38154,
3116 0x38160, 0x381c4,
3117 0x381d0, 0x38204,
3118 0x3820c, 0x38214,
3119 0x3821c, 0x3822c,
3120 0x38244, 0x38244,
3121 0x38254, 0x38274,
3122 0x3827c, 0x38280,
3123 0x38300, 0x38304,
3124 0x3830c, 0x38314,
3125 0x3831c, 0x3832c,
3126 0x38344, 0x38344,
3127 0x38354, 0x38374,
3128 0x3837c, 0x38380,
3129 0x38400, 0x38424,
3130 0x38438, 0x3843c,
3131 0x38480, 0x38480,
3132 0x384a8, 0x384a8,
3133 0x384b0, 0x384b4,
3134 0x384c8, 0x38514,
3135 0x38600, 0x3860c,
3136 0x3861c, 0x38624,
3137 0x38900, 0x38924,
3138 0x38938, 0x3893c,
3139 0x38980, 0x38980,
3140 0x389a8, 0x389a8,
3141 0x389b0, 0x389b4,
3142 0x389c8, 0x38a14,
3143 0x38b00, 0x38b0c,
3144 0x38b1c, 0x38b24,
3145 0x38e00, 0x38e00,
3146 0x38e18, 0x38e20,
3147 0x38e38, 0x38e40,
3148 0x38e58, 0x38e60,
3149 0x38e78, 0x38e80,
3150 0x38e98, 0x38ea0,
3151 0x38eb8, 0x38ec0,
3152 0x38ed8, 0x38ee0,
3153 0x38ef8, 0x38f08,
3154 0x38f10, 0x38f2c,
3155 0x38f80, 0x38ffc,
3156 0x39080, 0x39080,
3157 0x39088, 0x39090,
3158 0x39100, 0x39108,
3159 0x39120, 0x39128,
3160 0x39140, 0x39148,
3161 0x39160, 0x39168,
3162 0x39180, 0x39188,
3163 0x391a0, 0x391a8,
3164 0x391c0, 0x391c8,
3165 0x391e0, 0x391e8,
3166 0x39200, 0x39200,
3167 0x39208, 0x39240,
3168 0x39300, 0x39300,
3169 0x39308, 0x39340,
3170 0x39400, 0x39400,
3171 0x39408, 0x39440,
3172 0x39500, 0x39500,
3173 0x39508, 0x39540,
3174 0x39600, 0x39600,
3175 0x39608, 0x39640,
3176 0x39700, 0x39700,
3177 0x39708, 0x39740,
3178 0x39800, 0x39800,
3179 0x39808, 0x39840,
3180 0x39900, 0x39900,
3181 0x39908, 0x39940,
3182 0x39a00, 0x39a04,
3183 0x39a10, 0x39a14,
3184 0x39a1c, 0x39aa8,
3185 0x39b00, 0x39ecc,
3186 0x3a000, 0x3a004,
3187 0x3a050, 0x3a084,
3188 0x3a090, 0x3a09c,
3189 0x3a93c, 0x3a93c,
3190 0x3b93c, 0x3b93c,
3191 0x3c93c, 0x3c93c,
3192 0x3d93c, 0x3d93c,
3193 0x3e000, 0x3e020,
3194 0x3e03c, 0x3e05c,
3195 0x3e100, 0x3e120,
3196 0x3e13c, 0x3e15c,
3197 0x3e200, 0x3e220,
3198 0x3e23c, 0x3e25c,
3199 0x3e300, 0x3e320,
3200 0x3e33c, 0x3e35c,
3201 0x3f000, 0x3f034,
3202 0x3f100, 0x3f130,
3203 0x3f200, 0x3f218,
3204 0x44000, 0x44014,
3205 0x44020, 0x44028,
3206 0x44030, 0x44030,
3207 0x44100, 0x44114,
3208 0x44120, 0x44128,
3209 0x44130, 0x44130,
3210 0x44200, 0x44214,
3211 0x44220, 0x44228,
3212 0x44230, 0x44230,
3213 0x44300, 0x44314,
3214 0x44320, 0x44328,
3215 0x44330, 0x44330,
3216 0x44400, 0x44414,
3217 0x44420, 0x44428,
3218 0x44430, 0x44430,
3219 0x44500, 0x44514,
3220 0x44520, 0x44528,
3221 0x44530, 0x44530,
3222 0x44714, 0x44718,
3223 0x44730, 0x44730,
3224 0x447c0, 0x447c0,
3225 0x447f0, 0x447f0,
3226 0x447f8, 0x447fc,
3227 0x45000, 0x45014,
3228 0x45020, 0x45028,
3229 0x45030, 0x45030,
3230 0x45100, 0x45114,
3231 0x45120, 0x45128,
3232 0x45130, 0x45130,
3233 0x45200, 0x45214,
3234 0x45220, 0x45228,
3235 0x45230, 0x45230,
3236 0x45300, 0x45314,
3237 0x45320, 0x45328,
3238 0x45330, 0x45330,
3239 0x45400, 0x45414,
3240 0x45420, 0x45428,
3241 0x45430, 0x45430,
3242 0x45500, 0x45514,
3243 0x45520, 0x45528,
3244 0x45530, 0x45530,
3245 0x45714, 0x45718,
3246 0x45730, 0x45730,
3247 0x457c0, 0x457c0,
3248 0x457f0, 0x457f0,
3249 0x457f8, 0x457fc,
3250 0x46000, 0x46010,
3251 0x46020, 0x46034,
3252 0x46040, 0x46050,
3253 0x46060, 0x46088,
3254 0x47000, 0x4709c,
3255 0x470c0, 0x470d4,
3256 0x47100, 0x471a8,
3257 0x471b0, 0x471e8,
3258 0x47200, 0x47210,
3259 0x4721c, 0x47230,
3260 0x47238, 0x47238,
3261 0x47240, 0x472ac,
3262 0x472d0, 0x472f4,
3263 0x47300, 0x47310,
3264 0x47318, 0x47348,
3265 0x47350, 0x47354,
3266 0x47380, 0x47388,
3267 0x47390, 0x47394,
3268 0x47400, 0x47448,
3269 0x47450, 0x47458,
3270 0x47500, 0x4751c,
3271 0x47530, 0x4754c,
3272 0x47560, 0x4757c,
3273 0x47590, 0x475ac,
3274 0x47600, 0x47630,
3275 0x47640, 0x47644,
3276 0x47660, 0x4769c,
3277 0x47700, 0x47710,
3278 0x47740, 0x47750,
3279 0x4775c, 0x4779c,
3280 0x477b0, 0x477bc,
3281 0x477c4, 0x477c8,
3282 0x477d4, 0x477fc,
3283 0x48000, 0x48004,
3284 0x48018, 0x4801c,
3285 0x49304, 0x493f0,
3286 0x49400, 0x49410,
3287 0x49460, 0x494f4,
3288 0x50000, 0x50084,
3289 0x50090, 0x500cc,
3290 0x50300, 0x50384,
3291 0x50400, 0x50404,
3292 0x50800, 0x50884,
3293 0x50890, 0x508cc,
3294 0x50b00, 0x50b84,
3295 0x50c00, 0x50c04,
3296 0x51000, 0x51020,
3297 0x51028, 0x510c4,
3298 0x51104, 0x51108,
3299 0x51200, 0x51274,
3300 0x51300, 0x51324,
3301 0x51400, 0x51548,
3302 0x51550, 0x51554,
3303 0x5155c, 0x51584,
3304 0x5158c, 0x515c8,
3305 0x515f0, 0x515f4,
3306 0x58000, 0x58004,
3307 0x58018, 0x5801c,
3308 0x59304, 0x593f0,
3309 0x59400, 0x59410,
3310 0x59460, 0x594f4,
3311 };
3312
3313 u32 *buf_end = (u32 *)(buf + buf_size);
3314 const unsigned int *reg_ranges;
3315 int reg_ranges_size, range;
3316 unsigned int chip_version = chip_id(adap);
3317
3318 /*
3319 * Select the right set of register ranges to dump depending on the
3320 * adapter chip type.
3321 */
3322 switch (chip_version) {
3323 case CHELSIO_T4:
3324 if (adap->flags & IS_VF) {
3325 reg_ranges = t4vf_reg_ranges;
3326 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
3327 } else {
3328 reg_ranges = t4_reg_ranges;
3329 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
3330 }
3331 break;
3332
3333 case CHELSIO_T5:
3334 if (adap->flags & IS_VF) {
3335 reg_ranges = t5vf_reg_ranges;
3336 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
3337 } else {
3338 reg_ranges = t5_reg_ranges;
3339 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
3340 }
3341 break;
3342
3343 case CHELSIO_T6:
3344 if (adap->flags & IS_VF) {
3345 reg_ranges = t6vf_reg_ranges;
3346 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
3347 } else {
3348 reg_ranges = t6_reg_ranges;
3349 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
3350 }
3351 break;
3352
3353 case CHELSIO_T7:
3354 if (adap->flags & IS_VF) {
3355 reg_ranges = t6vf_reg_ranges;
3356 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
3357 } else {
3358 reg_ranges = t7_reg_ranges;
3359 reg_ranges_size = ARRAY_SIZE(t7_reg_ranges);
3360 }
3361 break;
3362
3363 default:
3364 CH_ERR(adap,
3365 "Unsupported chip version %d\n", chip_version);
3366 return;
3367 }
3368
3369 /*
3370 * Clear the register buffer and insert the appropriate register
3371 * values selected by the above register ranges.
3372 */
3373 memset(buf, 0, buf_size);
3374 for (range = 0; range < reg_ranges_size; range += 2) {
3375 unsigned int reg = reg_ranges[range];
3376 unsigned int last_reg = reg_ranges[range + 1];
3377 u32 *bufp = (u32 *)(buf + reg);
3378
3379 /*
3380 * Iterate across the register range filling in the register
3381 * buffer but don't write past the end of the register buffer.
3382 */
3383 while (reg <= last_reg && bufp < buf_end) {
3384 *bufp++ = t4_read_reg(adap, reg);
3385 reg += sizeof(u32);
3386 }
3387 }
3388 }
3389
3390 /*
3391 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID
3392 * header followed by one or more VPD-R sections, each with its own header.
3393 */
3394 struct t4_vpd_hdr {
3395 u8 id_tag;
3396 u8 id_len[2];
3397 u8 id_data[ID_LEN];
3398 };
3399
3400 struct t4_vpdr_hdr {
3401 u8 vpdr_tag;
3402 u8 vpdr_len[2];
3403 };
3404
3405 /*
3406 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
3407 */
3408 #define EEPROM_DELAY 10 /* 10us per poll spin */
3409 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
3410
3411 #define EEPROM_STAT_ADDR 0x7bfc
3412 #define VPD_SIZE 0x800
3413 #define VPD_BASE 0x400
3414 #define VPD_BASE_OLD 0
3415 #define VPD_LEN 1024
3416 #define VPD_INFO_FLD_HDR_SIZE 3
3417 #define CHELSIO_VPD_UNIQUE_ID 0x82
3418
3419 /*
3420 * Small utility function to wait till any outstanding VPD Access is complete.
3421 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
3422 * VPD Access in flight. This allows us to handle the problem of having a
3423 * previous VPD Access time out and prevent an attempt to inject a new VPD
3424 * Request before any in-flight VPD reguest has completed.
3425 */
t4_seeprom_wait(struct adapter * adapter)3426 static int t4_seeprom_wait(struct adapter *adapter)
3427 {
3428 unsigned int base = adapter->params.pci.vpd_cap_addr;
3429 int max_poll;
3430
3431 /*
3432 * If no VPD Access is in flight, we can just return success right
3433 * away.
3434 */
3435 if (!adapter->vpd_busy)
3436 return 0;
3437
3438 /*
3439 * Poll the VPD Capability Address/Flag register waiting for it
3440 * to indicate that the operation is complete.
3441 */
3442 max_poll = EEPROM_MAX_POLL;
3443 do {
3444 u16 val;
3445
3446 udelay(EEPROM_DELAY);
3447 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
3448
3449 /*
3450 * If the operation is complete, mark the VPD as no longer
3451 * busy and return success.
3452 */
3453 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
3454 adapter->vpd_busy = 0;
3455 return 0;
3456 }
3457 } while (--max_poll);
3458
3459 /*
3460 * Failure! Note that we leave the VPD Busy status set in order to
3461 * avoid pushing a new VPD Access request into the VPD Capability till
3462 * the current operation eventually succeeds. It's a bug to issue a
3463 * new request when an existing request is in flight and will result
3464 * in corrupt hardware state.
3465 */
3466 return -ETIMEDOUT;
3467 }
3468
3469 /**
3470 * t4_seeprom_read - read a serial EEPROM location
3471 * @adapter: adapter to read
3472 * @addr: EEPROM virtual address
3473 * @data: where to store the read data
3474 *
3475 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
3476 * VPD capability. Note that this function must be called with a virtual
3477 * address.
3478 */
t4_seeprom_read(struct adapter * adapter,u32 addr,u32 * data)3479 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
3480 {
3481 unsigned int base = adapter->params.pci.vpd_cap_addr;
3482 int ret;
3483
3484 /*
3485 * VPD Accesses must alway be 4-byte aligned!
3486 */
3487 if (addr >= EEPROMVSIZE || (addr & 3))
3488 return -EINVAL;
3489
3490 /*
3491 * Wait for any previous operation which may still be in flight to
3492 * complete.
3493 */
3494 ret = t4_seeprom_wait(adapter);
3495 if (ret) {
3496 CH_ERR(adapter, "VPD still busy from previous operation\n");
3497 return ret;
3498 }
3499
3500 /*
3501 * Issue our new VPD Read request, mark the VPD as being busy and wait
3502 * for our request to complete. If it doesn't complete, note the
3503 * error and return it to our caller. Note that we do not reset the
3504 * VPD Busy status!
3505 */
3506 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
3507 adapter->vpd_busy = 1;
3508 adapter->vpd_flag = PCI_VPD_ADDR_F;
3509 ret = t4_seeprom_wait(adapter);
3510 if (ret) {
3511 CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
3512 return ret;
3513 }
3514
3515 /*
3516 * Grab the returned data, swizzle it into our endianness and
3517 * return success.
3518 */
3519 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
3520 *data = le32_to_cpu(*data);
3521 return 0;
3522 }
3523
3524 /**
3525 * t4_seeprom_write - write a serial EEPROM location
3526 * @adapter: adapter to write
3527 * @addr: virtual EEPROM address
3528 * @data: value to write
3529 *
3530 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
3531 * VPD capability. Note that this function must be called with a virtual
3532 * address.
3533 */
t4_seeprom_write(struct adapter * adapter,u32 addr,u32 data)3534 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
3535 {
3536 unsigned int base = adapter->params.pci.vpd_cap_addr;
3537 int ret;
3538 u32 stats_reg;
3539 int max_poll;
3540
3541 /*
3542 * VPD Accesses must alway be 4-byte aligned!
3543 */
3544 if (addr >= EEPROMVSIZE || (addr & 3))
3545 return -EINVAL;
3546
3547 /*
3548 * Wait for any previous operation which may still be in flight to
3549 * complete.
3550 */
3551 ret = t4_seeprom_wait(adapter);
3552 if (ret) {
3553 CH_ERR(adapter, "VPD still busy from previous operation\n");
3554 return ret;
3555 }
3556
3557 /*
3558 * Issue our new VPD Read request, mark the VPD as being busy and wait
3559 * for our request to complete. If it doesn't complete, note the
3560 * error and return it to our caller. Note that we do not reset the
3561 * VPD Busy status!
3562 */
3563 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
3564 cpu_to_le32(data));
3565 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
3566 (u16)addr | PCI_VPD_ADDR_F);
3567 adapter->vpd_busy = 1;
3568 adapter->vpd_flag = 0;
3569 ret = t4_seeprom_wait(adapter);
3570 if (ret) {
3571 CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
3572 return ret;
3573 }
3574
3575 /*
3576 * Reset PCI_VPD_DATA register after a transaction and wait for our
3577 * request to complete. If it doesn't complete, return error.
3578 */
3579 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
3580 max_poll = EEPROM_MAX_POLL;
3581 do {
3582 udelay(EEPROM_DELAY);
3583 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
3584 } while ((stats_reg & 0x1) && --max_poll);
3585 if (!max_poll)
3586 return -ETIMEDOUT;
3587
3588 /* Return success! */
3589 return 0;
3590 }
3591
3592 /**
3593 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
3594 * @phys_addr: the physical EEPROM address
3595 * @fn: the PCI function number
3596 * @sz: size of function-specific area
3597 *
3598 * Translate a physical EEPROM address to virtual. The first 1K is
3599 * accessed through virtual addresses starting at 31K, the rest is
3600 * accessed through virtual addresses starting at 0.
3601 *
3602 * The mapping is as follows:
3603 * [0..1K) -> [31K..32K)
3604 * [1K..1K+A) -> [ES-A..ES)
3605 * [1K+A..ES) -> [0..ES-A-1K)
3606 *
3607 * where A = @fn * @sz, and ES = EEPROM size.
3608 */
t4_eeprom_ptov(unsigned int phys_addr,unsigned int fn,unsigned int sz)3609 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
3610 {
3611 fn *= sz;
3612 if (phys_addr < 1024)
3613 return phys_addr + (31 << 10);
3614 if (phys_addr < 1024 + fn)
3615 return EEPROMSIZE - fn + phys_addr - 1024;
3616 if (phys_addr < EEPROMSIZE)
3617 return phys_addr - 1024 - fn;
3618 return -EINVAL;
3619 }
3620
3621 /**
3622 * t4_seeprom_wp - enable/disable EEPROM write protection
3623 * @adapter: the adapter
3624 * @enable: whether to enable or disable write protection
3625 *
3626 * Enables or disables write protection on the serial EEPROM.
3627 */
t4_seeprom_wp(struct adapter * adapter,int enable)3628 int t4_seeprom_wp(struct adapter *adapter, int enable)
3629 {
3630 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
3631 }
3632
3633 /**
3634 * get_vpd_keyword_val - Locates an information field keyword in the VPD
3635 * @vpd: Pointer to buffered vpd data structure
3636 * @kw: The keyword to search for
3637 * @region: VPD region to search (starting from 0)
3638 *
3639 * Returns the value of the information field keyword or
3640 * -ENOENT otherwise.
3641 */
get_vpd_keyword_val(const u8 * vpd,const char * kw,int region)3642 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
3643 {
3644 int i, tag;
3645 unsigned int offset, len;
3646 const struct t4_vpdr_hdr *vpdr;
3647
3648 offset = sizeof(struct t4_vpd_hdr);
3649 vpdr = (const void *)(vpd + offset);
3650 tag = vpdr->vpdr_tag;
3651 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
3652 while (region--) {
3653 offset += sizeof(struct t4_vpdr_hdr) + len;
3654 vpdr = (const void *)(vpd + offset);
3655 if (++tag != vpdr->vpdr_tag)
3656 return -ENOENT;
3657 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
3658 }
3659 offset += sizeof(struct t4_vpdr_hdr);
3660
3661 if (offset + len > VPD_LEN) {
3662 return -ENOENT;
3663 }
3664
3665 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
3666 if (memcmp(vpd + i , kw , 2) == 0){
3667 i += VPD_INFO_FLD_HDR_SIZE;
3668 return i;
3669 }
3670
3671 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2];
3672 }
3673
3674 return -ENOENT;
3675 }
3676
3677
3678 /**
3679 * get_vpd_params - read VPD parameters from VPD EEPROM
3680 * @adapter: adapter to read
3681 * @p: where to store the parameters
3682 * @vpd: caller provided temporary space to read the VPD into
3683 *
3684 * Reads card parameters stored in VPD EEPROM.
3685 */
get_vpd_params(struct adapter * adapter,struct vpd_params * p,uint16_t device_id,u32 * buf)3686 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
3687 uint16_t device_id, u32 *buf)
3688 {
3689 int i, ret, addr;
3690 int ec, sn, pn, na, md;
3691 u8 csum;
3692 const u8 *vpd = (const u8 *)buf;
3693
3694 /*
3695 * Card information normally starts at VPD_BASE but early cards had
3696 * it at 0.
3697 */
3698 ret = t4_seeprom_read(adapter, VPD_BASE, buf);
3699 if (ret)
3700 return (ret);
3701
3702 /*
3703 * The VPD shall have a unique identifier specified by the PCI SIG.
3704 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
3705 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
3706 * is expected to automatically put this entry at the
3707 * beginning of the VPD.
3708 */
3709 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
3710
3711 for (i = 0; i < VPD_LEN; i += 4) {
3712 ret = t4_seeprom_read(adapter, addr + i, buf++);
3713 if (ret)
3714 return ret;
3715 }
3716
3717 #define FIND_VPD_KW(var,name) do { \
3718 var = get_vpd_keyword_val(vpd, name, 0); \
3719 if (var < 0) { \
3720 CH_ERR(adapter, "missing VPD keyword " name "\n"); \
3721 return -EINVAL; \
3722 } \
3723 } while (0)
3724
3725 FIND_VPD_KW(i, "RV");
3726 for (csum = 0; i >= 0; i--)
3727 csum += vpd[i];
3728
3729 if (csum) {
3730 CH_ERR(adapter,
3731 "corrupted VPD EEPROM, actual csum %u\n", csum);
3732 return -EINVAL;
3733 }
3734
3735 FIND_VPD_KW(ec, "EC");
3736 FIND_VPD_KW(sn, "SN");
3737 FIND_VPD_KW(pn, "PN");
3738 FIND_VPD_KW(na, "NA");
3739 #undef FIND_VPD_KW
3740
3741 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN);
3742 strstrip(p->id);
3743 memcpy(p->ec, vpd + ec, EC_LEN);
3744 strstrip(p->ec);
3745 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3746 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3747 strstrip(p->sn);
3748 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3749 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3750 strstrip((char *)p->pn);
3751 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3752 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3753 strstrip((char *)p->na);
3754
3755 if (device_id & 0x80)
3756 return 0; /* Custom card */
3757
3758 md = get_vpd_keyword_val(vpd, "VF", 1);
3759 if (md < 0) {
3760 snprintf(p->md, sizeof(p->md), "unknown");
3761 } else {
3762 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2];
3763 memcpy(p->md, vpd + md, min(i, MD_LEN));
3764 strstrip((char *)p->md);
3765 }
3766
3767 return 0;
3768 }
3769
3770 /* Flash Layout {start sector, # of sectors} for T4/T5/T6 adapters */
3771 static const struct t4_flash_loc_entry t4_flash_loc_arr[] = {
3772 [FLASH_LOC_EXP_ROM] = { 0, 6 },
3773 [FLASH_LOC_IBFT] = { 6, 1 },
3774 [FLASH_LOC_BOOTCFG] = { 7, 1 },
3775 [FLASH_LOC_FW] = { 8, 16 },
3776 [FLASH_LOC_FWBOOTSTRAP] = { 27, 1 },
3777 [FLASH_LOC_ISCSI_CRASH] = { 29, 1 },
3778 [FLASH_LOC_FCOE_CRASH] = { 30, 1 },
3779 [FLASH_LOC_CFG] = { 31, 1 },
3780 [FLASH_LOC_CUDBG] = { 32, 32 },
3781 [FLASH_LOC_BOOT_AREA] = { 0, 8 }, /* Spans complete Boot Area */
3782 [FLASH_LOC_END] = { 64, 0 },
3783 };
3784
3785 /* Flash Layout {start sector, # of sectors} for T7 adapters */
3786 static const struct t4_flash_loc_entry t7_flash_loc_arr[] = {
3787 [FLASH_LOC_VPD] = { 0, 1 },
3788 [FLASH_LOC_FWBOOTSTRAP] = { 1, 1 },
3789 [FLASH_LOC_FW] = { 2, 29 },
3790 [FLASH_LOC_CFG] = { 31, 1 },
3791 [FLASH_LOC_EXP_ROM] = { 32, 15 },
3792 [FLASH_LOC_IBFT] = { 47, 1 },
3793 [FLASH_LOC_BOOTCFG] = { 48, 1 },
3794 [FLASH_LOC_DPU_BOOT] = { 49, 13 },
3795 [FLASH_LOC_ISCSI_CRASH] = { 62, 1 },
3796 [FLASH_LOC_FCOE_CRASH] = { 63, 1 },
3797 [FLASH_LOC_VPD_BACKUP] = { 64, 1 },
3798 [FLASH_LOC_FWBOOTSTRAP_BACKUP] = { 65, 1 },
3799 [FLASH_LOC_FW_BACKUP] = { 66, 29 },
3800 [FLASH_LOC_CFG_BACK] = { 95, 1 },
3801 [FLASH_LOC_CUDBG] = { 96, 48 },
3802 [FLASH_LOC_CHIP_DUMP] = { 144, 48 },
3803 [FLASH_LOC_DPU_AREA] = { 192, 64 },
3804 [FLASH_LOC_BOOT_AREA] = { 32, 17 }, /* Spans complete UEFI/PXE Boot Area */
3805 [FLASH_LOC_END] = { 256, 0 },
3806 };
3807
3808 int
t4_flash_loc_start(struct adapter * adap,enum t4_flash_loc loc,unsigned int * lenp)3809 t4_flash_loc_start(struct adapter *adap, enum t4_flash_loc loc,
3810 unsigned int *lenp)
3811 {
3812 const struct t4_flash_loc_entry *l = chip_id(adap) >= CHELSIO_T7 ?
3813 &t7_flash_loc_arr[loc] : &t4_flash_loc_arr[loc];
3814
3815 if (lenp != NULL)
3816 *lenp = FLASH_MAX_SIZE(l->nsecs);
3817 return (FLASH_START(l->start_sec));
3818 }
3819
3820 /* serial flash and firmware constants and flash config file constants */
3821 enum {
3822 SF_ATTEMPTS = 10, /* max retries for SF operations */
3823
3824 /* flash command opcodes */
3825 SF_PROG_PAGE = 2, /* program 256B page */
3826 SF_WR_DISABLE = 4, /* disable writes */
3827 SF_RD_STATUS = 5, /* read status register */
3828 SF_WR_ENABLE = 6, /* enable writes */
3829 SF_RD_DATA_FAST = 0xb, /* read flash */
3830 SF_RD_ID = 0x9f, /* read ID */
3831 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */
3832 };
3833
3834 /**
3835 * sf1_read - read data from the serial flash
3836 * @adapter: the adapter
3837 * @byte_cnt: number of bytes to read
3838 * @cont: whether another operation will be chained
3839 * @lock: whether to lock SF for PL access only
3840 * @valp: where to store the read data
3841 *
3842 * Reads up to 4 bytes of data from the serial flash. The location of
3843 * the read needs to be specified prior to calling this by issuing the
3844 * appropriate commands to the serial flash.
3845 */
sf1_read(struct adapter * adapter,unsigned int byte_cnt,int cont,int lock,u32 * valp)3846 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3847 int lock, u32 *valp)
3848 {
3849 int ret;
3850 uint32_t op;
3851
3852 if (!byte_cnt || byte_cnt > 4)
3853 return -EINVAL;
3854 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3855 return -EBUSY;
3856 op = V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1);
3857 if (chip_id(adapter) >= CHELSIO_T7)
3858 op |= F_QUADREADDISABLE;
3859 t4_write_reg(adapter, A_SF_OP, op);
3860 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3861 if (!ret)
3862 *valp = t4_read_reg(adapter, A_SF_DATA);
3863 return ret;
3864 }
3865
3866 /**
3867 * sf1_write - write data to the serial flash
3868 * @adapter: the adapter
3869 * @byte_cnt: number of bytes to write
3870 * @cont: whether another operation will be chained
3871 * @lock: whether to lock SF for PL access only
3872 * @val: value to write
3873 *
3874 * Writes up to 4 bytes of data to the serial flash. The location of
3875 * the write needs to be specified prior to calling this by issuing the
3876 * appropriate commands to the serial flash.
3877 */
sf1_write(struct adapter * adapter,unsigned int byte_cnt,int cont,int lock,u32 val)3878 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3879 int lock, u32 val)
3880 {
3881 if (!byte_cnt || byte_cnt > 4)
3882 return -EINVAL;
3883 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3884 return -EBUSY;
3885 t4_write_reg(adapter, A_SF_DATA, val);
3886 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3887 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3888 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3889 }
3890
3891 /**
3892 * flash_wait_op - wait for a flash operation to complete
3893 * @adapter: the adapter
3894 * @attempts: max number of polls of the status register
3895 * @delay: delay between polls in ms
3896 *
3897 * Wait for a flash operation to complete by polling the status register.
3898 */
flash_wait_op(struct adapter * adapter,int attempts,int delay)3899 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3900 {
3901 int ret;
3902 u32 status;
3903
3904 while (1) {
3905 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3906 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3907 return ret;
3908 if (!(status & 1))
3909 return 0;
3910 if (--attempts == 0)
3911 return -EAGAIN;
3912 if (delay)
3913 msleep(delay);
3914 }
3915 }
3916
3917 /**
3918 * t4_read_flash - read words from serial flash
3919 * @adapter: the adapter
3920 * @addr: the start address for the read
3921 * @nwords: how many 32-bit words to read
3922 * @data: where to store the read data
3923 * @byte_oriented: whether to store data as bytes or as words
3924 *
3925 * Read the specified number of 32-bit words from the serial flash.
3926 * If @byte_oriented is set the read data is stored as a byte array
3927 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3928 * natural endianness.
3929 */
t4_read_flash(struct adapter * adapter,unsigned int addr,unsigned int nwords,u32 * data,int byte_oriented)3930 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3931 unsigned int nwords, u32 *data, int byte_oriented)
3932 {
3933 int ret;
3934
3935 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3936 return -EINVAL;
3937
3938 addr = swab32(addr) | SF_RD_DATA_FAST;
3939
3940 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3941 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3942 return ret;
3943
3944 for ( ; nwords; nwords--, data++) {
3945 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3946 if (nwords == 1)
3947 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3948 if (ret)
3949 return ret;
3950 if (byte_oriented)
3951 *data = (__force __u32)(cpu_to_be32(*data));
3952 }
3953 return 0;
3954 }
3955
3956 /**
3957 * t4_write_flash - write up to a page of data to the serial flash
3958 * @adapter: the adapter
3959 * @addr: the start address to write
3960 * @n: length of data to write in bytes
3961 * @data: the data to write
3962 * @byte_oriented: whether to store data as bytes or as words
3963 *
3964 * Writes up to a page of data (256 bytes) to the serial flash starting
3965 * at the given address. All the data must be written to the same page.
3966 * If @byte_oriented is set the write data is stored as byte stream
3967 * (i.e. matches what on disk), otherwise in big-endian.
3968 */
t4_write_flash(struct adapter * adapter,unsigned int addr,unsigned int n,const u8 * data,int byte_oriented)3969 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3970 unsigned int n, const u8 *data, int byte_oriented)
3971 {
3972 int ret;
3973 u32 buf[SF_PAGE_SIZE / 4];
3974 unsigned int i, c, left, val, offset = addr & 0xff;
3975
3976 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3977 return -EINVAL;
3978
3979 val = swab32(addr) | SF_PROG_PAGE;
3980
3981 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3982 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3983 goto unlock;
3984
3985 for (left = n; left; left -= c) {
3986 c = min(left, 4U);
3987 for (val = 0, i = 0; i < c; ++i)
3988 val = (val << 8) + *data++;
3989
3990 if (!byte_oriented)
3991 val = cpu_to_be32(val);
3992
3993 ret = sf1_write(adapter, c, c != left, 1, val);
3994 if (ret)
3995 goto unlock;
3996 }
3997 ret = flash_wait_op(adapter, 8, 1);
3998 if (ret)
3999 goto unlock;
4000
4001 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4002
4003 /* Read the page to verify the write succeeded */
4004 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
4005 byte_oriented);
4006 if (ret)
4007 return ret;
4008
4009 if (memcmp(data - n, (u8 *)buf + offset, n)) {
4010 CH_ERR(adapter,
4011 "failed to correctly write the flash page at %#x\n",
4012 addr);
4013 return -EIO;
4014 }
4015 return 0;
4016
4017 unlock:
4018 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4019 return ret;
4020 }
4021
4022 /**
4023 * t4_get_fw_version - read the firmware version
4024 * @adapter: the adapter
4025 * @vers: where to place the version
4026 *
4027 * Reads the FW version from flash.
4028 */
t4_get_fw_version(struct adapter * adapter,u32 * vers)4029 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
4030 {
4031 const int start = t4_flash_loc_start(adapter, FLASH_LOC_FW, NULL);
4032
4033 return t4_read_flash(adapter, start + offsetof(struct fw_hdr, fw_ver),
4034 1, vers, 0);
4035 }
4036
4037 /**
4038 * t4_get_fw_hdr - read the firmware header
4039 * @adapter: the adapter
4040 * @hdr: where to place the version
4041 *
4042 * Reads the FW header from flash into caller provided buffer.
4043 */
t4_get_fw_hdr(struct adapter * adapter,struct fw_hdr * hdr)4044 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
4045 {
4046 const int start = t4_flash_loc_start(adapter, FLASH_LOC_FW, NULL);
4047
4048 return t4_read_flash(adapter, start, sizeof (*hdr) / sizeof (uint32_t),
4049 (uint32_t *)hdr, 1);
4050 }
4051
4052 /**
4053 * t4_get_bs_version - read the firmware bootstrap version
4054 * @adapter: the adapter
4055 * @vers: where to place the version
4056 *
4057 * Reads the FW Bootstrap version from flash.
4058 */
t4_get_bs_version(struct adapter * adapter,u32 * vers)4059 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
4060 {
4061 const int start = t4_flash_loc_start(adapter, FLASH_LOC_FWBOOTSTRAP,
4062 NULL);
4063
4064 return t4_read_flash(adapter, start + offsetof(struct fw_hdr, fw_ver),
4065 1, vers, 0);
4066 }
4067
4068 /**
4069 * t4_get_tp_version - read the TP microcode version
4070 * @adapter: the adapter
4071 * @vers: where to place the version
4072 *
4073 * Reads the TP microcode version from flash.
4074 */
t4_get_tp_version(struct adapter * adapter,u32 * vers)4075 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
4076 {
4077 const int start = t4_flash_loc_start(adapter, FLASH_LOC_FW, NULL);
4078
4079 return t4_read_flash(adapter, start +
4080 offsetof(struct fw_hdr, tp_microcode_ver), 1, vers, 0);
4081 }
4082
4083 /**
4084 * t4_get_exprom_version - return the Expansion ROM version (if any)
4085 * @adapter: the adapter
4086 * @vers: where to place the version
4087 *
4088 * Reads the Expansion ROM header from FLASH and returns the version
4089 * number (if present) through the @vers return value pointer. We return
4090 * this in the Firmware Version Format since it's convenient. Return
4091 * 0 on success, -ENOENT if no Expansion ROM is present.
4092 */
t4_get_exprom_version(struct adapter * adapter,u32 * vers)4093 int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
4094 {
4095 struct exprom_header {
4096 unsigned char hdr_arr[16]; /* must start with 0x55aa */
4097 unsigned char hdr_ver[4]; /* Expansion ROM version */
4098 } *hdr;
4099 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
4100 sizeof(u32))];
4101 int ret;
4102 const int start = t4_flash_loc_start(adapter, FLASH_LOC_EXP_ROM, NULL);
4103
4104 ret = t4_read_flash(adapter, start, ARRAY_SIZE(exprom_header_buf),
4105 exprom_header_buf, 0);
4106 if (ret)
4107 return ret;
4108
4109 hdr = (struct exprom_header *)exprom_header_buf;
4110 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
4111 return -ENOENT;
4112
4113 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
4114 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
4115 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
4116 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
4117 return 0;
4118 }
4119
4120 /**
4121 * t4_get_scfg_version - return the Serial Configuration version
4122 * @adapter: the adapter
4123 * @vers: where to place the version
4124 *
4125 * Reads the Serial Configuration Version via the Firmware interface
4126 * (thus this can only be called once we're ready to issue Firmware
4127 * commands). The format of the Serial Configuration version is
4128 * adapter specific. Returns 0 on success, an error on failure.
4129 *
4130 * Note that early versions of the Firmware didn't include the ability
4131 * to retrieve the Serial Configuration version, so we zero-out the
4132 * return-value parameter in that case to avoid leaving it with
4133 * garbage in it.
4134 *
4135 * Also note that the Firmware will return its cached copy of the Serial
4136 * Initialization Revision ID, not the actual Revision ID as written in
4137 * the Serial EEPROM. This is only an issue if a new VPD has been written
4138 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
4139 * it's best to defer calling this routine till after a FW_RESET_CMD has
4140 * been issued if the Host Driver will be performing a full adapter
4141 * initialization.
4142 */
t4_get_scfg_version(struct adapter * adapter,u32 * vers)4143 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
4144 {
4145 u32 scfgrev_param;
4146 int ret;
4147
4148 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4149 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
4150 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
4151 1, &scfgrev_param, vers);
4152 if (ret)
4153 *vers = 0;
4154 return ret;
4155 }
4156
4157 /**
4158 * t4_get_vpd_version - return the VPD version
4159 * @adapter: the adapter
4160 * @vers: where to place the version
4161 *
4162 * Reads the VPD via the Firmware interface (thus this can only be called
4163 * once we're ready to issue Firmware commands). The format of the
4164 * VPD version is adapter specific. Returns 0 on success, an error on
4165 * failure.
4166 *
4167 * Note that early versions of the Firmware didn't include the ability
4168 * to retrieve the VPD version, so we zero-out the return-value parameter
4169 * in that case to avoid leaving it with garbage in it.
4170 *
4171 * Also note that the Firmware will return its cached copy of the VPD
4172 * Revision ID, not the actual Revision ID as written in the Serial
4173 * EEPROM. This is only an issue if a new VPD has been written and the
4174 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
4175 * to defer calling this routine till after a FW_RESET_CMD has been issued
4176 * if the Host Driver will be performing a full adapter initialization.
4177 */
t4_get_vpd_version(struct adapter * adapter,u32 * vers)4178 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
4179 {
4180 u32 vpdrev_param;
4181 int ret;
4182
4183 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4184 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
4185 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
4186 1, &vpdrev_param, vers);
4187 if (ret)
4188 *vers = 0;
4189 return ret;
4190 }
4191
4192 /**
4193 * t4_get_version_info - extract various chip/firmware version information
4194 * @adapter: the adapter
4195 *
4196 * Reads various chip/firmware version numbers and stores them into the
4197 * adapter Adapter Parameters structure. If any of the efforts fails
4198 * the first failure will be returned, but all of the version numbers
4199 * will be read.
4200 */
t4_get_version_info(struct adapter * adapter)4201 int t4_get_version_info(struct adapter *adapter)
4202 {
4203 int ret = 0;
4204
4205 #define FIRST_RET(__getvinfo) \
4206 do { \
4207 int __ret = __getvinfo; \
4208 if (__ret && !ret) \
4209 ret = __ret; \
4210 } while (0)
4211
4212 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
4213 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
4214 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
4215 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
4216 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
4217 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
4218
4219 #undef FIRST_RET
4220
4221 return ret;
4222 }
4223
4224 /**
4225 * t4_flash_erase_sectors - erase a range of flash sectors
4226 * @adapter: the adapter
4227 * @start: the first sector to erase
4228 * @end: the last sector to erase
4229 *
4230 * Erases the sectors in the given inclusive range.
4231 */
t4_flash_erase_sectors(struct adapter * adapter,int start,int end)4232 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
4233 {
4234 int ret = 0;
4235
4236 if (end >= adapter->params.sf_nsec)
4237 return -EINVAL;
4238
4239 while (start <= end) {
4240 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
4241 (ret = sf1_write(adapter, 4, 0, 1,
4242 SF_ERASE_SECTOR | (start << 8))) != 0 ||
4243 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
4244 CH_ERR(adapter,
4245 "erase of flash sector %d failed, error %d\n",
4246 start, ret);
4247 break;
4248 }
4249 start++;
4250 }
4251 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4252 return ret;
4253 }
4254
4255 /**
4256 * t4_flash_cfg_addr - return the address of the flash configuration file
4257 * @adapter: the adapter
4258 *
4259 * Return the address within the flash where the Firmware Configuration
4260 * File is stored, or an error if the device FLASH is too small to contain
4261 * a Firmware Configuration File.
4262 */
t4_flash_cfg_addr(struct adapter * adapter,unsigned int * lenp)4263 int t4_flash_cfg_addr(struct adapter *adapter, unsigned int *lenp)
4264 {
4265 unsigned int len = 0;
4266 const int cfg_start = t4_flash_loc_start(adapter, FLASH_LOC_CFG, &len);
4267
4268 /*
4269 * If the device FLASH isn't large enough to hold a Firmware
4270 * Configuration File, return an error.
4271 */
4272 if (adapter->params.sf_size < cfg_start + len)
4273 return -ENOSPC;
4274 if (lenp != NULL)
4275 *lenp = len;
4276 return (cfg_start);
4277 }
4278
4279 /*
4280 * Return TRUE if the specified firmware matches the adapter. I.e. T4
4281 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
4282 * and emit an error message for mismatched firmware to save our caller the
4283 * effort ...
4284 */
t4_fw_matches_chip(struct adapter * adap,const struct fw_hdr * hdr)4285 static int t4_fw_matches_chip(struct adapter *adap,
4286 const struct fw_hdr *hdr)
4287 {
4288 /*
4289 * The expression below will return FALSE for any unsupported adapter
4290 * which will keep us "honest" in the future ...
4291 */
4292 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
4293 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
4294 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6) ||
4295 (is_t7(adap) && hdr->chip == FW_HDR_CHIP_T7))
4296 return 1;
4297
4298 CH_ERR(adap,
4299 "FW image (%d) is not suitable for this adapter (%d)\n",
4300 hdr->chip, chip_id(adap));
4301 return 0;
4302 }
4303
4304 /**
4305 * t4_load_fw - download firmware
4306 * @adap: the adapter
4307 * @fw_data: the firmware image to write
4308 * @size: image size
4309 *
4310 * Write the supplied firmware image to the card's serial flash.
4311 */
t4_load_fw(struct adapter * adap,const u8 * fw_data,unsigned int size)4312 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
4313 {
4314 u32 csum;
4315 int ret, addr;
4316 unsigned int i;
4317 u8 first_page[SF_PAGE_SIZE];
4318 const u32 *p = (const u32 *)fw_data;
4319 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
4320 unsigned int fw_start_sec;
4321 unsigned int fw_start;
4322 unsigned int fw_size;
4323 enum t4_flash_loc loc;
4324
4325 loc = ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP ?
4326 FLASH_LOC_FWBOOTSTRAP : FLASH_LOC_FW;
4327 fw_start = t4_flash_loc_start(adap, loc, &fw_size);
4328 fw_start_sec = fw_start / SF_SEC_SIZE;
4329
4330 if (!size) {
4331 CH_ERR(adap, "FW image has no data\n");
4332 return -EINVAL;
4333 }
4334 if (size & 511) {
4335 CH_ERR(adap,
4336 "FW image size not multiple of 512 bytes\n");
4337 return -EINVAL;
4338 }
4339 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
4340 CH_ERR(adap,
4341 "FW image size differs from size in FW header\n");
4342 return -EINVAL;
4343 }
4344 if (size > fw_size) {
4345 CH_ERR(adap, "FW image too large, max is %u bytes\n",
4346 fw_size);
4347 return -EFBIG;
4348 }
4349 if (!t4_fw_matches_chip(adap, hdr))
4350 return -EINVAL;
4351
4352 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
4353 csum += be32_to_cpu(p[i]);
4354
4355 if (csum != 0xffffffff) {
4356 CH_ERR(adap,
4357 "corrupted firmware image, checksum %#x\n", csum);
4358 return -EINVAL;
4359 }
4360
4361 i = DIV_ROUND_UP(size, SF_SEC_SIZE); /* # of sectors spanned */
4362 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
4363 if (ret)
4364 goto out;
4365
4366 /*
4367 * We write the correct version at the end so the driver can see a bad
4368 * version if the FW write fails. Start by writing a copy of the
4369 * first page with a bad version.
4370 */
4371 memcpy(first_page, fw_data, SF_PAGE_SIZE);
4372 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
4373 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
4374 if (ret)
4375 goto out;
4376
4377 addr = fw_start;
4378 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
4379 addr += SF_PAGE_SIZE;
4380 fw_data += SF_PAGE_SIZE;
4381 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
4382 if (ret)
4383 goto out;
4384 }
4385
4386 ret = t4_write_flash(adap,
4387 fw_start + offsetof(struct fw_hdr, fw_ver),
4388 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
4389 out:
4390 if (ret)
4391 CH_ERR(adap, "firmware download failed, error %d\n",
4392 ret);
4393 return ret;
4394 }
4395
4396 /**
4397 * t4_fwcache - firmware cache operation
4398 * @adap: the adapter
4399 * @op : the operation (flush or flush and invalidate)
4400 */
t4_fwcache(struct adapter * adap,enum fw_params_param_dev_fwcache op)4401 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
4402 {
4403 struct fw_params_cmd c;
4404
4405 memset(&c, 0, sizeof(c));
4406 c.op_to_vfn =
4407 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
4408 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4409 V_FW_PARAMS_CMD_PFN(adap->pf) |
4410 V_FW_PARAMS_CMD_VFN(0));
4411 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4412 c.param[0].mnem =
4413 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4414 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
4415 c.param[0].val = cpu_to_be32(op);
4416
4417 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
4418 }
4419
t4_cim_read_pif_la(struct adapter * adap,u32 * pif_req,u32 * pif_rsp,unsigned int * pif_req_wrptr,unsigned int * pif_rsp_wrptr)4420 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
4421 unsigned int *pif_req_wrptr,
4422 unsigned int *pif_rsp_wrptr)
4423 {
4424 int i, j;
4425 u32 cfg, val, req, rsp;
4426
4427 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
4428 if (cfg & F_LADBGEN)
4429 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
4430
4431 val = t4_read_reg(adap, A_CIM_DEBUGSTS);
4432 req = G_POLADBGWRPTR(val);
4433 rsp = G_PILADBGWRPTR(val);
4434 if (pif_req_wrptr)
4435 *pif_req_wrptr = req;
4436 if (pif_rsp_wrptr)
4437 *pif_rsp_wrptr = rsp;
4438
4439 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
4440 for (j = 0; j < 6; j++) {
4441 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
4442 V_PILADBGRDPTR(rsp));
4443 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
4444 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
4445 req++;
4446 rsp++;
4447 }
4448 req = (req + 2) & M_POLADBGRDPTR;
4449 rsp = (rsp + 2) & M_PILADBGRDPTR;
4450 }
4451 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
4452 }
4453
t4_cim_read_ma_la(struct adapter * adap,u32 * ma_req,u32 * ma_rsp)4454 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
4455 {
4456 u32 cfg;
4457 int i, j, idx;
4458
4459 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
4460 if (cfg & F_LADBGEN)
4461 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
4462
4463 for (i = 0; i < CIM_MALA_SIZE; i++) {
4464 for (j = 0; j < 5; j++) {
4465 idx = 8 * i + j;
4466 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
4467 V_PILADBGRDPTR(idx));
4468 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
4469 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
4470 }
4471 }
4472 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
4473 }
4474
t4_ulprx_read_la(struct adapter * adap,u32 * la_buf)4475 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
4476 {
4477 unsigned int i, j;
4478
4479 for (i = 0; i < 8; i++) {
4480 u32 *p = la_buf + i;
4481
4482 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
4483 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
4484 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
4485 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
4486 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
4487 }
4488 }
4489
4490 /**
4491 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
4492 * @caps16: a 16-bit Port Capabilities value
4493 *
4494 * Returns the equivalent 32-bit Port Capabilities value.
4495 */
fwcaps16_to_caps32(uint16_t caps16)4496 static uint32_t fwcaps16_to_caps32(uint16_t caps16)
4497 {
4498 uint32_t caps32 = 0;
4499
4500 #define CAP16_TO_CAP32(__cap) \
4501 do { \
4502 if (caps16 & FW_PORT_CAP_##__cap) \
4503 caps32 |= FW_PORT_CAP32_##__cap; \
4504 } while (0)
4505
4506 CAP16_TO_CAP32(SPEED_100M);
4507 CAP16_TO_CAP32(SPEED_1G);
4508 CAP16_TO_CAP32(SPEED_25G);
4509 CAP16_TO_CAP32(SPEED_10G);
4510 CAP16_TO_CAP32(SPEED_40G);
4511 CAP16_TO_CAP32(SPEED_100G);
4512 CAP16_TO_CAP32(FC_RX);
4513 CAP16_TO_CAP32(FC_TX);
4514 CAP16_TO_CAP32(ANEG);
4515 CAP16_TO_CAP32(FORCE_PAUSE);
4516 CAP16_TO_CAP32(MDIAUTO);
4517 CAP16_TO_CAP32(MDISTRAIGHT);
4518 CAP16_TO_CAP32(FEC_RS);
4519 CAP16_TO_CAP32(FEC_BASER_RS);
4520 CAP16_TO_CAP32(802_3_PAUSE);
4521 CAP16_TO_CAP32(802_3_ASM_DIR);
4522
4523 #undef CAP16_TO_CAP32
4524
4525 return caps32;
4526 }
4527
4528 /**
4529 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4530 * @caps32: a 32-bit Port Capabilities value
4531 *
4532 * Returns the equivalent 16-bit Port Capabilities value. Note that
4533 * not all 32-bit Port Capabilities can be represented in the 16-bit
4534 * Port Capabilities and some fields/values may not make it.
4535 */
fwcaps32_to_caps16(uint32_t caps32)4536 static uint16_t fwcaps32_to_caps16(uint32_t caps32)
4537 {
4538 uint16_t caps16 = 0;
4539
4540 #define CAP32_TO_CAP16(__cap) \
4541 do { \
4542 if (caps32 & FW_PORT_CAP32_##__cap) \
4543 caps16 |= FW_PORT_CAP_##__cap; \
4544 } while (0)
4545
4546 CAP32_TO_CAP16(SPEED_100M);
4547 CAP32_TO_CAP16(SPEED_1G);
4548 CAP32_TO_CAP16(SPEED_10G);
4549 CAP32_TO_CAP16(SPEED_25G);
4550 CAP32_TO_CAP16(SPEED_40G);
4551 CAP32_TO_CAP16(SPEED_100G);
4552 CAP32_TO_CAP16(FC_RX);
4553 CAP32_TO_CAP16(FC_TX);
4554 CAP32_TO_CAP16(802_3_PAUSE);
4555 CAP32_TO_CAP16(802_3_ASM_DIR);
4556 CAP32_TO_CAP16(ANEG);
4557 CAP32_TO_CAP16(FORCE_PAUSE);
4558 CAP32_TO_CAP16(MDIAUTO);
4559 CAP32_TO_CAP16(MDISTRAIGHT);
4560 CAP32_TO_CAP16(FEC_RS);
4561 CAP32_TO_CAP16(FEC_BASER_RS);
4562
4563 #undef CAP32_TO_CAP16
4564
4565 return caps16;
4566 }
4567
fwcap_to_fec(uint32_t caps,bool unset_means_none)4568 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none)
4569 {
4570 int8_t fec = 0;
4571
4572 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0)
4573 return (unset_means_none ? FEC_NONE : 0);
4574
4575 if (caps & FW_PORT_CAP32_FEC_RS)
4576 fec |= FEC_RS;
4577 if (caps & FW_PORT_CAP32_FEC_BASER_RS)
4578 fec |= FEC_BASER_RS;
4579 if (caps & FW_PORT_CAP32_FEC_NO_FEC)
4580 fec |= FEC_NONE;
4581
4582 return (fec);
4583 }
4584
4585 /*
4586 * Note that 0 is not translated to NO_FEC.
4587 */
fec_to_fwcap(int8_t fec)4588 static uint32_t fec_to_fwcap(int8_t fec)
4589 {
4590 uint32_t caps = 0;
4591
4592 /* Only real FECs allowed. */
4593 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0);
4594
4595 if (fec & FEC_RS)
4596 caps |= FW_PORT_CAP32_FEC_RS;
4597 if (fec & FEC_BASER_RS)
4598 caps |= FW_PORT_CAP32_FEC_BASER_RS;
4599 if (fec & FEC_NONE)
4600 caps |= FW_PORT_CAP32_FEC_NO_FEC;
4601
4602 return (caps);
4603 }
4604
4605 /**
4606 * t4_link_l1cfg - apply link configuration to MAC/PHY
4607 * @phy: the PHY to setup
4608 * @mac: the MAC to setup
4609 * @lc: the requested link configuration
4610 *
4611 * Set up a port's MAC and PHY according to a desired link configuration.
4612 * - If the PHY can auto-negotiate first decide what to advertise, then
4613 * enable/disable auto-negotiation as desired, and reset.
4614 * - If the PHY does not auto-negotiate just reset it.
4615 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4616 * otherwise do it later based on the outcome of auto-negotiation.
4617 */
t4_link_l1cfg(struct adapter * adap,unsigned int mbox,unsigned int port,struct link_config * lc)4618 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
4619 struct link_config *lc)
4620 {
4621 struct fw_port_cmd c;
4622 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
4623 unsigned int aneg, fc, fec, speed, rcap;
4624
4625 fc = 0;
4626 if (lc->requested_fc & PAUSE_RX)
4627 fc |= FW_PORT_CAP32_FC_RX;
4628 if (lc->requested_fc & PAUSE_TX)
4629 fc |= FW_PORT_CAP32_FC_TX;
4630 if (!(lc->requested_fc & PAUSE_AUTONEG))
4631 fc |= FW_PORT_CAP32_FORCE_PAUSE;
4632
4633 if (lc->requested_aneg == AUTONEG_DISABLE)
4634 aneg = 0;
4635 else if (lc->requested_aneg == AUTONEG_ENABLE)
4636 aneg = FW_PORT_CAP32_ANEG;
4637 else
4638 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
4639
4640 if (aneg) {
4641 speed = lc->pcaps &
4642 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
4643 } else if (lc->requested_speed != 0)
4644 speed = speed_to_fwcap(lc->requested_speed);
4645 else
4646 speed = fwcap_top_speed(lc->pcaps);
4647
4648 fec = 0;
4649 if (fec_supported(speed)) {
4650 int force_fec;
4651
4652 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
4653 force_fec = lc->force_fec;
4654 else
4655 force_fec = 0;
4656
4657 if (lc->requested_fec == FEC_AUTO) {
4658 if (force_fec > 0) {
4659 /*
4660 * Must use FORCE_FEC even though requested FEC
4661 * is AUTO. Set all the FEC bits valid for the
4662 * speed and let the firmware pick one.
4663 */
4664 fec |= FW_PORT_CAP32_FORCE_FEC;
4665 if (speed & FW_PORT_CAP32_SPEED_25G) {
4666 fec |= FW_PORT_CAP32_FEC_RS;
4667 fec |= FW_PORT_CAP32_FEC_BASER_RS;
4668 fec |= FW_PORT_CAP32_FEC_NO_FEC;
4669 } else {
4670 fec |= FW_PORT_CAP32_FEC_RS;
4671 fec |= FW_PORT_CAP32_FEC_NO_FEC;
4672 }
4673 } else {
4674 /*
4675 * Set only 1b. Old firmwares can't deal with
4676 * multiple bits and new firmwares are free to
4677 * ignore this and try whatever FECs they want
4678 * because we aren't setting FORCE_FEC here.
4679 */
4680 fec |= fec_to_fwcap(lc->fec_hint);
4681 MPASS(powerof2(fec));
4682
4683 /*
4684 * Override the hint if the FEC is not valid for
4685 * the potential top speed. Request the best
4686 * FEC at that speed instead.
4687 */
4688 if ((speed & FW_PORT_CAP32_SPEED_25G) == 0 &&
4689 fec == FW_PORT_CAP32_FEC_BASER_RS) {
4690 fec = FW_PORT_CAP32_FEC_RS;
4691 }
4692 }
4693 } else {
4694 /*
4695 * User has explicitly requested some FEC(s). Set
4696 * FORCE_FEC unless prohibited from using it.
4697 */
4698 if (force_fec != 0)
4699 fec |= FW_PORT_CAP32_FORCE_FEC;
4700 fec |= fec_to_fwcap(lc->requested_fec &
4701 M_FW_PORT_CAP32_FEC);
4702 if (lc->requested_fec & FEC_MODULE)
4703 fec |= fec_to_fwcap(lc->fec_hint);
4704 }
4705
4706 /*
4707 * This is for compatibility with old firmwares. The original
4708 * way to request NO_FEC was to not set any of the FEC bits. New
4709 * firmwares understand this too.
4710 */
4711 if (fec == FW_PORT_CAP32_FEC_NO_FEC)
4712 fec = 0;
4713 }
4714
4715 /* Force AN on for BT cards. */
4716 if (isset(&adap->bt_map, port))
4717 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
4718
4719 rcap = aneg | speed | fc | fec;
4720 if ((rcap | lc->pcaps) != lc->pcaps) {
4721 #ifdef INVARIANTS
4722 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap,
4723 lc->pcaps, rcap & (rcap ^ lc->pcaps));
4724 #endif
4725 rcap &= lc->pcaps;
4726 }
4727 rcap |= mdi;
4728
4729 memset(&c, 0, sizeof(c));
4730 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4731 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4732 V_FW_PORT_CMD_PORTID(port));
4733 if (adap->params.port_caps32) {
4734 c.action_to_len16 =
4735 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
4736 FW_LEN16(c));
4737 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4738 } else {
4739 c.action_to_len16 =
4740 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
4741 FW_LEN16(c));
4742 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4743 }
4744
4745 lc->requested_caps = rcap;
4746 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4747 }
4748
4749 /**
4750 * t4_restart_aneg - restart autonegotiation
4751 * @adap: the adapter
4752 * @mbox: mbox to use for the FW command
4753 * @port: the port id
4754 *
4755 * Restarts autonegotiation for the selected port.
4756 */
t4_restart_aneg(struct adapter * adap,unsigned int mbox,unsigned int port)4757 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4758 {
4759 struct fw_port_cmd c;
4760
4761 memset(&c, 0, sizeof(c));
4762 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4763 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4764 V_FW_PORT_CMD_PORTID(port));
4765 c.action_to_len16 =
4766 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
4767 FW_LEN16(c));
4768 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4769 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4770 }
4771
4772 struct intr_details {
4773 u32 mask;
4774 const char *msg;
4775 };
4776
4777 struct intr_action {
4778 u32 mask;
4779 int arg;
4780 bool (*action)(struct adapter *, int, int);
4781 };
4782
4783 struct intr_info {
4784 const char *name; /* name of the INT_CAUSE register */
4785 int cause_reg; /* INT_CAUSE register */
4786 int enable_reg; /* INT_ENABLE register */
4787 u32 fatal; /* bits that are fatal */
4788 int flags; /* hints */
4789 const struct intr_details *details;
4790 const struct intr_action *actions;
4791 };
4792
4793 static inline char
intr_alert_char(u32 cause,u32 enable,u32 fatal)4794 intr_alert_char(u32 cause, u32 enable, u32 fatal)
4795 {
4796
4797 if (cause & fatal)
4798 return ('!');
4799 if (cause & enable)
4800 return ('*');
4801 return ('-');
4802 }
4803
4804 static void
show_intr_info(struct adapter * sc,const struct intr_info * ii,uint32_t cause,uint32_t ucause,uint32_t enabled,uint32_t fatal,int flags)4805 show_intr_info(struct adapter *sc, const struct intr_info *ii, uint32_t cause,
4806 uint32_t ucause, uint32_t enabled, uint32_t fatal, int flags)
4807 {
4808 uint32_t leftover, msgbits;
4809 const struct intr_details *details;
4810 char alert;
4811 const bool verbose = flags & IHF_VERBOSE;
4812
4813 if (verbose || ucause != 0 || flags & IHF_RUN_ALL_ACTIONS) {
4814 alert = intr_alert_char(cause, enabled, fatal);
4815 CH_ALERT(sc, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", alert,
4816 ii->name, ii->cause_reg, cause, enabled, fatal);
4817 }
4818
4819 leftover = verbose ? cause : ucause;
4820 for (details = ii->details; details && details->mask != 0; details++) {
4821 msgbits = details->mask & leftover;
4822 if (msgbits == 0)
4823 continue;
4824 alert = intr_alert_char(msgbits, enabled, fatal);
4825 CH_ALERT(sc, " %c [0x%08x] %s\n", alert, msgbits, details->msg);
4826 leftover &= ~msgbits;
4827 }
4828 if (leftover != 0 && leftover != (verbose ? cause : ucause))
4829 CH_ALERT(sc, " ? [0x%08x]\n", leftover);
4830 }
4831
4832 /*
4833 * Returns true for fatal error.
4834 */
4835 static bool
t4_handle_intr(struct adapter * sc,const struct intr_info * ii,uint32_t acause,int flags)4836 t4_handle_intr(struct adapter *sc, const struct intr_info *ii, uint32_t acause,
4837 int flags)
4838 {
4839 uint32_t cause, ucause, enabled, fatal;
4840 bool rc;
4841 const struct intr_action *action;
4842
4843 cause = t4_read_reg(sc, ii->cause_reg);
4844 enabled = t4_read_reg(sc, ii->enable_reg);
4845 flags |= ii->flags;
4846 fatal = ii->fatal & cause;
4847 if (flags & IHF_FATAL_IFF_ENABLED)
4848 fatal &= enabled;
4849 ucause = cause;
4850 if (flags & IHF_IGNORE_IF_DISABLED)
4851 ucause &= enabled;
4852 if (!(flags & IHF_NO_SHOW))
4853 show_intr_info(sc, ii, cause, ucause, enabled, fatal, flags);
4854
4855 rc = fatal != 0;
4856 for (action = ii->actions; action && action->mask != 0; action++) {
4857 if (action->action == NULL)
4858 continue;
4859 if (action->mask & (ucause | acause) ||
4860 flags & IHF_RUN_ALL_ACTIONS) {
4861 bool rc1 = (action->action)(sc, action->arg, flags);
4862 if (action->mask & ucause)
4863 rc |= rc1;
4864 }
4865 }
4866
4867 /* clear */
4868 if (cause != 0) {
4869 if (flags & IHF_CLR_ALL_SET) {
4870 t4_write_reg(sc, ii->cause_reg, cause);
4871 (void)t4_read_reg(sc, ii->cause_reg);
4872 } else if (ucause != 0 && flags & IHF_CLR_ALL_UNIGNORED) {
4873 t4_write_reg(sc, ii->cause_reg, ucause);
4874 (void)t4_read_reg(sc, ii->cause_reg);
4875 }
4876 }
4877
4878 return (rc);
4879 }
4880
4881 /*
4882 * Interrupt handler for the PCIE module.
4883 */
pcie_intr_handler(struct adapter * adap,int arg,int flags)4884 static bool pcie_intr_handler(struct adapter *adap, int arg, int flags)
4885 {
4886 static const struct intr_details sysbus_intr_details[] = {
4887 { F_RNPP, "RXNP array parity error" },
4888 { F_RPCP, "RXPC array parity error" },
4889 { F_RCIP, "RXCIF array parity error" },
4890 { F_RCCP, "Rx completions control array parity error" },
4891 { F_RFTP, "RXFT array parity error" },
4892 { 0 }
4893 };
4894 static const struct intr_info sysbus_intr_info = {
4895 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
4896 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4897 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,
4898 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP,
4899 .flags = 0,
4900 .details = sysbus_intr_details,
4901 .actions = NULL,
4902 };
4903 static const struct intr_details pcie_port_intr_details[] = {
4904 { F_TPCP, "TXPC array parity error" },
4905 { F_TNPP, "TXNP array parity error" },
4906 { F_TFTP, "TXFT array parity error" },
4907 { F_TCAP, "TXCA array parity error" },
4908 { F_TCIP, "TXCIF array parity error" },
4909 { F_RCAP, "RXCA array parity error" },
4910 { F_OTDD, "outbound request TLP discarded" },
4911 { F_RDPE, "Rx data parity error" },
4912 { F_TDUE, "Tx uncorrectable data error" },
4913 { 0 }
4914 };
4915 static const struct intr_info pcie_port_intr_info = {
4916 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
4917 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4918 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,
4919 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP |
4920 F_OTDD | F_RDPE | F_TDUE,
4921 .flags = 0,
4922 .details = pcie_port_intr_details,
4923 .actions = NULL,
4924 };
4925 static const struct intr_details pcie_intr_details[] = {
4926 { F_MSIADDRLPERR, "MSI AddrL parity error" },
4927 { F_MSIADDRHPERR, "MSI AddrH parity error" },
4928 { F_MSIDATAPERR, "MSI data parity error" },
4929 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" },
4930 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" },
4931 { F_MSIXDATAPERR, "MSI-X data parity error" },
4932 { F_MSIXDIPERR, "MSI-X DI parity error" },
4933 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" },
4934 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" },
4935 { F_TARTAGPERR, "PCIe target tag FIFO parity error" },
4936 { F_CCNTPERR, "PCIe CMD channel count parity error" },
4937 { F_CREQPERR, "PCIe CMD channel request parity error" },
4938 { F_CRSPPERR, "PCIe CMD channel response parity error" },
4939 { F_DCNTPERR, "PCIe DMA channel count parity error" },
4940 { F_DREQPERR, "PCIe DMA channel request parity error" },
4941 { F_DRSPPERR, "PCIe DMA channel response parity error" },
4942 { F_HCNTPERR, "PCIe HMA channel count parity error" },
4943 { F_HREQPERR, "PCIe HMA channel request parity error" },
4944 { F_HRSPPERR, "PCIe HMA channel response parity error" },
4945 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" },
4946 { F_FIDPERR, "PCIe FID parity error" },
4947 { F_INTXCLRPERR, "PCIe INTx clear parity error" },
4948 { F_MATAGPERR, "PCIe MA tag parity error" },
4949 { F_PIOTAGPERR, "PCIe PIO tag parity error" },
4950 { F_RXCPLPERR, "PCIe Rx completion parity error" },
4951 { F_RXWRPERR, "PCIe Rx write parity error" },
4952 { F_RPLPERR, "PCIe replay buffer parity error" },
4953 { F_PCIESINT, "PCIe core secondary fault" },
4954 { F_PCIEPINT, "PCIe core primary fault" },
4955 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" },
4956 { 0 }
4957 };
4958 static const struct intr_details t5_pcie_intr_details[] = {
4959 { F_IPGRPPERR, "Parity errors observed by IP" },
4960 { F_NONFATALERR, "PCIe non-fatal error" },
4961 { F_READRSPERR, "Outbound read error" },
4962 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" },
4963 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" },
4964 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" },
4965 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" },
4966 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" },
4967 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" },
4968 { F_MAGRPPERR, "MA group FIFO parity error" },
4969 { F_VFIDPERR, "VFID SRAM parity error" },
4970 { F_FIDPERR, "FID SRAM parity error" },
4971 { F_CFGSNPPERR, "config snoop FIFO parity error" },
4972 { F_HRSPPERR, "HMA channel response data SRAM parity error" },
4973 { F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4974 { F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4975 { F_DRSPPERR, "DMA channel response data SRAM parity error" },
4976 { F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4977 { F_CRSPPERR, "CMD channel response data SRAM parity error" },
4978 { F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4979 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" },
4980 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" },
4981 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" },
4982 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" },
4983 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" },
4984 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" },
4985 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" },
4986 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" },
4987 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" },
4988 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" },
4989 { F_MSTGRPPERR, "Master response read queue SRAM parity error" },
4990 { 0 }
4991 };
4992 struct intr_info pcie_intr_info = {
4993 .name = "PCIE_INT_CAUSE",
4994 .cause_reg = A_PCIE_INT_CAUSE,
4995 .enable_reg = A_PCIE_INT_ENABLE,
4996 .fatal = 0xffffffff,
4997 .flags = IHF_FATAL_IFF_ENABLED,
4998 .details = NULL,
4999 .actions = NULL,
5000 };
5001 struct intr_info pcie_int_cause_ext = {
5002 .name = "PCIE_INT_CAUSE_EXT",
5003 .cause_reg = A_PCIE_INT_CAUSE_EXT,
5004 .enable_reg = A_PCIE_INT_ENABLE_EXT,
5005 .fatal = 0,
5006 .flags = 0,
5007 .details = NULL,
5008 .actions = NULL,
5009 };
5010 struct intr_info pcie_int_cause_x8 = {
5011 .name = "PCIE_INT_CAUSE_X8",
5012 .cause_reg = A_PCIE_INT_CAUSE_X8,
5013 .enable_reg = A_PCIE_INT_ENABLE_X8,
5014 .fatal = 0,
5015 .flags = 0,
5016 .details = NULL,
5017 .actions = NULL,
5018 };
5019 bool fatal = false;
5020
5021 if (is_t4(adap)) {
5022 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, flags);
5023 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, flags);
5024
5025 pcie_intr_info.details = pcie_intr_details;
5026 } else {
5027 pcie_intr_info.details = t5_pcie_intr_details;
5028 }
5029 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, flags);
5030 if (chip_id(adap) > CHELSIO_T6) {
5031 fatal |= t4_handle_intr(adap, &pcie_int_cause_ext, 0, flags);
5032 fatal |= t4_handle_intr(adap, &pcie_int_cause_x8, 0, flags);
5033 }
5034
5035 return (fatal);
5036 }
5037
5038 /*
5039 * TP interrupt handler.
5040 */
tp_intr_handler(struct adapter * adap,int arg,int flags)5041 static bool tp_intr_handler(struct adapter *adap, int arg, int flags)
5042 {
5043 static const struct intr_details tp_intr_details[] = {
5044 { 0x3fffffff, "TP parity error" },
5045 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" },
5046 { 0 }
5047 };
5048 static const struct intr_info tp_intr_info = {
5049 .name = "TP_INT_CAUSE",
5050 .cause_reg = A_TP_INT_CAUSE,
5051 .enable_reg = A_TP_INT_ENABLE,
5052 .fatal = 0x7fffffff,
5053 .flags = IHF_FATAL_IFF_ENABLED,
5054 .details = tp_intr_details,
5055 .actions = NULL,
5056 };
5057 static const struct intr_info tp_inic_perr_cause = {
5058 .name = "TP_INIC_PERR_CAUSE",
5059 .cause_reg = A_TP_INIC_PERR_CAUSE,
5060 .enable_reg = A_TP_INIC_PERR_ENABLE,
5061 .fatal = 0xffffffff,
5062 .flags = IHF_FATAL_IFF_ENABLED,
5063 .details = NULL,
5064 .actions = NULL,
5065 };
5066 static const struct intr_info tp_c_perr_cause = {
5067 .name = "TP_C_PERR_CAUSE",
5068 .cause_reg = A_TP_C_PERR_CAUSE,
5069 .enable_reg = A_TP_C_PERR_ENABLE,
5070 .fatal = 0xffffffff,
5071 .flags = IHF_FATAL_IFF_ENABLED,
5072 .details = NULL,
5073 .actions = NULL,
5074 };
5075 static const struct intr_info tp_e_eg_perr_cause = {
5076 .name = "TP_E_EG_PERR_CAUSE",
5077 .cause_reg = A_TP_E_EG_PERR_CAUSE,
5078 .enable_reg = A_TP_E_EG_PERR_ENABLE,
5079 .fatal = 0xffffffff,
5080 .flags = IHF_FATAL_IFF_ENABLED,
5081 .details = NULL,
5082 .actions = NULL,
5083 };
5084 static const struct intr_info tp_e_in0_perr_cause = {
5085 .name = "TP_E_IN0_PERR_CAUSE",
5086 .cause_reg = A_TP_E_IN0_PERR_CAUSE,
5087 .enable_reg = A_TP_E_IN0_PERR_ENABLE,
5088 .fatal = 0xffffffff,
5089 .flags = IHF_FATAL_IFF_ENABLED,
5090 .details = NULL,
5091 .actions = NULL,
5092 };
5093 static const struct intr_info tp_e_in1_perr_cause = {
5094 .name = "TP_E_IN1_PERR_CAUSE",
5095 .cause_reg = A_TP_E_IN1_PERR_CAUSE,
5096 .enable_reg = A_TP_E_IN1_PERR_ENABLE,
5097 .fatal = 0xffffffff,
5098 .flags = IHF_FATAL_IFF_ENABLED,
5099 .details = NULL,
5100 .actions = NULL,
5101 };
5102 static const struct intr_info tp_o_perr_cause = {
5103 .name = "TP_O_PERR_CAUSE",
5104 .cause_reg = A_TP_O_PERR_CAUSE,
5105 .enable_reg = A_TP_O_PERR_ENABLE,
5106 .fatal = 0xffffffff,
5107 .flags = IHF_FATAL_IFF_ENABLED,
5108 .details = NULL,
5109 .actions = NULL,
5110 };
5111 bool fatal;
5112
5113 fatal = t4_handle_intr(adap, &tp_intr_info, 0, flags);
5114 if (chip_id(adap) > CHELSIO_T6) {
5115 fatal |= t4_handle_intr(adap, &tp_inic_perr_cause, 0, flags);
5116 fatal |= t4_handle_intr(adap, &tp_c_perr_cause, 0, flags);
5117 fatal |= t4_handle_intr(adap, &tp_e_eg_perr_cause, 0, flags);
5118 fatal |= t4_handle_intr(adap, &tp_e_in0_perr_cause, 0, flags);
5119 fatal |= t4_handle_intr(adap, &tp_e_in1_perr_cause, 0, flags);
5120 fatal |= t4_handle_intr(adap, &tp_o_perr_cause, 0, flags);
5121 }
5122
5123 return (fatal);
5124 }
5125
5126 /*
5127 * SGE interrupt handler.
5128 */
sge_intr_handler(struct adapter * adap,int arg,int flags)5129 static bool sge_intr_handler(struct adapter *adap, int arg, int flags)
5130 {
5131 static const struct intr_info sge_int1_info = {
5132 .name = "SGE_INT_CAUSE1",
5133 .cause_reg = A_SGE_INT_CAUSE1,
5134 .enable_reg = A_SGE_INT_ENABLE1,
5135 .fatal = 0xffffffff,
5136 .flags = IHF_FATAL_IFF_ENABLED,
5137 .details = NULL,
5138 .actions = NULL,
5139 };
5140 static const struct intr_info sge_int2_info = {
5141 .name = "SGE_INT_CAUSE2",
5142 .cause_reg = A_SGE_INT_CAUSE2,
5143 .enable_reg = A_SGE_INT_ENABLE2,
5144 .fatal = 0xffffffff,
5145 .flags = IHF_FATAL_IFF_ENABLED,
5146 .details = NULL,
5147 .actions = NULL,
5148 };
5149 static const struct intr_details sge_int3_details[] = {
5150 { F_ERR_FLM_DBP,
5151 "DBP pointer delivery for invalid context or QID" },
5152 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
5153 "Invalid QID or header request by IDMA" },
5154 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
5155 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
5156 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
5157 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
5158 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
5159 { F_ERR_TIMER_ABOVE_MAX_QID,
5160 "SGE GTS with timer 0-5 for IQID > 1023" },
5161 { F_ERR_CPL_EXCEED_IQE_SIZE,
5162 "SGE received CPL exceeding IQE size" },
5163 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
5164 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
5165 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
5166 { F_ERR_DROPPED_DB, "SGE DB dropped" },
5167 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
5168 "SGE IQID > 1023 received CPL for FL" },
5169 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5170 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
5171 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
5172 { F_ERR_ING_CTXT_PRIO,
5173 "Ingress context manager priority user error" },
5174 { F_ERR_EGR_CTXT_PRIO,
5175 "Egress context manager priority user error" },
5176 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" },
5177 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" },
5178 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
5179 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
5180 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
5181 { 0x0000000f, "SGE context access for invalid queue" },
5182 { 0 }
5183 };
5184 static const struct intr_details t6_sge_int3_details[] = {
5185 { F_ERR_FLM_DBP,
5186 "DBP pointer delivery for invalid context or QID" },
5187 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
5188 "Invalid QID or header request by IDMA" },
5189 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
5190 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
5191 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
5192 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
5193 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
5194 { F_ERR_TIMER_ABOVE_MAX_QID,
5195 "SGE GTS with timer 0-5 for IQID > 1023" },
5196 { F_ERR_CPL_EXCEED_IQE_SIZE,
5197 "SGE received CPL exceeding IQE size" },
5198 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
5199 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
5200 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
5201 { F_ERR_DROPPED_DB, "SGE DB dropped" },
5202 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
5203 "SGE IQID > 1023 received CPL for FL" },
5204 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5205 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
5206 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
5207 { F_ERR_ING_CTXT_PRIO,
5208 "Ingress context manager priority user error" },
5209 { F_ERR_EGR_CTXT_PRIO,
5210 "Egress context manager priority user error" },
5211 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" },
5212 { F_FATAL_WRE_LEN,
5213 "SGE WRE packet less than advertized length" },
5214 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
5215 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
5216 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
5217 { 0x0000000f, "SGE context access for invalid queue" },
5218 { 0 }
5219 };
5220 struct intr_info sge_int3_info = {
5221 .name = "SGE_INT_CAUSE3",
5222 .cause_reg = A_SGE_INT_CAUSE3,
5223 .enable_reg = A_SGE_INT_ENABLE3,
5224 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE,
5225 .flags = 0,
5226 .details = NULL,
5227 .actions = NULL,
5228 };
5229 static const struct intr_info sge_int4_info = {
5230 .name = "SGE_INT_CAUSE4",
5231 .cause_reg = A_SGE_INT_CAUSE4,
5232 .enable_reg = A_SGE_INT_ENABLE4,
5233 .fatal = 0,
5234 .flags = 0,
5235 .details = NULL,
5236 .actions = NULL,
5237 };
5238 static const struct intr_info sge_int5_info = {
5239 .name = "SGE_INT_CAUSE5",
5240 .cause_reg = A_SGE_INT_CAUSE5,
5241 .enable_reg = A_SGE_INT_ENABLE5,
5242 .fatal = 0xffffffff,
5243 .flags = IHF_FATAL_IFF_ENABLED,
5244 .details = NULL,
5245 .actions = NULL,
5246 };
5247 static const struct intr_info sge_int6_info = {
5248 .name = "SGE_INT_CAUSE6",
5249 .cause_reg = A_SGE_INT_CAUSE6,
5250 .enable_reg = A_SGE_INT_ENABLE6,
5251 .fatal = 0,
5252 .flags = 0,
5253 .details = NULL,
5254 .actions = NULL,
5255 };
5256 static const struct intr_info sge_int7_info = {
5257 .name = "SGE_INT_CAUSE7",
5258 .cause_reg = A_SGE_INT_CAUSE7,
5259 .enable_reg = A_SGE_INT_ENABLE7,
5260 .fatal = 0,
5261 .flags = 0,
5262 .details = NULL,
5263 .actions = NULL,
5264 };
5265 static const struct intr_info sge_int8_info = {
5266 .name = "SGE_INT_CAUSE8",
5267 .cause_reg = A_SGE_INT_CAUSE8,
5268 .enable_reg = A_SGE_INT_ENABLE8,
5269 .fatal = 0,
5270 .flags = 0,
5271 .details = NULL,
5272 .actions = NULL,
5273 };
5274 bool fatal;
5275 u32 v;
5276
5277 if (chip_id(adap) <= CHELSIO_T5) {
5278 sge_int3_info.details = sge_int3_details;
5279 } else {
5280 sge_int3_info.details = t6_sge_int3_details;
5281 }
5282
5283 fatal = false;
5284 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, flags);
5285 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, flags);
5286 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, flags);
5287 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, flags);
5288 if (chip_id(adap) >= CHELSIO_T5)
5289 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, flags);
5290 if (chip_id(adap) >= CHELSIO_T6)
5291 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, flags);
5292 if (chip_id(adap) >= CHELSIO_T7) {
5293 fatal |= t4_handle_intr(adap, &sge_int7_info, 0, flags);
5294 fatal |= t4_handle_intr(adap, &sge_int8_info, 0, flags);
5295 }
5296
5297 v = t4_read_reg(adap, A_SGE_ERROR_STATS);
5298 if (v & F_ERROR_QID_VALID) {
5299 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v));
5300 if (v & F_UNCAPTURED_ERROR)
5301 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n");
5302 t4_write_reg(adap, A_SGE_ERROR_STATS,
5303 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR);
5304 }
5305
5306 return (fatal);
5307 }
5308
5309 /*
5310 * CIM interrupt handler.
5311 */
cim_intr_handler(struct adapter * adap,int arg,int flags)5312 static bool cim_intr_handler(struct adapter *adap, int arg, int flags)
5313 {
5314 static const struct intr_details cim_host_intr_details[] = {
5315 /* T6+ */
5316 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" },
5317
5318 /* T5+ */
5319 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" },
5320 { F_PLCIM_MSTRSPDATAPARERR,
5321 "PL2CIM master response data parity error" },
5322 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" },
5323 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" },
5324 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" },
5325 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" },
5326 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" },
5327 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" },
5328
5329 /* T4+ */
5330 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" },
5331 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" },
5332 { F_MBHOSTPARERR, "CIM mailbox host read parity error" },
5333 { F_MBUPPARERR, "CIM mailbox uP parity error" },
5334 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" },
5335 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" },
5336 { F_IBQULPPARERR, "CIM IBQ ULP parity error" },
5337 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" },
5338 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */
5339 "CIM IBQ PCIe/SGE_HI parity error" },
5340 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" },
5341 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" },
5342 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" },
5343 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" },
5344 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" },
5345 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" },
5346 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" },
5347 { F_TIMER1INT, "CIM TIMER0 interrupt" },
5348 { F_TIMER0INT, "CIM TIMER0 interrupt" },
5349 { F_PREFDROPINT, "CIM control register prefetch drop" },
5350 { 0}
5351 };
5352 static const struct intr_info cim_host_intr_info = {
5353 .name = "CIM_HOST_INT_CAUSE",
5354 .cause_reg = A_CIM_HOST_INT_CAUSE,
5355 .enable_reg = A_CIM_HOST_INT_ENABLE,
5356 .fatal = 0x007fffe6,
5357 .flags = IHF_FATAL_IFF_ENABLED,
5358 .details = cim_host_intr_details,
5359 .actions = NULL,
5360 };
5361 static const struct intr_details cim_host_upacc_intr_details[] = {
5362 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" },
5363 { F_TIMEOUTMAINT, "CIM PIF MA timeout" },
5364 { F_TIMEOUTINT, "CIM PIF timeout" },
5365 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" },
5366 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" },
5367 { F_BLKWRPLINT, "CIM block write to PL space" },
5368 { F_BLKRDPLINT, "CIM block read from PL space" },
5369 { F_SGLWRPLINT,
5370 "CIM single write to PL space with illegal BEs" },
5371 { F_SGLRDPLINT,
5372 "CIM single read from PL space with illegal BEs" },
5373 { F_BLKWRCTLINT, "CIM block write to CTL space" },
5374 { F_BLKRDCTLINT, "CIM block read from CTL space" },
5375 { F_SGLWRCTLINT,
5376 "CIM single write to CTL space with illegal BEs" },
5377 { F_SGLRDCTLINT,
5378 "CIM single read from CTL space with illegal BEs" },
5379 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" },
5380 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" },
5381 { F_SGLWREEPROMINT,
5382 "CIM single write to EEPROM space with illegal BEs" },
5383 { F_SGLRDEEPROMINT,
5384 "CIM single read from EEPROM space with illegal BEs" },
5385 { F_BLKWRFLASHINT, "CIM block write to flash space" },
5386 { F_BLKRDFLASHINT, "CIM block read from flash space" },
5387 { F_SGLWRFLASHINT, "CIM single write to flash space" },
5388 { F_SGLRDFLASHINT,
5389 "CIM single read from flash space with illegal BEs" },
5390 { F_BLKWRBOOTINT, "CIM block write to boot space" },
5391 { F_BLKRDBOOTINT, "CIM block read from boot space" },
5392 { F_SGLWRBOOTINT, "CIM single write to boot space" },
5393 { F_SGLRDBOOTINT,
5394 "CIM single read from boot space with illegal BEs" },
5395 { F_ILLWRBEINT, "CIM illegal write BEs" },
5396 { F_ILLRDBEINT, "CIM illegal read BEs" },
5397 { F_ILLRDINT, "CIM illegal read" },
5398 { F_ILLWRINT, "CIM illegal write" },
5399 { F_ILLTRANSINT, "CIM illegal transaction" },
5400 { F_RSVDSPACEINT, "CIM reserved space access" },
5401 {0}
5402 };
5403 static const struct intr_info cim_host_upacc_intr_info = {
5404 .name = "CIM_HOST_UPACC_INT_CAUSE",
5405 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
5406 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
5407 .fatal = 0x3fffeeff,
5408 .flags = IHF_FATAL_IFF_ENABLED,
5409 .details = cim_host_upacc_intr_details,
5410 .actions = NULL,
5411 };
5412 static const struct intr_info cim_pf_host_intr_info = {
5413 .name = "CIM_PF_HOST_INT_CAUSE",
5414 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
5415 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),
5416 .fatal = 0,
5417 .flags = 0,
5418 .details = NULL,
5419 .actions = NULL,
5420 };
5421 static const struct intr_info cim_perr_cause = {
5422 .name = "CIM_PERR_CAUSE",
5423 .cause_reg = A_CIM_PERR_CAUSE,
5424 .enable_reg = A_CIM_PERR_ENABLE,
5425 .fatal = 0xffffffff,
5426 .flags = IHF_FATAL_IFF_ENABLED,
5427 .details = NULL,
5428 .actions = NULL,
5429 };
5430 u32 val, fw_err;
5431 bool fatal;
5432
5433 /*
5434 * When the Firmware detects an internal error which normally wouldn't
5435 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
5436 * to make sure the Host sees the Firmware Crash. So if we have a
5437 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
5438 * interrupt.
5439 */
5440 fw_err = t4_read_reg(adap, A_PCIE_FW);
5441 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE);
5442 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) ||
5443 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) {
5444 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT);
5445 }
5446
5447 fatal = (fw_err & F_PCIE_FW_ERR) != 0;
5448 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, flags);
5449 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, flags);
5450 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, flags);
5451 if (chip_id(adap) > CHELSIO_T6)
5452 fatal |= t4_handle_intr(adap, &cim_perr_cause, 0, flags);
5453 if (fatal)
5454 t4_os_cim_err(adap);
5455
5456 return (fatal);
5457 }
5458
5459 /*
5460 * ULP RX interrupt handler.
5461 */
ulprx_intr_handler(struct adapter * adap,int arg,int flags)5462 static bool ulprx_intr_handler(struct adapter *adap, int arg, int flags)
5463 {
5464 static const struct intr_details ulprx_intr_details[] = {
5465 /* T5+ */
5466 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
5467 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
5468
5469 /* T4+ */
5470 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
5471 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
5472 { 0x007fffff, "ULPRX parity error" },
5473 { 0 }
5474 };
5475 static const struct intr_info ulprx_intr_info = {
5476 .name = "ULP_RX_INT_CAUSE",
5477 .cause_reg = A_ULP_RX_INT_CAUSE,
5478 .enable_reg = A_ULP_RX_INT_ENABLE,
5479 .fatal = 0x07ffffff,
5480 .flags = IHF_FATAL_IFF_ENABLED,
5481 .details = ulprx_intr_details,
5482 .actions = NULL,
5483 };
5484 static const struct intr_info ulprx_intr2_info = {
5485 .name = "ULP_RX_INT_CAUSE_2",
5486 .cause_reg = A_ULP_RX_INT_CAUSE_2,
5487 .enable_reg = A_ULP_RX_INT_ENABLE_2,
5488 .fatal = 0,
5489 .flags = 0,
5490 .details = NULL,
5491 .actions = NULL,
5492 };
5493 static const struct intr_info ulprx_int_cause_pcmd = {
5494 .name = "ULP_RX_INT_CAUSE_PCMD",
5495 .cause_reg = A_ULP_RX_INT_CAUSE_PCMD,
5496 .enable_reg = A_ULP_RX_INT_ENABLE_PCMD,
5497 .fatal = 0,
5498 .flags = 0,
5499 .details = NULL,
5500 .actions = NULL,
5501 };
5502 static const struct intr_info ulprx_int_cause_data = {
5503 .name = "ULP_RX_INT_CAUSE_DATA",
5504 .cause_reg = A_ULP_RX_INT_CAUSE_DATA,
5505 .enable_reg = A_ULP_RX_INT_ENABLE_DATA,
5506 .fatal = 0,
5507 .flags = 0,
5508 .details = NULL,
5509 .actions = NULL,
5510 };
5511 static const struct intr_info ulprx_int_cause_arb = {
5512 .name = "ULP_RX_INT_CAUSE_ARB",
5513 .cause_reg = A_ULP_RX_INT_CAUSE_ARB,
5514 .enable_reg = A_ULP_RX_INT_ENABLE_ARB,
5515 .fatal = 0,
5516 .flags = 0,
5517 .details = NULL,
5518 .actions = NULL,
5519 };
5520 static const struct intr_info ulprx_int_cause_intf = {
5521 .name = "ULP_RX_INT_CAUSE_INTERFACE",
5522 .cause_reg = A_ULP_RX_INT_CAUSE_INTERFACE,
5523 .enable_reg = A_ULP_RX_INT_ENABLE_INTERFACE,
5524 .fatal = 0,
5525 .flags = 0,
5526 .details = NULL,
5527 .actions = NULL,
5528 };
5529 bool fatal = false;
5530
5531 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, flags);
5532 if (chip_id(adap) < CHELSIO_T7)
5533 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, flags);
5534 else {
5535 fatal |= t4_handle_intr(adap, &ulprx_int_cause_pcmd, 0, flags);
5536 fatal |= t4_handle_intr(adap, &ulprx_int_cause_data, 0, flags);
5537 fatal |= t4_handle_intr(adap, &ulprx_int_cause_arb, 0, flags);
5538 fatal |= t4_handle_intr(adap, &ulprx_int_cause_intf, 0, flags);
5539 }
5540
5541 return (fatal);
5542 }
5543
5544 /*
5545 * ULP TX interrupt handler.
5546 */
ulptx_intr_handler(struct adapter * adap,int arg,int flags)5547 static bool ulptx_intr_handler(struct adapter *adap, int arg, int flags)
5548 {
5549 static const struct intr_details ulptx_intr_details[] = {
5550 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
5551 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
5552 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
5553 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
5554 { 0x0fffffff, "ULPTX parity error" },
5555 { 0 }
5556 };
5557 static const struct intr_info ulptx_intr_info = {
5558 .name = "ULP_TX_INT_CAUSE",
5559 .cause_reg = A_ULP_TX_INT_CAUSE,
5560 .enable_reg = A_ULP_TX_INT_ENABLE,
5561 .fatal = 0x0fffffff,
5562 .flags = IHF_FATAL_IFF_ENABLED,
5563 .details = ulptx_intr_details,
5564 .actions = NULL,
5565 };
5566 static const struct intr_info ulptx_intr_info2 = {
5567 .name = "ULP_TX_INT_CAUSE_2",
5568 .cause_reg = A_ULP_TX_INT_CAUSE_2,
5569 .enable_reg = A_ULP_TX_INT_ENABLE_2,
5570 .fatal = 0xffffffff,
5571 .flags = IHF_FATAL_IFF_ENABLED,
5572 .details = NULL,
5573 .actions = NULL,
5574 };
5575 static const struct intr_info ulptx_intr_info3 = {
5576 .name = "ULP_TX_INT_CAUSE_3",
5577 .cause_reg = A_ULP_TX_INT_CAUSE_3,
5578 .enable_reg = A_ULP_TX_INT_ENABLE_3,
5579 .fatal = 0xffffffff,
5580 .flags = IHF_FATAL_IFF_ENABLED,
5581 .details = NULL,
5582 .actions = NULL,
5583 };
5584 static const struct intr_info ulptx_intr_info4 = {
5585 .name = "ULP_TX_INT_CAUSE_4",
5586 .cause_reg = A_ULP_TX_INT_CAUSE_4,
5587 .enable_reg = A_ULP_TX_INT_ENABLE_4,
5588 .fatal = 0xffffffff,
5589 .flags = IHF_FATAL_IFF_ENABLED,
5590 .details = NULL,
5591 .actions = NULL,
5592 };
5593 static const struct intr_info ulptx_intr_info5 = {
5594 .name = "ULP_TX_INT_CAUSE_5",
5595 .cause_reg = A_ULP_TX_INT_CAUSE_5,
5596 .enable_reg = A_ULP_TX_INT_ENABLE_5,
5597 .fatal = 0xffffffff,
5598 .flags = IHF_FATAL_IFF_ENABLED,
5599 .details = NULL,
5600 .actions = NULL,
5601 };
5602 static const struct intr_info ulptx_intr_info6 = {
5603 .name = "ULP_TX_INT_CAUSE_6",
5604 .cause_reg = A_ULP_TX_INT_CAUSE_6,
5605 .enable_reg = A_ULP_TX_INT_ENABLE_6,
5606 .fatal = 0xffffffff,
5607 .flags = IHF_FATAL_IFF_ENABLED,
5608 .details = NULL,
5609 .actions = NULL,
5610 };
5611 static const struct intr_info ulptx_intr_info7 = {
5612 .name = "ULP_TX_INT_CAUSE_7",
5613 .cause_reg = A_ULP_TX_INT_CAUSE_7,
5614 .enable_reg = A_ULP_TX_INT_ENABLE_7,
5615 .fatal = 0,
5616 .flags = 0,
5617 .details = NULL,
5618 .actions = NULL,
5619 };
5620 static const struct intr_info ulptx_intr_info8 = {
5621 .name = "ULP_TX_INT_CAUSE_8",
5622 .cause_reg = A_ULP_TX_INT_CAUSE_8,
5623 .enable_reg = A_ULP_TX_INT_ENABLE_8,
5624 .fatal = 0,
5625 .flags = 0,
5626 .details = NULL,
5627 .actions = NULL,
5628 };
5629 bool fatal = false;
5630
5631 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, flags);
5632 if (chip_id(adap) > CHELSIO_T4)
5633 fatal |= t4_handle_intr(adap, &ulptx_intr_info2, 0, flags);
5634 if (chip_id(adap) > CHELSIO_T6) {
5635 fatal |= t4_handle_intr(adap, &ulptx_intr_info3, 0, flags);
5636 fatal |= t4_handle_intr(adap, &ulptx_intr_info4, 0, flags);
5637 fatal |= t4_handle_intr(adap, &ulptx_intr_info5, 0, flags);
5638 fatal |= t4_handle_intr(adap, &ulptx_intr_info6, 0, flags);
5639 fatal |= t4_handle_intr(adap, &ulptx_intr_info7, 0, flags);
5640 fatal |= t4_handle_intr(adap, &ulptx_intr_info8, 0, flags);
5641 }
5642
5643 return (fatal);
5644 }
5645
pmtx_dump_dbg_stats(struct adapter * adap,int arg,int flags)5646 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, int flags)
5647 {
5648 int i;
5649 u32 data[17];
5650
5651 if (flags & IHF_NO_SHOW)
5652 return (false);
5653
5654 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
5655 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
5656 for (i = 0; i < ARRAY_SIZE(data); i++) {
5657 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
5658 A_PM_TX_DBG_STAT0 + i, data[i]);
5659 }
5660
5661 return (false);
5662 }
5663
5664 /*
5665 * PM TX interrupt handler.
5666 */
pmtx_intr_handler(struct adapter * adap,int arg,int flags)5667 static bool pmtx_intr_handler(struct adapter *adap, int arg, int flags)
5668 {
5669 static const struct intr_details pmtx_int_cause_fields[] = {
5670 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
5671 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
5672 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
5673 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" },
5674 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
5675 { 0x00f00000, "PMTX icspi FIFO Rx framing error" },
5676 { 0x000f0000, "PMTX icspi FIFO Tx framing error" },
5677 { 0x0000f000, "PMTX oespi FIFO Rx framing error" },
5678 { 0x00000f00, "PMTX oespi FIFO Tx framing error" },
5679 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
5680 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" },
5681 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" },
5682 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" },
5683 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
5684 { 0 }
5685 };
5686 static const struct intr_action pmtx_int_cause_actions[] = {
5687 { 0xffffffff, -1, pmtx_dump_dbg_stats },
5688 { 0 },
5689 };
5690 static const struct intr_info pmtx_int_cause = {
5691 .name = "PM_TX_INT_CAUSE",
5692 .cause_reg = A_PM_TX_INT_CAUSE,
5693 .enable_reg = A_PM_TX_INT_ENABLE,
5694 .fatal = 0xffffffff,
5695 .flags = 0,
5696 .details = pmtx_int_cause_fields,
5697 .actions = pmtx_int_cause_actions,
5698 };
5699
5700 return (t4_handle_intr(adap, &pmtx_int_cause, 0, flags));
5701 }
5702
5703 /*
5704 * PM RX interrupt handler.
5705 */
pmrx_intr_handler(struct adapter * adap,int arg,int flags)5706 static bool pmrx_intr_handler(struct adapter *adap, int arg, int flags)
5707 {
5708 static const struct intr_details pmrx_int_cause_fields[] = {
5709 /* T6+ */
5710 { 0x18000000, "PMRX ospi overflow" },
5711 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
5712 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" },
5713 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" },
5714 { F_SDC_ERR, "PMRX SDC error" },
5715
5716 /* T4+ */
5717 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" },
5718 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
5719 { 0x0003c000, "PMRX iespi Rx framing error" },
5720 { 0x00003c00, "PMRX iespi Tx framing error" },
5721 { 0x00000300, "PMRX ocspi Rx framing error" },
5722 { 0x000000c0, "PMRX ocspi Tx framing error" },
5723 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
5724 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" },
5725 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" },
5726 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" },
5727 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
5728 { 0 }
5729 };
5730 static const struct intr_info pmrx_int_cause = {
5731 .name = "PM_RX_INT_CAUSE",
5732 .cause_reg = A_PM_RX_INT_CAUSE,
5733 .enable_reg = A_PM_RX_INT_ENABLE,
5734 .fatal = 0x1fffffff,
5735 .flags = IHF_FATAL_IFF_ENABLED,
5736 .details = pmrx_int_cause_fields,
5737 .actions = NULL,
5738 };
5739
5740 return (t4_handle_intr(adap, &pmrx_int_cause, 0, flags));
5741 }
5742
5743 /*
5744 * CPL switch interrupt handler.
5745 */
cplsw_intr_handler(struct adapter * adap,int arg,int flags)5746 static bool cplsw_intr_handler(struct adapter *adap, int arg, int flags)
5747 {
5748 static const struct intr_details cplsw_int_cause_fields[] = {
5749 /* T5+ */
5750 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
5751 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
5752
5753 /* T4+ */
5754 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" },
5755 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" },
5756 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" },
5757 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" },
5758 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" },
5759 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
5760 { 0 }
5761 };
5762 static const struct intr_info cplsw_int_cause = {
5763 .name = "CPL_INTR_CAUSE",
5764 .cause_reg = A_CPL_INTR_CAUSE,
5765 .enable_reg = A_CPL_INTR_ENABLE,
5766 .fatal = 0xffffffff,
5767 .flags = IHF_FATAL_IFF_ENABLED,
5768 .details = cplsw_int_cause_fields,
5769 .actions = NULL,
5770 };
5771
5772 return (t4_handle_intr(adap, &cplsw_int_cause, 0, flags));
5773 }
5774
5775 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
5776 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR)
5777 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \
5778 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \
5779 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \
5780 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR)
5781 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
5782 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
5783 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
5784 #define T7_LE_FATAL_MASK (T6_LE_FATAL_MASK | F_CACHESRAMPERR | F_CACHEINTPERR)
5785
5786 /*
5787 * LE interrupt handler.
5788 */
le_intr_handler(struct adapter * adap,int arg,int flags)5789 static bool le_intr_handler(struct adapter *adap, int arg, int flags)
5790 {
5791 static const struct intr_details le_intr_details[] = {
5792 { F_REQQPARERR, "LE request queue parity error" },
5793 { F_UNKNOWNCMD, "LE unknown command" },
5794 { F_ACTRGNFULL, "LE active region full" },
5795 { F_PARITYERR, "LE parity error" },
5796 { F_LIPMISS, "LE LIP miss" },
5797 { F_LIP0, "LE 0 LIP error" },
5798 { 0 }
5799 };
5800 static const struct intr_details t6_le_intr_details[] = {
5801 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" },
5802 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" },
5803 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" },
5804 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" },
5805 { F_TOTCNTERR, "LE total active < TCAM count" },
5806 { F_CMDPRSRINTERR, "LE internal error in parser" },
5807 { F_CMDTIDERR, "Incorrect tid in LE command" },
5808 { F_T6_ACTRGNFULL, "LE active region full" },
5809 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" },
5810 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" },
5811 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" },
5812 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" },
5813 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" },
5814 { F_TCAMACCFAIL, "LE TCAM access failure" },
5815 { F_T6_UNKNOWNCMD, "LE unknown command" },
5816 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" },
5817 { F_T6_LIPMISS, "LE CLIP lookup miss" },
5818 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
5819 { 0 }
5820 };
5821 struct intr_info le_intr_info = {
5822 .name = "LE_DB_INT_CAUSE",
5823 .cause_reg = A_LE_DB_INT_CAUSE,
5824 .enable_reg = A_LE_DB_INT_ENABLE,
5825 .fatal = 0,
5826 .flags = IHF_FATAL_IFF_ENABLED,
5827 .details = NULL,
5828 .actions = NULL,
5829 };
5830
5831 if (chip_id(adap) <= CHELSIO_T5) {
5832 le_intr_info.details = le_intr_details;
5833 le_intr_info.fatal = T5_LE_FATAL_MASK;
5834 } else {
5835 le_intr_info.details = t6_le_intr_details;
5836 if (chip_id(adap) < CHELSIO_T7)
5837 le_intr_info.fatal = T6_LE_FATAL_MASK;
5838 else
5839 le_intr_info.fatal = T7_LE_FATAL_MASK;
5840 }
5841
5842 return (t4_handle_intr(adap, &le_intr_info, 0, flags));
5843 }
5844
5845 /*
5846 * MPS interrupt handler.
5847 */
mps_intr_handler(struct adapter * adap,int arg,int flags)5848 static bool mps_intr_handler(struct adapter *adap, int arg, int flags)
5849 {
5850 static const struct intr_details mps_rx_perr_intr_details[] = {
5851 { 0xffffffff, "MPS Rx parity error" },
5852 { 0 }
5853 };
5854 static const struct intr_info mps_rx_perr_intr_info = {
5855 .name = "MPS_RX_PERR_INT_CAUSE",
5856 .cause_reg = A_MPS_RX_PERR_INT_CAUSE,
5857 .enable_reg = A_MPS_RX_PERR_INT_ENABLE,
5858 .fatal = 0xffffffff,
5859 .flags = IHF_FATAL_IFF_ENABLED,
5860 .details = mps_rx_perr_intr_details,
5861 .actions = NULL,
5862 };
5863 static const struct intr_info mps_rx_perr_intr_info2 = {
5864 .name = "MPS_RX_PERR_INT_CAUSE2",
5865 .cause_reg = A_MPS_RX_PERR_INT_CAUSE2,
5866 .enable_reg = A_MPS_RX_PERR_INT_ENABLE2,
5867 .fatal = 0xffffffff,
5868 .flags = IHF_FATAL_IFF_ENABLED,
5869 .details = NULL,
5870 .actions = NULL,
5871 };
5872 static const struct intr_info mps_rx_perr_intr_info3 = {
5873 .name = "MPS_RX_PERR_INT_CAUSE3",
5874 .cause_reg = A_MPS_RX_PERR_INT_CAUSE3,
5875 .enable_reg = A_MPS_RX_PERR_INT_ENABLE3,
5876 .fatal = 0xffffffff,
5877 .flags = IHF_FATAL_IFF_ENABLED,
5878 .details = NULL,
5879 .actions = NULL,
5880 };
5881 static const struct intr_info mps_rx_perr_intr_info4 = {
5882 .name = "MPS_RX_PERR_INT_CAUSE4",
5883 .cause_reg = A_MPS_RX_PERR_INT_CAUSE4,
5884 .enable_reg = A_MPS_RX_PERR_INT_ENABLE4,
5885 .fatal = 0xffffffff,
5886 .flags = IHF_FATAL_IFF_ENABLED,
5887 .details = NULL,
5888 .actions = NULL,
5889 };
5890 static const struct intr_info mps_rx_perr_intr_info5 = {
5891 .name = "MPS_RX_PERR_INT_CAUSE5",
5892 .cause_reg = A_MPS_RX_PERR_INT_CAUSE5,
5893 .enable_reg = A_MPS_RX_PERR_INT_ENABLE5,
5894 .fatal = 0xffffffff,
5895 .flags = IHF_FATAL_IFF_ENABLED,
5896 .details = NULL,
5897 .actions = NULL,
5898 };
5899 static const struct intr_info mps_rx_perr_intr_info6 = {
5900 .name = "MPS_RX_PERR_INT_CAUSE6",
5901 .cause_reg = A_MPS_RX_PERR_INT_CAUSE6,
5902 .enable_reg = A_MPS_RX_PERR_INT_ENABLE6,
5903 .fatal = 0xffffffff,
5904 .flags = IHF_FATAL_IFF_ENABLED,
5905 .details = NULL,
5906 .actions = NULL,
5907 };
5908 static const struct intr_details mps_tx_intr_details[] = {
5909 { F_PORTERR, "MPS Tx destination port is disabled" },
5910 { F_FRMERR, "MPS Tx framing error" },
5911 { F_SECNTERR, "MPS Tx SOP/EOP error" },
5912 { F_BUBBLE, "MPS Tx underflow" },
5913 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" },
5914 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" },
5915 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" },
5916 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" },
5917 { 0 }
5918 };
5919 static const struct intr_info mps_tx_intr_info = {
5920 .name = "MPS_TX_INT_CAUSE",
5921 .cause_reg = A_MPS_TX_INT_CAUSE,
5922 .enable_reg = A_MPS_TX_INT_ENABLE,
5923 .fatal = 0x1ffff,
5924 .flags = IHF_FATAL_IFF_ENABLED,
5925 .details = mps_tx_intr_details,
5926 .actions = NULL,
5927 };
5928 static const struct intr_info mps_tx_intr_info2 = {
5929 .name = "MPS_TX_INT2_CAUSE",
5930 .cause_reg = A_MPS_TX_INT2_CAUSE,
5931 .enable_reg = A_MPS_TX_INT2_ENABLE,
5932 .fatal = 0xffffffff,
5933 .flags = IHF_FATAL_IFF_ENABLED,
5934 .details = NULL,
5935 .actions = NULL,
5936 };
5937 static const struct intr_info mps_tx_intr_info3 = {
5938 .name = "MPS_TX_INT3_CAUSE",
5939 .cause_reg = A_MPS_TX_INT3_CAUSE,
5940 .enable_reg = A_MPS_TX_INT3_ENABLE,
5941 .fatal = 0xffffffff,
5942 .flags = IHF_FATAL_IFF_ENABLED,
5943 .details = NULL,
5944 .actions = NULL,
5945 };
5946 static const struct intr_info mps_tx_intr_info4 = {
5947 .name = "MPS_TX_INT4_CAUSE",
5948 .cause_reg = A_MPS_TX_INT4_CAUSE,
5949 .enable_reg = A_MPS_TX_INT4_ENABLE,
5950 .fatal = 0xffffffff,
5951 .flags = IHF_FATAL_IFF_ENABLED,
5952 .details = NULL,
5953 .actions = NULL,
5954 };
5955 static const struct intr_details mps_trc_intr_details[] = {
5956 { F_MISCPERR, "MPS TRC misc parity error" },
5957 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
5958 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" },
5959 { 0 }
5960 };
5961 static const struct intr_info mps_trc_intr_info = {
5962 .name = "MPS_TRC_INT_CAUSE",
5963 .cause_reg = A_MPS_TRC_INT_CAUSE,
5964 .enable_reg = A_MPS_TRC_INT_ENABLE,
5965 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
5966 .flags = 0,
5967 .details = mps_trc_intr_details,
5968 .actions = NULL,
5969 };
5970 static const struct intr_info t7_mps_trc_intr_info = {
5971 .name = "MPS_TRC_INT_CAUSE",
5972 .cause_reg = A_T7_MPS_TRC_INT_CAUSE,
5973 .enable_reg = A_T7_MPS_TRC_INT_ENABLE,
5974 .fatal = 0xffffffff,
5975 .flags = IHF_FATAL_IFF_ENABLED,
5976 .details = mps_trc_intr_details,
5977 .actions = NULL,
5978 };
5979 static const struct intr_info t7_mps_trc_intr_info2 = {
5980 .name = "MPS_TRC_INT_CAUSE2",
5981 .cause_reg = A_MPS_TRC_INT_CAUSE2,
5982 .enable_reg = A_MPS_TRC_INT_ENABLE2,
5983 .fatal = 0xffffffff,
5984 .flags = IHF_FATAL_IFF_ENABLED,
5985 .details = NULL,
5986 .actions = NULL,
5987 };
5988 static const struct intr_details mps_stat_sram_intr_details[] = {
5989 { 0xffffffff, "MPS statistics SRAM parity error" },
5990 { 0 }
5991 };
5992 static const struct intr_info mps_stat_sram_intr_info = {
5993 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
5994 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
5995 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
5996 .fatal = 0x1fffffff,
5997 .flags = IHF_FATAL_IFF_ENABLED,
5998 .details = mps_stat_sram_intr_details,
5999 .actions = NULL,
6000 };
6001 static const struct intr_details mps_stat_tx_intr_details[] = {
6002 { 0xffffff, "MPS statistics Tx FIFO parity error" },
6003 { 0 }
6004 };
6005 static const struct intr_info mps_stat_tx_intr_info = {
6006 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
6007 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
6008 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,
6009 .fatal = 0xffffff,
6010 .flags = IHF_FATAL_IFF_ENABLED,
6011 .details = mps_stat_tx_intr_details,
6012 .actions = NULL,
6013 };
6014 static const struct intr_details mps_stat_rx_intr_details[] = {
6015 { 0xffffff, "MPS statistics Rx FIFO parity error" },
6016 { 0 }
6017 };
6018 static const struct intr_info mps_stat_rx_intr_info = {
6019 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
6020 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
6021 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,
6022 .fatal = 0xffffff,
6023 .flags = 0,
6024 .details = mps_stat_rx_intr_details,
6025 .actions = NULL,
6026 };
6027 static const struct intr_details mps_cls_intr_details[] = {
6028 { F_HASHSRAM, "MPS hash SRAM parity error" },
6029 { F_MATCHTCAM, "MPS match TCAM parity error" },
6030 { F_MATCHSRAM, "MPS match SRAM parity error" },
6031 { 0 }
6032 };
6033 static const struct intr_info mps_cls_intr_info = {
6034 .name = "MPS_CLS_INT_CAUSE",
6035 .cause_reg = A_MPS_CLS_INT_CAUSE,
6036 .enable_reg = A_MPS_CLS_INT_ENABLE,
6037 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM,
6038 .flags = 0,
6039 .details = mps_cls_intr_details,
6040 .actions = NULL,
6041 };
6042 static const struct intr_details mps_stat_sram1_intr_details[] = {
6043 { 0xff, "MPS statistics SRAM1 parity error" },
6044 { 0 }
6045 };
6046 static const struct intr_info mps_stat_sram1_intr_info = {
6047 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
6048 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
6049 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,
6050 .fatal = 0xff,
6051 .flags = 0,
6052 .details = mps_stat_sram1_intr_details,
6053 .actions = NULL,
6054 };
6055 bool fatal = false;
6056
6057 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, flags);
6058 if (chip_id(adap) > CHELSIO_T6) {
6059 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info2, 0, flags);
6060 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info3, 0, flags);
6061 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info4, 0, flags);
6062 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info5, 0, flags);
6063 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info6, 0, flags);
6064 }
6065 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, flags);
6066 if (chip_id(adap) > CHELSIO_T6) {
6067 fatal |= t4_handle_intr(adap, &mps_tx_intr_info2, 0, flags);
6068 fatal |= t4_handle_intr(adap, &mps_tx_intr_info3, 0, flags);
6069 fatal |= t4_handle_intr(adap, &mps_tx_intr_info4, 0, flags);
6070 fatal |= t4_handle_intr(adap, &t7_mps_trc_intr_info, 0, flags);
6071 fatal |= t4_handle_intr(adap, &t7_mps_trc_intr_info2, 0, flags);
6072 } else
6073 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, flags);
6074 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, flags);
6075 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, flags);
6076 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, flags);
6077 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, flags);
6078 if (chip_id(adap) > CHELSIO_T4)
6079 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, flags);
6080
6081 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
6082 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */
6083
6084 return (fatal);
6085
6086 }
6087
6088 /*
6089 * EDC/MC interrupt handler.
6090 */
mem_intr_handler(struct adapter * adap,int idx,int flags)6091 static bool mem_intr_handler(struct adapter *adap, int idx, int flags)
6092 {
6093 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
6094 unsigned int count_reg, v;
6095 static const struct intr_details mem_intr_details[] = {
6096 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" },
6097 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" },
6098 { F_PERR_INT_CAUSE, "FIFO parity error" },
6099 { 0 }
6100 };
6101 char rname[32];
6102 struct intr_info ii = {
6103 .name = &rname[0],
6104 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE,
6105 .details = mem_intr_details,
6106 .flags = 0,
6107 .actions = NULL,
6108 };
6109 bool fatal = false;
6110 int i = 0;
6111
6112 switch (idx) {
6113 case MEM_EDC1: i = 1;
6114 /* fall through */
6115 case MEM_EDC0:
6116 snprintf(rname, sizeof(rname), "EDC%u_INT_CAUSE", i);
6117 if (is_t4(adap)) {
6118 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, i);
6119 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, i);
6120 count_reg = EDC_REG(A_EDC_ECC_STATUS, i);
6121 } else {
6122 ii.cause_reg = EDC_T5_REG(A_EDC_H_INT_CAUSE, i);
6123 ii.enable_reg = EDC_T5_REG(A_EDC_H_INT_ENABLE, i);
6124 count_reg = EDC_T5_REG(A_EDC_H_ECC_STATUS, i);
6125 }
6126 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6127 if (chip_id(adap) > CHELSIO_T6) {
6128 snprintf(rname, sizeof(rname), "EDC%u_PAR_CAUSE", i);
6129 ii.cause_reg = EDC_T5_REG(A_EDC_H_PAR_CAUSE, i);
6130 ii.enable_reg = EDC_T5_REG(A_EDC_H_PAR_ENABLE, i);
6131 ii.fatal = 0xffffffff;
6132 ii.details = NULL;
6133 ii.flags = IHF_FATAL_IFF_ENABLED;
6134 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6135 }
6136 break;
6137 case MEM_MC1:
6138 if (is_t4(adap) || is_t6(adap))
6139 return (false);
6140 i = 1;
6141 /* fall through */
6142 case MEM_MC0:
6143 snprintf(rname, sizeof(rname), "MC%u_INT_CAUSE", i);
6144 if (is_t4(adap)) {
6145 ii.cause_reg = A_MC_INT_CAUSE;
6146 ii.enable_reg = A_MC_INT_ENABLE;
6147 count_reg = A_MC_ECC_STATUS;
6148 } else if (chip_id(adap) < CHELSIO_T7) {
6149 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, i);
6150 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, i);
6151 count_reg = MC_REG(A_MC_P_ECC_STATUS, i);
6152 } else {
6153 ii.cause_reg = MC_T7_REG(A_T7_MC_P_INT_CAUSE, i);
6154 ii.enable_reg = MC_T7_REG(A_T7_MC_P_INT_ENABLE, i);
6155 count_reg = MC_T7_REG(A_T7_MC_P_ECC_STATUS, i);
6156 }
6157 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6158
6159 snprintf(rname, sizeof(rname), "MC%u_PAR_CAUSE", i);
6160 if (is_t4(adap)) {
6161 ii.cause_reg = A_MC_PAR_CAUSE;
6162 ii.enable_reg = A_MC_PAR_ENABLE;
6163 } else if (chip_id(adap) < CHELSIO_T7) {
6164 ii.cause_reg = MC_REG(A_MC_P_PAR_CAUSE, i);
6165 ii.enable_reg = MC_REG(A_MC_P_PAR_ENABLE, i);
6166 } else {
6167 ii.cause_reg = MC_T7_REG(A_T7_MC_P_PAR_CAUSE, i);
6168 ii.enable_reg = MC_T7_REG(A_T7_MC_P_PAR_ENABLE, i);
6169 }
6170 ii.fatal = 0xffffffff;
6171 ii.details = NULL;
6172 ii.flags = IHF_FATAL_IFF_ENABLED;
6173 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6174
6175 if (chip_id(adap) > CHELSIO_T6) {
6176 snprintf(rname, sizeof(rname), "MC%u_DDRCTL_INT_CAUSE", i);
6177 ii.cause_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_CAUSE, i);
6178 ii.enable_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_ENABLE, i);
6179 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6180
6181 snprintf(rname, sizeof(rname), "MC%u_ECC_UE_INT_CAUSE", i);
6182 ii.cause_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_CAUSE, i);
6183 ii.enable_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_ENABLE, i);
6184 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6185 }
6186 break;
6187 }
6188
6189 v = t4_read_reg(adap, count_reg);
6190 if (v != 0) {
6191 if (G_ECC_UECNT(v) != 0 && !(flags & IHF_NO_SHOW)) {
6192 CH_ALERT(adap,
6193 " %s: %u uncorrectable ECC data error(s)\n",
6194 name[idx], G_ECC_UECNT(v));
6195 }
6196 if (G_ECC_CECNT(v) != 0 && !(flags & IHF_NO_SHOW)) {
6197 if (idx <= MEM_EDC1)
6198 t4_edc_err_read(adap, idx);
6199 CH_WARN_RATELIMIT(adap,
6200 " %s: %u correctable ECC data error(s)\n",
6201 name[idx], G_ECC_CECNT(v));
6202 }
6203 t4_write_reg(adap, count_reg, 0xffffffff);
6204 }
6205
6206 return (fatal);
6207 }
6208
ma_wrap_status(struct adapter * adap,int arg,int flags)6209 static bool ma_wrap_status(struct adapter *adap, int arg, int flags)
6210 {
6211 u32 v;
6212
6213 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS);
6214 if (!(flags & IHF_NO_SHOW)) {
6215 CH_ALERT(adap,
6216 " MA address wrap-around by client %u to address %#x\n",
6217 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4);
6218 }
6219 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v);
6220
6221 return (false);
6222 }
6223
6224
6225 /*
6226 * MA interrupt handler.
6227 */
ma_intr_handler(struct adapter * adap,int arg,int flags)6228 static bool ma_intr_handler(struct adapter *adap, int arg, int flags)
6229 {
6230 static const struct intr_action ma_intr_actions[] = {
6231 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status },
6232 { 0 },
6233 };
6234 static const struct intr_info ma_intr_info = {
6235 .name = "MA_INT_CAUSE",
6236 .cause_reg = A_MA_INT_CAUSE,
6237 .enable_reg = A_MA_INT_ENABLE,
6238 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE,
6239 .flags = IHF_FATAL_IFF_ENABLED,
6240 .details = NULL,
6241 .actions = ma_intr_actions,
6242 };
6243 static const struct intr_info ma_perr_status1 = {
6244 .name = "MA_PARITY_ERROR_STATUS1",
6245 .cause_reg = A_MA_PARITY_ERROR_STATUS1,
6246 .enable_reg = A_MA_PARITY_ERROR_ENABLE1,
6247 .fatal = 0xffffffff,
6248 .flags = 0,
6249 .details = NULL,
6250 .actions = NULL,
6251 };
6252 static const struct intr_info ma_perr_status2 = {
6253 .name = "MA_PARITY_ERROR_STATUS2",
6254 .cause_reg = A_MA_PARITY_ERROR_STATUS2,
6255 .enable_reg = A_MA_PARITY_ERROR_ENABLE2,
6256 .fatal = 0xffffffff,
6257 .flags = 0,
6258 .details = NULL,
6259 .actions = NULL,
6260 };
6261 bool fatal;
6262
6263 fatal = false;
6264 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, flags);
6265 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, flags);
6266 if (chip_id(adap) > CHELSIO_T4)
6267 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, flags);
6268
6269 return (fatal);
6270 }
6271
6272 /*
6273 * SMB interrupt handler.
6274 */
smb_intr_handler(struct adapter * adap,int arg,int flags)6275 static bool smb_intr_handler(struct adapter *adap, int arg, int flags)
6276 {
6277 static const struct intr_details smb_int_cause_fields[] = {
6278 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" },
6279 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" },
6280 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" },
6281 { 0 }
6282 };
6283 static const struct intr_info smb_int_cause = {
6284 .name = "SMB_INT_CAUSE",
6285 .cause_reg = A_SMB_INT_CAUSE,
6286 .enable_reg = A_SMB_INT_ENABLE,
6287 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT,
6288 .flags = 0,
6289 .details = smb_int_cause_fields,
6290 .actions = NULL,
6291 };
6292 return (t4_handle_intr(adap, &smb_int_cause, 0, flags));
6293 }
6294
6295 /*
6296 * NC-SI interrupt handler.
6297 */
ncsi_intr_handler(struct adapter * adap,int arg,int flags)6298 static bool ncsi_intr_handler(struct adapter *adap, int arg, int flags)
6299 {
6300 static const struct intr_details ncsi_int_cause_fields[] = {
6301 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" },
6302 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" },
6303 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" },
6304 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" },
6305 { 0 }
6306 };
6307 static const struct intr_info ncsi_int_cause = {
6308 .name = "NCSI_INT_CAUSE",
6309 .cause_reg = A_NCSI_INT_CAUSE,
6310 .enable_reg = A_NCSI_INT_ENABLE,
6311 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR |
6312 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR,
6313 .flags = 0,
6314 .details = ncsi_int_cause_fields,
6315 .actions = NULL,
6316 };
6317 static const struct intr_info ncsi_xgmac0_int_cause = {
6318 .name = "NCSI_XGMAC0_INT_CAUSE",
6319 .cause_reg = A_NCSI_XGMAC0_INT_CAUSE,
6320 .enable_reg = A_NCSI_XGMAC0_INT_ENABLE,
6321 .fatal = 0,
6322 .flags = 0,
6323 .details = NULL,
6324 .actions = NULL,
6325 };
6326 bool fatal = false;
6327
6328 fatal |= t4_handle_intr(adap, &ncsi_int_cause, 0, flags);
6329 if (chip_id(adap) > CHELSIO_T6)
6330 fatal |= t4_handle_intr(adap, &ncsi_xgmac0_int_cause, 0, flags);
6331 return (fatal);
6332 }
6333
6334 /*
6335 * MAC interrupt handler.
6336 */
mac_intr_handler(struct adapter * adap,int port,int flags)6337 static bool mac_intr_handler(struct adapter *adap, int port, int flags)
6338 {
6339 static const struct intr_info mac_int_cause_cmn = {
6340 .name = "MAC_INT_CAUSE_CMN",
6341 .cause_reg = A_MAC_INT_CAUSE_CMN,
6342 .enable_reg = A_MAC_INT_EN_CMN,
6343 .fatal = 0,
6344 .flags = 0,
6345 .details = NULL,
6346 .actions = NULL,
6347 };
6348 static const struct intr_info mac_perr_cause_mtip = {
6349 .name = "MAC_PERR_INT_CAUSE_MTIP",
6350 .cause_reg = A_MAC_PERR_INT_CAUSE_MTIP,
6351 .enable_reg = A_MAC_PERR_INT_EN_MTIP,
6352 .fatal = 0xffffffff,
6353 .flags = IHF_FATAL_IFF_ENABLED | IHF_IGNORE_IF_DISABLED,
6354 .details = NULL,
6355 .actions = NULL,
6356 };
6357 static const struct intr_info mac_cerr_cause_mtip = {
6358 .name = "MAC_CERR_INT_CAUSE_MTIP",
6359 .cause_reg = A_MAC_CERR_INT_CAUSE_MTIP,
6360 .enable_reg = A_MAC_CERR_INT_EN_MTIP,
6361 .fatal = 0,
6362 .flags = 0,
6363 .details = NULL,
6364 .actions = NULL,
6365 };
6366 static const struct intr_info mac_ios_int_cause_quad0 = {
6367 .name = "MAC_IOS_INTR_CAUSE_QUAD0",
6368 .cause_reg = A_MAC_IOS_INTR_CAUSE_QUAD0,
6369 .enable_reg = A_MAC_IOS_INTR_EN_QUAD0,
6370 .fatal = 0,
6371 .flags = 0,
6372 .details = NULL,
6373 .actions = NULL,
6374 };
6375 static const struct intr_info mac_ios_int_cause_quad1 = {
6376 .name = "MAC_IOS_INTR_CAUSE_QUAD1",
6377 .cause_reg = A_MAC_IOS_INTR_CAUSE_QUAD1,
6378 .enable_reg = A_MAC_IOS_INTR_EN_QUAD1,
6379 .fatal = 0,
6380 .flags = 0,
6381 .details = NULL,
6382 .actions = NULL,
6383 };
6384 static const struct intr_details mac_intr_details[] = {
6385 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" },
6386 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" },
6387 { 0 }
6388 };
6389 char name[32];
6390 struct intr_info ii;
6391 bool fatal = false;
6392
6393 if (port > 1 && is_t6(adap))
6394 return (false);
6395
6396 if (is_t4(adap)) {
6397 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
6398 ii.name = &name[0];
6399 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
6400 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);
6401 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
6402 ii.flags = 0;
6403 ii.details = mac_intr_details;
6404 ii.actions = NULL;
6405 } else if (chip_id(adap) < CHELSIO_T7) {
6406 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
6407 ii.name = &name[0];
6408 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
6409 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);
6410 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
6411 ii.flags = 0;
6412 ii.details = mac_intr_details;
6413 ii.actions = NULL;
6414 } else {
6415 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
6416 ii.name = &name[0];
6417 ii.cause_reg = T7_PORT_REG(port, A_T7_MAC_PORT_INT_CAUSE);
6418 ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_INT_EN);
6419 ii.fatal = 0xffffffff;
6420 ii.flags = IHF_FATAL_IFF_ENABLED;
6421 ii.details = NULL;
6422 ii.actions = NULL;
6423 }
6424 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6425 if (is_t4(adap))
6426 return (fatal);
6427
6428 MPASS(chip_id(adap) >= CHELSIO_T5);
6429 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
6430 if (chip_id(adap) > CHELSIO_T6) {
6431 ii.name = &name[0];
6432 ii.cause_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_CAUSE);
6433 ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_EN);
6434 ii.fatal = 0xffffffff;
6435 ii.flags = IHF_FATAL_IFF_ENABLED;
6436 ii.details = NULL;
6437 ii.actions = NULL;
6438 } else {
6439 ii.name = &name[0];
6440 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
6441 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);
6442 ii.fatal = 0xffffffff;
6443 ii.flags = IHF_FATAL_IFF_ENABLED;
6444 ii.details = NULL;
6445 ii.actions = NULL;
6446 }
6447 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6448 if (is_t5(adap))
6449 return (fatal);
6450
6451 MPASS(chip_id(adap) >= CHELSIO_T6);
6452 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
6453 if (chip_id(adap) > CHELSIO_T6) {
6454 ii.name = &name[0];
6455 ii.cause_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_CAUSE_100G);
6456 ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_EN_100G);
6457 ii.fatal = 0xffffffff;
6458 ii.flags = IHF_FATAL_IFF_ENABLED;
6459 ii.details = NULL;
6460 ii.actions = NULL;
6461 } else {
6462 ii.name = &name[0];
6463 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
6464 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);
6465 ii.fatal = 0xffffffff;
6466 ii.flags = IHF_FATAL_IFF_ENABLED;
6467 ii.details = NULL;
6468 ii.actions = NULL;
6469 }
6470 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6471 if (is_t6(adap))
6472 return (fatal);
6473
6474 MPASS(chip_id(adap) >= CHELSIO_T7);
6475 fatal |= t4_handle_intr(adap, &mac_int_cause_cmn, 0, flags);
6476 fatal |= t4_handle_intr(adap, &mac_perr_cause_mtip, 0, flags);
6477 fatal |= t4_handle_intr(adap, &mac_cerr_cause_mtip, 0, flags);
6478 fatal |= t4_handle_intr(adap, &mac_ios_int_cause_quad0, 0, flags);
6479 fatal |= t4_handle_intr(adap, &mac_ios_int_cause_quad1, 0, flags);
6480
6481 return (fatal);
6482 }
6483
pl_timeout_status(struct adapter * adap,int arg,int flags)6484 static bool pl_timeout_status(struct adapter *adap, int arg, int flags)
6485 {
6486 if (flags & IHF_NO_SHOW)
6487 return (false);
6488
6489 CH_ALERT(adap, " PL_TIMEOUT_STATUS 0x%08x 0x%08x\n",
6490 t4_read_reg(adap, A_PL_TIMEOUT_STATUS0),
6491 t4_read_reg(adap, A_PL_TIMEOUT_STATUS1));
6492
6493 return (false);
6494 }
6495
plpl_intr_handler(struct adapter * adap,int arg,int flags)6496 static bool plpl_intr_handler(struct adapter *adap, int arg, int flags)
6497 {
6498 static const struct intr_details plpl_int_cause_fields[] = {
6499 { F_PL_BUSPERR, "Bus parity error" },
6500 { F_FATALPERR, "Fatal parity error" },
6501 { F_INVALIDACCESS, "Global reserved memory access" },
6502 { F_TIMEOUT, "Bus timeout" },
6503 { F_PLERR, "Module reserved access" },
6504 { F_PERRVFID, "VFID_MAP parity error" },
6505 { 0 }
6506 };
6507 static const struct intr_action plpl_int_cause_actions[] = {
6508 { F_TIMEOUT, -1, pl_timeout_status },
6509 { 0 },
6510 };
6511 static const struct intr_info plpl_int_cause = {
6512 .name = "PL_PL_INT_CAUSE",
6513 .cause_reg = A_PL_PL_INT_CAUSE,
6514 .enable_reg = A_PL_PL_INT_ENABLE,
6515 .fatal = F_FATALPERR | F_PERRVFID,
6516 .flags = IHF_FATAL_IFF_ENABLED | IHF_IGNORE_IF_DISABLED,
6517 .details = plpl_int_cause_fields,
6518 .actions = plpl_int_cause_actions,
6519 };
6520
6521 return (t4_handle_intr(adap, &plpl_int_cause, 0, flags));
6522 }
6523
6524 /* similar to t4_port_reg */
6525 static inline u32
t7_tlstx_reg(u8 instance,u8 channel,u32 reg)6526 t7_tlstx_reg(u8 instance, u8 channel, u32 reg)
6527 {
6528 MPASS(instance <= 1);
6529 MPASS(channel < NUM_TLS_TX_CH_INSTANCES);
6530 return (instance * (CRYPTO_1_BASE_ADDR - CRYPTO_0_BASE_ADDR) +
6531 TLS_TX_CH_REG(reg, channel));
6532 }
6533
6534 /*
6535 * CRYPTO (aka TLS_TX) interrupt handler.
6536 */
tlstx_intr_handler(struct adapter * adap,int idx,int flags)6537 static bool tlstx_intr_handler(struct adapter *adap, int idx, int flags)
6538 {
6539 static const struct intr_details tlstx_int_cause_fields[] = {
6540 { F_KEX_CERR, "KEX SRAM Correctable error" },
6541 { F_KEYLENERR, "IPsec Key length error" },
6542 { F_INTF1_PERR, "Input Interface1 parity error" },
6543 { F_INTF0_PERR, "Input Interface0 parity error" },
6544 { F_KEX_PERR, "KEX SRAM Parity error" },
6545 { 0 }
6546 };
6547 struct intr_info ii = {
6548 .fatal = F_KEX_PERR | F_INTF0_PERR | F_INTF1_PERR,
6549 .flags = IHF_FATAL_IFF_ENABLED,
6550 .details = tlstx_int_cause_fields,
6551 .actions = NULL,
6552 };
6553 char name[32];
6554 int ch;
6555 bool fatal = false;
6556
6557 for (ch = 0; ch < NUM_TLS_TX_CH_INSTANCES; ch++) {
6558 snprintf(name, sizeof(name), "TLSTX%u_CH%u_INT_CAUSE", idx, ch);
6559 ii.name = &name[0];
6560 ii.cause_reg = t7_tlstx_reg(idx, ch, A_TLS_TX_CH_INT_CAUSE);
6561 ii.enable_reg = t7_tlstx_reg(idx, ch, A_TLS_TX_CH_INT_ENABLE);
6562 fatal |= t4_handle_intr(adap, &ii, 0, flags);
6563 }
6564
6565 return (fatal);
6566 }
6567
6568 /*
6569 * HMA interrupt handler.
6570 */
hma_intr_handler(struct adapter * adap,int idx,int flags)6571 static bool hma_intr_handler(struct adapter *adap, int idx, int flags)
6572 {
6573 static const struct intr_details hma_int_cause_fields[] = {
6574 { F_GK_UF_INT_CAUSE, "Gatekeeper underflow" },
6575 { F_IDTF_INT_CAUSE, "Invalid descriptor fault" },
6576 { F_OTF_INT_CAUSE, "Offset translation fault" },
6577 { F_RTF_INT_CAUSE, "Region translation fault" },
6578 { F_PCIEMST_INT_CAUSE, "PCIe master access error" },
6579 { F_MAMST_INT_CAUSE, "MA master access error" },
6580 { 1, "FIFO parity error" },
6581 { 0 }
6582 };
6583 static const struct intr_info hma_int_cause = {
6584 .name = "HMA_INT_CAUSE",
6585 .cause_reg = A_HMA_INT_CAUSE,
6586 .enable_reg = A_HMA_INT_ENABLE,
6587 .fatal = 7,
6588 .flags = 0,
6589 .details = hma_int_cause_fields,
6590 .actions = NULL,
6591 };
6592
6593 return (t4_handle_intr(adap, &hma_int_cause, 0, flags));
6594 }
6595
6596 /*
6597 * CRYPTO_KEY interrupt handler.
6598 */
cryptokey_intr_handler(struct adapter * adap,int idx,int flags)6599 static bool cryptokey_intr_handler(struct adapter *adap, int idx, int flags)
6600 {
6601 static const struct intr_details cryptokey_int_cause_fields[] = {
6602 { F_MA_FIFO_PERR, "MA arbiter FIFO parity error" },
6603 { F_MA_RSP_PERR, "MA response IF parity error" },
6604 { F_ING_CACHE_DATA_PERR, "Ingress key cache data parity error" },
6605 { F_ING_CACHE_TAG_PERR, "Ingress key cache tag parity error" },
6606 { F_LKP_KEY_REQ_PERR, "Ingress key req parity error" },
6607 { F_LKP_CLIP_TCAM_PERR, "Ingress LKP CLIP TCAM parity error" },
6608 { F_LKP_MAIN_TCAM_PERR, "Ingress LKP main TCAM parity error" },
6609 { F_EGR_KEY_REQ_PERR, "Egress key req or FIFO3 parity error" },
6610 { F_EGR_CACHE_DATA_PERR, "Egress key cache data parity error" },
6611 { F_EGR_CACHE_TAG_PERR, "Egress key cache tag parity error" },
6612 { F_CIM_PERR, "CIM interface parity error" },
6613 { F_MA_INV_RSP_TAG, "MA invalid response tag" },
6614 { F_ING_KEY_RANGE_ERR, "Ingress key range error" },
6615 { F_ING_MFIFO_OVFL, "Ingress MFIFO overflow" },
6616 { F_LKP_REQ_OVFL, "Ingress lookup FIFO overflow" },
6617 { F_EOK_WAIT_ERR, "EOK wait error" },
6618 { F_EGR_KEY_RANGE_ERR, "Egress key range error" },
6619 { F_EGR_MFIFO_OVFL, "Egress MFIFO overflow" },
6620 { F_SEQ_WRAP_HP_OVFL, "Sequence wrap (hi-pri)" },
6621 { F_SEQ_WRAP_LP_OVFL, "Sequence wrap (lo-pri)" },
6622 { F_EGR_SEQ_WRAP_HP, "Egress sequence wrap (hi-pri)" },
6623 { F_EGR_SEQ_WRAP_LP, "Egress sequence wrap (lo-pri)" },
6624 { 0 }
6625 };
6626 static const struct intr_info cryptokey_int_cause = {
6627 .name = "CRYPTO_KEY_INT_CAUSE",
6628 .cause_reg = A_CRYPTO_KEY_INT_CAUSE,
6629 .enable_reg = A_CRYPTO_KEY_INT_ENABLE,
6630 .fatal = 0xffffffff,
6631 .flags = IHF_FATAL_IFF_ENABLED,
6632 .details = cryptokey_int_cause_fields,
6633 .actions = NULL,
6634 };
6635
6636 return (t4_handle_intr(adap, &cryptokey_int_cause, 0, flags));
6637 }
6638
6639 /*
6640 * GCACHE interrupt handler.
6641 */
gcache_intr_handler(struct adapter * adap,int idx,int flags)6642 static bool gcache_intr_handler(struct adapter *adap, int idx, int flags)
6643 {
6644 static const struct intr_details gcache_int_cause_fields[] = {
6645 { F_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE, "GC1 SRAM rsp dataq perr" },
6646 { F_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE, "GC0 SRAM rsp dataq perr" },
6647 { F_GC1_WQDATA_FIFO_PERR_INT_CAUSE, "GC1 wqdata FIFO perr" },
6648 { F_GC0_WQDATA_FIFO_PERR_INT_CAUSE, "GC0 wqdata FIFO perr" },
6649 { F_GC1_RDTAG_QUEUE_PERR_INT_CAUSE, "GC1 rdtag queue perr" },
6650 { F_GC0_RDTAG_QUEUE_PERR_INT_CAUSE, "GC0 rdtag queue perr" },
6651 { F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE, "GC1 SRAM rdtag queue perr" },
6652 { F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE, "GC0 SRAM rdtag queue perr" },
6653 { F_GC1_RSP_PERR_INT_CAUSE, "GC1 rsp perr" },
6654 { F_GC0_RSP_PERR_INT_CAUSE, "GC0 rsp perr" },
6655 { F_GC1_LRU_UERR_INT_CAUSE, "GC1 lru uerr" },
6656 { F_GC0_LRU_UERR_INT_CAUSE, "GC0 lru uerr" },
6657 { F_GC1_TAG_UERR_INT_CAUSE, "GC1 tag uerr" },
6658 { F_GC0_TAG_UERR_INT_CAUSE, "GC0 tag uerr" },
6659 { F_GC1_LRU_CERR_INT_CAUSE, "GC1 lru cerr" },
6660 { F_GC0_LRU_CERR_INT_CAUSE, "GC0 lru cerr" },
6661 { F_GC1_TAG_CERR_INT_CAUSE, "GC1 tag cerr" },
6662 { F_GC0_TAG_CERR_INT_CAUSE, "GC0 tag cerr" },
6663 { F_GC1_CE_INT_CAUSE, "GC1 correctable error" },
6664 { F_GC0_CE_INT_CAUSE, "GC0 correctable error" },
6665 { F_GC1_UE_INT_CAUSE, "GC1 uncorrectable error" },
6666 { F_GC0_UE_INT_CAUSE, "GC0 uncorrectable error" },
6667 { F_GC1_CMD_PAR_INT_CAUSE, "GC1 cmd perr" },
6668 { F_GC1_DATA_PAR_INT_CAUSE, "GC1 data perr" },
6669 { F_GC0_CMD_PAR_INT_CAUSE, "GC0 cmd perr" },
6670 { F_GC0_DATA_PAR_INT_CAUSE, "GC0 data perr" },
6671 { F_ILLADDRACCESS1_INT_CAUSE, "GC1 illegal address access" },
6672 { F_ILLADDRACCESS0_INT_CAUSE, "GC0 illegal address access" },
6673 { 0 }
6674 };
6675 static const struct intr_info gcache_perr_cause = {
6676 .name = "GCACHE_PAR_CAUSE",
6677 .cause_reg = A_GCACHE_PAR_CAUSE,
6678 .enable_reg = A_GCACHE_PAR_ENABLE,
6679 .fatal = 0xffffffff,
6680 .flags = IHF_FATAL_IFF_ENABLED,
6681 .details = NULL,
6682 .actions = NULL,
6683 };
6684 static const struct intr_info gcache_int_cause = {
6685 .name = "GCACHE_INT_CAUSE",
6686 .cause_reg = A_GCACHE_INT_CAUSE,
6687 .enable_reg = A_GCACHE_INT_ENABLE,
6688 .fatal = 0,
6689 .flags = 0,
6690 .details = gcache_int_cause_fields,
6691 .actions = NULL,
6692 };
6693 bool fatal = false;
6694
6695 fatal |= t4_handle_intr(adap, &gcache_int_cause, 0, flags);
6696 fatal |= t4_handle_intr(adap, &gcache_perr_cause, 0, flags);
6697
6698 return (fatal);
6699 }
6700
6701 /*
6702 * ARM interrupt handler.
6703 */
arm_intr_handler(struct adapter * adap,int idx,int flags)6704 static bool arm_intr_handler(struct adapter *adap, int idx, int flags)
6705 {
6706 static const struct intr_info arm_perr_cause0 = {
6707 .name = "ARM_PERR_INT_CAUSE0",
6708 .cause_reg = A_ARM_PERR_INT_CAUSE0,
6709 .enable_reg = A_ARM_PERR_INT_ENB0,
6710 .fatal = 0xffffffff,
6711 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6712 .details = NULL,
6713 .actions = NULL,
6714 };
6715 static const struct intr_info arm_perr_cause1 = {
6716 .name = "ARM_PERR_INT_CAUSE1",
6717 .cause_reg = A_ARM_PERR_INT_CAUSE1,
6718 .enable_reg = A_ARM_PERR_INT_ENB1,
6719 .fatal = 0xffffffff,
6720 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6721 .details = NULL,
6722 .actions = NULL,
6723 };
6724 static const struct intr_info arm_perr_cause2 = {
6725 .name = "ARM_PERR_INT_CAUSE2",
6726 .cause_reg = A_ARM_PERR_INT_CAUSE2,
6727 .enable_reg = A_ARM_PERR_INT_ENB2,
6728 .fatal = 0xffffffff,
6729 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6730 .details = NULL,
6731 .actions = NULL,
6732 };
6733 static const struct intr_info arm_cerr_cause0 = {
6734 .name = "ARM_CERR_INT_CAUSE",
6735 .cause_reg = A_ARM_CERR_INT_CAUSE0,
6736 .enable_reg = A_ARM_CERR_INT_ENB0,
6737 .fatal = 0,
6738 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6739 .details = NULL,
6740 .actions = NULL,
6741 };
6742 static const struct intr_info arm_err_cause0 = {
6743 .name = "ARM_ERR_INT_CAUSE",
6744 .cause_reg = A_ARM_ERR_INT_CAUSE0,
6745 .enable_reg = A_ARM_ERR_INT_ENB0,
6746 .fatal = 0,
6747 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6748 .details = NULL,
6749 .actions = NULL,
6750 };
6751 static const struct intr_info arm_periph_cause = {
6752 .name = "ARM_PERIPHERAL_INT_CAUSE",
6753 .cause_reg = A_ARM_PERIPHERAL_INT_CAUSE,
6754 .enable_reg = A_ARM_PERIPHERAL_INT_ENB,
6755 .fatal = 0,
6756 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6757 .details = NULL,
6758 .actions = NULL,
6759 };
6760 static const struct intr_info arm_nvme_db_emu_cause = {
6761 .name = "ARM_NVME_DB_EMU_INT_CAUSE",
6762 .cause_reg = A_ARM_NVME_DB_EMU_INT_CAUSE,
6763 .enable_reg = A_ARM_NVME_DB_EMU_INT_ENABLE,
6764 .fatal = 0,
6765 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6766 .details = NULL,
6767 .actions = NULL,
6768 };
6769 bool fatal = false;
6770
6771 fatal |= t4_handle_intr(adap, &arm_perr_cause0, 0, flags);
6772 fatal |= t4_handle_intr(adap, &arm_perr_cause1, 0, flags);
6773 fatal |= t4_handle_intr(adap, &arm_perr_cause2, 0, flags);
6774 fatal |= t4_handle_intr(adap, &arm_cerr_cause0, 0, flags);
6775 fatal |= t4_handle_intr(adap, &arm_err_cause0, 0, flags);
6776 fatal |= t4_handle_intr(adap, &arm_periph_cause, 0, flags);
6777 fatal |= t4_handle_intr(adap, &arm_nvme_db_emu_cause, 0, flags);
6778
6779 return (fatal);
6780 }
6781
6782 static inline uint32_t
get_perr_ucause(struct adapter * sc,const struct intr_info * ii)6783 get_perr_ucause(struct adapter *sc, const struct intr_info *ii)
6784 {
6785 uint32_t cause;
6786
6787 cause = t4_read_reg(sc, ii->cause_reg);
6788 if (ii->flags & IHF_IGNORE_IF_DISABLED)
6789 cause &= t4_read_reg(sc, ii->enable_reg);
6790 return (cause);
6791 }
6792
6793 static uint32_t
t4_perr_to_ic(struct adapter * adap,uint32_t perr)6794 t4_perr_to_ic(struct adapter *adap, uint32_t perr)
6795 {
6796 uint32_t mask;
6797
6798 if (adap->chip_params->nchan > 2)
6799 mask = F_MAC0 | F_MAC1 | F_MAC2 | F_MAC3;
6800 else
6801 mask = F_MAC0 | F_MAC1;
6802 return (perr & mask ? perr | mask : perr);
6803 }
6804
6805 static uint32_t
t7_perr_to_ic1(uint32_t perr)6806 t7_perr_to_ic1(uint32_t perr)
6807 {
6808 uint32_t cause = 0;
6809
6810 if (perr & F_T7_PL_PERR_ULP_TX)
6811 cause |= F_T7_ULP_TX;
6812 if (perr & F_T7_PL_PERR_SGE)
6813 cause |= F_T7_SGE;
6814 if (perr & F_T7_PL_PERR_HMA)
6815 cause |= F_T7_HMA;
6816 if (perr & F_T7_PL_PERR_CPL_SWITCH)
6817 cause |= F_T7_CPL_SWITCH;
6818 if (perr & F_T7_PL_PERR_ULP_RX)
6819 cause |= F_T7_ULP_RX;
6820 if (perr & F_T7_PL_PERR_PM_RX)
6821 cause |= F_T7_PM_RX;
6822 if (perr & F_T7_PL_PERR_PM_TX)
6823 cause |= F_T7_PM_TX;
6824 if (perr & F_T7_PL_PERR_MA)
6825 cause |= F_T7_MA;
6826 if (perr & F_T7_PL_PERR_TP)
6827 cause |= F_T7_TP;
6828 if (perr & F_T7_PL_PERR_LE)
6829 cause |= F_T7_LE;
6830 if (perr & F_T7_PL_PERR_EDC1)
6831 cause |= F_T7_EDC1;
6832 if (perr & F_T7_PL_PERR_EDC0)
6833 cause |= F_T7_EDC0;
6834 if (perr & F_T7_PL_PERR_MC1)
6835 cause |= F_T7_MC1;
6836 if (perr & F_T7_PL_PERR_MC0)
6837 cause |= F_T7_MC0;
6838 if (perr & F_T7_PL_PERR_PCIE)
6839 cause |= F_T7_PCIE;
6840 if (perr & F_T7_PL_PERR_UART)
6841 cause |= F_T7_UART;
6842 if (perr & F_T7_PL_PERR_PMU)
6843 cause |= F_PMU;
6844 if (perr & F_T7_PL_PERR_MAC)
6845 cause |= F_MAC0 | F_MAC1 | F_MAC2 | F_MAC3;
6846 if (perr & F_T7_PL_PERR_SMB)
6847 cause |= F_SMB;
6848 if (perr & F_T7_PL_PERR_SF)
6849 cause |= F_SF;
6850 if (perr & F_T7_PL_PERR_PL)
6851 cause |= F_PL;
6852 if (perr & F_T7_PL_PERR_NCSI)
6853 cause |= F_NCSI;
6854 if (perr & F_T7_PL_PERR_MPS)
6855 cause |= F_MPS;
6856 if (perr & F_T7_PL_PERR_MI)
6857 cause |= F_MI;
6858 if (perr & F_T7_PL_PERR_DBG)
6859 cause |= F_DBG;
6860 if (perr & F_T7_PL_PERR_I2CM)
6861 cause |= F_I2CM;
6862 if (perr & F_T7_PL_PERR_CIM)
6863 cause |= F_CIM;
6864
6865 return (cause);
6866 }
6867
6868 static uint32_t
t7_perr_to_ic2(uint32_t perr)6869 t7_perr_to_ic2(uint32_t perr)
6870 {
6871 uint32_t cause = 0;
6872
6873 if (perr & F_T7_PL_PERR_CRYPTO_KEY)
6874 cause |= F_CRYPTO_KEY;
6875 if (perr & F_T7_PL_PERR_CRYPTO1)
6876 cause |= F_CRYPTO1;
6877 if (perr & F_T7_PL_PERR_CRYPTO0)
6878 cause |= F_CRYPTO0;
6879 if (perr & F_T7_PL_PERR_GCACHE)
6880 cause |= F_GCACHE;
6881 if (perr & F_T7_PL_PERR_ARM)
6882 cause |= F_ARM;
6883
6884 return (cause);
6885 }
6886
6887 /**
6888 * t4_slow_intr_handler - control path interrupt handler
6889 * @adap: the adapter
6890 *
6891 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
6892 * The designation 'slow' is because it involves register reads, while
6893 * data interrupts typically don't involve any MMIOs.
6894 */
t4_slow_intr_handler(struct adapter * adap,int flags)6895 bool t4_slow_intr_handler(struct adapter *adap, int flags)
6896 {
6897 static const struct intr_details pl_int_cause_fields[] = {
6898 { F_MC1, "MC1" },
6899 { F_UART, "UART" },
6900 { F_ULP_TX, "ULP TX" },
6901 { F_SGE, "SGE" },
6902 { F_HMA, "HMA" },
6903 { F_CPL_SWITCH, "CPL Switch" },
6904 { F_ULP_RX, "ULP RX" },
6905 { F_PM_RX, "PM RX" },
6906 { F_PM_TX, "PM TX" },
6907 { F_MA, "MA" },
6908 { F_TP, "TP" },
6909 { F_LE, "LE" },
6910 { F_EDC1, "EDC1" },
6911 { F_EDC0, "EDC0" },
6912 { F_MC, "MC0" },
6913 { F_PCIE, "PCIE" },
6914 { F_PMU, "PMU" },
6915 { F_MAC3, "MAC3" },
6916 { F_MAC2, "MAC2" },
6917 { F_MAC1, "MAC1" },
6918 { F_MAC0, "MAC0" },
6919 { F_SMB, "SMB" },
6920 { F_SF, "SF" },
6921 { F_PL, "PL" },
6922 { F_NCSI, "NC-SI" },
6923 { F_MPS, "MPS" },
6924 { F_MI, "MI" },
6925 { F_DBG, "DBG" },
6926 { F_I2CM, "I2CM" },
6927 { F_CIM, "CIM" },
6928 { 0 }
6929 };
6930 static const struct intr_action pl_int_cause_actions[] = {
6931 { F_ULP_TX, -1, ulptx_intr_handler },
6932 { F_SGE, -1, sge_intr_handler },
6933 { F_CPL_SWITCH, -1, cplsw_intr_handler },
6934 { F_ULP_RX, -1, ulprx_intr_handler },
6935 { F_PM_RX, -1, pmtx_intr_handler },
6936 { F_PM_TX, -1, pmtx_intr_handler },
6937 { F_MA, -1, ma_intr_handler },
6938 { F_TP, -1, tp_intr_handler },
6939 { F_LE, -1, le_intr_handler },
6940 { F_EDC0, MEM_EDC0, mem_intr_handler },
6941 { F_EDC1, MEM_EDC1, mem_intr_handler },
6942 { F_MC0, MEM_MC0, mem_intr_handler },
6943 { F_MC1, MEM_MC1, mem_intr_handler },
6944 { F_PCIE, -1, pcie_intr_handler },
6945 { F_MAC0, 0, mac_intr_handler },
6946 { F_MAC1, 1, mac_intr_handler },
6947 { F_MAC2, 2, mac_intr_handler },
6948 { F_MAC3, 3, mac_intr_handler },
6949 { F_SMB, -1, smb_intr_handler },
6950 { F_PL, -1, plpl_intr_handler },
6951 { F_NCSI, -1, ncsi_intr_handler },
6952 { F_MPS, -1, mps_intr_handler },
6953 { F_CIM, -1, cim_intr_handler },
6954 { 0 }
6955 };
6956 static const struct intr_info pl_int_cause = {
6957 .name = "PL_INT_CAUSE",
6958 .cause_reg = A_PL_INT_CAUSE,
6959 .enable_reg = A_PL_INT_ENABLE,
6960 .fatal = 0,
6961 .flags = IHF_IGNORE_IF_DISABLED,
6962 .details = pl_int_cause_fields,
6963 .actions = pl_int_cause_actions,
6964 };
6965 static const struct intr_info pl_perr_cause = {
6966 .name = "PL_PERR_CAUSE",
6967 .cause_reg = A_PL_PERR_CAUSE,
6968 .enable_reg = A_PL_PERR_ENABLE,
6969 .fatal = 0xffffffff,
6970 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
6971 .details = pl_int_cause_fields,
6972 .actions = NULL,
6973 };
6974 static const struct intr_details t7_pl_int_cause_fields[] = {
6975 { F_T7_FLR, "FLR" },
6976 { F_T7_SW_CIM, "SW CIM" },
6977 { F_T7_ULP_TX, "ULP TX" },
6978 { F_T7_SGE, "SGE" },
6979 { F_T7_HMA, "HMA" },
6980 { F_T7_CPL_SWITCH, "CPL Switch" },
6981 { F_T7_ULP_RX, "ULP RX" },
6982 { F_T7_PM_RX, "PM RX" },
6983 { F_T7_PM_TX, "PM TX" },
6984 { F_T7_MA, "MA" },
6985 { F_T7_TP, "TP" },
6986 { F_T7_LE, "LE" },
6987 { F_T7_EDC1, "EDC1" },
6988 { F_T7_EDC0, "EDC0" },
6989 { F_T7_MC1, "MC1" },
6990 { F_T7_MC0, "MC0" },
6991 { F_T7_PCIE, "PCIE" },
6992 { F_T7_UART, "UART" },
6993 { F_PMU, "PMU" },
6994 { F_MAC3, "MAC3" },
6995 { F_MAC2, "MAC2" },
6996 { F_MAC1, "MAC1" },
6997 { F_MAC0, "MAC0" },
6998 { F_SMB, "SMB" },
6999 { F_SF, "SF" },
7000 { F_PL, "PL" },
7001 { F_NCSI, "NC-SI" },
7002 { F_MPS, "MPS" },
7003 { F_MI, "MI" },
7004 { F_DBG, "DBG" },
7005 { F_I2CM, "I2CM" },
7006 { F_CIM, "CIM" },
7007 { 0 }
7008 };
7009 static const struct intr_action t7_pl_int_cause_actions[] = {
7010 { F_T7_ULP_TX, -1, ulptx_intr_handler },
7011 { F_T7_SGE, -1, sge_intr_handler },
7012 { F_T7_HMA, -1, hma_intr_handler },
7013 { F_T7_CPL_SWITCH, -1, cplsw_intr_handler },
7014 { F_T7_ULP_RX, -1, ulprx_intr_handler },
7015 { F_T7_PM_RX, -1, pmrx_intr_handler },
7016 { F_T7_PM_TX, -1, pmtx_intr_handler },
7017 { F_T7_MA, -1, ma_intr_handler },
7018 { F_T7_TP, -1, tp_intr_handler },
7019 { F_T7_LE, -1, le_intr_handler },
7020 { F_T7_EDC0, MEM_EDC0, mem_intr_handler },
7021 { F_T7_EDC1, MEM_EDC1, mem_intr_handler },
7022 { F_T7_MC0, MEM_MC0, mem_intr_handler },
7023 { F_T7_MC1, MEM_MC1, mem_intr_handler },
7024 { F_T7_PCIE, -1, pcie_intr_handler },
7025 { F_MAC0, 0, mac_intr_handler },
7026 { F_MAC1, 1, mac_intr_handler },
7027 { F_MAC2, 2, mac_intr_handler },
7028 { F_MAC3, 3, mac_intr_handler },
7029 { F_SMB, -1, smb_intr_handler },
7030 { F_PL, -1, plpl_intr_handler },
7031 { F_NCSI, -1, ncsi_intr_handler },
7032 { F_MPS, -1, mps_intr_handler },
7033 { F_CIM, -1, cim_intr_handler },
7034 { 0 }
7035 };
7036 static const struct intr_info t7_pl_int_cause = {
7037 .name = "PL_INT_CAUSE",
7038 .cause_reg = A_PL_INT_CAUSE,
7039 .enable_reg = A_PL_INT_ENABLE,
7040 .fatal = 0,
7041 .flags = IHF_IGNORE_IF_DISABLED,
7042 .details = t7_pl_int_cause_fields,
7043 .actions = t7_pl_int_cause_actions,
7044 };
7045 static const struct intr_details t7_pl_int_cause2_fields[] = {
7046 { F_CRYPTO_KEY, "CRYPTO KEY" },
7047 { F_CRYPTO1, "CRYPTO1" },
7048 { F_CRYPTO0, "CRYPTO0" },
7049 { F_GCACHE, "GCACHE" },
7050 { F_ARM, "ARM" },
7051 { 0 }
7052 };
7053 static const struct intr_action t7_pl_int_cause2_actions[] = {
7054 { F_CRYPTO_KEY, -1, cryptokey_intr_handler },
7055 { F_CRYPTO1, 1, tlstx_intr_handler },
7056 { F_CRYPTO0, 0, tlstx_intr_handler },
7057 { F_GCACHE, -1, gcache_intr_handler },
7058 { F_ARM, -1, arm_intr_handler },
7059 { 0 }
7060 };
7061 static const struct intr_info t7_pl_int_cause2 = {
7062 .name = "PL_INT_CAUSE2",
7063 .cause_reg = A_PL_INT_CAUSE2,
7064 .enable_reg = A_PL_INT_ENABLE2,
7065 .fatal = 0,
7066 .flags = IHF_IGNORE_IF_DISABLED,
7067 .details = t7_pl_int_cause2_fields,
7068 .actions = t7_pl_int_cause2_actions,
7069 };
7070 static const struct intr_details t7_pl_perr_cause_fields[] = {
7071 { F_T7_PL_PERR_CRYPTO_KEY, "CRYPTO KEY" },
7072 { F_T7_PL_PERR_CRYPTO1, "CRYPTO1" },
7073 { F_T7_PL_PERR_CRYPTO0, "CRYPTO0" },
7074 { F_T7_PL_PERR_GCACHE, "GCACHE" },
7075 { F_T7_PL_PERR_ARM, "ARM" },
7076 { F_T7_PL_PERR_ULP_TX, "ULP TX" },
7077 { F_T7_PL_PERR_SGE, "SGE" },
7078 { F_T7_PL_PERR_HMA, "HMA" },
7079 { F_T7_PL_PERR_CPL_SWITCH, "CPL Switch" },
7080 { F_T7_PL_PERR_ULP_RX, "ULP RX" },
7081 { F_T7_PL_PERR_PM_RX, "PM RX" },
7082 { F_T7_PL_PERR_PM_TX, "PM TX" },
7083 { F_T7_PL_PERR_MA, "MA" },
7084 { F_T7_PL_PERR_TP, "TP" },
7085 { F_T7_PL_PERR_LE, "LE" },
7086 { F_T7_PL_PERR_EDC1, "EDC1" },
7087 { F_T7_PL_PERR_EDC0, "EDC0" },
7088 { F_T7_PL_PERR_MC1, "MC1" },
7089 { F_T7_PL_PERR_MC0, "MC0" },
7090 { F_T7_PL_PERR_PCIE, "PCIE" },
7091 { F_T7_PL_PERR_UART, "UART" },
7092 { F_T7_PL_PERR_PMU, "PMU" },
7093 { F_T7_PL_PERR_MAC, "MAC" },
7094 { F_T7_PL_PERR_SMB, "SMB" },
7095 { F_T7_PL_PERR_SF, "SF" },
7096 { F_T7_PL_PERR_PL, "PL" },
7097 { F_T7_PL_PERR_NCSI, "NC-SI" },
7098 { F_T7_PL_PERR_MPS, "MPS" },
7099 { F_T7_PL_PERR_MI, "MI" },
7100 { F_T7_PL_PERR_DBG, "DBG" },
7101 { F_T7_PL_PERR_I2CM, "I2CM" },
7102 { F_T7_PL_PERR_CIM, "CIM" },
7103 { 0 }
7104 };
7105 static const struct intr_info t7_pl_perr_cause = {
7106 .name = "PL_PERR_CAUSE",
7107 .cause_reg = A_PL_PERR_CAUSE,
7108 .enable_reg = A_PL_PERR_ENABLE,
7109 .fatal = 0xffffffff,
7110 .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED,
7111 .details = t7_pl_perr_cause_fields,
7112 .actions = NULL,
7113 };
7114 bool fatal = false;
7115 uint32_t perr;
7116
7117 if (chip_id(adap) < CHELSIO_T7) {
7118 perr = get_perr_ucause(adap, &pl_perr_cause);
7119 fatal |= t4_handle_intr(adap, &pl_perr_cause, 0,
7120 flags & ~(IHF_CLR_ALL_SET | IHF_CLR_ALL_UNIGNORED));
7121 fatal |= t4_handle_intr(adap, &pl_int_cause,
7122 t4_perr_to_ic(adap, perr), flags);
7123 t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
7124 (void)t4_read_reg(adap, pl_perr_cause.cause_reg);
7125 } else {
7126 perr = get_perr_ucause(adap, &t7_pl_perr_cause);
7127 fatal |= t4_handle_intr(adap, &t7_pl_perr_cause, 0,
7128 flags & ~(IHF_CLR_ALL_SET | IHF_CLR_ALL_UNIGNORED));
7129 fatal |= t4_handle_intr(adap, &t7_pl_int_cause,
7130 t7_perr_to_ic1(perr), flags);
7131 fatal |= t4_handle_intr(adap, &t7_pl_int_cause2,
7132 t7_perr_to_ic2(perr), flags);
7133 t4_write_reg(adap, t7_pl_perr_cause.cause_reg, perr);
7134 (void)t4_read_reg(adap, t7_pl_perr_cause.cause_reg);
7135 }
7136 return (fatal);
7137 }
7138
t4_intr_clear(struct adapter * adap)7139 void t4_intr_clear(struct adapter *adap)
7140 {
7141 #if 1
7142 if (chip_id(adap) >= CHELSIO_T7)
7143 t4_write_reg(adap, A_SGE_INT_CAUSE8, 0xffffffff);
7144 #endif
7145 (void)t4_slow_intr_handler(adap,
7146 IHF_NO_SHOW | IHF_RUN_ALL_ACTIONS | IHF_CLR_ALL_SET);
7147 }
7148
7149 /**
7150 * t4_intr_enable - enable interrupts
7151 * @adapter: the adapter whose interrupts should be enabled
7152 *
7153 * Enable PF-specific interrupts for the calling function and the top-level
7154 * interrupt concentrator for global interrupts. Interrupts are already
7155 * enabled at each module, here we just enable the roots of the interrupt
7156 * hierarchies.
7157 *
7158 * Note: this function should be called only when the driver manages
7159 * non PF-specific interrupts from the various HW modules. Only one PCI
7160 * function at a time should be doing this.
7161 */
t4_intr_enable(struct adapter * adap)7162 void t4_intr_enable(struct adapter *adap)
7163 {
7164 u32 mask, val;
7165
7166 if (adap->intr_flags & IHF_INTR_CLEAR_ON_INIT)
7167 t4_intr_clear(adap);
7168 if (chip_id(adap) <= CHELSIO_T5)
7169 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT |
7170 F_DBFIFO_LP_INT;
7171 else
7172 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
7173 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
7174 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
7175 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
7176 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
7177 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_EGRESS_SIZE_ERR;
7178 mask = val;
7179 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, mask, val);
7180 if (chip_id(adap) >= CHELSIO_T7)
7181 t4_write_reg(adap, A_SGE_INT_ENABLE4, 0xffffffff);
7182 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), F_PFSW | F_PFCIM);
7183 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
7184 #if 1
7185 if (chip_id(adap) >= CHELSIO_T7)
7186 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_MAC0 | F_MAC1 | F_MAC2 | F_MAC3, 0);
7187 #endif
7188 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
7189 }
7190
7191 /**
7192 * t4_intr_disable - disable interrupts
7193 * @adap: the adapter whose interrupts should be disabled
7194 *
7195 * Disable interrupts. We only disable the top-level interrupt
7196 * concentrators. The caller must be a PCI function managing global
7197 * interrupts.
7198 */
t4_intr_disable(struct adapter * adap)7199 void t4_intr_disable(struct adapter *adap)
7200 {
7201
7202 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
7203 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
7204 }
7205
7206 /**
7207 * hash_mac_addr - return the hash value of a MAC address
7208 * @addr: the 48-bit Ethernet MAC address
7209 *
7210 * Hashes a MAC address according to the hash function used by HW inexact
7211 * (hash) address matching.
7212 */
hash_mac_addr(const u8 * addr)7213 static int hash_mac_addr(const u8 *addr)
7214 {
7215 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
7216 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
7217 a ^= b;
7218 a ^= (a >> 12);
7219 a ^= (a >> 6);
7220 return a & 0x3f;
7221 }
7222
7223 /**
7224 * t4_config_rss_range - configure a portion of the RSS mapping table
7225 * @adapter: the adapter
7226 * @mbox: mbox to use for the FW command
7227 * @viid: virtual interface whose RSS subtable is to be written
7228 * @start: start entry in the table to write
7229 * @n: how many table entries to write
7230 * @rspq: values for the "response queue" (Ingress Queue) lookup table
7231 * @nrspq: number of values in @rspq
7232 *
7233 * Programs the selected part of the VI's RSS mapping table with the
7234 * provided values. If @nrspq < @n the supplied values are used repeatedly
7235 * until the full table range is populated.
7236 *
7237 * The caller must ensure the values in @rspq are in the range allowed for
7238 * @viid.
7239 */
t4_config_rss_range(struct adapter * adapter,int mbox,unsigned int viid,int start,int n,const u16 * rspq,unsigned int nrspq)7240 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
7241 int start, int n, const u16 *rspq, unsigned int nrspq)
7242 {
7243 int ret;
7244 const u16 *rsp = rspq;
7245 const u16 *rsp_end = rspq + nrspq;
7246 struct fw_rss_ind_tbl_cmd cmd;
7247
7248 memset(&cmd, 0, sizeof(cmd));
7249 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
7250 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7251 V_FW_RSS_IND_TBL_CMD_VIID(viid));
7252 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
7253
7254 /*
7255 * Each firmware RSS command can accommodate up to 32 RSS Ingress
7256 * Queue Identifiers. These Ingress Queue IDs are packed three to
7257 * a 32-bit word as 10-bit values with the upper remaining 2 bits
7258 * reserved.
7259 */
7260 while (n > 0) {
7261 int nq = min(n, 32);
7262 int nq_packed = 0;
7263 __be32 *qp = &cmd.iq0_to_iq2;
7264
7265 /*
7266 * Set up the firmware RSS command header to send the next
7267 * "nq" Ingress Queue IDs to the firmware.
7268 */
7269 cmd.niqid = cpu_to_be16(nq);
7270 cmd.startidx = cpu_to_be16(start);
7271
7272 /*
7273 * "nq" more done for the start of the next loop.
7274 */
7275 start += nq;
7276 n -= nq;
7277
7278 /*
7279 * While there are still Ingress Queue IDs to stuff into the
7280 * current firmware RSS command, retrieve them from the
7281 * Ingress Queue ID array and insert them into the command.
7282 */
7283 while (nq > 0) {
7284 /*
7285 * Grab up to the next 3 Ingress Queue IDs (wrapping
7286 * around the Ingress Queue ID array if necessary) and
7287 * insert them into the firmware RSS command at the
7288 * current 3-tuple position within the commad.
7289 */
7290 u16 qbuf[3];
7291 u16 *qbp = qbuf;
7292 int nqbuf = min(3, nq);
7293
7294 nq -= nqbuf;
7295 qbuf[0] = qbuf[1] = qbuf[2] = 0;
7296 while (nqbuf && nq_packed < 32) {
7297 nqbuf--;
7298 nq_packed++;
7299 *qbp++ = *rsp++;
7300 if (rsp >= rsp_end)
7301 rsp = rspq;
7302 }
7303 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
7304 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
7305 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
7306 }
7307
7308 /*
7309 * Send this portion of the RRS table update to the firmware;
7310 * bail out on any errors.
7311 */
7312 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
7313 if (ret)
7314 return ret;
7315 }
7316 return 0;
7317 }
7318
7319 /**
7320 * t4_config_glbl_rss - configure the global RSS mode
7321 * @adapter: the adapter
7322 * @mbox: mbox to use for the FW command
7323 * @mode: global RSS mode
7324 * @flags: mode-specific flags
7325 *
7326 * Sets the global RSS mode.
7327 */
t4_config_glbl_rss(struct adapter * adapter,int mbox,unsigned int mode,unsigned int flags)7328 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
7329 unsigned int flags)
7330 {
7331 struct fw_rss_glb_config_cmd c;
7332
7333 memset(&c, 0, sizeof(c));
7334 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
7335 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
7336 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7337 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
7338 c.u.manual.mode_pkd =
7339 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
7340 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
7341 c.u.basicvirtual.mode_keymode =
7342 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
7343 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
7344 } else
7345 return -EINVAL;
7346 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
7347 }
7348
7349 /**
7350 * t4_config_vi_rss - configure per VI RSS settings
7351 * @adapter: the adapter
7352 * @mbox: mbox to use for the FW command
7353 * @viid: the VI id
7354 * @flags: RSS flags
7355 * @defq: id of the default RSS queue for the VI.
7356 * @skeyidx: RSS secret key table index for non-global mode
7357 * @skey: RSS vf_scramble key for VI.
7358 *
7359 * Configures VI-specific RSS properties.
7360 */
t4_config_vi_rss(struct adapter * adapter,int mbox,unsigned int viid,unsigned int flags,unsigned int defq,unsigned int skeyidx,unsigned int skey)7361 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
7362 unsigned int flags, unsigned int defq, unsigned int skeyidx,
7363 unsigned int skey)
7364 {
7365 struct fw_rss_vi_config_cmd c;
7366
7367 memset(&c, 0, sizeof(c));
7368 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
7369 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7370 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
7371 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7372 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
7373 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
7374 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
7375 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
7376 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
7377
7378 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
7379 }
7380
7381 /* Read an RSS table row */
rd_rss_row(struct adapter * adap,int row,u32 * val)7382 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
7383 {
7384 if (chip_id(adap) < CHELSIO_T7) {
7385 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
7386 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE,
7387 F_LKPTBLROWVLD, 1, 5, 0, val);
7388 } else {
7389 t4_write_reg(adap, A_TP_RSS_CONFIG_SRAM, 0xB0000 | row);
7390 return t7_wait_sram_done(adap, A_TP_RSS_CONFIG_SRAM,
7391 A_TP_RSS_LKP_TABLE, 5, 0, val);
7392 }
7393 }
7394
7395 /**
7396 * t4_read_rss - read the contents of the RSS mapping table
7397 * @adapter: the adapter
7398 * @map: holds the contents of the RSS mapping table
7399 *
7400 * Reads the contents of the RSS hash->queue mapping table.
7401 */
t4_read_rss(struct adapter * adapter,u16 * map)7402 int t4_read_rss(struct adapter *adapter, u16 *map)
7403 {
7404 u32 val;
7405 int i, ret;
7406 int rss_nentries = adapter->chip_params->rss_nentries;
7407
7408 for (i = 0; i < rss_nentries / 2; ++i) {
7409 ret = rd_rss_row(adapter, i, &val);
7410 if (ret)
7411 return ret;
7412 *map++ = G_LKPTBLQUEUE0(val);
7413 *map++ = G_LKPTBLQUEUE1(val);
7414 }
7415 return 0;
7416 }
7417
7418 /**
7419 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
7420 * @adap: the adapter
7421 * @cmd: TP fw ldst address space type
7422 * @vals: where the indirect register values are stored/written
7423 * @nregs: how many indirect registers to read/write
7424 * @start_idx: index of first indirect register to read/write
7425 * @rw: Read (1) or Write (0)
7426 * @sleep_ok: if true we may sleep while awaiting command completion
7427 *
7428 * Access TP indirect registers through LDST
7429 **/
t4_tp_fw_ldst_rw(struct adapter * adap,int cmd,u32 * vals,unsigned int nregs,unsigned int start_index,unsigned int rw,bool sleep_ok)7430 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
7431 unsigned int nregs, unsigned int start_index,
7432 unsigned int rw, bool sleep_ok)
7433 {
7434 int ret = 0;
7435 unsigned int i;
7436 struct fw_ldst_cmd c;
7437
7438 for (i = 0; i < nregs; i++) {
7439 memset(&c, 0, sizeof(c));
7440 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7441 F_FW_CMD_REQUEST |
7442 (rw ? F_FW_CMD_READ :
7443 F_FW_CMD_WRITE) |
7444 V_FW_LDST_CMD_ADDRSPACE(cmd));
7445 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7446
7447 c.u.addrval.addr = cpu_to_be32(start_index + i);
7448 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
7449 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
7450 sleep_ok);
7451 if (ret)
7452 return ret;
7453
7454 if (rw)
7455 vals[i] = be32_to_cpu(c.u.addrval.val);
7456 }
7457 return 0;
7458 }
7459
7460 /**
7461 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
7462 * @adap: the adapter
7463 * @reg_addr: Address Register
7464 * @reg_data: Data register
7465 * @buff: where the indirect register values are stored/written
7466 * @nregs: how many indirect registers to read/write
7467 * @start_index: index of first indirect register to read/write
7468 * @rw: READ(1) or WRITE(0)
7469 * @sleep_ok: if true we may sleep while awaiting command completion
7470 *
7471 * Read/Write TP indirect registers through LDST if possible.
7472 * Else, use backdoor access
7473 **/
t4_tp_indirect_rw(struct adapter * adap,u32 reg_addr,u32 reg_data,u32 * buff,u32 nregs,u32 start_index,int rw,bool sleep_ok)7474 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
7475 u32 *buff, u32 nregs, u32 start_index, int rw,
7476 bool sleep_ok)
7477 {
7478 int rc = -EINVAL;
7479 int cmd;
7480
7481 switch (reg_addr) {
7482 case A_TP_PIO_ADDR:
7483 cmd = FW_LDST_ADDRSPC_TP_PIO;
7484 break;
7485 case A_TP_TM_PIO_ADDR:
7486 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
7487 break;
7488 case A_TP_MIB_INDEX:
7489 cmd = FW_LDST_ADDRSPC_TP_MIB;
7490 break;
7491 default:
7492 goto indirect_access;
7493 }
7494
7495 if (t4_use_ldst(adap))
7496 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
7497 sleep_ok);
7498
7499 indirect_access:
7500
7501 if (rc) {
7502 if (rw)
7503 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
7504 start_index);
7505 else
7506 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
7507 start_index);
7508 }
7509 }
7510
7511 /**
7512 * t4_tp_pio_read - Read TP PIO registers
7513 * @adap: the adapter
7514 * @buff: where the indirect register values are written
7515 * @nregs: how many indirect registers to read
7516 * @start_index: index of first indirect register to read
7517 * @sleep_ok: if true we may sleep while awaiting command completion
7518 *
7519 * Read TP PIO Registers
7520 **/
t4_tp_pio_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)7521 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
7522 u32 start_index, bool sleep_ok)
7523 {
7524 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
7525 start_index, 1, sleep_ok);
7526 }
7527
7528 /**
7529 * t4_tp_pio_write - Write TP PIO registers
7530 * @adap: the adapter
7531 * @buff: where the indirect register values are stored
7532 * @nregs: how many indirect registers to write
7533 * @start_index: index of first indirect register to write
7534 * @sleep_ok: if true we may sleep while awaiting command completion
7535 *
7536 * Write TP PIO Registers
7537 **/
t4_tp_pio_write(struct adapter * adap,const u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)7538 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
7539 u32 start_index, bool sleep_ok)
7540 {
7541 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7542 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
7543 }
7544
7545 /**
7546 * t4_tp_tm_pio_read - Read TP TM PIO registers
7547 * @adap: the adapter
7548 * @buff: where the indirect register values are written
7549 * @nregs: how many indirect registers to read
7550 * @start_index: index of first indirect register to read
7551 * @sleep_ok: if true we may sleep while awaiting command completion
7552 *
7553 * Read TP TM PIO Registers
7554 **/
t4_tp_tm_pio_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)7555 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
7556 u32 start_index, bool sleep_ok)
7557 {
7558 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
7559 nregs, start_index, 1, sleep_ok);
7560 }
7561
7562 /**
7563 * t4_tp_mib_read - Read TP MIB registers
7564 * @adap: the adapter
7565 * @buff: where the indirect register values are written
7566 * @nregs: how many indirect registers to read
7567 * @start_index: index of first indirect register to read
7568 * @sleep_ok: if true we may sleep while awaiting command completion
7569 *
7570 * Read TP MIB Registers
7571 **/
t4_tp_mib_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)7572 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
7573 bool sleep_ok)
7574 {
7575 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
7576 start_index, 1, sleep_ok);
7577 }
7578
7579 /**
7580 * t4_read_rss_key - read the global RSS key
7581 * @adap: the adapter
7582 * @key: 10-entry array holding the 320-bit RSS key
7583 * @sleep_ok: if true we may sleep while awaiting command completion
7584 *
7585 * Reads the global 320-bit RSS key.
7586 */
t4_read_rss_key(struct adapter * adap,u32 * key,bool sleep_ok)7587 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
7588 {
7589 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
7590 }
7591
7592 /**
7593 * t4_write_rss_key - program one of the RSS keys
7594 * @adap: the adapter
7595 * @key: 10-entry array holding the 320-bit RSS key
7596 * @idx: which RSS key to write
7597 * @sleep_ok: if true we may sleep while awaiting command completion
7598 *
7599 * Writes one of the RSS keys with the given 320-bit value. If @idx is
7600 * 0..15 the corresponding entry in the RSS key table is written,
7601 * otherwise the global RSS key is written.
7602 */
t4_write_rss_key(struct adapter * adap,const u32 * key,int idx,bool sleep_ok)7603 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
7604 bool sleep_ok)
7605 {
7606 u8 rss_key_addr_cnt = 16;
7607 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
7608
7609 /*
7610 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
7611 * allows access to key addresses 16-63 by using KeyWrAddrX
7612 * as index[5:4](upper 2) into key table
7613 */
7614 if ((chip_id(adap) > CHELSIO_T5) &&
7615 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
7616 rss_key_addr_cnt = 32;
7617
7618 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
7619
7620 if (idx >= 0 && idx < rss_key_addr_cnt) {
7621 if (rss_key_addr_cnt > 16)
7622 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
7623 vrt | V_KEYWRADDRX(idx >> 4) |
7624 V_T6_VFWRADDR(idx) | F_KEYWREN);
7625 else
7626 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
7627 vrt| V_KEYWRADDR(idx) | F_KEYWREN);
7628 }
7629 }
7630
7631 /**
7632 * t4_read_rss_pf_config - read PF RSS Configuration Table
7633 * @adapter: the adapter
7634 * @index: the entry in the PF RSS table to read
7635 * @valp: where to store the returned value
7636 * @sleep_ok: if true we may sleep while awaiting command completion
7637 *
7638 * Reads the PF RSS Configuration Table at the specified index and returns
7639 * the value found there.
7640 */
t4_read_rss_pf_config(struct adapter * adapter,unsigned int index,u32 * valp,bool sleep_ok)7641 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
7642 u32 *valp, bool sleep_ok)
7643 {
7644 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
7645 }
7646
7647 /**
7648 * t4_write_rss_pf_config - write PF RSS Configuration Table
7649 * @adapter: the adapter
7650 * @index: the entry in the VF RSS table to read
7651 * @val: the value to store
7652 * @sleep_ok: if true we may sleep while awaiting command completion
7653 *
7654 * Writes the PF RSS Configuration Table at the specified index with the
7655 * specified value.
7656 */
t4_write_rss_pf_config(struct adapter * adapter,unsigned int index,u32 val,bool sleep_ok)7657 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
7658 u32 val, bool sleep_ok)
7659 {
7660 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
7661 sleep_ok);
7662 }
7663
7664 /**
7665 * t4_read_rss_vf_config - read VF RSS Configuration Table
7666 * @adapter: the adapter
7667 * @index: the entry in the VF RSS table to read
7668 * @vfl: where to store the returned VFL
7669 * @vfh: where to store the returned VFH
7670 * @sleep_ok: if true we may sleep while awaiting command completion
7671 *
7672 * Reads the VF RSS Configuration Table at the specified index and returns
7673 * the (VFL, VFH) values found there.
7674 */
t4_read_rss_vf_config(struct adapter * adapter,unsigned int index,u32 * vfl,u32 * vfh,bool sleep_ok)7675 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
7676 u32 *vfl, u32 *vfh, bool sleep_ok)
7677 {
7678 u32 vrt, mask, data;
7679
7680 if (chip_id(adapter) <= CHELSIO_T5) {
7681 mask = V_VFWRADDR(M_VFWRADDR);
7682 data = V_VFWRADDR(index);
7683 } else {
7684 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
7685 data = V_T6_VFWRADDR(index);
7686 }
7687 /*
7688 * Request that the index'th VF Table values be read into VFL/VFH.
7689 */
7690 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
7691 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
7692 vrt |= data | F_VFRDEN;
7693 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
7694
7695 /*
7696 * Grab the VFL/VFH values ...
7697 */
7698 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
7699 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
7700 }
7701
7702 /**
7703 * t4_write_rss_vf_config - write VF RSS Configuration Table
7704 *
7705 * @adapter: the adapter
7706 * @index: the entry in the VF RSS table to write
7707 * @vfl: the VFL to store
7708 * @vfh: the VFH to store
7709 *
7710 * Writes the VF RSS Configuration Table at the specified index with the
7711 * specified (VFL, VFH) values.
7712 */
t4_write_rss_vf_config(struct adapter * adapter,unsigned int index,u32 vfl,u32 vfh,bool sleep_ok)7713 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
7714 u32 vfl, u32 vfh, bool sleep_ok)
7715 {
7716 u32 vrt, mask, data;
7717
7718 if (chip_id(adapter) <= CHELSIO_T5) {
7719 mask = V_VFWRADDR(M_VFWRADDR);
7720 data = V_VFWRADDR(index);
7721 } else {
7722 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
7723 data = V_T6_VFWRADDR(index);
7724 }
7725
7726 /*
7727 * Load up VFL/VFH with the values to be written ...
7728 */
7729 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
7730 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
7731
7732 /*
7733 * Write the VFL/VFH into the VF Table at index'th location.
7734 */
7735 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
7736 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
7737 vrt |= data | F_VFRDEN;
7738 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
7739 }
7740
7741 /**
7742 * t4_read_rss_pf_map - read PF RSS Map
7743 * @adapter: the adapter
7744 * @sleep_ok: if true we may sleep while awaiting command completion
7745 *
7746 * Reads the PF RSS Map register and returns its value.
7747 */
t4_read_rss_pf_map(struct adapter * adapter,bool sleep_ok)7748 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
7749 {
7750 u32 pfmap;
7751
7752 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
7753
7754 return pfmap;
7755 }
7756
7757 /**
7758 * t4_write_rss_pf_map - write PF RSS Map
7759 * @adapter: the adapter
7760 * @pfmap: PF RSS Map value
7761 *
7762 * Writes the specified value to the PF RSS Map register.
7763 */
t4_write_rss_pf_map(struct adapter * adapter,u32 pfmap,bool sleep_ok)7764 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
7765 {
7766 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
7767 }
7768
7769 /**
7770 * t4_read_rss_pf_mask - read PF RSS Mask
7771 * @adapter: the adapter
7772 * @sleep_ok: if true we may sleep while awaiting command completion
7773 *
7774 * Reads the PF RSS Mask register and returns its value.
7775 */
t4_read_rss_pf_mask(struct adapter * adapter,bool sleep_ok)7776 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
7777 {
7778 u32 pfmask;
7779
7780 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
7781
7782 return pfmask;
7783 }
7784
7785 /**
7786 * t4_write_rss_pf_mask - write PF RSS Mask
7787 * @adapter: the adapter
7788 * @pfmask: PF RSS Mask value
7789 *
7790 * Writes the specified value to the PF RSS Mask register.
7791 */
t4_write_rss_pf_mask(struct adapter * adapter,u32 pfmask,bool sleep_ok)7792 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
7793 {
7794 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
7795 }
7796
7797 /**
7798 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
7799 * @adap: the adapter
7800 * @v4: holds the TCP/IP counter values
7801 * @v6: holds the TCP/IPv6 counter values
7802 * @sleep_ok: if true we may sleep while awaiting command completion
7803 *
7804 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
7805 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
7806 */
t4_tp_get_tcp_stats(struct adapter * adap,struct tp_tcp_stats * v4,struct tp_tcp_stats * v6,bool sleep_ok)7807 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
7808 struct tp_tcp_stats *v6, bool sleep_ok)
7809 {
7810 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
7811
7812 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
7813 #define STAT(x) val[STAT_IDX(x)]
7814 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
7815
7816 if (v4) {
7817 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
7818 A_TP_MIB_TCP_OUT_RST, sleep_ok);
7819 v4->tcp_out_rsts = STAT(OUT_RST);
7820 v4->tcp_in_segs = STAT64(IN_SEG);
7821 v4->tcp_out_segs = STAT64(OUT_SEG);
7822 v4->tcp_retrans_segs = STAT64(RXT_SEG);
7823 }
7824 if (v6) {
7825 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
7826 A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
7827 v6->tcp_out_rsts = STAT(OUT_RST);
7828 v6->tcp_in_segs = STAT64(IN_SEG);
7829 v6->tcp_out_segs = STAT64(OUT_SEG);
7830 v6->tcp_retrans_segs = STAT64(RXT_SEG);
7831 }
7832 #undef STAT64
7833 #undef STAT
7834 #undef STAT_IDX
7835 }
7836
7837 /**
7838 * t4_tp_get_err_stats - read TP's error MIB counters
7839 * @adap: the adapter
7840 * @st: holds the counter values
7841 * @sleep_ok: if true we may sleep while awaiting command completion
7842 *
7843 * Returns the values of TP's error counters.
7844 */
t4_tp_get_err_stats(struct adapter * adap,struct tp_err_stats * st,bool sleep_ok)7845 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
7846 bool sleep_ok)
7847 {
7848 int nchan = adap->chip_params->nchan;
7849
7850 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
7851 sleep_ok);
7852
7853 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
7854 sleep_ok);
7855
7856 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
7857 sleep_ok);
7858
7859 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
7860 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
7861
7862 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
7863 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
7864
7865 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
7866 sleep_ok);
7867
7868 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
7869 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
7870
7871 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
7872 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
7873
7874 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
7875 sleep_ok);
7876 }
7877
7878 /**
7879 * t4_tp_get_err_stats - read TP's error MIB counters
7880 * @adap: the adapter
7881 * @st: holds the counter values
7882 * @sleep_ok: if true we may sleep while awaiting command completion
7883 *
7884 * Returns the values of TP's error counters.
7885 */
t4_tp_get_tnl_stats(struct adapter * adap,struct tp_tnl_stats * st,bool sleep_ok)7886 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st,
7887 bool sleep_ok)
7888 {
7889 int nchan = adap->chip_params->nchan;
7890
7891 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0,
7892 sleep_ok);
7893 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0,
7894 sleep_ok);
7895 }
7896
7897 /**
7898 * t4_tp_get_proxy_stats - read TP's proxy MIB counters
7899 * @adap: the adapter
7900 * @st: holds the counter values
7901 *
7902 * Returns the values of TP's proxy counters.
7903 */
t4_tp_get_proxy_stats(struct adapter * adap,struct tp_proxy_stats * st,bool sleep_ok)7904 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
7905 bool sleep_ok)
7906 {
7907 int nchan = adap->chip_params->nchan;
7908
7909 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
7910 }
7911
7912 /**
7913 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
7914 * @adap: the adapter
7915 * @st: holds the counter values
7916 * @sleep_ok: if true we may sleep while awaiting command completion
7917 *
7918 * Returns the values of TP's CPL counters.
7919 */
t4_tp_get_cpl_stats(struct adapter * adap,struct tp_cpl_stats * st,bool sleep_ok)7920 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
7921 bool sleep_ok)
7922 {
7923 int nchan = adap->chip_params->nchan;
7924
7925 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
7926
7927 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
7928 }
7929
7930 /**
7931 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
7932 * @adap: the adapter
7933 * @st: holds the counter values
7934 *
7935 * Returns the values of TP's RDMA counters.
7936 */
t4_tp_get_rdma_stats(struct adapter * adap,struct tp_rdma_stats * st,bool sleep_ok)7937 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
7938 bool sleep_ok)
7939 {
7940 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
7941 sleep_ok);
7942
7943 if (chip_id(adap) >= CHELSIO_T7)
7944 /* read RDMA stats IN and OUT for all ports at once */
7945 t4_tp_mib_read(adap, &st->pkts_in[0], 28, A_TP_MIB_RDMA_IN_PKT_0,
7946 sleep_ok);
7947 }
7948
7949 /**
7950 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
7951 * @adap: the adapter
7952 * @idx: the port index
7953 * @st: holds the counter values
7954 * @sleep_ok: if true we may sleep while awaiting command completion
7955 *
7956 * Returns the values of TP's FCoE counters for the selected port.
7957 */
t4_get_fcoe_stats(struct adapter * adap,unsigned int idx,struct tp_fcoe_stats * st,bool sleep_ok)7958 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
7959 struct tp_fcoe_stats *st, bool sleep_ok)
7960 {
7961 u32 val[2];
7962
7963 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
7964 sleep_ok);
7965
7966 t4_tp_mib_read(adap, &st->frames_drop, 1,
7967 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
7968
7969 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
7970 sleep_ok);
7971
7972 st->octets_ddp = ((u64)val[0] << 32) | val[1];
7973 }
7974
7975 /**
7976 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
7977 * @adap: the adapter
7978 * @st: holds the counter values
7979 * @sleep_ok: if true we may sleep while awaiting command completion
7980 *
7981 * Returns the values of TP's counters for non-TCP directly-placed packets.
7982 */
t4_get_usm_stats(struct adapter * adap,struct tp_usm_stats * st,bool sleep_ok)7983 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
7984 bool sleep_ok)
7985 {
7986 u32 val[4];
7987
7988 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
7989
7990 st->frames = val[0];
7991 st->drops = val[1];
7992 st->octets = ((u64)val[2] << 32) | val[3];
7993 }
7994
7995 /**
7996 * t4_tp_get_tid_stats - read TP's tid MIB counters.
7997 * @adap: the adapter
7998 * @st: holds the counter values
7999 * @sleep_ok: if true we may sleep while awaiting command completion
8000 *
8001 * Returns the values of TP's counters for tids.
8002 */
t4_tp_get_tid_stats(struct adapter * adap,struct tp_tid_stats * st,bool sleep_ok)8003 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st,
8004 bool sleep_ok)
8005 {
8006
8007 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok);
8008 }
8009
8010 /**
8011 * t4_read_mtu_tbl - returns the values in the HW path MTU table
8012 * @adap: the adapter
8013 * @mtus: where to store the MTU values
8014 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
8015 *
8016 * Reads the HW path MTU table.
8017 */
t4_read_mtu_tbl(struct adapter * adap,u16 * mtus,u8 * mtu_log)8018 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
8019 {
8020 u32 v;
8021 int i;
8022
8023 for (i = 0; i < NMTUS; ++i) {
8024 t4_write_reg(adap, A_TP_MTU_TABLE,
8025 V_MTUINDEX(0xff) | V_MTUVALUE(i));
8026 v = t4_read_reg(adap, A_TP_MTU_TABLE);
8027 mtus[i] = G_MTUVALUE(v);
8028 if (mtu_log)
8029 mtu_log[i] = G_MTUWIDTH(v);
8030 }
8031 }
8032
8033 /**
8034 * t4_read_cong_tbl - reads the congestion control table
8035 * @adap: the adapter
8036 * @incr: where to store the alpha values
8037 *
8038 * Reads the additive increments programmed into the HW congestion
8039 * control table.
8040 */
t4_read_cong_tbl(struct adapter * adap,u16 incr[NMTUS][NCCTRL_WIN])8041 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
8042 {
8043 unsigned int mtu, w;
8044
8045 for (mtu = 0; mtu < NMTUS; ++mtu)
8046 for (w = 0; w < NCCTRL_WIN; ++w) {
8047 t4_write_reg(adap, A_TP_CCTRL_TABLE,
8048 V_ROWINDEX(0xffff) | (mtu << 5) | w);
8049 incr[mtu][w] = (u16)t4_read_reg(adap,
8050 A_TP_CCTRL_TABLE) & 0x1fff;
8051 }
8052 }
8053
8054 /**
8055 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
8056 * @adap: the adapter
8057 * @addr: the indirect TP register address
8058 * @mask: specifies the field within the register to modify
8059 * @val: new value for the field
8060 *
8061 * Sets a field of an indirect TP register to the given value.
8062 */
t4_tp_wr_bits_indirect(struct adapter * adap,unsigned int addr,unsigned int mask,unsigned int val)8063 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
8064 unsigned int mask, unsigned int val)
8065 {
8066 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
8067 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
8068 t4_write_reg(adap, A_TP_PIO_DATA, val);
8069 }
8070
8071 /**
8072 * init_cong_ctrl - initialize congestion control parameters
8073 * @a: the alpha values for congestion control
8074 * @b: the beta values for congestion control
8075 *
8076 * Initialize the congestion control parameters.
8077 */
init_cong_ctrl(unsigned short * a,unsigned short * b)8078 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
8079 {
8080 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
8081 a[9] = 2;
8082 a[10] = 3;
8083 a[11] = 4;
8084 a[12] = 5;
8085 a[13] = 6;
8086 a[14] = 7;
8087 a[15] = 8;
8088 a[16] = 9;
8089 a[17] = 10;
8090 a[18] = 14;
8091 a[19] = 17;
8092 a[20] = 21;
8093 a[21] = 25;
8094 a[22] = 30;
8095 a[23] = 35;
8096 a[24] = 45;
8097 a[25] = 60;
8098 a[26] = 80;
8099 a[27] = 100;
8100 a[28] = 200;
8101 a[29] = 300;
8102 a[30] = 400;
8103 a[31] = 500;
8104
8105 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
8106 b[9] = b[10] = 1;
8107 b[11] = b[12] = 2;
8108 b[13] = b[14] = b[15] = b[16] = 3;
8109 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
8110 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
8111 b[28] = b[29] = 6;
8112 b[30] = b[31] = 7;
8113 }
8114
8115 /* The minimum additive increment value for the congestion control table */
8116 #define CC_MIN_INCR 2U
8117
8118 /**
8119 * t4_load_mtus - write the MTU and congestion control HW tables
8120 * @adap: the adapter
8121 * @mtus: the values for the MTU table
8122 * @alpha: the values for the congestion control alpha parameter
8123 * @beta: the values for the congestion control beta parameter
8124 *
8125 * Write the HW MTU table with the supplied MTUs and the high-speed
8126 * congestion control table with the supplied alpha, beta, and MTUs.
8127 * We write the two tables together because the additive increments
8128 * depend on the MTUs.
8129 */
t4_load_mtus(struct adapter * adap,const unsigned short * mtus,const unsigned short * alpha,const unsigned short * beta)8130 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
8131 const unsigned short *alpha, const unsigned short *beta)
8132 {
8133 static const unsigned int avg_pkts[NCCTRL_WIN] = {
8134 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
8135 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
8136 28672, 40960, 57344, 81920, 114688, 163840, 229376
8137 };
8138
8139 unsigned int i, w;
8140
8141 for (i = 0; i < NMTUS; ++i) {
8142 unsigned int mtu = mtus[i];
8143 unsigned int log2 = fls(mtu);
8144
8145 if (!(mtu & ((1 << log2) >> 2))) /* round */
8146 log2--;
8147 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
8148 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
8149
8150 for (w = 0; w < NCCTRL_WIN; ++w) {
8151 unsigned int inc;
8152
8153 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
8154 CC_MIN_INCR);
8155
8156 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
8157 (w << 16) | (beta[w] << 13) | inc);
8158 }
8159 }
8160 }
8161
8162 /**
8163 * t4_set_pace_tbl - set the pace table
8164 * @adap: the adapter
8165 * @pace_vals: the pace values in microseconds
8166 * @start: index of the first entry in the HW pace table to set
8167 * @n: how many entries to set
8168 *
8169 * Sets (a subset of the) HW pace table.
8170 */
t4_set_pace_tbl(struct adapter * adap,const unsigned int * pace_vals,unsigned int start,unsigned int n)8171 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
8172 unsigned int start, unsigned int n)
8173 {
8174 unsigned int vals[NTX_SCHED], i;
8175 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
8176
8177 if (n > NTX_SCHED)
8178 return -ERANGE;
8179
8180 /* convert values from us to dack ticks, rounding to closest value */
8181 for (i = 0; i < n; i++, pace_vals++) {
8182 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
8183 if (vals[i] > 0x7ff)
8184 return -ERANGE;
8185 if (*pace_vals && vals[i] == 0)
8186 return -ERANGE;
8187 }
8188 for (i = 0; i < n; i++, start++)
8189 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
8190 return 0;
8191 }
8192
8193 /**
8194 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler
8195 * @adap: the adapter
8196 * @kbps: target rate in Kbps
8197 * @sched: the scheduler index
8198 *
8199 * Configure a Tx HW scheduler for the target rate.
8200 */
t4_set_sched_bps(struct adapter * adap,int sched,unsigned int kbps)8201 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
8202 {
8203 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
8204 unsigned int clk = adap->params.vpd.cclk * 1000;
8205 unsigned int selected_cpt = 0, selected_bpt = 0;
8206
8207 if (kbps > 0) {
8208 kbps *= 125; /* -> bytes */
8209 for (cpt = 1; cpt <= 255; cpt++) {
8210 tps = clk / cpt;
8211 bpt = (kbps + tps / 2) / tps;
8212 if (bpt > 0 && bpt <= 255) {
8213 v = bpt * tps;
8214 delta = v >= kbps ? v - kbps : kbps - v;
8215 if (delta < mindelta) {
8216 mindelta = delta;
8217 selected_cpt = cpt;
8218 selected_bpt = bpt;
8219 }
8220 } else if (selected_cpt)
8221 break;
8222 }
8223 if (!selected_cpt)
8224 return -EINVAL;
8225 }
8226 t4_write_reg(adap, A_TP_TM_PIO_ADDR,
8227 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
8228 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8229 if (sched & 1)
8230 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
8231 else
8232 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
8233 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
8234 return 0;
8235 }
8236
8237 /**
8238 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
8239 * @adap: the adapter
8240 * @sched: the scheduler index
8241 * @ipg: the interpacket delay in tenths of nanoseconds
8242 *
8243 * Set the interpacket delay for a HW packet rate scheduler.
8244 */
t4_set_sched_ipg(struct adapter * adap,int sched,unsigned int ipg)8245 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
8246 {
8247 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
8248
8249 /* convert ipg to nearest number of core clocks */
8250 ipg *= core_ticks_per_usec(adap);
8251 ipg = (ipg + 5000) / 10000;
8252 if (ipg > M_TXTIMERSEPQ0)
8253 return -EINVAL;
8254
8255 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8256 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8257 if (sched & 1)
8258 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
8259 else
8260 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
8261 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
8262 t4_read_reg(adap, A_TP_TM_PIO_DATA);
8263 return 0;
8264 }
8265
8266 /*
8267 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
8268 * clocks. The formula is
8269 *
8270 * bytes/s = bytes256 * 256 * ClkFreq / 4096
8271 *
8272 * which is equivalent to
8273 *
8274 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
8275 */
chan_rate(struct adapter * adap,unsigned int bytes256)8276 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
8277 {
8278 u64 v = (u64)bytes256 * adap->params.vpd.cclk;
8279
8280 return v * 62 + v / 2;
8281 }
8282
8283 /**
8284 * t4_get_chan_txrate - get the current per channel Tx rates
8285 * @adap: the adapter
8286 * @nic_rate: rates for NIC traffic
8287 * @ofld_rate: rates for offloaded traffic
8288 *
8289 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
8290 * for each channel.
8291 */
t4_get_chan_txrate(struct adapter * adap,u64 * nic_rate,u64 * ofld_rate)8292 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
8293 {
8294 u32 v;
8295
8296 v = t4_read_reg(adap, A_TP_TX_TRATE);
8297 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
8298 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
8299 if (adap->chip_params->nchan > 2) {
8300 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
8301 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
8302 }
8303
8304 v = t4_read_reg(adap, A_TP_TX_ORATE);
8305 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
8306 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
8307 if (adap->chip_params->nchan > 2) {
8308 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
8309 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
8310 }
8311 }
8312
8313 /**
8314 * t4_set_trace_filter - configure one of the tracing filters
8315 * @adap: the adapter
8316 * @tp: the desired trace filter parameters
8317 * @idx: which filter to configure
8318 * @enable: whether to enable or disable the filter
8319 *
8320 * Configures one of the tracing filters available in HW. If @tp is %NULL
8321 * it indicates that the filter is already written in the register and it
8322 * just needs to be enabled or disabled.
8323 */
t4_set_trace_filter(struct adapter * adap,const struct trace_params * tp,int idx,int enable)8324 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
8325 int idx, int enable)
8326 {
8327 int i, ofst;
8328 u32 match_ctl_a, match_ctl_b;
8329 u32 data_reg, mask_reg, cfg;
8330 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
8331
8332 if (idx < 0 || idx >= NTRACE)
8333 return -EINVAL;
8334
8335 if (chip_id(adap) >= CHELSIO_T7) {
8336 match_ctl_a = T7_MPS_TRC_FILTER_MATCH_CTL_A(idx);
8337 match_ctl_b = T7_MPS_TRC_FILTER_MATCH_CTL_B(idx);
8338 } else {
8339 match_ctl_a = MPS_TRC_FILTER_MATCH_CTL_A(idx);
8340 match_ctl_b = MPS_TRC_FILTER_MATCH_CTL_B(idx);
8341 }
8342
8343 if (tp == NULL || !enable) {
8344 t4_set_reg_field(adap, match_ctl_a, en, enable ? en : 0);
8345 return 0;
8346 }
8347
8348 /*
8349 * TODO - After T4 data book is updated, specify the exact
8350 * section below.
8351 *
8352 * See T4 data book - MPS section for a complete description
8353 * of the below if..else handling of A_MPS_TRC_CFG register
8354 * value.
8355 */
8356 cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
8357 if (cfg & F_TRCMULTIFILTER) {
8358 /*
8359 * If multiple tracers are enabled, then maximum
8360 * capture size is 2.5KB (FIFO size of a single channel)
8361 * minus 2 flits for CPL_TRACE_PKT header.
8362 */
8363 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
8364 return -EINVAL;
8365 } else {
8366 /*
8367 * If multiple tracers are disabled, to avoid deadlocks
8368 * maximum packet capture size of 9600 bytes is recommended.
8369 * Also in this mode, only trace0 can be enabled and running.
8370 */
8371 if (tp->snap_len > 9600 || idx)
8372 return -EINVAL;
8373 }
8374
8375 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
8376 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
8377 tp->min_len > M_TFMINPKTSIZE)
8378 return -EINVAL;
8379
8380 /* stop the tracer we'll be changing */
8381 t4_set_reg_field(adap, match_ctl_a, en, 0);
8382
8383 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
8384 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
8385 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
8386
8387 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
8388 t4_write_reg(adap, data_reg, tp->data[i]);
8389 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
8390 }
8391 t4_write_reg(adap, match_ctl_b, V_TFCAPTUREMAX(tp->snap_len) |
8392 V_TFMINPKTSIZE(tp->min_len));
8393 t4_write_reg(adap, match_ctl_a, V_TFOFFSET(tp->skip_ofst) |
8394 V_TFLENGTH(tp->skip_len) | en | (is_t4(adap) ?
8395 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
8396 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
8397
8398 return 0;
8399 }
8400
8401 /**
8402 * t4_get_trace_filter - query one of the tracing filters
8403 * @adap: the adapter
8404 * @tp: the current trace filter parameters
8405 * @idx: which trace filter to query
8406 * @enabled: non-zero if the filter is enabled
8407 *
8408 * Returns the current settings of one of the HW tracing filters.
8409 */
t4_get_trace_filter(struct adapter * adap,struct trace_params * tp,int idx,int * enabled)8410 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
8411 int *enabled)
8412 {
8413 u32 ctla, ctlb;
8414 int i, ofst;
8415 u32 data_reg, mask_reg;
8416
8417 if (chip_id(adap) >= CHELSIO_T7) {
8418 ctla = t4_read_reg(adap, T7_MPS_TRC_FILTER_MATCH_CTL_A(idx));
8419 ctlb = t4_read_reg(adap, T7_MPS_TRC_FILTER_MATCH_CTL_B(idx));
8420 } else {
8421 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A(idx));
8422 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B(idx));
8423 }
8424
8425 if (is_t4(adap)) {
8426 *enabled = !!(ctla & F_TFEN);
8427 tp->port = G_TFPORT(ctla);
8428 tp->invert = !!(ctla & F_TFINVERTMATCH);
8429 } else {
8430 *enabled = !!(ctla & F_T5_TFEN);
8431 tp->port = G_T5_TFPORT(ctla);
8432 tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
8433 }
8434 tp->snap_len = G_TFCAPTUREMAX(ctlb);
8435 tp->min_len = G_TFMINPKTSIZE(ctlb);
8436 tp->skip_ofst = G_TFOFFSET(ctla);
8437 tp->skip_len = G_TFLENGTH(ctla);
8438
8439 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
8440 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
8441 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
8442
8443 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
8444 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
8445 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
8446 }
8447 }
8448
8449 /**
8450 * t4_set_trace_rss_control - configure the trace rss control register
8451 * @adap: the adapter
8452 * @chan: the channel number for RSS control
8453 * @qid: queue number
8454 *
8455 * Configures the MPS tracing RSS control parameter for specified
8456 * @chan channel and @qid queue number.
8457 */
t4_set_trace_rss_control(struct adapter * adap,u8 chan,u16 qid)8458 void t4_set_trace_rss_control(struct adapter *adap, u8 chan, u16 qid)
8459 {
8460 u32 mps_trc_rss_control;
8461
8462 switch (chip_id(adap)) {
8463 case CHELSIO_T4:
8464 mps_trc_rss_control = A_MPS_TRC_RSS_CONTROL;
8465 break;
8466 case CHELSIO_T5:
8467 case CHELSIO_T6:
8468 mps_trc_rss_control = A_MPS_T5_TRC_RSS_CONTROL;
8469 break;
8470 case CHELSIO_T7:
8471 default:
8472 mps_trc_rss_control = A_T7_MPS_T5_TRC_RSS_CONTROL;
8473 break;
8474 }
8475
8476 t4_write_reg(adap, mps_trc_rss_control,
8477 V_RSSCONTROL(chan) | V_QUEUENUMBER(qid));
8478 }
8479
8480 /**
8481 * t4_pmtx_get_stats - returns the HW stats from PMTX
8482 * @adap: the adapter
8483 * @cnt: where to store the count statistics
8484 * @cycles: where to store the cycle statistics
8485 *
8486 * Returns performance statistics from PMTX.
8487 */
t4_pmtx_get_stats(struct adapter * adap,u32 cnt[],u64 cycles[])8488 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
8489 {
8490 int i;
8491 u32 data[2];
8492
8493 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
8494 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
8495 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
8496 if (is_t4(adap))
8497 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
8498 else {
8499 t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
8500 A_PM_TX_DBG_DATA, data, 2,
8501 chip_id(adap) >= CHELSIO_T7 ?
8502 A_T7_PM_TX_DBG_STAT_MSB :
8503 A_PM_TX_DBG_STAT_MSB);
8504 cycles[i] = (((u64)data[0] << 32) | data[1]);
8505 }
8506 }
8507 }
8508
8509 /**
8510 * t4_pmrx_get_stats - returns the HW stats from PMRX
8511 * @adap: the adapter
8512 * @cnt: where to store the count statistics
8513 * @cycles: where to store the cycle statistics
8514 *
8515 * Returns performance statistics from PMRX.
8516 */
t4_pmrx_get_stats(struct adapter * adap,u32 cnt[],u64 cycles[])8517 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
8518 {
8519 int i;
8520 u32 data[2];
8521
8522 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
8523 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
8524 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
8525 if (is_t4(adap)) {
8526 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
8527 } else {
8528 t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
8529 A_PM_RX_DBG_DATA, data, 2,
8530 A_PM_RX_DBG_STAT_MSB);
8531 cycles[i] = (((u64)data[0] << 32) | data[1]);
8532 }
8533 }
8534 }
8535
8536 /**
8537 * t4_pmrx_cache_get_stats - returns the HW PMRX cache stats
8538 * @adap: the adapter
8539 * @stats: where to store the statistics
8540 *
8541 * Returns performance statistics of PMRX cache.
8542 */
t4_pmrx_cache_get_stats(struct adapter * adap,u32 stats[])8543 void t4_pmrx_cache_get_stats(struct adapter *adap, u32 stats[])
8544 {
8545 u8 i, j;
8546
8547 for (i = 0, j = 0; i < T7_PM_RX_CACHE_NSTATS / 3; i++, j += 3) {
8548 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, 0x100 + i);
8549 stats[j] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
8550 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, A_PM_RX_DBG_DATA,
8551 &stats[j + 1], 2, A_PM_RX_DBG_STAT_MSB);
8552 }
8553 }
8554
8555 /**
8556 * t4_get_mps_bg_map - return the buffer groups associated with a port
8557 * @adap: the adapter
8558 * @idx: the port index
8559 *
8560 * Returns a bitmap indicating which MPS buffer groups are associated
8561 * with the given port. Bit i is set if buffer group i is used by the
8562 * port.
8563 */
t4_get_mps_bg_map(struct adapter * adap,int idx)8564 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
8565 {
8566 u32 n;
8567
8568 if (adap->params.mps_bg_map != UINT32_MAX)
8569 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
8570
8571 n = adap->params.nports;
8572 MPASS(n > 0 && n <= MAX_NPORTS);
8573 if (n == 1)
8574 return idx == 0 ? 0xf : 0;
8575 if (n == 2 && chip_id(adap) <= CHELSIO_T5)
8576 return idx < 2 ? (3 << (2 * idx)) : 0;
8577 return 1 << idx;
8578 }
8579
8580 /*
8581 * TP RX e-channels associated with the port.
8582 */
t4_get_rx_e_chan_map(struct adapter * adap,int idx)8583 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
8584 {
8585 const u32 n = adap->params.nports;
8586 const u32 all_chan = (1 << adap->chip_params->nchan) - 1;
8587
8588 switch (adap->params.tp.lb_mode) {
8589 case 0:
8590 if (n == 1)
8591 return (all_chan);
8592 if (n == 2 && chip_id(adap) <= CHELSIO_T5)
8593 return (3 << (2 * idx));
8594 return (1 << idx);
8595 case 1:
8596 MPASS(n == 1);
8597 return (all_chan);
8598 case 2:
8599 MPASS(n <= 2);
8600 return (3 << (2 * idx));
8601 default:
8602 CH_ERR(adap, "Unsupported LB mode %d\n",
8603 adap->params.tp.lb_mode);
8604 return (0);
8605 }
8606 }
8607
8608 /*
8609 * TP RX c-channel associated with the port.
8610 */
t4_get_rx_c_chan(struct adapter * adap,int idx)8611 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx)
8612 {
8613 if (adap->params.tp_ch_map != UINT32_MAX)
8614 return (adap->params.tp_ch_map >> (8 * idx)) & 0xff;
8615 return 0;
8616 }
8617
8618 /*
8619 * TP TX c-channel associated with the port.
8620 */
t4_get_tx_c_chan(struct adapter * adap,int idx)8621 static unsigned int t4_get_tx_c_chan(struct adapter *adap, int idx)
8622 {
8623 if (adap->params.tx_tp_ch_map != UINT32_MAX)
8624 return (adap->params.tx_tp_ch_map >> (8 * idx)) & 0xff;
8625 return idx;
8626 }
8627
8628 /**
8629 * t4_get_port_type_description - return Port Type string description
8630 * @port_type: firmware Port Type enumeration
8631 */
t4_get_port_type_description(enum fw_port_type port_type)8632 const char *t4_get_port_type_description(enum fw_port_type port_type)
8633 {
8634 static const char *const port_type_description[] = {
8635 "Fiber_XFI",
8636 "Fiber_XAUI",
8637 "BT_SGMII",
8638 "BT_XFI",
8639 "BT_XAUI",
8640 "KX4",
8641 "CX4",
8642 "KX",
8643 "KR",
8644 "SFP",
8645 "BP_AP",
8646 "BP4_AP",
8647 "QSFP_10G",
8648 "QSA",
8649 "QSFP",
8650 "BP40_BA",
8651 "KR4_100G",
8652 "CR4_QSFP",
8653 "CR_QSFP",
8654 "CR2_QSFP",
8655 "SFP28",
8656 "KR_SFP28",
8657 "KR_XLAUI",
8658 };
8659
8660 if (port_type < ARRAY_SIZE(port_type_description))
8661 return port_type_description[port_type];
8662 return "UNKNOWN";
8663 }
8664
8665 /**
8666 * t4_get_port_stats_offset - collect port stats relative to a previous
8667 * snapshot
8668 * @adap: The adapter
8669 * @idx: The port
8670 * @stats: Current stats to fill
8671 * @offset: Previous stats snapshot
8672 */
t4_get_port_stats_offset(struct adapter * adap,int idx,struct port_stats * stats,struct port_stats * offset)8673 void t4_get_port_stats_offset(struct adapter *adap, int idx,
8674 struct port_stats *stats,
8675 struct port_stats *offset)
8676 {
8677 u64 *s, *o;
8678 int i;
8679
8680 t4_get_port_stats(adap, idx, stats);
8681 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
8682 i < (sizeof(struct port_stats)/sizeof(u64)) ;
8683 i++, s++, o++)
8684 *s -= *o;
8685 }
8686
8687 /**
8688 * t4_get_port_stats - collect port statistics
8689 * @adap: the adapter
8690 * @idx: the port index
8691 * @p: the stats structure to fill
8692 *
8693 * Collect statistics related to the given port from HW.
8694 */
t4_get_port_stats(struct adapter * adap,int idx,struct port_stats * p)8695 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
8696 {
8697 struct port_info *pi;
8698 int port_id, tx_chan;
8699 u32 bgmap, stat_ctl;
8700
8701 port_id = adap->port_map[idx];
8702 MPASS(port_id >= 0 && port_id <= adap->params.nports);
8703 pi = adap->port[port_id];
8704
8705 #define GET_STAT(name) \
8706 t4_read_reg64(adap, \
8707 t4_port_reg(adap, tx_chan, A_MPS_PORT_STAT_##name##_L));
8708 memset(p, 0, sizeof(*p));
8709 for (tx_chan = pi->tx_chan;
8710 tx_chan < pi->tx_chan + adap->params.tp.lb_nchan; tx_chan++) {
8711 p->tx_pause += GET_STAT(TX_PORT_PAUSE);
8712 p->tx_octets += GET_STAT(TX_PORT_BYTES);
8713 p->tx_frames += GET_STAT(TX_PORT_FRAMES);
8714 p->tx_bcast_frames += GET_STAT(TX_PORT_BCAST);
8715 p->tx_mcast_frames += GET_STAT(TX_PORT_MCAST);
8716 p->tx_ucast_frames += GET_STAT(TX_PORT_UCAST);
8717 p->tx_error_frames += GET_STAT(TX_PORT_ERROR);
8718 p->tx_frames_64 += GET_STAT(TX_PORT_64B);
8719 p->tx_frames_65_127 += GET_STAT(TX_PORT_65B_127B);
8720 p->tx_frames_128_255 += GET_STAT(TX_PORT_128B_255B);
8721 p->tx_frames_256_511 += GET_STAT(TX_PORT_256B_511B);
8722 p->tx_frames_512_1023 += GET_STAT(TX_PORT_512B_1023B);
8723 p->tx_frames_1024_1518 += GET_STAT(TX_PORT_1024B_1518B);
8724 p->tx_frames_1519_max += GET_STAT(TX_PORT_1519B_MAX);
8725 p->tx_drop += GET_STAT(TX_PORT_DROP);
8726 p->tx_ppp0 += GET_STAT(TX_PORT_PPP0);
8727 p->tx_ppp1 += GET_STAT(TX_PORT_PPP1);
8728 p->tx_ppp2 += GET_STAT(TX_PORT_PPP2);
8729 p->tx_ppp3 += GET_STAT(TX_PORT_PPP3);
8730 p->tx_ppp4 += GET_STAT(TX_PORT_PPP4);
8731 p->tx_ppp5 += GET_STAT(TX_PORT_PPP5);
8732 p->tx_ppp6 += GET_STAT(TX_PORT_PPP6);
8733 p->tx_ppp7 += GET_STAT(TX_PORT_PPP7);
8734
8735 p->rx_pause += GET_STAT(RX_PORT_PAUSE);
8736 p->rx_octets += GET_STAT(RX_PORT_BYTES);
8737 p->rx_frames += GET_STAT(RX_PORT_FRAMES);
8738 p->rx_bcast_frames += GET_STAT(RX_PORT_BCAST);
8739 p->rx_mcast_frames += GET_STAT(RX_PORT_MCAST);
8740 p->rx_ucast_frames += GET_STAT(RX_PORT_UCAST);
8741 p->rx_too_long += GET_STAT(RX_PORT_MTU_ERROR);
8742 p->rx_jabber += GET_STAT(RX_PORT_MTU_CRC_ERROR);
8743 p->rx_len_err += GET_STAT(RX_PORT_LEN_ERROR);
8744 p->rx_symbol_err += GET_STAT(RX_PORT_SYM_ERROR);
8745 p->rx_runt += GET_STAT(RX_PORT_LESS_64B);
8746 p->rx_frames_64 += GET_STAT(RX_PORT_64B);
8747 p->rx_frames_65_127 += GET_STAT(RX_PORT_65B_127B);
8748 p->rx_frames_128_255 += GET_STAT(RX_PORT_128B_255B);
8749 p->rx_frames_256_511 += GET_STAT(RX_PORT_256B_511B);
8750 p->rx_frames_512_1023 += GET_STAT(RX_PORT_512B_1023B);
8751 p->rx_frames_1024_1518 += GET_STAT(RX_PORT_1024B_1518B);
8752 p->rx_frames_1519_max += GET_STAT(RX_PORT_1519B_MAX);
8753 p->rx_ppp0 += GET_STAT(RX_PORT_PPP0);
8754 p->rx_ppp1 += GET_STAT(RX_PORT_PPP1);
8755 p->rx_ppp2 += GET_STAT(RX_PORT_PPP2);
8756 p->rx_ppp3 += GET_STAT(RX_PORT_PPP3);
8757 p->rx_ppp4 += GET_STAT(RX_PORT_PPP4);
8758 p->rx_ppp5 += GET_STAT(RX_PORT_PPP5);
8759 p->rx_ppp6 += GET_STAT(RX_PORT_PPP6);
8760 p->rx_ppp7 += GET_STAT(RX_PORT_PPP7);
8761 if (!is_t6(adap)) {
8762 MPASS(pi->fcs_reg == A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L);
8763 p->rx_fcs_err += GET_STAT(RX_PORT_CRC_ERROR);
8764 }
8765 }
8766 #undef GET_STAT
8767
8768 if (is_t6(adap) && pi->fcs_reg != -1)
8769 p->rx_fcs_err = t4_read_reg64(adap,
8770 t4_port_reg(adap, pi->tx_chan, pi->fcs_reg)) - pi->fcs_base;
8771
8772 if (chip_id(adap) >= CHELSIO_T5) {
8773 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
8774 if (stat_ctl & F_COUNTPAUSESTATTX) {
8775 p->tx_frames -= p->tx_pause;
8776 p->tx_octets -= p->tx_pause * 64;
8777 }
8778 if (stat_ctl & F_COUNTPAUSEMCTX)
8779 p->tx_mcast_frames -= p->tx_pause;
8780 if (stat_ctl & F_COUNTPAUSESTATRX) {
8781 p->rx_frames -= p->rx_pause;
8782 p->rx_octets -= p->rx_pause * 64;
8783 }
8784 if (stat_ctl & F_COUNTPAUSEMCRX)
8785 p->rx_mcast_frames -= p->rx_pause;
8786 }
8787
8788 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
8789 bgmap = pi->mps_bg_map;
8790 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
8791 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
8792 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
8793 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
8794 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
8795 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
8796 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
8797 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
8798 #undef GET_STAT_COM
8799 }
8800
8801 /**
8802 * t4_get_lb_stats - collect loopback port statistics
8803 * @adap: the adapter
8804 * @idx: the loopback port index
8805 * @p: the stats structure to fill
8806 *
8807 * Return HW statistics for the given loopback port.
8808 */
t4_get_lb_stats(struct adapter * adap,int idx,struct lb_port_stats * p)8809 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
8810 {
8811
8812 #define GET_STAT(name) \
8813 t4_read_reg64(adap, \
8814 t4_port_reg(adap, idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))
8815 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
8816
8817 p->octets = GET_STAT(BYTES);
8818 p->frames = GET_STAT(FRAMES);
8819 p->bcast_frames = GET_STAT(BCAST);
8820 p->mcast_frames = GET_STAT(MCAST);
8821 p->ucast_frames = GET_STAT(UCAST);
8822 p->error_frames = GET_STAT(ERROR);
8823
8824 p->frames_64 = GET_STAT(64B);
8825 p->frames_65_127 = GET_STAT(65B_127B);
8826 p->frames_128_255 = GET_STAT(128B_255B);
8827 p->frames_256_511 = GET_STAT(256B_511B);
8828 p->frames_512_1023 = GET_STAT(512B_1023B);
8829 p->frames_1024_1518 = GET_STAT(1024B_1518B);
8830 p->frames_1519_max = GET_STAT(1519B_MAX);
8831 p->drop = GET_STAT(DROP_FRAMES);
8832
8833 if (idx < adap->params.nports) {
8834 u32 bg = adap2pinfo(adap, idx)->mps_bg_map;
8835
8836 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
8837 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
8838 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
8839 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
8840 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
8841 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
8842 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
8843 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
8844 }
8845
8846 #undef GET_STAT
8847 #undef GET_STAT_COM
8848 }
8849
8850 /**
8851 * t4_wol_magic_enable - enable/disable magic packet WoL
8852 * @adap: the adapter
8853 * @port: the physical port index
8854 * @addr: MAC address expected in magic packets, %NULL to disable
8855 *
8856 * Enables/disables magic packet wake-on-LAN for the selected port.
8857 */
t4_wol_magic_enable(struct adapter * adap,unsigned int port,const u8 * addr)8858 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
8859 const u8 *addr)
8860 {
8861 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
8862
8863 if (is_t4(adap)) {
8864 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
8865 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
8866 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
8867 } else if (chip_id(adap) < CHELSIO_T7) {
8868 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
8869 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
8870 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
8871 } else {
8872 mag_id_reg_l = T7_PORT_REG(port, A_T7_MAC_PORT_MAGIC_MACID_LO);
8873 mag_id_reg_h = T7_PORT_REG(port, A_T7_MAC_PORT_MAGIC_MACID_HI);
8874 port_cfg_reg = T7_PORT_REG(port, A_MAC_PORT_CFG2);
8875 }
8876
8877 if (addr) {
8878 t4_write_reg(adap, mag_id_reg_l,
8879 (addr[2] << 24) | (addr[3] << 16) |
8880 (addr[4] << 8) | addr[5]);
8881 t4_write_reg(adap, mag_id_reg_h,
8882 (addr[0] << 8) | addr[1]);
8883 }
8884 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
8885 V_MAGICEN(addr != NULL));
8886 }
8887
8888 /**
8889 * t4_wol_pat_enable - enable/disable pattern-based WoL
8890 * @adap: the adapter
8891 * @port: the physical port index
8892 * @map: bitmap of which HW pattern filters to set
8893 * @mask0: byte mask for bytes 0-63 of a packet
8894 * @mask1: byte mask for bytes 64-127 of a packet
8895 * @crc: Ethernet CRC for selected bytes
8896 * @enable: enable/disable switch
8897 *
8898 * Sets the pattern filters indicated in @map to mask out the bytes
8899 * specified in @mask0/@mask1 in received packets and compare the CRC of
8900 * the resulting packet against @crc. If @enable is %true pattern-based
8901 * WoL is enabled, otherwise disabled.
8902 */
t4_wol_pat_enable(struct adapter * adap,unsigned int port,unsigned int map,u64 mask0,u64 mask1,unsigned int crc,bool enable)8903 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
8904 u64 mask0, u64 mask1, unsigned int crc, bool enable)
8905 {
8906 int i;
8907 u32 port_cfg_reg;
8908
8909 if (is_t4(adap))
8910 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
8911 else if (chip_id(adap) < CHELSIO_T7)
8912 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
8913 else
8914 port_cfg_reg = T7_PORT_REG(port, A_MAC_PORT_CFG2);
8915
8916 if (!enable) {
8917 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
8918 return 0;
8919 }
8920 if (map > 0xff)
8921 return -EINVAL;
8922
8923 #define EPIO_REG(name) \
8924 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
8925 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
8926
8927 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
8928 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
8929 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
8930
8931 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
8932 if (!(map & 1))
8933 continue;
8934
8935 /* write byte masks */
8936 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
8937 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
8938 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
8939 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
8940 return -ETIMEDOUT;
8941
8942 /* write CRC */
8943 t4_write_reg(adap, EPIO_REG(DATA0), crc);
8944 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
8945 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
8946 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
8947 return -ETIMEDOUT;
8948 }
8949 #undef EPIO_REG
8950
8951 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
8952 return 0;
8953 }
8954
8955 /* t4_mk_filtdelwr - create a delete filter WR
8956 * @ftid: the filter ID
8957 * @wr: the filter work request to populate
8958 * @qid: ingress queue to receive the delete notification
8959 *
8960 * Creates a filter work request to delete the supplied filter. If @qid is
8961 * negative the delete notification is suppressed.
8962 */
t4_mk_filtdelwr(unsigned int ftid,struct fw_filter_wr * wr,int qid)8963 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
8964 {
8965 memset(wr, 0, sizeof(*wr));
8966 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
8967 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
8968 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
8969 V_FW_FILTER_WR_NOREPLY(qid < 0));
8970 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
8971 if (qid >= 0)
8972 wr->rx_chan_rx_rpl_iq =
8973 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
8974 }
8975
8976 #define INIT_CMD(var, cmd, rd_wr) do { \
8977 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
8978 F_FW_CMD_REQUEST | \
8979 F_FW_CMD_##rd_wr); \
8980 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
8981 } while (0)
8982
t4_fwaddrspace_write(struct adapter * adap,unsigned int mbox,u32 addr,u32 val)8983 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
8984 u32 addr, u32 val)
8985 {
8986 u32 ldst_addrspace;
8987 struct fw_ldst_cmd c;
8988
8989 memset(&c, 0, sizeof(c));
8990 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
8991 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
8992 F_FW_CMD_REQUEST |
8993 F_FW_CMD_WRITE |
8994 ldst_addrspace);
8995 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
8996 c.u.addrval.addr = cpu_to_be32(addr);
8997 c.u.addrval.val = cpu_to_be32(val);
8998
8999 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
9000 }
9001
9002 /**
9003 * t4_mdio_rd - read a PHY register through MDIO
9004 * @adap: the adapter
9005 * @mbox: mailbox to use for the FW command
9006 * @phy_addr: the PHY address
9007 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
9008 * @reg: the register to read
9009 * @valp: where to store the value
9010 *
9011 * Issues a FW command through the given mailbox to read a PHY register.
9012 */
t4_mdio_rd(struct adapter * adap,unsigned int mbox,unsigned int phy_addr,unsigned int mmd,unsigned int reg,unsigned int * valp)9013 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
9014 unsigned int mmd, unsigned int reg, unsigned int *valp)
9015 {
9016 int ret;
9017 u32 ldst_addrspace;
9018 struct fw_ldst_cmd c;
9019
9020 memset(&c, 0, sizeof(c));
9021 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
9022 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9023 F_FW_CMD_REQUEST | F_FW_CMD_READ |
9024 ldst_addrspace);
9025 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9026 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
9027 V_FW_LDST_CMD_MMD(mmd));
9028 c.u.mdio.raddr = cpu_to_be16(reg);
9029
9030 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9031 if (ret == 0)
9032 *valp = be16_to_cpu(c.u.mdio.rval);
9033 return ret;
9034 }
9035
9036 /**
9037 * t4_mdio_wr - write a PHY register through MDIO
9038 * @adap: the adapter
9039 * @mbox: mailbox to use for the FW command
9040 * @phy_addr: the PHY address
9041 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
9042 * @reg: the register to write
9043 * @valp: value to write
9044 *
9045 * Issues a FW command through the given mailbox to write a PHY register.
9046 */
t4_mdio_wr(struct adapter * adap,unsigned int mbox,unsigned int phy_addr,unsigned int mmd,unsigned int reg,unsigned int val)9047 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
9048 unsigned int mmd, unsigned int reg, unsigned int val)
9049 {
9050 u32 ldst_addrspace;
9051 struct fw_ldst_cmd c;
9052
9053 memset(&c, 0, sizeof(c));
9054 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
9055 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9056 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
9057 ldst_addrspace);
9058 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9059 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
9060 V_FW_LDST_CMD_MMD(mmd));
9061 c.u.mdio.raddr = cpu_to_be16(reg);
9062 c.u.mdio.rval = cpu_to_be16(val);
9063
9064 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
9065 }
9066
9067 /**
9068 *
9069 * t4_sge_decode_idma_state - decode the idma state
9070 * @adap: the adapter
9071 * @state: the state idma is stuck in
9072 */
t4_sge_decode_idma_state(struct adapter * adapter,int state)9073 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
9074 {
9075 static const char * const t4_decode[] = {
9076 "IDMA_IDLE",
9077 "IDMA_PUSH_MORE_CPL_FIFO",
9078 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
9079 "Not used",
9080 "IDMA_PHYSADDR_SEND_PCIEHDR",
9081 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
9082 "IDMA_PHYSADDR_SEND_PAYLOAD",
9083 "IDMA_SEND_FIFO_TO_IMSG",
9084 "IDMA_FL_REQ_DATA_FL_PREP",
9085 "IDMA_FL_REQ_DATA_FL",
9086 "IDMA_FL_DROP",
9087 "IDMA_FL_H_REQ_HEADER_FL",
9088 "IDMA_FL_H_SEND_PCIEHDR",
9089 "IDMA_FL_H_PUSH_CPL_FIFO",
9090 "IDMA_FL_H_SEND_CPL",
9091 "IDMA_FL_H_SEND_IP_HDR_FIRST",
9092 "IDMA_FL_H_SEND_IP_HDR",
9093 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
9094 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
9095 "IDMA_FL_H_SEND_IP_HDR_PADDING",
9096 "IDMA_FL_D_SEND_PCIEHDR",
9097 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
9098 "IDMA_FL_D_REQ_NEXT_DATA_FL",
9099 "IDMA_FL_SEND_PCIEHDR",
9100 "IDMA_FL_PUSH_CPL_FIFO",
9101 "IDMA_FL_SEND_CPL",
9102 "IDMA_FL_SEND_PAYLOAD_FIRST",
9103 "IDMA_FL_SEND_PAYLOAD",
9104 "IDMA_FL_REQ_NEXT_DATA_FL",
9105 "IDMA_FL_SEND_NEXT_PCIEHDR",
9106 "IDMA_FL_SEND_PADDING",
9107 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
9108 "IDMA_FL_SEND_FIFO_TO_IMSG",
9109 "IDMA_FL_REQ_DATAFL_DONE",
9110 "IDMA_FL_REQ_HEADERFL_DONE",
9111 };
9112 static const char * const t5_decode[] = {
9113 "IDMA_IDLE",
9114 "IDMA_ALMOST_IDLE",
9115 "IDMA_PUSH_MORE_CPL_FIFO",
9116 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
9117 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
9118 "IDMA_PHYSADDR_SEND_PCIEHDR",
9119 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
9120 "IDMA_PHYSADDR_SEND_PAYLOAD",
9121 "IDMA_SEND_FIFO_TO_IMSG",
9122 "IDMA_FL_REQ_DATA_FL",
9123 "IDMA_FL_DROP",
9124 "IDMA_FL_DROP_SEND_INC",
9125 "IDMA_FL_H_REQ_HEADER_FL",
9126 "IDMA_FL_H_SEND_PCIEHDR",
9127 "IDMA_FL_H_PUSH_CPL_FIFO",
9128 "IDMA_FL_H_SEND_CPL",
9129 "IDMA_FL_H_SEND_IP_HDR_FIRST",
9130 "IDMA_FL_H_SEND_IP_HDR",
9131 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
9132 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
9133 "IDMA_FL_H_SEND_IP_HDR_PADDING",
9134 "IDMA_FL_D_SEND_PCIEHDR",
9135 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
9136 "IDMA_FL_D_REQ_NEXT_DATA_FL",
9137 "IDMA_FL_SEND_PCIEHDR",
9138 "IDMA_FL_PUSH_CPL_FIFO",
9139 "IDMA_FL_SEND_CPL",
9140 "IDMA_FL_SEND_PAYLOAD_FIRST",
9141 "IDMA_FL_SEND_PAYLOAD",
9142 "IDMA_FL_REQ_NEXT_DATA_FL",
9143 "IDMA_FL_SEND_NEXT_PCIEHDR",
9144 "IDMA_FL_SEND_PADDING",
9145 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
9146 };
9147 static const char * const t6_decode[] = {
9148 "IDMA_IDLE",
9149 "IDMA_PUSH_MORE_CPL_FIFO",
9150 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
9151 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
9152 "IDMA_PHYSADDR_SEND_PCIEHDR",
9153 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
9154 "IDMA_PHYSADDR_SEND_PAYLOAD",
9155 "IDMA_FL_REQ_DATA_FL",
9156 "IDMA_FL_DROP",
9157 "IDMA_FL_DROP_SEND_INC",
9158 "IDMA_FL_H_REQ_HEADER_FL",
9159 "IDMA_FL_H_SEND_PCIEHDR",
9160 "IDMA_FL_H_PUSH_CPL_FIFO",
9161 "IDMA_FL_H_SEND_CPL",
9162 "IDMA_FL_H_SEND_IP_HDR_FIRST",
9163 "IDMA_FL_H_SEND_IP_HDR",
9164 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
9165 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
9166 "IDMA_FL_H_SEND_IP_HDR_PADDING",
9167 "IDMA_FL_D_SEND_PCIEHDR",
9168 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
9169 "IDMA_FL_D_REQ_NEXT_DATA_FL",
9170 "IDMA_FL_SEND_PCIEHDR",
9171 "IDMA_FL_PUSH_CPL_FIFO",
9172 "IDMA_FL_SEND_CPL",
9173 "IDMA_FL_SEND_PAYLOAD_FIRST",
9174 "IDMA_FL_SEND_PAYLOAD",
9175 "IDMA_FL_REQ_NEXT_DATA_FL",
9176 "IDMA_FL_SEND_NEXT_PCIEHDR",
9177 "IDMA_FL_SEND_PADDING",
9178 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
9179 };
9180 static const u32 sge_regs[] = {
9181 A_SGE_DEBUG_DATA_LOW_INDEX_2,
9182 A_SGE_DEBUG_DATA_LOW_INDEX_3,
9183 A_SGE_DEBUG_DATA_HIGH_INDEX_10,
9184 };
9185 const char * const *sge_idma_decode;
9186 int sge_idma_decode_nstates;
9187 int i;
9188 unsigned int chip_version = chip_id(adapter);
9189
9190 /* Select the right set of decode strings to dump depending on the
9191 * adapter chip type.
9192 */
9193 switch (chip_version) {
9194 case CHELSIO_T4:
9195 sge_idma_decode = (const char * const *)t4_decode;
9196 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
9197 break;
9198
9199 case CHELSIO_T5:
9200 sge_idma_decode = (const char * const *)t5_decode;
9201 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
9202 break;
9203
9204 case CHELSIO_T6:
9205 case CHELSIO_T7:
9206 sge_idma_decode = (const char * const *)t6_decode;
9207 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
9208 break;
9209
9210 default:
9211 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version);
9212 return;
9213 }
9214
9215 if (state < sge_idma_decode_nstates)
9216 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
9217 else
9218 CH_WARN(adapter, "idma state %d unknown\n", state);
9219
9220 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
9221 CH_WARN(adapter, "SGE register %#x value %#x\n",
9222 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
9223 }
9224
9225 /**
9226 * t4_sge_ctxt_flush - flush the SGE context cache
9227 * @adap: the adapter
9228 * @mbox: mailbox to use for the FW command
9229 *
9230 * Issues a FW command through the given mailbox to flush the
9231 * SGE context cache.
9232 */
t4_sge_ctxt_flush(struct adapter * adap,unsigned int mbox,int ctxt_type)9233 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
9234 {
9235 int ret;
9236 u32 ldst_addrspace;
9237 struct fw_ldst_cmd c;
9238
9239 memset(&c, 0, sizeof(c));
9240 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ?
9241 FW_LDST_ADDRSPC_SGE_EGRC :
9242 FW_LDST_ADDRSPC_SGE_INGC);
9243 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9244 F_FW_CMD_REQUEST | F_FW_CMD_READ |
9245 ldst_addrspace);
9246 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9247 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
9248
9249 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9250 return ret;
9251 }
9252
9253 /**
9254 * t4_fw_hello - establish communication with FW
9255 * @adap: the adapter
9256 * @mbox: mailbox to use for the FW command
9257 * @evt_mbox: mailbox to receive async FW events
9258 * @master: specifies the caller's willingness to be the device master
9259 * @state: returns the current device state (if non-NULL)
9260 *
9261 * Issues a command to establish communication with FW. Returns either
9262 * an error (negative integer) or the mailbox of the Master PF.
9263 */
t4_fw_hello(struct adapter * adap,unsigned int mbox,unsigned int evt_mbox,enum dev_master master,enum dev_state * state)9264 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
9265 enum dev_master master, enum dev_state *state)
9266 {
9267 int ret;
9268 struct fw_hello_cmd c;
9269 u32 v;
9270 unsigned int master_mbox;
9271 int retries = FW_CMD_HELLO_RETRIES;
9272
9273 retry:
9274 memset(&c, 0, sizeof(c));
9275 INIT_CMD(c, HELLO, WRITE);
9276 c.err_to_clearinit = cpu_to_be32(
9277 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
9278 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
9279 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
9280 mbox : M_FW_HELLO_CMD_MBMASTER) |
9281 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
9282 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
9283 F_FW_HELLO_CMD_CLEARINIT);
9284
9285 /*
9286 * Issue the HELLO command to the firmware. If it's not successful
9287 * but indicates that we got a "busy" or "timeout" condition, retry
9288 * the HELLO until we exhaust our retry limit. If we do exceed our
9289 * retry limit, check to see if the firmware left us any error
9290 * information and report that if so ...
9291 */
9292 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9293 if (ret != FW_SUCCESS) {
9294 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
9295 goto retry;
9296 return ret;
9297 }
9298
9299 v = be32_to_cpu(c.err_to_clearinit);
9300 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
9301 if (state) {
9302 if (v & F_FW_HELLO_CMD_ERR)
9303 *state = DEV_STATE_ERR;
9304 else if (v & F_FW_HELLO_CMD_INIT)
9305 *state = DEV_STATE_INIT;
9306 else
9307 *state = DEV_STATE_UNINIT;
9308 }
9309
9310 /*
9311 * If we're not the Master PF then we need to wait around for the
9312 * Master PF Driver to finish setting up the adapter.
9313 *
9314 * Note that we also do this wait if we're a non-Master-capable PF and
9315 * there is no current Master PF; a Master PF may show up momentarily
9316 * and we wouldn't want to fail pointlessly. (This can happen when an
9317 * OS loads lots of different drivers rapidly at the same time). In
9318 * this case, the Master PF returned by the firmware will be
9319 * M_PCIE_FW_MASTER so the test below will work ...
9320 */
9321 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
9322 master_mbox != mbox) {
9323 int waiting = FW_CMD_HELLO_TIMEOUT;
9324
9325 /*
9326 * Wait for the firmware to either indicate an error or
9327 * initialized state. If we see either of these we bail out
9328 * and report the issue to the caller. If we exhaust the
9329 * "hello timeout" and we haven't exhausted our retries, try
9330 * again. Otherwise bail with a timeout error.
9331 */
9332 for (;;) {
9333 u32 pcie_fw;
9334
9335 msleep(50);
9336 waiting -= 50;
9337
9338 /*
9339 * If neither Error nor Initialialized are indicated
9340 * by the firmware keep waiting till we exhaust our
9341 * timeout ... and then retry if we haven't exhausted
9342 * our retries ...
9343 */
9344 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
9345 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
9346 if (waiting <= 0) {
9347 if (retries-- > 0)
9348 goto retry;
9349
9350 return -ETIMEDOUT;
9351 }
9352 continue;
9353 }
9354
9355 /*
9356 * We either have an Error or Initialized condition
9357 * report errors preferentially.
9358 */
9359 if (state) {
9360 if (pcie_fw & F_PCIE_FW_ERR)
9361 *state = DEV_STATE_ERR;
9362 else if (pcie_fw & F_PCIE_FW_INIT)
9363 *state = DEV_STATE_INIT;
9364 }
9365
9366 /*
9367 * If we arrived before a Master PF was selected and
9368 * there's not a valid Master PF, grab its identity
9369 * for our caller.
9370 */
9371 if (master_mbox == M_PCIE_FW_MASTER &&
9372 (pcie_fw & F_PCIE_FW_MASTER_VLD))
9373 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
9374 break;
9375 }
9376 }
9377
9378 return master_mbox;
9379 }
9380
9381 /**
9382 * t4_fw_bye - end communication with FW
9383 * @adap: the adapter
9384 * @mbox: mailbox to use for the FW command
9385 *
9386 * Issues a command to terminate communication with FW.
9387 */
t4_fw_bye(struct adapter * adap,unsigned int mbox)9388 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
9389 {
9390 struct fw_bye_cmd c;
9391
9392 memset(&c, 0, sizeof(c));
9393 INIT_CMD(c, BYE, WRITE);
9394 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
9395 }
9396
9397 /**
9398 * t4_fw_reset - issue a reset to FW
9399 * @adap: the adapter
9400 * @mbox: mailbox to use for the FW command
9401 * @reset: specifies the type of reset to perform
9402 *
9403 * Issues a reset command of the specified type to FW.
9404 */
t4_fw_reset(struct adapter * adap,unsigned int mbox,int reset)9405 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
9406 {
9407 struct fw_reset_cmd c;
9408
9409 memset(&c, 0, sizeof(c));
9410 INIT_CMD(c, RESET, WRITE);
9411 c.val = cpu_to_be32(reset);
9412 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
9413 }
9414
9415 /**
9416 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
9417 * @adap: the adapter
9418 * @mbox: mailbox to use for the FW RESET command (if desired)
9419 * @force: force uP into RESET even if FW RESET command fails
9420 *
9421 * Issues a RESET command to firmware (if desired) with a HALT indication
9422 * and then puts the microprocessor into RESET state. The RESET command
9423 * will only be issued if a legitimate mailbox is provided (mbox <=
9424 * M_PCIE_FW_MASTER).
9425 *
9426 * This is generally used in order for the host to safely manipulate the
9427 * adapter without fear of conflicting with whatever the firmware might
9428 * be doing. The only way out of this state is to RESTART the firmware
9429 * ...
9430 */
t4_fw_halt(struct adapter * adap,unsigned int mbox,int force)9431 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
9432 {
9433 int ret = 0;
9434
9435 /*
9436 * If a legitimate mailbox is provided, issue a RESET command
9437 * with a HALT indication.
9438 */
9439 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) {
9440 struct fw_reset_cmd c;
9441
9442 memset(&c, 0, sizeof(c));
9443 INIT_CMD(c, RESET, WRITE);
9444 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
9445 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
9446 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
9447 }
9448
9449 /*
9450 * Normally we won't complete the operation if the firmware RESET
9451 * command fails but if our caller insists we'll go ahead and put the
9452 * uP into RESET. This can be useful if the firmware is hung or even
9453 * missing ... We'll have to take the risk of putting the uP into
9454 * RESET without the cooperation of firmware in that case.
9455 *
9456 * We also force the firmware's HALT flag to be on in case we bypassed
9457 * the firmware RESET command above or we're dealing with old firmware
9458 * which doesn't have the HALT capability. This will serve as a flag
9459 * for the incoming firmware to know that it's coming out of a HALT
9460 * rather than a RESET ... if it's new enough to understand that ...
9461 */
9462 if (ret == 0 || force) {
9463 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
9464 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
9465 F_PCIE_FW_HALT);
9466 }
9467
9468 /*
9469 * And we always return the result of the firmware RESET command
9470 * even when we force the uP into RESET ...
9471 */
9472 return ret;
9473 }
9474
9475 /**
9476 * t4_fw_restart - restart the firmware by taking the uP out of RESET
9477 * @adap: the adapter
9478 *
9479 * Restart firmware previously halted by t4_fw_halt(). On successful
9480 * return the previous PF Master remains as the new PF Master and there
9481 * is no need to issue a new HELLO command, etc.
9482 */
t4_fw_restart(struct adapter * adap,unsigned int mbox)9483 int t4_fw_restart(struct adapter *adap, unsigned int mbox)
9484 {
9485 int ms;
9486
9487 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
9488 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
9489 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
9490 return FW_SUCCESS;
9491 msleep(100);
9492 ms += 100;
9493 }
9494
9495 return -ETIMEDOUT;
9496 }
9497
9498 /**
9499 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
9500 * @adap: the adapter
9501 * @mbox: mailbox to use for the FW RESET command (if desired)
9502 * @fw_data: the firmware image to write
9503 * @size: image size
9504 * @force: force upgrade even if firmware doesn't cooperate
9505 *
9506 * Perform all of the steps necessary for upgrading an adapter's
9507 * firmware image. Normally this requires the cooperation of the
9508 * existing firmware in order to halt all existing activities
9509 * but if an invalid mailbox token is passed in we skip that step
9510 * (though we'll still put the adapter microprocessor into RESET in
9511 * that case).
9512 *
9513 * On successful return the new firmware will have been loaded and
9514 * the adapter will have been fully RESET losing all previous setup
9515 * state. On unsuccessful return the adapter may be completely hosed ...
9516 * positive errno indicates that the adapter is ~probably~ intact, a
9517 * negative errno indicates that things are looking bad ...
9518 */
t4_fw_upgrade(struct adapter * adap,unsigned int mbox,const u8 * fw_data,unsigned int size,int force)9519 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
9520 const u8 *fw_data, unsigned int size, int force)
9521 {
9522 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
9523 unsigned int bootstrap =
9524 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
9525 int ret;
9526
9527 if (!t4_fw_matches_chip(adap, fw_hdr))
9528 return -EINVAL;
9529
9530 if (!bootstrap) {
9531 ret = t4_fw_halt(adap, mbox, force);
9532 if (ret < 0 && !force)
9533 return ret;
9534 }
9535
9536 ret = t4_load_fw(adap, fw_data, size);
9537 if (ret < 0 || bootstrap)
9538 return ret;
9539
9540 return t4_fw_restart(adap, mbox);
9541 }
9542
9543 /**
9544 * t4_fw_initialize - ask FW to initialize the device
9545 * @adap: the adapter
9546 * @mbox: mailbox to use for the FW command
9547 *
9548 * Issues a command to FW to partially initialize the device. This
9549 * performs initialization that generally doesn't depend on user input.
9550 */
t4_fw_initialize(struct adapter * adap,unsigned int mbox)9551 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
9552 {
9553 struct fw_initialize_cmd c;
9554
9555 memset(&c, 0, sizeof(c));
9556 INIT_CMD(c, INITIALIZE, WRITE);
9557 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
9558 }
9559
9560 /**
9561 * t4_query_params_rw - query FW or device parameters
9562 * @adap: the adapter
9563 * @mbox: mailbox to use for the FW command
9564 * @pf: the PF
9565 * @vf: the VF
9566 * @nparams: the number of parameters
9567 * @params: the parameter names
9568 * @val: the parameter values
9569 * @rw: Write and read flag
9570 *
9571 * Reads the value of FW or device parameters. Up to 7 parameters can be
9572 * queried at once.
9573 */
t4_query_params_rw(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val,int rw)9574 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
9575 unsigned int vf, unsigned int nparams, const u32 *params,
9576 u32 *val, int rw)
9577 {
9578 int i, ret;
9579 struct fw_params_cmd c;
9580 __be32 *p = &c.param[0].mnem;
9581
9582 if (nparams > 7)
9583 return -EINVAL;
9584
9585 memset(&c, 0, sizeof(c));
9586 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
9587 F_FW_CMD_REQUEST | F_FW_CMD_READ |
9588 V_FW_PARAMS_CMD_PFN(pf) |
9589 V_FW_PARAMS_CMD_VFN(vf));
9590 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
9591
9592 for (i = 0; i < nparams; i++) {
9593 *p++ = cpu_to_be32(*params++);
9594 if (rw)
9595 *p = cpu_to_be32(*(val + i));
9596 p++;
9597 }
9598
9599 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9600
9601 /*
9602 * We always copy back the results, even if there's an error. We'll
9603 * get an error if any of the parameters was unknown to the Firmware,
9604 * but there will be results for the others ... (Older Firmware
9605 * stopped at the first unknown parameter; newer Firmware processes
9606 * them all and flags the unknown parameters with a return value of
9607 * ~0UL.)
9608 */
9609 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
9610 *val++ = be32_to_cpu(*p);
9611
9612 return ret;
9613 }
9614
t4_query_params(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val)9615 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
9616 unsigned int vf, unsigned int nparams, const u32 *params,
9617 u32 *val)
9618 {
9619 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
9620 }
9621
9622 /**
9623 * t4_set_params_timeout - sets FW or device parameters
9624 * @adap: the adapter
9625 * @mbox: mailbox to use for the FW command
9626 * @pf: the PF
9627 * @vf: the VF
9628 * @nparams: the number of parameters
9629 * @params: the parameter names
9630 * @val: the parameter values
9631 * @timeout: the timeout time
9632 *
9633 * Sets the value of FW or device parameters. Up to 7 parameters can be
9634 * specified at once.
9635 */
t4_set_params_timeout(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,const u32 * val,int timeout)9636 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
9637 unsigned int pf, unsigned int vf,
9638 unsigned int nparams, const u32 *params,
9639 const u32 *val, int timeout)
9640 {
9641 struct fw_params_cmd c;
9642 __be32 *p = &c.param[0].mnem;
9643
9644 if (nparams > 7)
9645 return -EINVAL;
9646
9647 memset(&c, 0, sizeof(c));
9648 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
9649 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
9650 V_FW_PARAMS_CMD_PFN(pf) |
9651 V_FW_PARAMS_CMD_VFN(vf));
9652 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
9653
9654 while (nparams--) {
9655 *p++ = cpu_to_be32(*params++);
9656 *p++ = cpu_to_be32(*val++);
9657 }
9658
9659 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
9660 }
9661
9662 /**
9663 * t4_set_params - sets FW or device parameters
9664 * @adap: the adapter
9665 * @mbox: mailbox to use for the FW command
9666 * @pf: the PF
9667 * @vf: the VF
9668 * @nparams: the number of parameters
9669 * @params: the parameter names
9670 * @val: the parameter values
9671 *
9672 * Sets the value of FW or device parameters. Up to 7 parameters can be
9673 * specified at once.
9674 */
t4_set_params(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,const u32 * val)9675 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
9676 unsigned int vf, unsigned int nparams, const u32 *params,
9677 const u32 *val)
9678 {
9679 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
9680 FW_CMD_MAX_TIMEOUT);
9681 }
9682
9683 /**
9684 * t4_cfg_pfvf - configure PF/VF resource limits
9685 * @adap: the adapter
9686 * @mbox: mailbox to use for the FW command
9687 * @pf: the PF being configured
9688 * @vf: the VF being configured
9689 * @txq: the max number of egress queues
9690 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
9691 * @rxqi: the max number of interrupt-capable ingress queues
9692 * @rxq: the max number of interruptless ingress queues
9693 * @tc: the PCI traffic class
9694 * @vi: the max number of virtual interfaces
9695 * @cmask: the channel access rights mask for the PF/VF
9696 * @pmask: the port access rights mask for the PF/VF
9697 * @nexact: the maximum number of exact MPS filters
9698 * @rcaps: read capabilities
9699 * @wxcaps: write/execute capabilities
9700 *
9701 * Configures resource limits and capabilities for a physical or virtual
9702 * function.
9703 */
t4_cfg_pfvf(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int txq,unsigned int txq_eth_ctrl,unsigned int rxqi,unsigned int rxq,unsigned int tc,unsigned int vi,unsigned int cmask,unsigned int pmask,unsigned int nexact,unsigned int rcaps,unsigned int wxcaps)9704 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
9705 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
9706 unsigned int rxqi, unsigned int rxq, unsigned int tc,
9707 unsigned int vi, unsigned int cmask, unsigned int pmask,
9708 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
9709 {
9710 struct fw_pfvf_cmd c;
9711
9712 memset(&c, 0, sizeof(c));
9713 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
9714 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
9715 V_FW_PFVF_CMD_VFN(vf));
9716 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
9717 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
9718 V_FW_PFVF_CMD_NIQ(rxq));
9719 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
9720 V_FW_PFVF_CMD_PMASK(pmask) |
9721 V_FW_PFVF_CMD_NEQ(txq));
9722 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
9723 V_FW_PFVF_CMD_NVI(vi) |
9724 V_FW_PFVF_CMD_NEXACTF(nexact));
9725 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
9726 V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
9727 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
9728 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
9729 }
9730
9731 /**
9732 * t4_alloc_vi_func - allocate a virtual interface
9733 * @adap: the adapter
9734 * @mbox: mailbox to use for the FW command
9735 * @port: physical port associated with the VI
9736 * @pf: the PF owning the VI
9737 * @vf: the VF owning the VI
9738 * @nmac: number of MAC addresses needed (1 to 5)
9739 * @mac: the MAC addresses of the VI
9740 * @rss_size: size of RSS table slice associated with this VI
9741 * @portfunc: which Port Application Function MAC Address is desired
9742 * @idstype: Intrusion Detection Type
9743 *
9744 * Allocates a virtual interface for the given physical port. If @mac is
9745 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
9746 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
9747 * @mac should be large enough to hold @nmac Ethernet addresses, they are
9748 * stored consecutively so the space needed is @nmac * 6 bytes.
9749 * Returns a negative error number or the non-negative VI id.
9750 */
t4_alloc_vi_func(struct adapter * adap,unsigned int mbox,unsigned int port,unsigned int pf,unsigned int vf,unsigned int nmac,u8 * mac,u16 * rss_size,uint8_t * vfvld,uint16_t * vin,unsigned int portfunc,unsigned int idstype)9751 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
9752 unsigned int port, unsigned int pf, unsigned int vf,
9753 unsigned int nmac, u8 *mac, u16 *rss_size,
9754 uint8_t *vfvld, uint16_t *vin,
9755 unsigned int portfunc, unsigned int idstype)
9756 {
9757 int ret;
9758 struct fw_vi_cmd c;
9759
9760 memset(&c, 0, sizeof(c));
9761 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
9762 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
9763 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
9764 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
9765 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
9766 V_FW_VI_CMD_FUNC(portfunc));
9767 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
9768 c.nmac = nmac - 1;
9769 if(!rss_size)
9770 c.norss_rsssize = F_FW_VI_CMD_NORSS;
9771
9772 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9773 if (ret)
9774 return ret;
9775 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
9776
9777 if (mac) {
9778 memcpy(mac, c.mac, sizeof(c.mac));
9779 switch (nmac) {
9780 case 5:
9781 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
9782 case 4:
9783 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
9784 case 3:
9785 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
9786 case 2:
9787 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
9788 }
9789 }
9790 if (rss_size)
9791 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
9792 if (vfvld) {
9793 *vfvld = adap->params.viid_smt_extn_support ?
9794 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) :
9795 G_FW_VIID_VIVLD(ret);
9796 }
9797 if (vin) {
9798 *vin = adap->params.viid_smt_extn_support ?
9799 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) :
9800 G_FW_VIID_VIN(ret);
9801 }
9802
9803 return ret;
9804 }
9805
9806 /**
9807 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
9808 * @adap: the adapter
9809 * @mbox: mailbox to use for the FW command
9810 * @port: physical port associated with the VI
9811 * @pf: the PF owning the VI
9812 * @vf: the VF owning the VI
9813 * @nmac: number of MAC addresses needed (1 to 5)
9814 * @mac: the MAC addresses of the VI
9815 * @rss_size: size of RSS table slice associated with this VI
9816 *
9817 * backwards compatible and convieniance routine to allocate a Virtual
9818 * Interface with a Ethernet Port Application Function and Intrustion
9819 * Detection System disabled.
9820 */
t4_alloc_vi(struct adapter * adap,unsigned int mbox,unsigned int port,unsigned int pf,unsigned int vf,unsigned int nmac,u8 * mac,u16 * rss_size,uint8_t * vfvld,uint16_t * vin)9821 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
9822 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
9823 u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
9824 {
9825 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
9826 vfvld, vin, FW_VI_FUNC_ETH, 0);
9827 }
9828
9829 /**
9830 * t4_free_vi - free a virtual interface
9831 * @adap: the adapter
9832 * @mbox: mailbox to use for the FW command
9833 * @pf: the PF owning the VI
9834 * @vf: the VF owning the VI
9835 * @viid: virtual interface identifiler
9836 *
9837 * Free a previously allocated virtual interface.
9838 */
t4_free_vi(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int viid)9839 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
9840 unsigned int vf, unsigned int viid)
9841 {
9842 struct fw_vi_cmd c;
9843
9844 memset(&c, 0, sizeof(c));
9845 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
9846 F_FW_CMD_REQUEST |
9847 F_FW_CMD_EXEC |
9848 V_FW_VI_CMD_PFN(pf) |
9849 V_FW_VI_CMD_VFN(vf));
9850 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
9851 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
9852
9853 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9854 }
9855
9856 /**
9857 * t4_set_rxmode - set Rx properties of a virtual interface
9858 * @adap: the adapter
9859 * @mbox: mailbox to use for the FW command
9860 * @viid: the VI id
9861 * @mtu: the new MTU or -1
9862 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
9863 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
9864 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
9865 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
9866 * @sleep_ok: if true we may sleep while awaiting command completion
9867 *
9868 * Sets Rx properties of a virtual interface.
9869 */
t4_set_rxmode(struct adapter * adap,unsigned int mbox,unsigned int viid,int mtu,int promisc,int all_multi,int bcast,int vlanex,bool sleep_ok)9870 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
9871 int mtu, int promisc, int all_multi, int bcast, int vlanex,
9872 bool sleep_ok)
9873 {
9874 struct fw_vi_rxmode_cmd c;
9875
9876 /* convert to FW values */
9877 if (mtu < 0)
9878 mtu = M_FW_VI_RXMODE_CMD_MTU;
9879 if (promisc < 0)
9880 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
9881 if (all_multi < 0)
9882 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
9883 if (bcast < 0)
9884 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
9885 if (vlanex < 0)
9886 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
9887
9888 memset(&c, 0, sizeof(c));
9889 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
9890 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
9891 V_FW_VI_RXMODE_CMD_VIID(viid));
9892 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
9893 c.mtu_to_vlanexen =
9894 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
9895 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
9896 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
9897 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
9898 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
9899 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
9900 }
9901
9902 /**
9903 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
9904 * @adap: the adapter
9905 * @viid: the VI id
9906 * @mac: the MAC address
9907 * @mask: the mask
9908 * @vni: the VNI id for the tunnel protocol
9909 * @vni_mask: mask for the VNI id
9910 * @dip_hit: to enable DIP match for the MPS entry
9911 * @lookup_type: MAC address for inner (1) or outer (0) header
9912 * @sleep_ok: call is allowed to sleep
9913 *
9914 * Allocates an MPS entry with specified MAC address and VNI value.
9915 *
9916 * Returns a negative error number or the allocated index for this mac.
9917 */
t4_alloc_encap_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int vni,unsigned int vni_mask,u8 dip_hit,u8 lookup_type,bool sleep_ok)9918 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
9919 const u8 *addr, const u8 *mask, unsigned int vni,
9920 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
9921 bool sleep_ok)
9922 {
9923 struct fw_vi_mac_cmd c;
9924 struct fw_vi_mac_vni *p = c.u.exact_vni;
9925 int ret = 0;
9926 u32 val;
9927
9928 memset(&c, 0, sizeof(c));
9929 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
9930 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
9931 V_FW_VI_MAC_CMD_VIID(viid));
9932 val = V_FW_CMD_LEN16(1) |
9933 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI);
9934 c.freemacs_to_len16 = cpu_to_be32(val);
9935 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
9936 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
9937 memcpy(p->macaddr, addr, sizeof(p->macaddr));
9938 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
9939
9940 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) |
9941 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) |
9942 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type));
9943 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask));
9944
9945 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
9946 if (ret == 0)
9947 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
9948 return ret;
9949 }
9950
9951 /**
9952 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
9953 * @adap: the adapter
9954 * @viid: the VI id
9955 * @mac: the MAC address
9956 * @mask: the mask
9957 * @idx: index at which to add this entry
9958 * @port_id: the port index
9959 * @lookup_type: MAC address for inner (1) or outer (0) header
9960 * @sleep_ok: call is allowed to sleep
9961 *
9962 * Adds the mac entry at the specified index using raw mac interface.
9963 *
9964 * Returns a negative error number or the allocated index for this mac.
9965 */
t4_alloc_raw_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int idx,u8 lookup_type,u8 port_id,bool sleep_ok)9966 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
9967 const u8 *addr, const u8 *mask, unsigned int idx,
9968 u8 lookup_type, u8 port_id, bool sleep_ok)
9969 {
9970 int ret = 0;
9971 struct fw_vi_mac_cmd c;
9972 struct fw_vi_mac_raw *p = &c.u.raw;
9973 u32 val;
9974
9975 memset(&c, 0, sizeof(c));
9976 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
9977 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
9978 V_FW_VI_MAC_CMD_VIID(viid));
9979 val = V_FW_CMD_LEN16(1) |
9980 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
9981 c.freemacs_to_len16 = cpu_to_be32(val);
9982
9983 /* Specify that this is an inner mac address */
9984 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx));
9985
9986 /* Lookup Type. Outer header: 0, Inner header: 1 */
9987 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
9988 V_DATAPORTNUM(port_id));
9989 /* Lookup mask and port mask */
9990 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
9991 V_DATAPORTNUM(M_DATAPORTNUM));
9992
9993 /* Copy the address and the mask */
9994 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
9995 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
9996
9997 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
9998 if (ret == 0) {
9999 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd));
10000 if (ret != idx)
10001 ret = -ENOMEM;
10002 }
10003
10004 return ret;
10005 }
10006
10007 /**
10008 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
10009 * @adap: the adapter
10010 * @mbox: mailbox to use for the FW command
10011 * @viid: the VI id
10012 * @free: if true any existing filters for this VI id are first removed
10013 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
10014 * @addr: the MAC address(es)
10015 * @idx: where to store the index of each allocated filter
10016 * @hash: pointer to hash address filter bitmap
10017 * @sleep_ok: call is allowed to sleep
10018 *
10019 * Allocates an exact-match filter for each of the supplied addresses and
10020 * sets it to the corresponding address. If @idx is not %NULL it should
10021 * have at least @naddr entries, each of which will be set to the index of
10022 * the filter allocated for the corresponding MAC address. If a filter
10023 * could not be allocated for an address its index is set to 0xffff.
10024 * If @hash is not %NULL addresses that fail to allocate an exact filter
10025 * are hashed and update the hash filter bitmap pointed at by @hash.
10026 *
10027 * Returns a negative error number or the number of filters allocated.
10028 */
t4_alloc_mac_filt(struct adapter * adap,unsigned int mbox,unsigned int viid,bool free,unsigned int naddr,const u8 ** addr,u16 * idx,u64 * hash,bool sleep_ok)10029 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
10030 unsigned int viid, bool free, unsigned int naddr,
10031 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
10032 {
10033 int offset, ret = 0;
10034 struct fw_vi_mac_cmd c;
10035 unsigned int nfilters = 0;
10036 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
10037 unsigned int rem = naddr;
10038
10039 if (naddr > max_naddr)
10040 return -EINVAL;
10041
10042 for (offset = 0; offset < naddr ; /**/) {
10043 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
10044 ? rem
10045 : ARRAY_SIZE(c.u.exact));
10046 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
10047 u.exact[fw_naddr]), 16);
10048 struct fw_vi_mac_exact *p;
10049 int i;
10050
10051 memset(&c, 0, sizeof(c));
10052 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
10053 F_FW_CMD_REQUEST |
10054 F_FW_CMD_WRITE |
10055 V_FW_CMD_EXEC(free) |
10056 V_FW_VI_MAC_CMD_VIID(viid));
10057 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
10058 V_FW_CMD_LEN16(len16));
10059
10060 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
10061 p->valid_to_idx =
10062 cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
10063 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
10064 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
10065 }
10066
10067 /*
10068 * It's okay if we run out of space in our MAC address arena.
10069 * Some of the addresses we submit may get stored so we need
10070 * to run through the reply to see what the results were ...
10071 */
10072 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
10073 if (ret && ret != -FW_ENOMEM)
10074 break;
10075
10076 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
10077 u16 index = G_FW_VI_MAC_CMD_IDX(
10078 be16_to_cpu(p->valid_to_idx));
10079
10080 if (idx)
10081 idx[offset+i] = (index >= max_naddr
10082 ? 0xffff
10083 : index);
10084 if (index < max_naddr)
10085 nfilters++;
10086 else if (hash)
10087 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
10088 }
10089
10090 free = false;
10091 offset += fw_naddr;
10092 rem -= fw_naddr;
10093 }
10094
10095 if (ret == 0 || ret == -FW_ENOMEM)
10096 ret = nfilters;
10097 return ret;
10098 }
10099
10100 /**
10101 * t4_free_encap_mac_filt - frees MPS entry at given index
10102 * @adap: the adapter
10103 * @viid: the VI id
10104 * @idx: index of MPS entry to be freed
10105 * @sleep_ok: call is allowed to sleep
10106 *
10107 * Frees the MPS entry at supplied index
10108 *
10109 * Returns a negative error number or zero on success
10110 */
t4_free_encap_mac_filt(struct adapter * adap,unsigned int viid,int idx,bool sleep_ok)10111 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
10112 int idx, bool sleep_ok)
10113 {
10114 struct fw_vi_mac_exact *p;
10115 struct fw_vi_mac_cmd c;
10116 u8 addr[] = {0,0,0,0,0,0};
10117 int ret = 0;
10118 u32 exact;
10119
10120 memset(&c, 0, sizeof(c));
10121 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
10122 F_FW_CMD_REQUEST |
10123 F_FW_CMD_WRITE |
10124 V_FW_CMD_EXEC(0) |
10125 V_FW_VI_MAC_CMD_VIID(viid));
10126 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC);
10127 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
10128 exact |
10129 V_FW_CMD_LEN16(1));
10130 p = c.u.exact;
10131 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
10132 V_FW_VI_MAC_CMD_IDX(idx));
10133 memcpy(p->macaddr, addr, sizeof(p->macaddr));
10134
10135 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
10136 return ret;
10137 }
10138
10139 /**
10140 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
10141 * @adap: the adapter
10142 * @viid: the VI id
10143 * @addr: the MAC address
10144 * @mask: the mask
10145 * @idx: index of the entry in mps tcam
10146 * @lookup_type: MAC address for inner (1) or outer (0) header
10147 * @port_id: the port index
10148 * @sleep_ok: call is allowed to sleep
10149 *
10150 * Removes the mac entry at the specified index using raw mac interface.
10151 *
10152 * Returns a negative error number on failure.
10153 */
t4_free_raw_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int idx,u8 lookup_type,u8 port_id,bool sleep_ok)10154 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
10155 const u8 *addr, const u8 *mask, unsigned int idx,
10156 u8 lookup_type, u8 port_id, bool sleep_ok)
10157 {
10158 struct fw_vi_mac_cmd c;
10159 struct fw_vi_mac_raw *p = &c.u.raw;
10160 u32 raw;
10161
10162 memset(&c, 0, sizeof(c));
10163 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
10164 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
10165 V_FW_CMD_EXEC(0) |
10166 V_FW_VI_MAC_CMD_VIID(viid));
10167 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
10168 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
10169 raw |
10170 V_FW_CMD_LEN16(1));
10171
10172 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) |
10173 FW_VI_MAC_ID_BASED_FREE);
10174
10175 /* Lookup Type. Outer header: 0, Inner header: 1 */
10176 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
10177 V_DATAPORTNUM(port_id));
10178 /* Lookup mask and port mask */
10179 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
10180 V_DATAPORTNUM(M_DATAPORTNUM));
10181
10182 /* Copy the address and the mask */
10183 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
10184 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
10185
10186 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
10187 }
10188
10189 /**
10190 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
10191 * @adap: the adapter
10192 * @mbox: mailbox to use for the FW command
10193 * @viid: the VI id
10194 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
10195 * @addr: the MAC address(es)
10196 * @sleep_ok: call is allowed to sleep
10197 *
10198 * Frees the exact-match filter for each of the supplied addresses
10199 *
10200 * Returns a negative error number or the number of filters freed.
10201 */
t4_free_mac_filt(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int naddr,const u8 ** addr,bool sleep_ok)10202 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
10203 unsigned int viid, unsigned int naddr,
10204 const u8 **addr, bool sleep_ok)
10205 {
10206 int offset, ret = 0;
10207 struct fw_vi_mac_cmd c;
10208 unsigned int nfilters = 0;
10209 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
10210 unsigned int rem = naddr;
10211
10212 if (naddr > max_naddr)
10213 return -EINVAL;
10214
10215 for (offset = 0; offset < (int)naddr ; /**/) {
10216 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
10217 ? rem
10218 : ARRAY_SIZE(c.u.exact));
10219 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
10220 u.exact[fw_naddr]), 16);
10221 struct fw_vi_mac_exact *p;
10222 int i;
10223
10224 memset(&c, 0, sizeof(c));
10225 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
10226 F_FW_CMD_REQUEST |
10227 F_FW_CMD_WRITE |
10228 V_FW_CMD_EXEC(0) |
10229 V_FW_VI_MAC_CMD_VIID(viid));
10230 c.freemacs_to_len16 =
10231 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
10232 V_FW_CMD_LEN16(len16));
10233
10234 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
10235 p->valid_to_idx = cpu_to_be16(
10236 F_FW_VI_MAC_CMD_VALID |
10237 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
10238 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
10239 }
10240
10241 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
10242 if (ret)
10243 break;
10244
10245 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
10246 u16 index = G_FW_VI_MAC_CMD_IDX(
10247 be16_to_cpu(p->valid_to_idx));
10248
10249 if (index < max_naddr)
10250 nfilters++;
10251 }
10252
10253 offset += fw_naddr;
10254 rem -= fw_naddr;
10255 }
10256
10257 if (ret == 0)
10258 ret = nfilters;
10259 return ret;
10260 }
10261
10262 /**
10263 * t4_change_mac - modifies the exact-match filter for a MAC address
10264 * @adap: the adapter
10265 * @mbox: mailbox to use for the FW command
10266 * @viid: the VI id
10267 * @idx: index of existing filter for old value of MAC address, or -1
10268 * @addr: the new MAC address value
10269 * @persist: whether a new MAC allocation should be persistent
10270 * @smt_idx: add MAC to SMT and return its index, or NULL
10271 *
10272 * Modifies an exact-match filter and sets it to the new MAC address if
10273 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
10274 * latter case the address is added persistently if @persist is %true.
10275 *
10276 * Note that in general it is not possible to modify the value of a given
10277 * filter so the generic way to modify an address filter is to free the one
10278 * being used by the old address value and allocate a new filter for the
10279 * new address value.
10280 *
10281 * Returns a negative error number or the index of the filter with the new
10282 * MAC value. Note that this index may differ from @idx.
10283 */
t4_change_mac(struct adapter * adap,unsigned int mbox,unsigned int viid,int idx,const u8 * addr,bool persist,uint16_t * smt_idx)10284 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
10285 int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
10286 {
10287 int ret, mode;
10288 struct fw_vi_mac_cmd c;
10289 struct fw_vi_mac_exact *p = c.u.exact;
10290 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
10291
10292 if (idx < 0) /* new allocation */
10293 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
10294 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
10295
10296 memset(&c, 0, sizeof(c));
10297 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
10298 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
10299 V_FW_VI_MAC_CMD_VIID(viid));
10300 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
10301 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
10302 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
10303 V_FW_VI_MAC_CMD_IDX(idx));
10304 memcpy(p->macaddr, addr, sizeof(p->macaddr));
10305
10306 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10307 if (ret == 0) {
10308 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
10309 if (ret >= max_mac_addr)
10310 ret = -ENOMEM;
10311 if (smt_idx) {
10312 if (adap->params.viid_smt_extn_support)
10313 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
10314 else {
10315 if (chip_id(adap) <= CHELSIO_T5)
10316 *smt_idx = (viid & M_FW_VIID_VIN) << 1;
10317 else
10318 *smt_idx = viid & M_FW_VIID_VIN;
10319 }
10320 }
10321 }
10322 return ret;
10323 }
10324
10325 /**
10326 * t4_set_addr_hash - program the MAC inexact-match hash filter
10327 * @adap: the adapter
10328 * @mbox: mailbox to use for the FW command
10329 * @viid: the VI id
10330 * @ucast: whether the hash filter should also match unicast addresses
10331 * @vec: the value to be written to the hash filter
10332 * @sleep_ok: call is allowed to sleep
10333 *
10334 * Sets the 64-bit inexact-match hash filter for a virtual interface.
10335 */
t4_set_addr_hash(struct adapter * adap,unsigned int mbox,unsigned int viid,bool ucast,u64 vec,bool sleep_ok)10336 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
10337 bool ucast, u64 vec, bool sleep_ok)
10338 {
10339 struct fw_vi_mac_cmd c;
10340 u32 val;
10341
10342 memset(&c, 0, sizeof(c));
10343 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
10344 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
10345 V_FW_VI_ENABLE_CMD_VIID(viid));
10346 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
10347 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
10348 c.freemacs_to_len16 = cpu_to_be32(val);
10349 c.u.hash.hashvec = cpu_to_be64(vec);
10350 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
10351 }
10352
10353 /**
10354 * t4_enable_vi_params - enable/disable a virtual interface
10355 * @adap: the adapter
10356 * @mbox: mailbox to use for the FW command
10357 * @viid: the VI id
10358 * @rx_en: 1=enable Rx, 0=disable Rx
10359 * @tx_en: 1=enable Tx, 0=disable Tx
10360 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
10361 *
10362 * Enables/disables a virtual interface. Note that setting DCB Enable
10363 * only makes sense when enabling a Virtual Interface ...
10364 */
t4_enable_vi_params(struct adapter * adap,unsigned int mbox,unsigned int viid,bool rx_en,bool tx_en,bool dcb_en)10365 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
10366 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
10367 {
10368 struct fw_vi_enable_cmd c;
10369
10370 memset(&c, 0, sizeof(c));
10371 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
10372 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
10373 V_FW_VI_ENABLE_CMD_VIID(viid));
10374 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
10375 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
10376 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
10377 FW_LEN16(c));
10378 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
10379 }
10380
10381 /**
10382 * t4_enable_vi - enable/disable a virtual interface
10383 * @adap: the adapter
10384 * @mbox: mailbox to use for the FW command
10385 * @viid: the VI id
10386 * @rx_en: 1=enable Rx, 0=disable Rx
10387 * @tx_en: 1=enable Tx, 0=disable Tx
10388 *
10389 * Enables/disables a virtual interface. Note that setting DCB Enable
10390 * only makes sense when enabling a Virtual Interface ...
10391 */
t4_enable_vi(struct adapter * adap,unsigned int mbox,unsigned int viid,bool rx_en,bool tx_en)10392 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
10393 bool rx_en, bool tx_en)
10394 {
10395 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
10396 }
10397
10398 /**
10399 * t4_identify_port - identify a VI's port by blinking its LED
10400 * @adap: the adapter
10401 * @mbox: mailbox to use for the FW command
10402 * @viid: the VI id
10403 * @nblinks: how many times to blink LED at 2.5 Hz
10404 *
10405 * Identifies a VI's port by blinking its LED.
10406 */
t4_identify_port(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int nblinks)10407 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
10408 unsigned int nblinks)
10409 {
10410 struct fw_vi_enable_cmd c;
10411
10412 memset(&c, 0, sizeof(c));
10413 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
10414 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
10415 V_FW_VI_ENABLE_CMD_VIID(viid));
10416 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
10417 c.blinkdur = cpu_to_be16(nblinks);
10418 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
10419 }
10420
10421 /**
10422 * t4_iq_stop - stop an ingress queue and its FLs
10423 * @adap: the adapter
10424 * @mbox: mailbox to use for the FW command
10425 * @pf: the PF owning the queues
10426 * @vf: the VF owning the queues
10427 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
10428 * @iqid: ingress queue id
10429 * @fl0id: FL0 queue id or 0xffff if no attached FL0
10430 * @fl1id: FL1 queue id or 0xffff if no attached FL1
10431 *
10432 * Stops an ingress queue and its associated FLs, if any. This causes
10433 * any current or future data/messages destined for these queues to be
10434 * tossed.
10435 */
t4_iq_stop(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int iqtype,unsigned int iqid,unsigned int fl0id,unsigned int fl1id)10436 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
10437 unsigned int vf, unsigned int iqtype, unsigned int iqid,
10438 unsigned int fl0id, unsigned int fl1id)
10439 {
10440 struct fw_iq_cmd c;
10441
10442 memset(&c, 0, sizeof(c));
10443 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
10444 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
10445 V_FW_IQ_CMD_VFN(vf));
10446 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
10447 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
10448 c.iqid = cpu_to_be16(iqid);
10449 c.fl0id = cpu_to_be16(fl0id);
10450 c.fl1id = cpu_to_be16(fl1id);
10451 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
10452 }
10453
10454 /**
10455 * t4_iq_free - free an ingress queue and its FLs
10456 * @adap: the adapter
10457 * @mbox: mailbox to use for the FW command
10458 * @pf: the PF owning the queues
10459 * @vf: the VF owning the queues
10460 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
10461 * @iqid: ingress queue id
10462 * @fl0id: FL0 queue id or 0xffff if no attached FL0
10463 * @fl1id: FL1 queue id or 0xffff if no attached FL1
10464 *
10465 * Frees an ingress queue and its associated FLs, if any.
10466 */
t4_iq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int iqtype,unsigned int iqid,unsigned int fl0id,unsigned int fl1id)10467 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
10468 unsigned int vf, unsigned int iqtype, unsigned int iqid,
10469 unsigned int fl0id, unsigned int fl1id)
10470 {
10471 struct fw_iq_cmd c;
10472
10473 memset(&c, 0, sizeof(c));
10474 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
10475 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
10476 V_FW_IQ_CMD_VFN(vf));
10477 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
10478 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
10479 c.iqid = cpu_to_be16(iqid);
10480 c.fl0id = cpu_to_be16(fl0id);
10481 c.fl1id = cpu_to_be16(fl1id);
10482 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
10483 }
10484
10485 /**
10486 * t4_eth_eq_stop - stop an Ethernet egress queue
10487 * @adap: the adapter
10488 * @mbox: mailbox to use for the FW command
10489 * @pf: the PF owning the queues
10490 * @vf: the VF owning the queues
10491 * @eqid: egress queue id
10492 *
10493 * Stops an Ethernet egress queue. The queue can be reinitialized or
10494 * freed but is not otherwise functional after this call.
10495 */
t4_eth_eq_stop(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)10496 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
10497 unsigned int vf, unsigned int eqid)
10498 {
10499 struct fw_eq_eth_cmd c;
10500
10501 memset(&c, 0, sizeof(c));
10502 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
10503 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
10504 V_FW_EQ_ETH_CMD_PFN(pf) |
10505 V_FW_EQ_ETH_CMD_VFN(vf));
10506 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c));
10507 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
10508 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
10509 }
10510
10511 /**
10512 * t4_eth_eq_free - free an Ethernet egress queue
10513 * @adap: the adapter
10514 * @mbox: mailbox to use for the FW command
10515 * @pf: the PF owning the queue
10516 * @vf: the VF owning the queue
10517 * @eqid: egress queue id
10518 *
10519 * Frees an Ethernet egress queue.
10520 */
t4_eth_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)10521 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
10522 unsigned int vf, unsigned int eqid)
10523 {
10524 struct fw_eq_eth_cmd c;
10525
10526 memset(&c, 0, sizeof(c));
10527 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
10528 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
10529 V_FW_EQ_ETH_CMD_PFN(pf) |
10530 V_FW_EQ_ETH_CMD_VFN(vf));
10531 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
10532 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
10533 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
10534 }
10535
10536 /**
10537 * t4_ctrl_eq_free - free a control egress queue
10538 * @adap: the adapter
10539 * @mbox: mailbox to use for the FW command
10540 * @pf: the PF owning the queue
10541 * @vf: the VF owning the queue
10542 * @eqid: egress queue id
10543 *
10544 * Frees a control egress queue.
10545 */
t4_ctrl_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)10546 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
10547 unsigned int vf, unsigned int eqid)
10548 {
10549 struct fw_eq_ctrl_cmd c;
10550
10551 memset(&c, 0, sizeof(c));
10552 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
10553 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
10554 V_FW_EQ_CTRL_CMD_PFN(pf) |
10555 V_FW_EQ_CTRL_CMD_VFN(vf));
10556 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
10557 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
10558 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
10559 }
10560
10561 /**
10562 * t4_ofld_eq_free - free an offload egress queue
10563 * @adap: the adapter
10564 * @mbox: mailbox to use for the FW command
10565 * @pf: the PF owning the queue
10566 * @vf: the VF owning the queue
10567 * @eqid: egress queue id
10568 *
10569 * Frees a control egress queue.
10570 */
t4_ofld_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)10571 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
10572 unsigned int vf, unsigned int eqid)
10573 {
10574 struct fw_eq_ofld_cmd c;
10575
10576 memset(&c, 0, sizeof(c));
10577 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
10578 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
10579 V_FW_EQ_OFLD_CMD_PFN(pf) |
10580 V_FW_EQ_OFLD_CMD_VFN(vf));
10581 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
10582 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
10583 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
10584 }
10585
10586 /**
10587 * t4_link_down_rc_str - return a string for a Link Down Reason Code
10588 * @link_down_rc: Link Down Reason Code
10589 *
10590 * Returns a string representation of the Link Down Reason Code.
10591 */
t4_link_down_rc_str(unsigned char link_down_rc)10592 const char *t4_link_down_rc_str(unsigned char link_down_rc)
10593 {
10594 static const char *reason[] = {
10595 "Link Down",
10596 "Remote Fault",
10597 "Auto-negotiation Failure",
10598 "Reserved3",
10599 "Insufficient Airflow",
10600 "Unable To Determine Reason",
10601 "No RX Signal Detected",
10602 "Reserved7",
10603 };
10604
10605 if (link_down_rc >= ARRAY_SIZE(reason))
10606 return "Bad Reason Code";
10607
10608 return reason[link_down_rc];
10609 }
10610
10611 /*
10612 * Return the highest speed set in the port capabilities, in Mb/s.
10613 */
fwcap_to_speed(uint32_t caps)10614 unsigned int fwcap_to_speed(uint32_t caps)
10615 {
10616 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
10617 do { \
10618 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
10619 return __speed; \
10620 } while (0)
10621
10622 TEST_SPEED_RETURN(400G, 400000);
10623 TEST_SPEED_RETURN(200G, 200000);
10624 TEST_SPEED_RETURN(100G, 100000);
10625 TEST_SPEED_RETURN(50G, 50000);
10626 TEST_SPEED_RETURN(40G, 40000);
10627 TEST_SPEED_RETURN(25G, 25000);
10628 TEST_SPEED_RETURN(10G, 10000);
10629 TEST_SPEED_RETURN(1G, 1000);
10630 TEST_SPEED_RETURN(100M, 100);
10631
10632 #undef TEST_SPEED_RETURN
10633
10634 return 0;
10635 }
10636
10637 /*
10638 * Return the port capabilities bit for the given speed, which is in Mb/s.
10639 */
speed_to_fwcap(unsigned int speed)10640 uint32_t speed_to_fwcap(unsigned int speed)
10641 {
10642 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
10643 do { \
10644 if (speed == __speed) \
10645 return FW_PORT_CAP32_SPEED_##__caps_speed; \
10646 } while (0)
10647
10648 TEST_SPEED_RETURN(400G, 400000);
10649 TEST_SPEED_RETURN(200G, 200000);
10650 TEST_SPEED_RETURN(100G, 100000);
10651 TEST_SPEED_RETURN(50G, 50000);
10652 TEST_SPEED_RETURN(40G, 40000);
10653 TEST_SPEED_RETURN(25G, 25000);
10654 TEST_SPEED_RETURN(10G, 10000);
10655 TEST_SPEED_RETURN(1G, 1000);
10656 TEST_SPEED_RETURN(100M, 100);
10657
10658 #undef TEST_SPEED_RETURN
10659
10660 return 0;
10661 }
10662
10663 /*
10664 * Return the port capabilities bit for the highest speed in the capabilities.
10665 */
fwcap_top_speed(uint32_t caps)10666 uint32_t fwcap_top_speed(uint32_t caps)
10667 {
10668 #define TEST_SPEED_RETURN(__caps_speed) \
10669 do { \
10670 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
10671 return FW_PORT_CAP32_SPEED_##__caps_speed; \
10672 } while (0)
10673
10674 TEST_SPEED_RETURN(400G);
10675 TEST_SPEED_RETURN(200G);
10676 TEST_SPEED_RETURN(100G);
10677 TEST_SPEED_RETURN(50G);
10678 TEST_SPEED_RETURN(40G);
10679 TEST_SPEED_RETURN(25G);
10680 TEST_SPEED_RETURN(10G);
10681 TEST_SPEED_RETURN(1G);
10682 TEST_SPEED_RETURN(100M);
10683
10684 #undef TEST_SPEED_RETURN
10685
10686 return 0;
10687 }
10688
10689 /**
10690 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
10691 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
10692 *
10693 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
10694 * 32-bit Port Capabilities value.
10695 */
lstatus_to_fwcap(u32 lstatus)10696 static uint32_t lstatus_to_fwcap(u32 lstatus)
10697 {
10698 uint32_t linkattr = 0;
10699
10700 /*
10701 * Unfortunately the format of the Link Status in the old
10702 * 16-bit Port Information message isn't the same as the
10703 * 16-bit Port Capabilities bitfield used everywhere else ...
10704 */
10705 if (lstatus & F_FW_PORT_CMD_RXPAUSE)
10706 linkattr |= FW_PORT_CAP32_FC_RX;
10707 if (lstatus & F_FW_PORT_CMD_TXPAUSE)
10708 linkattr |= FW_PORT_CAP32_FC_TX;
10709 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
10710 linkattr |= FW_PORT_CAP32_SPEED_100M;
10711 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
10712 linkattr |= FW_PORT_CAP32_SPEED_1G;
10713 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
10714 linkattr |= FW_PORT_CAP32_SPEED_10G;
10715 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
10716 linkattr |= FW_PORT_CAP32_SPEED_25G;
10717 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
10718 linkattr |= FW_PORT_CAP32_SPEED_40G;
10719 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
10720 linkattr |= FW_PORT_CAP32_SPEED_100G;
10721
10722 return linkattr;
10723 }
10724
10725 /*
10726 * Updates all fields owned by the common code in port_info and link_config
10727 * based on information provided by the firmware. Does not touch any
10728 * requested_* field.
10729 */
handle_port_info(struct port_info * pi,const struct fw_port_cmd * p,enum fw_port_action action,bool * mod_changed,bool * link_changed)10730 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
10731 enum fw_port_action action, bool *mod_changed, bool *link_changed)
10732 {
10733 struct link_config old_lc, *lc = &pi->link_cfg;
10734 unsigned char fc;
10735 u32 stat, linkattr;
10736 int old_ptype, old_mtype;
10737
10738 old_ptype = pi->port_type;
10739 old_mtype = pi->mod_type;
10740 old_lc = *lc;
10741 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
10742 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
10743
10744 pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
10745 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
10746 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
10747 G_FW_PORT_CMD_MDIOADDR(stat) : -1;
10748
10749 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap));
10750 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap));
10751 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap));
10752 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
10753 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
10754
10755 linkattr = lstatus_to_fwcap(stat);
10756 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) {
10757 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32);
10758
10759 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat);
10760 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat);
10761 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ?
10762 G_FW_PORT_CMD_MDIOADDR32(stat) : -1;
10763
10764 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32);
10765 lc->acaps = be32_to_cpu(p->u.info32.acaps32);
10766 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32);
10767 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0;
10768 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat);
10769
10770 linkattr = be32_to_cpu(p->u.info32.linkattr32);
10771 } else {
10772 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action);
10773 return;
10774 }
10775
10776 lc->speed = fwcap_to_speed(linkattr);
10777 lc->fec = fwcap_to_fec(linkattr, true);
10778
10779 fc = 0;
10780 if (linkattr & FW_PORT_CAP32_FC_RX)
10781 fc |= PAUSE_RX;
10782 if (linkattr & FW_PORT_CAP32_FC_TX)
10783 fc |= PAUSE_TX;
10784 lc->fc = fc;
10785
10786 if (mod_changed != NULL)
10787 *mod_changed = false;
10788 if (link_changed != NULL)
10789 *link_changed = false;
10790 if (old_ptype != pi->port_type || old_mtype != pi->mod_type ||
10791 old_lc.pcaps != lc->pcaps) {
10792 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE)
10793 lc->fec_hint = fwcap_to_fec(lc->acaps, true);
10794 if (mod_changed != NULL)
10795 *mod_changed = true;
10796 }
10797 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed ||
10798 old_lc.fec != lc->fec || old_lc.fc != lc->fc) {
10799 if (link_changed != NULL)
10800 *link_changed = true;
10801 }
10802 }
10803
10804 /**
10805 * t4_update_port_info - retrieve and update port information if changed
10806 * @pi: the port_info
10807 *
10808 * We issue a Get Port Information Command to the Firmware and, if
10809 * successful, we check to see if anything is different from what we
10810 * last recorded and update things accordingly.
10811 */
t4_update_port_info(struct port_info * pi)10812 int t4_update_port_info(struct port_info *pi)
10813 {
10814 struct adapter *sc = pi->adapter;
10815 struct fw_port_cmd cmd;
10816 enum fw_port_action action;
10817 int ret;
10818
10819 memset(&cmd, 0, sizeof(cmd));
10820 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
10821 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10822 V_FW_PORT_CMD_PORTID(pi->hw_port));
10823 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
10824 FW_PORT_ACTION_GET_PORT_INFO;
10825 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
10826 FW_LEN16(cmd));
10827 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
10828 if (ret)
10829 return ret;
10830
10831 handle_port_info(pi, &cmd, action, NULL, NULL);
10832 return 0;
10833 }
10834
10835 /**
10836 * t4_handle_fw_rpl - process a FW reply message
10837 * @adap: the adapter
10838 * @rpl: start of the FW message
10839 *
10840 * Processes a FW message, such as link state change messages.
10841 */
t4_handle_fw_rpl(struct adapter * adap,const __be64 * rpl)10842 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
10843 {
10844 u8 opcode = *(const u8 *)rpl;
10845 const struct fw_port_cmd *p = (const void *)rpl;
10846 enum fw_port_action action =
10847 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
10848 bool mod_changed, link_changed;
10849
10850 if (opcode == FW_PORT_CMD &&
10851 (action == FW_PORT_ACTION_GET_PORT_INFO ||
10852 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
10853 /* link/module state change message */
10854 int hw_port = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
10855 int port_id = adap->port_map[hw_port];
10856 struct port_info *pi;
10857
10858 MPASS(port_id >= 0 && port_id < adap->params.nports);
10859 pi = adap->port[port_id];
10860 PORT_LOCK(pi);
10861 handle_port_info(pi, p, action, &mod_changed, &link_changed);
10862 PORT_UNLOCK(pi);
10863 if (mod_changed)
10864 t4_os_portmod_changed(pi);
10865 if (link_changed) {
10866 PORT_LOCK(pi);
10867 t4_os_link_changed(pi);
10868 PORT_UNLOCK(pi);
10869 }
10870 } else {
10871 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
10872 return -EINVAL;
10873 }
10874 return 0;
10875 }
10876
10877 /**
10878 * get_pci_mode - determine a card's PCI mode
10879 * @adapter: the adapter
10880 * @p: where to store the PCI settings
10881 *
10882 * Determines a card's PCI mode and associated parameters, such as speed
10883 * and width.
10884 */
get_pci_mode(struct adapter * adapter,struct pci_params * p)10885 static void get_pci_mode(struct adapter *adapter,
10886 struct pci_params *p)
10887 {
10888 u16 val;
10889 u32 pcie_cap;
10890
10891 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
10892 if (pcie_cap) {
10893 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
10894 p->speed = val & PCI_EXP_LNKSTA_CLS;
10895 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
10896 }
10897 }
10898
10899 struct flash_desc {
10900 u32 vendor_and_model_id;
10901 u32 size_mb;
10902 };
10903
t4_get_flash_params(struct adapter * adapter)10904 int t4_get_flash_params(struct adapter *adapter)
10905 {
10906 /*
10907 * Table for non-standard supported Flash parts. Note, all Flash
10908 * parts must have 64KB sectors.
10909 */
10910 static struct flash_desc supported_flash[] = {
10911 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
10912 };
10913
10914 int ret;
10915 u32 flashid = 0;
10916 unsigned int part, manufacturer;
10917 unsigned int density, size = 0;
10918
10919
10920 /*
10921 * Issue a Read ID Command to the Flash part. We decode supported
10922 * Flash parts and their sizes from this. There's a newer Query
10923 * Command which can retrieve detailed geometry information but many
10924 * Flash parts don't support it.
10925 */
10926 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
10927 if (!ret)
10928 ret = sf1_read(adapter, 3, 0, 1, &flashid);
10929 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
10930 if (ret < 0)
10931 return ret;
10932
10933 /*
10934 * Check to see if it's one of our non-standard supported Flash parts.
10935 */
10936 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
10937 if (supported_flash[part].vendor_and_model_id == flashid) {
10938 adapter->params.sf_size =
10939 supported_flash[part].size_mb;
10940 adapter->params.sf_nsec =
10941 adapter->params.sf_size / SF_SEC_SIZE;
10942 goto found;
10943 }
10944
10945 /*
10946 * Decode Flash part size. The code below looks repetative with
10947 * common encodings, but that's not guaranteed in the JEDEC
10948 * specification for the Read JADEC ID command. The only thing that
10949 * we're guaranteed by the JADEC specification is where the
10950 * Manufacturer ID is in the returned result. After that each
10951 * Manufacturer ~could~ encode things completely differently.
10952 * Note, all Flash parts must have 64KB sectors.
10953 */
10954 manufacturer = flashid & 0xff;
10955 switch (manufacturer) {
10956 case 0x20: /* Micron/Numonix */
10957 /*
10958 * This Density -> Size decoding table is taken from Micron
10959 * Data Sheets.
10960 */
10961 density = (flashid >> 16) & 0xff;
10962 switch (density) {
10963 case 0x14: size = 1 << 20; break; /* 1MB */
10964 case 0x15: size = 1 << 21; break; /* 2MB */
10965 case 0x16: size = 1 << 22; break; /* 4MB */
10966 case 0x17: size = 1 << 23; break; /* 8MB */
10967 case 0x18: size = 1 << 24; break; /* 16MB */
10968 case 0x19: size = 1 << 25; break; /* 32MB */
10969 case 0x20: size = 1 << 26; break; /* 64MB */
10970 case 0x21: size = 1 << 27; break; /* 128MB */
10971 case 0x22: size = 1 << 28; break; /* 256MB */
10972 }
10973 break;
10974
10975 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */
10976 /*
10977 * This Density -> Size decoding table is taken from ISSI
10978 * Data Sheets.
10979 */
10980 density = (flashid >> 16) & 0xff;
10981 switch (density) {
10982 case 0x16: size = 1 << 25; break; /* 32MB */
10983 case 0x17: size = 1 << 26; break; /* 64MB */
10984 }
10985 break;
10986
10987 case 0xc2: /* Macronix */
10988 /*
10989 * This Density -> Size decoding table is taken from Macronix
10990 * Data Sheets.
10991 */
10992 density = (flashid >> 16) & 0xff;
10993 switch (density) {
10994 case 0x17: size = 1 << 23; break; /* 8MB */
10995 case 0x18: size = 1 << 24; break; /* 16MB */
10996 }
10997 break;
10998
10999 case 0xef: /* Winbond */
11000 /*
11001 * This Density -> Size decoding table is taken from Winbond
11002 * Data Sheets.
11003 */
11004 density = (flashid >> 16) & 0xff;
11005 switch (density) {
11006 case 0x17: size = 1 << 23; break; /* 8MB */
11007 case 0x18: size = 1 << 24; break; /* 16MB */
11008 }
11009 break;
11010 }
11011
11012 /* If we didn't recognize the FLASH part, that's no real issue: the
11013 * Hardware/Software contract says that Hardware will _*ALWAYS*_ use a
11014 * FLASH part which has 64KB sectors and is at least 4MB or 16MB in
11015 * size, depending on the board.
11016 */
11017 if (size == 0) {
11018 size = chip_id(adapter) >= CHELSIO_T7 ? 16 : 4;
11019 CH_WARN(adapter, "Unknown Flash Part %#x, assuming %uMB\n",
11020 flashid, size);
11021 size <<= 20;
11022 }
11023
11024 /*
11025 * Store decoded Flash size and fall through into vetting code.
11026 */
11027 adapter->params.sf_size = size;
11028 adapter->params.sf_nsec = size / SF_SEC_SIZE;
11029
11030 found:
11031 /*
11032 * We should ~probably~ reject adapters with FLASHes which are too
11033 * small but we have some legacy FPGAs with small FLASHes that we'd
11034 * still like to use. So instead we emit a scary message ...
11035 */
11036 if (adapter->params.sf_size < FLASH_MIN_SIZE)
11037 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
11038 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
11039
11040 return 0;
11041 }
11042
set_pcie_completion_timeout(struct adapter * adapter,u8 range)11043 static void set_pcie_completion_timeout(struct adapter *adapter,
11044 u8 range)
11045 {
11046 u16 val;
11047 u32 pcie_cap;
11048
11049 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
11050 if (pcie_cap) {
11051 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
11052 val &= 0xfff0;
11053 val |= range ;
11054 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
11055 }
11056 }
11057
t4_get_chip_params(int chipid)11058 const struct chip_params *t4_get_chip_params(int chipid)
11059 {
11060 static const struct chip_params chip_params[] = {
11061 {
11062 /* T4 */
11063 .nchan = NCHAN,
11064 .pm_stats_cnt = PM_NSTATS,
11065 .cng_ch_bits_log = 2,
11066 .nsched_cls = 15,
11067 .cim_num_ibq = CIM_NUM_IBQ,
11068 .cim_num_obq = CIM_NUM_OBQ,
11069 .filter_opt_len = FILTER_OPT_LEN,
11070 .filter_num_opt = S_FT_LAST + 1,
11071 .mps_rplc_size = 128,
11072 .vfcount = 128,
11073 .sge_fl_db = F_DBPRIO,
11074 .sge_ctxt_size = SGE_CTXT_SIZE,
11075 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
11076 .rss_nentries = RSS_NENTRIES,
11077 .cim_la_size = CIMLA_SIZE,
11078 },
11079 {
11080 /* T5 */
11081 .nchan = NCHAN,
11082 .pm_stats_cnt = PM_NSTATS,
11083 .cng_ch_bits_log = 2,
11084 .nsched_cls = 16,
11085 .cim_num_ibq = CIM_NUM_IBQ,
11086 .cim_num_obq = CIM_NUM_OBQ_T5,
11087 .filter_opt_len = T5_FILTER_OPT_LEN,
11088 .filter_num_opt = S_FT_LAST + 1,
11089 .mps_rplc_size = 128,
11090 .vfcount = 128,
11091 .sge_fl_db = F_DBPRIO | F_DBTYPE,
11092 .sge_ctxt_size = SGE_CTXT_SIZE,
11093 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
11094 .rss_nentries = RSS_NENTRIES,
11095 .cim_la_size = CIMLA_SIZE,
11096 },
11097 {
11098 /* T6 */
11099 .nchan = T6_NCHAN,
11100 .pm_stats_cnt = T6_PM_NSTATS,
11101 .cng_ch_bits_log = 3,
11102 .nsched_cls = 16,
11103 .cim_num_ibq = CIM_NUM_IBQ,
11104 .cim_num_obq = CIM_NUM_OBQ_T5,
11105 .filter_opt_len = T5_FILTER_OPT_LEN,
11106 .filter_num_opt = S_FT_LAST + 1,
11107 .mps_rplc_size = 256,
11108 .vfcount = 256,
11109 .sge_fl_db = 0,
11110 .sge_ctxt_size = SGE_CTXT_SIZE,
11111 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
11112 .rss_nentries = T6_RSS_NENTRIES,
11113 .cim_la_size = CIMLA_SIZE_T6,
11114 },
11115 {
11116 /* T7 */
11117 .nchan = NCHAN,
11118 .pm_stats_cnt = T6_PM_NSTATS,
11119 .cng_ch_bits_log = 2,
11120 .nsched_cls = 16,
11121 .cim_num_ibq = CIM_NUM_IBQ_T7,
11122 .cim_num_obq = CIM_NUM_OBQ_T7,
11123 .filter_opt_len = T7_FILTER_OPT_LEN,
11124 .filter_num_opt = S_T7_FT_LAST + 1,
11125 .mps_rplc_size = 256,
11126 .vfcount = 256,
11127 .sge_fl_db = 0,
11128 .sge_ctxt_size = SGE_CTXT_SIZE_T7,
11129 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES * 3,
11130 .rss_nentries = T7_RSS_NENTRIES,
11131 .cim_la_size = CIMLA_SIZE_T6,
11132 },
11133 };
11134
11135 chipid -= CHELSIO_T4;
11136 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
11137 return NULL;
11138
11139 return &chip_params[chipid];
11140 }
11141
11142 /**
11143 * t4_prep_adapter - prepare SW and HW for operation
11144 * @adapter: the adapter
11145 * @buf: temporary space of at least VPD_LEN size provided by the caller.
11146 *
11147 * Initialize adapter SW state for the various HW modules, set initial
11148 * values for some adapter tunables, take PHYs out of reset, and
11149 * initialize the MDIO interface.
11150 */
t4_prep_adapter(struct adapter * adapter,u32 * buf)11151 int t4_prep_adapter(struct adapter *adapter, u32 *buf)
11152 {
11153 int ret;
11154 uint16_t device_id;
11155 uint32_t pl_rev;
11156
11157 get_pci_mode(adapter, &adapter->params.pci);
11158
11159 pl_rev = t4_read_reg(adapter, A_PL_REV);
11160 adapter->params.chipid = G_CHIPID(pl_rev);
11161 adapter->params.rev = G_REV(pl_rev);
11162 if (adapter->params.chipid == 0) {
11163 /* T4 did not have chipid in PL_REV (T5 onwards do) */
11164 adapter->params.chipid = CHELSIO_T4;
11165
11166 /* T4A1 chip is not supported */
11167 if (adapter->params.rev == 1) {
11168 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
11169 return -EINVAL;
11170 }
11171 }
11172
11173 adapter->chip_params = t4_get_chip_params(chip_id(adapter));
11174 if (adapter->chip_params == NULL)
11175 return -EINVAL;
11176
11177 adapter->params.pci.vpd_cap_addr =
11178 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
11179
11180 ret = t4_get_flash_params(adapter);
11181 if (ret < 0)
11182 return ret;
11183
11184 /* Cards with real ASICs have the chipid in the PCIe device id */
11185 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
11186 if (device_id >> 12 == chip_id(adapter))
11187 adapter->params.cim_la_size = adapter->chip_params->cim_la_size;
11188 else {
11189 /* FPGA */
11190 adapter->params.fpga = 1;
11191 adapter->params.cim_la_size = 2 * adapter->chip_params->cim_la_size;
11192 }
11193
11194 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf);
11195 if (ret < 0)
11196 return ret;
11197
11198 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
11199
11200 /*
11201 * Default port and clock for debugging in case we can't reach FW.
11202 */
11203 adapter->params.nports = 1;
11204 adapter->params.portvec = 1;
11205 adapter->params.vpd.cclk = 50000;
11206
11207 /* Set pci completion timeout value to 4 seconds. */
11208 set_pcie_completion_timeout(adapter, 0xd);
11209 return 0;
11210 }
11211
11212 /**
11213 * t4_shutdown_adapter - shut down adapter, host & wire
11214 * @adapter: the adapter
11215 *
11216 * Perform an emergency shutdown of the adapter and stop it from
11217 * continuing any further communication on the ports or DMA to the
11218 * host. This is typically used when the adapter and/or firmware
11219 * have crashed and we want to prevent any further accidental
11220 * communication with the rest of the world. This will also force
11221 * the port Link Status to go down -- if register writes work --
11222 * which should help our peers figure out that we're down.
11223 */
t4_shutdown_adapter(struct adapter * adapter)11224 int t4_shutdown_adapter(struct adapter *adapter)
11225 {
11226 int port;
11227 const bool bt = adapter->bt_map != 0;
11228
11229 t4_intr_disable(adapter);
11230 if (bt)
11231 t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000);
11232 for_each_port(adapter, port) {
11233 u32 a_port_cfg = is_t4(adapter) ?
11234 t4_port_reg(adapter, port, A_XGMAC_PORT_CFG) :
11235 t4_port_reg(adapter, port, A_MAC_PORT_CFG);
11236
11237 t4_write_reg(adapter, a_port_cfg,
11238 t4_read_reg(adapter, a_port_cfg)
11239 & ~V_SIGNAL_DET(1));
11240 if (!bt) {
11241 u32 hss_cfg0 = is_t4(adapter) ?
11242 t4_port_reg(adapter, port, A_XGMAC_PORT_HSS_CFG0) :
11243 t4_port_reg(adapter, port, A_MAC_PORT_HSS_CFG0);
11244 t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB |
11245 F_HSSPDWNPLLA | F_HSSPLLBYPB | F_HSSPLLBYPA,
11246 F_HSSPDWNPLLB | F_HSSPDWNPLLA | F_HSSPLLBYPB |
11247 F_HSSPLLBYPA);
11248 }
11249 }
11250 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
11251
11252 return 0;
11253 }
11254
11255 /**
11256 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
11257 * @adapter: the adapter
11258 * @qid: the Queue ID
11259 * @qtype: the Ingress or Egress type for @qid
11260 * @user: true if this request is for a user mode queue
11261 * @pbar2_qoffset: BAR2 Queue Offset
11262 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
11263 *
11264 * Returns the BAR2 SGE Queue Registers information associated with the
11265 * indicated Absolute Queue ID. These are passed back in return value
11266 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
11267 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
11268 *
11269 * This may return an error which indicates that BAR2 SGE Queue
11270 * registers aren't available. If an error is not returned, then the
11271 * following values are returned:
11272 *
11273 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
11274 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
11275 *
11276 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
11277 * require the "Inferred Queue ID" ability may be used. E.g. the
11278 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
11279 * then these "Inferred Queue ID" register may not be used.
11280 */
t4_bar2_sge_qregs(struct adapter * adapter,unsigned int qid,enum t4_bar2_qtype qtype,int user,u64 * pbar2_qoffset,unsigned int * pbar2_qid)11281 int t4_bar2_sge_qregs(struct adapter *adapter,
11282 unsigned int qid,
11283 enum t4_bar2_qtype qtype,
11284 int user,
11285 u64 *pbar2_qoffset,
11286 unsigned int *pbar2_qid)
11287 {
11288 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
11289 u64 bar2_page_offset, bar2_qoffset;
11290 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
11291
11292 /* T4 doesn't support BAR2 SGE Queue registers for kernel
11293 * mode queues.
11294 */
11295 if (!user && is_t4(adapter))
11296 return -EINVAL;
11297
11298 /* Get our SGE Page Size parameters.
11299 */
11300 page_shift = adapter->params.sge.page_shift;
11301 page_size = 1 << page_shift;
11302
11303 /* Get the right Queues per Page parameters for our Queue.
11304 */
11305 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
11306 ? adapter->params.sge.eq_s_qpp
11307 : adapter->params.sge.iq_s_qpp);
11308 qpp_mask = (1 << qpp_shift) - 1;
11309
11310 /* Calculate the basics of the BAR2 SGE Queue register area:
11311 * o The BAR2 page the Queue registers will be in.
11312 * o The BAR2 Queue ID.
11313 * o The BAR2 Queue ID Offset into the BAR2 page.
11314 */
11315 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
11316 bar2_qid = qid & qpp_mask;
11317 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
11318
11319 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
11320 * hardware will infer the Absolute Queue ID simply from the writes to
11321 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
11322 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
11323 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
11324 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
11325 * from the BAR2 Page and BAR2 Queue ID.
11326 *
11327 * One important censequence of this is that some BAR2 SGE registers
11328 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
11329 * there. But other registers synthesize the SGE Queue ID purely
11330 * from the writes to the registers -- the Write Combined Doorbell
11331 * Buffer is a good example. These BAR2 SGE Registers are only
11332 * available for those BAR2 SGE Register areas where the SGE Absolute
11333 * Queue ID can be inferred from simple writes.
11334 */
11335 bar2_qoffset = bar2_page_offset;
11336 bar2_qinferred = (bar2_qid_offset < page_size);
11337 if (bar2_qinferred) {
11338 bar2_qoffset += bar2_qid_offset;
11339 bar2_qid = 0;
11340 }
11341
11342 *pbar2_qoffset = bar2_qoffset;
11343 *pbar2_qid = bar2_qid;
11344 return 0;
11345 }
11346
11347 /**
11348 * t4_init_devlog_ncores_params - initialize adap->params.devlog and ncores
11349 * @adap: the adapter
11350 * @fw_attach: whether we can talk to the firmware
11351 */
t4_init_devlog_ncores_params(struct adapter * adap,int fw_attach)11352 int t4_init_devlog_ncores_params(struct adapter *adap, int fw_attach)
11353 {
11354 struct devlog_params *dparams = &adap->params.devlog;
11355 u32 pf_dparams;
11356 unsigned int devlog_meminfo;
11357 struct fw_devlog_cmd devlog_cmd;
11358 int ret;
11359
11360 /* If we're dealing with newer firmware, the Device Log Paramerters
11361 * are stored in a designated register which allows us to access the
11362 * Device Log even if we can't talk to the firmware.
11363 */
11364 pf_dparams =
11365 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
11366 if (pf_dparams && pf_dparams != UINT32_MAX) {
11367 unsigned int nentries, nentries128, ncore_shift;
11368
11369 ncore_shift = (G_PCIE_FW_PF_DEVLOG_COUNT_MSB(pf_dparams) << 1) |
11370 G_PCIE_FW_PF_DEVLOG_COUNT_LSB(pf_dparams);
11371 adap->params.ncores = 1 << ncore_shift;
11372
11373 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
11374 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
11375 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
11376 nentries = (nentries128 + 1) * 128;
11377 dparams->size = nentries * sizeof(struct fw_devlog_e);
11378
11379 return 0;
11380 }
11381
11382 /*
11383 * For any failing returns ...
11384 */
11385 adap->params.ncores = 1;
11386 memset(dparams, 0, sizeof *dparams);
11387
11388 /*
11389 * If we can't talk to the firmware, there's really nothing we can do
11390 * at this point.
11391 */
11392 if (!fw_attach)
11393 return -ENXIO;
11394
11395 /* Otherwise, ask the firmware for it's Device Log Parameters.
11396 */
11397 memset(&devlog_cmd, 0, sizeof devlog_cmd);
11398 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
11399 F_FW_CMD_REQUEST | F_FW_CMD_READ);
11400 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
11401 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
11402 &devlog_cmd);
11403 if (ret)
11404 return ret;
11405
11406 devlog_meminfo =
11407 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
11408 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
11409 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
11410 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
11411
11412 return 0;
11413 }
11414
11415 /**
11416 * t4_init_sge_params - initialize adap->params.sge
11417 * @adapter: the adapter
11418 *
11419 * Initialize various fields of the adapter's SGE Parameters structure.
11420 */
t4_init_sge_params(struct adapter * adapter)11421 int t4_init_sge_params(struct adapter *adapter)
11422 {
11423 u32 r;
11424 struct sge_params *sp = &adapter->params.sge;
11425 unsigned i, tscale = 1;
11426
11427 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
11428 sp->counter_val[0] = G_THRESHOLD_0(r);
11429 sp->counter_val[1] = G_THRESHOLD_1(r);
11430 sp->counter_val[2] = G_THRESHOLD_2(r);
11431 sp->counter_val[3] = G_THRESHOLD_3(r);
11432
11433 if (chip_id(adapter) >= CHELSIO_T6) {
11434 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
11435 tscale = G_TSCALE(r);
11436 if (tscale == 0)
11437 tscale = 1;
11438 else
11439 tscale += 2;
11440 }
11441
11442 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
11443 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
11444 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
11445 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
11446 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
11447 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
11448 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
11449 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
11450 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
11451
11452 r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
11453 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
11454 if (is_t4(adapter))
11455 sp->fl_starve_threshold2 = sp->fl_starve_threshold;
11456 else if (is_t5(adapter))
11457 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
11458 else
11459 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
11460
11461 /* egress queues: log2 of # of doorbells per BAR2 page */
11462 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
11463 r >>= S_QUEUESPERPAGEPF0 +
11464 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
11465 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
11466
11467 /* ingress queues: log2 of # of doorbells per BAR2 page */
11468 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
11469 r >>= S_QUEUESPERPAGEPF0 +
11470 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
11471 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
11472
11473 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
11474 r >>= S_HOSTPAGESIZEPF0 +
11475 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
11476 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
11477
11478 r = t4_read_reg(adapter, A_SGE_CONTROL);
11479 sp->sge_control = r;
11480 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
11481 sp->fl_pktshift = G_PKTSHIFT(r);
11482 if (chip_id(adapter) <= CHELSIO_T5) {
11483 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
11484 X_INGPADBOUNDARY_SHIFT);
11485 } else {
11486 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
11487 X_T6_INGPADBOUNDARY_SHIFT);
11488 }
11489 if (is_t4(adapter))
11490 sp->pack_boundary = sp->pad_boundary;
11491 else {
11492 r = t4_read_reg(adapter, A_SGE_CONTROL2);
11493 if (G_INGPACKBOUNDARY(r) == 0)
11494 sp->pack_boundary = 16;
11495 else
11496 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
11497 }
11498 for (i = 0; i < SGE_FLBUF_SIZES; i++)
11499 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
11500 A_SGE_FL_BUFFER_SIZE0 + (4 * i));
11501
11502 return 0;
11503 }
11504
11505 /* Convert the LE's hardware hash mask to a shorter filter mask. */
11506 static inline uint16_t
hashmask_to_filtermask(struct adapter * adap,uint64_t hashmask,uint16_t filter_mode)11507 hashmask_to_filtermask(struct adapter *adap, uint64_t hashmask, uint16_t filter_mode)
11508 {
11509 int first, last, i;
11510 uint16_t filter_mask;
11511 uint64_t mask; /* field mask */
11512
11513
11514 if (chip_id(adap) >= CHELSIO_T7) {
11515 first = S_T7_FT_FIRST;
11516 last = S_T7_FT_LAST;
11517 } else {
11518 first = S_FT_FIRST;
11519 last = S_FT_LAST;
11520 }
11521
11522 for (filter_mask = 0, i = first; i <= last; i++) {
11523 if ((filter_mode & (1 << i)) == 0)
11524 continue;
11525 mask = (1 << t4_filter_field_width(adap, i)) - 1;
11526 if ((hashmask & mask) == mask)
11527 filter_mask |= 1 << i;
11528 hashmask >>= t4_filter_field_width(adap, i);
11529 }
11530
11531 return (filter_mask);
11532 }
11533
11534 /*
11535 * Read and cache the adapter's compressed filter mode and ingress config.
11536 */
11537 static void
read_filter_mode_and_ingress_config(struct adapter * adap)11538 read_filter_mode_and_ingress_config(struct adapter *adap)
11539 {
11540 int rc;
11541 uint32_t v, param[2], val[2];
11542 struct tp_params *tpp = &adap->params.tp;
11543 uint64_t hash_mask;
11544
11545 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11546 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
11547 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
11548 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11549 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
11550 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
11551 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val);
11552 if (rc == 0) {
11553 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]);
11554 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]);
11555 tpp->vnic_mode = val[1];
11556 } else {
11557 /*
11558 * Old firmware. Read filter mode/mask and ingress config
11559 * straight from the hardware.
11560 */
11561 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true);
11562 tpp->filter_mode = v & 0xffff;
11563
11564 hash_mask = 0;
11565 if (chip_id(adap) > CHELSIO_T4) {
11566 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3));
11567 hash_mask = v;
11568 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
11569 hash_mask |= (u64)v << 32;
11570 }
11571 if (chip_id(adap) >= CHELSIO_T7) {
11572 /*
11573 * This param came before T7 so T7+ firmwares should
11574 * always support this query.
11575 */
11576 CH_WARN(adap, "query for filter mode/mask failed: %d\n",
11577 rc);
11578 }
11579 tpp->filter_mask = hashmask_to_filtermask(adap, hash_mask,
11580 tpp->filter_mode);
11581
11582 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true);
11583 if (v & F_VNIC)
11584 tpp->vnic_mode = FW_VNIC_MODE_PF_VF;
11585 else
11586 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN;
11587 }
11588
11589 /*
11590 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
11591 * shift positions of several elements of the Compressed Filter Tuple
11592 * for this adapter which we need frequently ...
11593 */
11594 if (chip_id(adap) >= CHELSIO_T7) {
11595 tpp->ipsecidx_shift = t4_filter_field_shift(adap, F_IPSECIDX);
11596 tpp->fcoe_shift = t4_filter_field_shift(adap, F_T7_FCOE);
11597 tpp->port_shift = t4_filter_field_shift(adap, F_T7_PORT);
11598 tpp->vnic_shift = t4_filter_field_shift(adap, F_T7_VNIC_ID);
11599 tpp->vlan_shift = t4_filter_field_shift(adap, F_T7_VLAN);
11600 tpp->tos_shift = t4_filter_field_shift(adap, F_T7_TOS);
11601 tpp->protocol_shift = t4_filter_field_shift(adap, F_T7_PROTOCOL);
11602 tpp->ethertype_shift = t4_filter_field_shift(adap, F_T7_ETHERTYPE);
11603 tpp->macmatch_shift = t4_filter_field_shift(adap, F_T7_MACMATCH);
11604 tpp->matchtype_shift = t4_filter_field_shift(adap, F_T7_MPSHITTYPE);
11605 tpp->frag_shift = t4_filter_field_shift(adap, F_T7_FRAGMENTATION);
11606 tpp->roce_shift = t4_filter_field_shift(adap, F_ROCE);
11607 tpp->synonly_shift = t4_filter_field_shift(adap, F_SYNONLY);
11608 tpp->tcpflags_shift = t4_filter_field_shift(adap, F_TCPFLAGS);
11609 } else {
11610 tpp->ipsecidx_shift = -1;
11611 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
11612 tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
11613 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
11614 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
11615 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
11616 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
11617 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
11618 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
11619 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
11620 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
11621 tpp->roce_shift = -1;
11622 tpp->synonly_shift = -1;
11623 tpp->tcpflags_shift = -1;
11624 }
11625 }
11626
11627 /**
11628 * t4_init_tp_params - initialize adap->params.tp
11629 * @adap: the adapter
11630 *
11631 * Initialize various fields of the adapter's TP Parameters structure.
11632 */
t4_init_tp_params(struct adapter * adap)11633 int t4_init_tp_params(struct adapter *adap)
11634 {
11635 u32 tx_len, rx_len, r, v;
11636 struct tp_params *tpp = &adap->params.tp;
11637
11638 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
11639 tpp->tre = G_TIMERRESOLUTION(v);
11640 tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
11641
11642 read_filter_mode_and_ingress_config(adap);
11643
11644 tpp->rx_pkt_encap = false;
11645 tpp->lb_mode = 0;
11646 tpp->lb_nchan = 1;
11647 if (chip_id(adap) > CHELSIO_T5) {
11648 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
11649 tpp->rx_pkt_encap = v & F_CRXPKTENC;
11650 if (chip_id(adap) >= CHELSIO_T7) {
11651 t4_tp_pio_read(adap, &v, 1, A_TP_CHANNEL_MAP, true);
11652 tpp->lb_mode = G_T7_LB_MODE(v);
11653 if (tpp->lb_mode == 1)
11654 tpp->lb_nchan = 4;
11655 else if (tpp->lb_mode == 2)
11656 tpp->lb_nchan = 2;
11657 }
11658 }
11659
11660 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE);
11661 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE);
11662
11663 r = t4_read_reg(adap, A_TP_PARA_REG2);
11664 rx_len = min(rx_len, G_MAXRXDATA(r));
11665 tx_len = min(tx_len, G_MAXRXDATA(r));
11666
11667 r = t4_read_reg(adap, A_TP_PARA_REG7);
11668 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r));
11669 rx_len = min(rx_len, v);
11670 tx_len = min(tx_len, v);
11671
11672 tpp->max_tx_pdu = tx_len;
11673 tpp->max_rx_pdu = rx_len;
11674
11675 return 0;
11676 }
11677
11678 /**
11679 * t4_filter_field_width - returns the width of a filter field
11680 * @adap: the adapter
11681 * @filter_field: the filter field whose width is being requested
11682 *
11683 * Return the shift position of a filter field within the Compressed
11684 * Filter Tuple. The filter field is specified via its selection bit
11685 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
11686 */
t4_filter_field_width(const struct adapter * adap,int filter_field)11687 int t4_filter_field_width(const struct adapter *adap, int filter_field)
11688 {
11689 const int nopt = adap->chip_params->filter_num_opt;
11690 static const uint8_t width_t7[] = {
11691 W_FT_IPSECIDX,
11692 W_FT_FCOE,
11693 W_FT_PORT,
11694 W_FT_VNIC_ID,
11695 W_FT_VLAN,
11696 W_FT_TOS,
11697 W_FT_PROTOCOL,
11698 W_FT_ETHERTYPE,
11699 W_FT_MACMATCH,
11700 W_FT_MPSHITTYPE,
11701 W_FT_FRAGMENTATION,
11702 W_FT_ROCE,
11703 W_FT_SYNONLY,
11704 W_FT_TCPFLAGS
11705 };
11706 static const uint8_t width_t4[] = {
11707 W_FT_FCOE,
11708 W_FT_PORT,
11709 W_FT_VNIC_ID,
11710 W_FT_VLAN,
11711 W_FT_TOS,
11712 W_FT_PROTOCOL,
11713 W_FT_ETHERTYPE,
11714 W_FT_MACMATCH,
11715 W_FT_MPSHITTYPE,
11716 W_FT_FRAGMENTATION
11717 };
11718 const uint8_t *width = chip_id(adap) >= CHELSIO_T7 ? width_t7 : width_t4;
11719
11720 if (filter_field < 0 || filter_field >= nopt)
11721 return (0);
11722 return (width[filter_field]);
11723 }
11724
11725 /**
11726 * t4_filter_field_shift - calculate filter field shift
11727 * @adap: the adapter
11728 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
11729 *
11730 * Return the shift position of a filter field within the Compressed
11731 * Filter Tuple. The filter field is specified via its selection bit
11732 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
11733 */
t4_filter_field_shift(const struct adapter * adap,int filter_sel)11734 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
11735 {
11736 const unsigned int filter_mode = adap->params.tp.filter_mode;
11737 unsigned int sel;
11738 int field_shift;
11739
11740 if ((filter_mode & filter_sel) == 0)
11741 return -1;
11742
11743 if (chip_id(adap) >= CHELSIO_T7) {
11744 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
11745 switch (filter_mode & sel) {
11746 case F_IPSECIDX:
11747 field_shift += W_FT_IPSECIDX;
11748 break;
11749 case F_T7_FCOE:
11750 field_shift += W_FT_FCOE;
11751 break;
11752 case F_T7_PORT:
11753 field_shift += W_FT_PORT;
11754 break;
11755 case F_T7_VNIC_ID:
11756 field_shift += W_FT_VNIC_ID;
11757 break;
11758 case F_T7_VLAN:
11759 field_shift += W_FT_VLAN;
11760 break;
11761 case F_T7_TOS:
11762 field_shift += W_FT_TOS;
11763 break;
11764 case F_T7_PROTOCOL:
11765 field_shift += W_FT_PROTOCOL;
11766 break;
11767 case F_T7_ETHERTYPE:
11768 field_shift += W_FT_ETHERTYPE;
11769 break;
11770 case F_T7_MACMATCH:
11771 field_shift += W_FT_MACMATCH;
11772 break;
11773 case F_T7_MPSHITTYPE:
11774 field_shift += W_FT_MPSHITTYPE;
11775 break;
11776 case F_T7_FRAGMENTATION:
11777 field_shift += W_FT_FRAGMENTATION;
11778 break;
11779 case F_ROCE:
11780 field_shift += W_FT_ROCE;
11781 break;
11782 case F_SYNONLY:
11783 field_shift += W_FT_SYNONLY;
11784 break;
11785 case F_TCPFLAGS:
11786 field_shift += W_FT_TCPFLAGS;
11787 break;
11788 }
11789 }
11790 return field_shift;
11791 }
11792
11793 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
11794 switch (filter_mode & sel) {
11795 case F_FCOE:
11796 field_shift += W_FT_FCOE;
11797 break;
11798 case F_PORT:
11799 field_shift += W_FT_PORT;
11800 break;
11801 case F_VNIC_ID:
11802 field_shift += W_FT_VNIC_ID;
11803 break;
11804 case F_VLAN:
11805 field_shift += W_FT_VLAN;
11806 break;
11807 case F_TOS:
11808 field_shift += W_FT_TOS;
11809 break;
11810 case F_PROTOCOL:
11811 field_shift += W_FT_PROTOCOL;
11812 break;
11813 case F_ETHERTYPE:
11814 field_shift += W_FT_ETHERTYPE;
11815 break;
11816 case F_MACMATCH:
11817 field_shift += W_FT_MACMATCH;
11818 break;
11819 case F_MPSHITTYPE:
11820 field_shift += W_FT_MPSHITTYPE;
11821 break;
11822 case F_FRAGMENTATION:
11823 field_shift += W_FT_FRAGMENTATION;
11824 break;
11825 }
11826 }
11827 return field_shift;
11828 }
11829
t4_port_init(struct adapter * adap,int mbox,int pf,int vf,int port_id)11830 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
11831 {
11832 u8 addr[6];
11833 int ret, i, j;
11834 struct port_info *p = adap2pinfo(adap, port_id);
11835 u32 param, val;
11836 struct vi_info *vi = &p->vi[0];
11837
11838 for (i = 0, j = -1; i <= p->port_id; i++) {
11839 do {
11840 j++;
11841 } while ((adap->params.portvec & (1 << j)) == 0);
11842 }
11843
11844 p->hw_port = j;
11845 p->tx_chan = t4_get_tx_c_chan(adap, j);
11846 p->rx_chan = t4_get_rx_c_chan(adap, j);
11847 p->mps_bg_map = t4_get_mps_bg_map(adap, j);
11848 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
11849
11850 if (!(adap->flags & IS_VF) ||
11851 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
11852 t4_update_port_info(p);
11853 }
11854
11855 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size,
11856 &vi->vfvld, &vi->vin);
11857 if (ret < 0)
11858 return ret;
11859
11860 vi->viid = ret;
11861 t4_os_set_hw_addr(p, addr);
11862
11863 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11864 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
11865 V_FW_PARAMS_PARAM_YZ(vi->viid);
11866 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val);
11867 if (ret)
11868 vi->rss_base = 0xffff;
11869 else {
11870 /* MPASS((val >> 16) == rss_size); */
11871 vi->rss_base = val & 0xffff;
11872 }
11873
11874 return 0;
11875 }
11876
t4_read_cimq_cfg_ibq_core(struct adapter * adap,u8 coreid,u32 qid,u16 * base,u16 * size,u16 * thres)11877 static void t4_read_cimq_cfg_ibq_core(struct adapter *adap, u8 coreid, u32 qid,
11878 u16 *base, u16 *size, u16 *thres)
11879 {
11880 unsigned int v, m;
11881
11882 if (chip_id(adap) > CHELSIO_T6) {
11883 v = F_T7_IBQSELECT | V_T7_QUENUMSELECT(qid) |
11884 V_CORESELECT(coreid);
11885 /* value is in 512-byte units */
11886 m = 512;
11887 } else {
11888 v = F_IBQSELECT | V_QUENUMSELECT(qid);
11889 /* value is in 256-byte units */
11890 m = 256;
11891 }
11892
11893 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, v);
11894 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
11895 if (base)
11896 *base = G_CIMQBASE(v) * m;
11897 if (size)
11898 *size = G_CIMQSIZE(v) * m;
11899 if (thres)
11900 *thres = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
11901 }
11902
t4_read_cimq_cfg_obq_core(struct adapter * adap,u8 coreid,u32 qid,u16 * base,u16 * size)11903 static void t4_read_cimq_cfg_obq_core(struct adapter *adap, u8 coreid, u32 qid,
11904 u16 *base, u16 *size)
11905 {
11906 unsigned int v, m;
11907
11908 if (chip_id(adap) > CHELSIO_T6) {
11909 v = F_T7_OBQSELECT | V_T7_QUENUMSELECT(qid) |
11910 V_CORESELECT(coreid);
11911 /* value is in 512-byte units */
11912 m = 512;
11913 } else {
11914 v = F_OBQSELECT | V_QUENUMSELECT(qid);
11915 /* value is in 256-byte units */
11916 m = 256;
11917 }
11918
11919 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, v);
11920 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
11921 if (base)
11922 *base = G_CIMQBASE(v) * m;
11923 if (size)
11924 *size = G_CIMQSIZE(v) * m;
11925 }
11926
11927 /**
11928 * t4_read_cimq_cfg_core - read CIM queue configuration on specific core
11929 * @adap: the adapter
11930 * @coreid: the uP coreid
11931 * @base: holds the queue base addresses in bytes
11932 * @size: holds the queue sizes in bytes
11933 * @thres: holds the queue full thresholds in bytes
11934 *
11935 * Returns the current configuration of the CIM queues, starting with
11936 * the IBQs, then the OBQs, on a specific @coreid.
11937 */
t4_read_cimq_cfg_core(struct adapter * adap,u8 coreid,u16 * base,u16 * size,u16 * thres)11938 void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
11939 u16 *size, u16 *thres)
11940 {
11941 unsigned int cim_num_ibq = adap->chip_params->cim_num_ibq;
11942 unsigned int cim_num_obq = adap->chip_params->cim_num_obq;
11943 unsigned int i;
11944
11945 for (i = 0; i < cim_num_ibq; i++, base++, size++, thres++)
11946 t4_read_cimq_cfg_ibq_core(adap, coreid, i, base, size, thres);
11947
11948 for (i = 0; i < cim_num_obq; i++, base++, size++)
11949 t4_read_cimq_cfg_obq_core(adap, coreid, i, base, size);
11950 }
11951
t4_read_cim_ibq_data_core(struct adapter * adap,u8 coreid,u32 addr,u32 * data)11952 static int t4_read_cim_ibq_data_core(struct adapter *adap, u8 coreid, u32 addr,
11953 u32 *data)
11954 {
11955 int ret, attempts;
11956 unsigned int v;
11957
11958 /* It might take 3-10ms before the IBQ debug read access is allowed.
11959 * Wait for 1 Sec with a delay of 1 usec.
11960 */
11961 attempts = 1000000;
11962
11963 if (chip_id(adap) > CHELSIO_T6)
11964 v = V_T7_IBQDBGADDR(addr) | V_IBQDBGCORE(coreid);
11965 else
11966 v = V_IBQDBGADDR(addr);
11967
11968 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, v | F_IBQDBGEN);
11969 ret = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
11970 attempts, 1);
11971 if (ret)
11972 return ret;
11973
11974 *data = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
11975 return 0;
11976 }
11977
11978 /**
11979 * t4_read_cim_ibq_core - read the contents of a CIM inbound queue on
11980 * specific core
11981 * @adap: the adapter
11982 * @coreid: the uP coreid
11983 * @qid: the queue index
11984 * @data: where to store the queue contents
11985 * @n: capacity of @data in 32-bit words
11986 *
11987 * Reads the contents of the selected CIM queue starting at address 0 up
11988 * to the capacity of @data on a specific @coreid. @n must be a multiple
11989 * of 4. Returns < 0 on error and the number of 32-bit words actually
11990 * read on success.
11991 */
t4_read_cim_ibq_core(struct adapter * adap,u8 coreid,u32 qid,u32 * data,size_t n)11992 int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
11993 size_t n)
11994 {
11995 unsigned int cim_num_ibq = adap->chip_params->cim_num_ibq;
11996 u16 i, addr, nwords;
11997 int ret;
11998
11999 if (qid > (cim_num_ibq - 1) || (n & 3))
12000 return -EINVAL;
12001
12002 t4_read_cimq_cfg_ibq_core(adap, coreid, qid, &addr, &nwords, NULL);
12003 addr >>= sizeof(u16);
12004 nwords >>= sizeof(u16);
12005 if (n > nwords)
12006 n = nwords;
12007
12008 for (i = 0; i < n; i++, addr++, data++) {
12009 ret = t4_read_cim_ibq_data_core(adap, coreid, addr, data);
12010 if (ret < 0)
12011 return ret;
12012 }
12013
12014 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
12015 return i;
12016 }
12017
t4_read_cim_obq_data_core(struct adapter * adap,u8 coreid,u32 addr,u32 * data)12018 static int t4_read_cim_obq_data_core(struct adapter *adap, u8 coreid, u32 addr,
12019 u32 *data)
12020 {
12021 unsigned int v;
12022 int ret;
12023
12024 if (chip_id(adap) > CHELSIO_T6)
12025 v = V_T7_OBQDBGADDR(addr) | V_OBQDBGCORE(coreid);
12026 else
12027 v = V_OBQDBGADDR(addr);
12028
12029 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, v | F_OBQDBGEN);
12030 ret = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 2, 1);
12031 if (ret)
12032 return ret;
12033
12034 *data = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
12035 return 0;
12036 }
12037
12038 /**
12039 * t4_read_cim_obq_core - read the contents of a CIM outbound queue on
12040 * specific core
12041 * @adap: the adapter
12042 * @coreid: the uP coreid
12043 * @qid: the queue index
12044 * @data: where to store the queue contents
12045 * @n: capacity of @data in 32-bit words
12046 *
12047 * Reads the contents of the selected CIM queue starting at address 0 up
12048 * to the capacity of @data on specific @coreid. @n must be a multiple
12049 * of 4. Returns < 0 on error and the number of 32-bit words actually
12050 * read on success.
12051 */
t4_read_cim_obq_core(struct adapter * adap,u8 coreid,u32 qid,u32 * data,size_t n)12052 int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
12053 size_t n)
12054 {
12055 unsigned int cim_num_obq = adap->chip_params->cim_num_obq;
12056 u16 i, addr, nwords;
12057 int ret;
12058
12059 if ((qid > (cim_num_obq - 1)) || (n & 3))
12060 return -EINVAL;
12061
12062 t4_read_cimq_cfg_obq_core(adap, coreid, qid, &addr, &nwords);
12063 addr >>= sizeof(u16);
12064 nwords >>= sizeof(u16);
12065 if (n > nwords)
12066 n = nwords;
12067
12068 for (i = 0; i < n; i++, addr++, data++) {
12069 ret = t4_read_cim_obq_data_core(adap, coreid, addr, data);
12070 if (ret < 0)
12071 return ret;
12072 }
12073
12074 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
12075 return i;
12076 }
12077
12078 /**
12079 * t4_cim_read_core - read a block from CIM internal address space
12080 * of a control register group on specific core.
12081 * @adap: the adapter
12082 * @group: the control register group to select for read
12083 * @coreid: the uP coreid
12084 * @addr: the start address within the CIM address space
12085 * @n: number of words to read
12086 * @valp: where to store the result
12087 *
12088 * Reads a block of 4-byte words from the CIM intenal address space
12089 * of a control register @group on a specific @coreid.
12090 */
t4_cim_read_core(struct adapter * adap,u8 group,u8 coreid,unsigned int addr,unsigned int n,unsigned int * valp)12091 int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
12092 unsigned int addr, unsigned int n,
12093 unsigned int *valp)
12094 {
12095 unsigned int hostbusy, v = 0;
12096 int ret = 0;
12097
12098 if (chip_id(adap) > CHELSIO_T6) {
12099 hostbusy = F_T7_HOSTBUSY;
12100 v = V_HOSTGRPSEL(group) | V_HOSTCORESEL(coreid);
12101 } else {
12102 hostbusy = F_HOSTBUSY;
12103 }
12104
12105 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & hostbusy)
12106 return -EBUSY;
12107
12108 for ( ; !ret && n--; addr += 4) {
12109 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | v);
12110 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, hostbusy,
12111 0, 5, 2);
12112 if (!ret)
12113 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
12114 }
12115
12116 return ret;
12117 }
12118
12119 /**
12120 * t4_cim_write_core - write a block into CIM internal address space
12121 * of a control register group on specific core.
12122 * @adap: the adapter
12123 * @group: the control register group to select for write
12124 * @coreid: the uP coreid
12125 * @addr: the start address within the CIM address space
12126 * @n: number of words to write
12127 * @valp: set of values to write
12128 *
12129 * Writes a block of 4-byte words into the CIM intenal address space
12130 * of a control register @group on a specific @coreid.
12131 */
t4_cim_write_core(struct adapter * adap,u8 group,u8 coreid,unsigned int addr,unsigned int n,const unsigned int * valp)12132 int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
12133 unsigned int addr, unsigned int n,
12134 const unsigned int *valp)
12135 {
12136 unsigned int hostbusy, v;
12137 int ret = 0;
12138
12139 if (chip_id(adap) > CHELSIO_T6) {
12140 hostbusy = F_T7_HOSTBUSY;
12141 v = F_T7_HOSTWRITE | V_HOSTGRPSEL(group) |
12142 V_HOSTCORESEL(coreid);
12143 } else {
12144 hostbusy = F_HOSTBUSY;
12145 v = F_HOSTWRITE;
12146 }
12147
12148 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & hostbusy)
12149 return -EBUSY;
12150
12151 for ( ; !ret && n--; addr += 4) {
12152 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
12153 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | v);
12154 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, hostbusy,
12155 0, 5, 2);
12156 }
12157
12158 return ret;
12159 }
12160
12161 /**
12162 * t4_cim_read_la_core - read CIM LA capture buffer on specific core
12163 * @adap: the adapter
12164 * @coreid: uP coreid
12165 * @la_buf: where to store the LA data
12166 * @wrptr: the HW write pointer within the capture buffer
12167 *
12168 * Reads the contents of the CIM LA buffer on a specific @coreid
12169 * with the most recent entry at the end of the returned data
12170 * and with the entry at @wrptr first. We try to leave the LA
12171 * in the running state we find it in.
12172 */
t4_cim_read_la_core(struct adapter * adap,u8 coreid,u32 * la_buf,u32 * wrptr)12173 int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
12174 u32 *wrptr)
12175 {
12176 unsigned int cfg, val, idx;
12177 int i, ret;
12178
12179 ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1, &cfg);
12180 if (ret)
12181 return ret;
12182
12183 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */
12184 val = 0;
12185 ret = t4_cim_write_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
12186 &val);
12187 if (ret)
12188 return ret;
12189 }
12190
12191 ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1, &val);
12192 if (ret)
12193 goto restart;
12194
12195 idx = G_UPDBGLAWRPTR(val);
12196 if (wrptr)
12197 *wrptr = idx;
12198
12199 for (i = 0; i < adap->params.cim_la_size; i++) {
12200 val = V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN;
12201 ret = t4_cim_write_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
12202 &val);
12203 if (ret)
12204 break;
12205 ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
12206 &val);
12207 if (ret)
12208 break;
12209 if (val & F_UPDBGLARDEN) {
12210 ret = -ETIMEDOUT;
12211 break;
12212 }
12213 ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_DATA, 1,
12214 &la_buf[i]);
12215 if (ret)
12216 break;
12217
12218 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
12219 * identify the 32-bit portion of the full 312-bit data
12220 */
12221 if ((chip_id(adap) > CHELSIO_T5) && (idx & 0xf) >= 9)
12222 idx = (idx & 0xff0) + 0x10;
12223 else
12224 idx++;
12225 /* address can't exceed 0xfff */
12226 idx &= M_UPDBGLARDPTR;
12227 }
12228 restart:
12229 if (cfg & F_UPDBGLAEN) {
12230 int r;
12231
12232 val = cfg & ~F_UPDBGLARDEN;
12233 r = t4_cim_write_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
12234 &val);
12235 if (!ret)
12236 ret = r;
12237 }
12238
12239 return ret;
12240 }
12241
12242 /**
12243 * t4_tp_read_la - read TP LA capture buffer
12244 * @adap: the adapter
12245 * @la_buf: where to store the LA data
12246 * @wrptr: the HW write pointer within the capture buffer
12247 *
12248 * Reads the contents of the TP LA buffer with the most recent entry at
12249 * the end of the returned data and with the entry at @wrptr first.
12250 * We leave the LA in the running state we find it in.
12251 */
t4_tp_read_la(struct adapter * adap,u64 * la_buf,unsigned int * wrptr)12252 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
12253 {
12254 bool last_incomplete;
12255 unsigned int i, cfg, val, idx;
12256
12257 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
12258 if (cfg & F_DBGLAENABLE) /* freeze LA */
12259 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
12260 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
12261
12262 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
12263 idx = G_DBGLAWPTR(val);
12264 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
12265 if (last_incomplete)
12266 idx = (idx + 1) & M_DBGLARPTR;
12267 if (wrptr)
12268 *wrptr = idx;
12269
12270 val &= 0xffff;
12271 val &= ~V_DBGLARPTR(M_DBGLARPTR);
12272 val |= adap->params.tp.la_mask;
12273
12274 for (i = 0; i < TPLA_SIZE; i++) {
12275 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
12276 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
12277 idx = (idx + 1) & M_DBGLARPTR;
12278 }
12279
12280 /* Wipe out last entry if it isn't valid */
12281 if (last_incomplete)
12282 la_buf[TPLA_SIZE - 1] = ~0ULL;
12283
12284 if (cfg & F_DBGLAENABLE) /* restore running state */
12285 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
12286 cfg | adap->params.tp.la_mask);
12287 }
12288
12289 /*
12290 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
12291 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
12292 * state for more than the Warning Threshold then we'll issue a warning about
12293 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
12294 * appears to be hung every Warning Repeat second till the situation clears.
12295 * If the situation clears, we'll note that as well.
12296 */
12297 #define SGE_IDMA_WARN_THRESH 1
12298 #define SGE_IDMA_WARN_REPEAT 300
12299
12300 /**
12301 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
12302 * @adapter: the adapter
12303 * @idma: the adapter IDMA Monitor state
12304 *
12305 * Initialize the state of an SGE Ingress DMA Monitor.
12306 */
t4_idma_monitor_init(struct adapter * adapter,struct sge_idma_monitor_state * idma)12307 void t4_idma_monitor_init(struct adapter *adapter,
12308 struct sge_idma_monitor_state *idma)
12309 {
12310 /* Initialize the state variables for detecting an SGE Ingress DMA
12311 * hang. The SGE has internal counters which count up on each clock
12312 * tick whenever the SGE finds its Ingress DMA State Engines in the
12313 * same state they were on the previous clock tick. The clock used is
12314 * the Core Clock so we have a limit on the maximum "time" they can
12315 * record; typically a very small number of seconds. For instance,
12316 * with a 600MHz Core Clock, we can only count up to a bit more than
12317 * 7s. So we'll synthesize a larger counter in order to not run the
12318 * risk of having the "timers" overflow and give us the flexibility to
12319 * maintain a Hung SGE State Machine of our own which operates across
12320 * a longer time frame.
12321 */
12322 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
12323 idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
12324 }
12325
12326 /**
12327 * t4_idma_monitor - monitor SGE Ingress DMA state
12328 * @adapter: the adapter
12329 * @idma: the adapter IDMA Monitor state
12330 * @hz: number of ticks/second
12331 * @ticks: number of ticks since the last IDMA Monitor call
12332 */
t4_idma_monitor(struct adapter * adapter,struct sge_idma_monitor_state * idma,int hz,int ticks)12333 void t4_idma_monitor(struct adapter *adapter,
12334 struct sge_idma_monitor_state *idma,
12335 int hz, int ticks)
12336 {
12337 int i, idma_same_state_cnt[2];
12338
12339 /* Read the SGE Debug Ingress DMA Same State Count registers. These
12340 * are counters inside the SGE which count up on each clock when the
12341 * SGE finds its Ingress DMA State Engines in the same states they
12342 * were in the previous clock. The counters will peg out at
12343 * 0xffffffff without wrapping around so once they pass the 1s
12344 * threshold they'll stay above that till the IDMA state changes.
12345 */
12346 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
12347 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
12348 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
12349
12350 for (i = 0; i < 2; i++) {
12351 u32 debug0, debug11;
12352
12353 /* If the Ingress DMA Same State Counter ("timer") is less
12354 * than 1s, then we can reset our synthesized Stall Timer and
12355 * continue. If we have previously emitted warnings about a
12356 * potential stalled Ingress Queue, issue a note indicating
12357 * that the Ingress Queue has resumed forward progress.
12358 */
12359 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
12360 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
12361 CH_WARN(adapter, "SGE idma%d, queue %u, "
12362 "resumed after %d seconds\n",
12363 i, idma->idma_qid[i],
12364 idma->idma_stalled[i]/hz);
12365 idma->idma_stalled[i] = 0;
12366 continue;
12367 }
12368
12369 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
12370 * domain. The first time we get here it'll be because we
12371 * passed the 1s Threshold; each additional time it'll be
12372 * because the RX Timer Callback is being fired on its regular
12373 * schedule.
12374 *
12375 * If the stall is below our Potential Hung Ingress Queue
12376 * Warning Threshold, continue.
12377 */
12378 if (idma->idma_stalled[i] == 0) {
12379 idma->idma_stalled[i] = hz;
12380 idma->idma_warn[i] = 0;
12381 } else {
12382 idma->idma_stalled[i] += ticks;
12383 idma->idma_warn[i] -= ticks;
12384 }
12385
12386 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
12387 continue;
12388
12389 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
12390 */
12391 if (idma->idma_warn[i] > 0)
12392 continue;
12393 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
12394
12395 /* Read and save the SGE IDMA State and Queue ID information.
12396 * We do this every time in case it changes across time ...
12397 * can't be too careful ...
12398 */
12399 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
12400 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
12401 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
12402
12403 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
12404 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
12405 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
12406
12407 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
12408 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
12409 i, idma->idma_qid[i], idma->idma_state[i],
12410 idma->idma_stalled[i]/hz,
12411 debug0, debug11);
12412 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
12413 }
12414 }
12415
12416 /**
12417 * t4_set_vf_mac - Set MAC address for the specified VF
12418 * @adapter: The adapter
12419 * @pf: the PF used to instantiate the VFs
12420 * @vf: one of the VFs instantiated by the specified PF
12421 * @naddr: the number of MAC addresses
12422 * @addr: the MAC address(es) to be set to the specified VF
12423 */
t4_set_vf_mac(struct adapter * adapter,unsigned int pf,unsigned int vf,unsigned int naddr,u8 * addr)12424 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf,
12425 unsigned int naddr, u8 *addr)
12426 {
12427 struct fw_acl_mac_cmd cmd;
12428
12429 memset(&cmd, 0, sizeof(cmd));
12430 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) |
12431 F_FW_CMD_REQUEST |
12432 F_FW_CMD_WRITE |
12433 V_FW_ACL_MAC_CMD_PFN(pf) |
12434 V_FW_ACL_MAC_CMD_VFN(vf));
12435
12436 /* Note: Do not enable the ACL */
12437 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
12438 cmd.nmac = naddr;
12439
12440 switch (pf) {
12441 case 3:
12442 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
12443 break;
12444 case 2:
12445 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
12446 break;
12447 case 1:
12448 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
12449 break;
12450 case 0:
12451 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
12452 break;
12453 }
12454
12455 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
12456 }
12457
12458 /**
12459 * t4_read_pace_tbl - read the pace table
12460 * @adap: the adapter
12461 * @pace_vals: holds the returned values
12462 *
12463 * Returns the values of TP's pace table in microseconds.
12464 */
t4_read_pace_tbl(struct adapter * adap,unsigned int pace_vals[NTX_SCHED])12465 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
12466 {
12467 unsigned int i, v;
12468
12469 for (i = 0; i < NTX_SCHED; i++) {
12470 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
12471 v = t4_read_reg(adap, A_TP_PACE_TABLE);
12472 pace_vals[i] = dack_ticks_to_usec(adap, v);
12473 }
12474 }
12475
12476 /**
12477 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
12478 * @adap: the adapter
12479 * @sched: the scheduler index
12480 * @kbps: the byte rate in Kbps
12481 * @ipg: the interpacket delay in tenths of nanoseconds
12482 *
12483 * Return the current configuration of a HW Tx scheduler.
12484 */
t4_get_tx_sched(struct adapter * adap,unsigned int sched,unsigned int * kbps,unsigned int * ipg,bool sleep_ok)12485 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
12486 unsigned int *ipg, bool sleep_ok)
12487 {
12488 unsigned int v, addr, bpt, cpt;
12489
12490 if (kbps) {
12491 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
12492 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
12493 if (sched & 1)
12494 v >>= 16;
12495 bpt = (v >> 8) & 0xff;
12496 cpt = v & 0xff;
12497 if (!cpt)
12498 *kbps = 0; /* scheduler disabled */
12499 else {
12500 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
12501 *kbps = (v * bpt) / 125;
12502 }
12503 }
12504 if (ipg) {
12505 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
12506 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
12507 if (sched & 1)
12508 v >>= 16;
12509 v &= 0xffff;
12510 *ipg = (10000 * v) / core_ticks_per_usec(adap);
12511 }
12512 }
12513
12514 /**
12515 * t4_load_cfg - download config file
12516 * @adap: the adapter
12517 * @cfg_data: the cfg text file to write
12518 * @size: text file size
12519 *
12520 * Write the supplied config text file to the card's serial flash.
12521 */
t4_load_cfg(struct adapter * adap,const u8 * cfg_data,unsigned int size)12522 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
12523 {
12524 int ret, i, n, cfg_addr;
12525 unsigned int addr, len;
12526 unsigned int flash_cfg_start_sec;
12527
12528 cfg_addr = t4_flash_cfg_addr(adap, &len);
12529 if (cfg_addr < 0)
12530 return cfg_addr;
12531
12532 if (size > len) {
12533 CH_ERR(adap, "cfg file too large, max is %u bytes\n", len);
12534 return -EFBIG;
12535 }
12536
12537 flash_cfg_start_sec = cfg_addr / SF_SEC_SIZE;
12538 i = DIV_ROUND_UP(len, SF_SEC_SIZE);
12539 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
12540 flash_cfg_start_sec + i - 1);
12541 /*
12542 * If size == 0 then we're simply erasing the FLASH sectors associated
12543 * with the on-adapter Firmware Configuration File.
12544 */
12545 if (ret || size == 0)
12546 goto out;
12547
12548 /* this will write to the flash up to SF_PAGE_SIZE at a time */
12549 addr = cfg_addr;
12550 for (i = 0; i < size; i += SF_PAGE_SIZE) {
12551 n = min(size - i, SF_PAGE_SIZE);
12552 ret = t4_write_flash(adap, addr, n, cfg_data, 1);
12553 if (ret)
12554 goto out;
12555 addr += SF_PAGE_SIZE;
12556 cfg_data += SF_PAGE_SIZE;
12557 }
12558
12559 out:
12560 if (ret)
12561 CH_ERR(adap, "config file %s failed %d\n",
12562 (size == 0 ? "clear" : "download"), ret);
12563 return ret;
12564 }
12565
12566 /**
12567 * t5_fw_init_extern_mem - initialize the external memory
12568 * @adap: the adapter
12569 *
12570 * Initializes the external memory on T5.
12571 */
t5_fw_init_extern_mem(struct adapter * adap)12572 int t5_fw_init_extern_mem(struct adapter *adap)
12573 {
12574 u32 params[1], val[1];
12575 int ret;
12576
12577 if (!is_t5(adap))
12578 return 0;
12579
12580 val[0] = 0xff; /* Initialize all MCs */
12581 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
12582 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
12583 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
12584 FW_CMD_MAX_TIMEOUT);
12585
12586 return ret;
12587 }
12588
12589 /* BIOS boot headers */
12590 typedef struct pci_expansion_rom_header {
12591 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
12592 u8 reserved[22]; /* Reserved per processor Architecture data */
12593 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
12594 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
12595
12596 /* Legacy PCI Expansion ROM Header */
12597 typedef struct legacy_pci_expansion_rom_header {
12598 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
12599 u8 size512; /* Current Image Size in units of 512 bytes */
12600 u8 initentry_point[4];
12601 u8 cksum; /* Checksum computed on the entire Image */
12602 u8 reserved[16]; /* Reserved */
12603 u8 pcir_offset[2]; /* Offset to PCI Data Struture */
12604 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
12605
12606 /* EFI PCI Expansion ROM Header */
12607 typedef struct efi_pci_expansion_rom_header {
12608 u8 signature[2]; // ROM signature. The value 0xaa55
12609 u8 initialization_size[2]; /* Units 512. Includes this header */
12610 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
12611 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */
12612 u8 efi_machine_type[2]; /* Machine type from EFI image header */
12613 u8 compression_type[2]; /* Compression type. */
12614 /*
12615 * Compression type definition
12616 * 0x0: uncompressed
12617 * 0x1: Compressed
12618 * 0x2-0xFFFF: Reserved
12619 */
12620 u8 reserved[8]; /* Reserved */
12621 u8 efi_image_header_offset[2]; /* Offset to EFI Image */
12622 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
12623 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
12624
12625 /* PCI Data Structure Format */
12626 typedef struct pcir_data_structure { /* PCI Data Structure */
12627 u8 signature[4]; /* Signature. The string "PCIR" */
12628 u8 vendor_id[2]; /* Vendor Identification */
12629 u8 device_id[2]; /* Device Identification */
12630 u8 vital_product[2]; /* Pointer to Vital Product Data */
12631 u8 length[2]; /* PCIR Data Structure Length */
12632 u8 revision; /* PCIR Data Structure Revision */
12633 u8 class_code[3]; /* Class Code */
12634 u8 image_length[2]; /* Image Length. Multiple of 512B */
12635 u8 code_revision[2]; /* Revision Level of Code/Data */
12636 u8 code_type; /* Code Type. */
12637 /*
12638 * PCI Expansion ROM Code Types
12639 * 0x00: Intel IA-32, PC-AT compatible. Legacy
12640 * 0x01: Open Firmware standard for PCI. FCODE
12641 * 0x02: Hewlett-Packard PA RISC. HP reserved
12642 * 0x03: EFI Image. EFI
12643 * 0x04-0xFF: Reserved.
12644 */
12645 u8 indicator; /* Indicator. Identifies the last image in the ROM */
12646 u8 reserved[2]; /* Reserved */
12647 } pcir_data_t; /* PCI__DATA_STRUCTURE */
12648
12649 /* BOOT constants */
12650 enum {
12651 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
12652 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
12653 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
12654 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
12655 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */
12656 VENDOR_ID = 0x1425, /* Vendor ID */
12657 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
12658 };
12659
12660 /*
12661 * modify_device_id - Modifies the device ID of the Boot BIOS image
12662 * @adatper: the device ID to write.
12663 * @boot_data: the boot image to modify.
12664 *
12665 * Write the supplied device ID to the boot BIOS image.
12666 */
modify_device_id(int device_id,u8 * boot_data)12667 static void modify_device_id(int device_id, u8 *boot_data)
12668 {
12669 legacy_pci_exp_rom_header_t *header;
12670 pcir_data_t *pcir_header;
12671 u32 cur_header = 0;
12672
12673 /*
12674 * Loop through all chained images and change the device ID's
12675 */
12676 while (1) {
12677 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
12678 pcir_header = (pcir_data_t *) &boot_data[cur_header +
12679 le16_to_cpu(*(u16*)header->pcir_offset)];
12680
12681 /*
12682 * Only modify the Device ID if code type is Legacy or HP.
12683 * 0x00: Okay to modify
12684 * 0x01: FCODE. Do not be modify
12685 * 0x03: Okay to modify
12686 * 0x04-0xFF: Do not modify
12687 */
12688 if (pcir_header->code_type == 0x00) {
12689 u8 csum = 0;
12690 int i;
12691
12692 /*
12693 * Modify Device ID to match current adatper
12694 */
12695 *(u16*) pcir_header->device_id = device_id;
12696
12697 /*
12698 * Set checksum temporarily to 0.
12699 * We will recalculate it later.
12700 */
12701 header->cksum = 0x0;
12702
12703 /*
12704 * Calculate and update checksum
12705 */
12706 for (i = 0; i < (header->size512 * 512); i++)
12707 csum += (u8)boot_data[cur_header + i];
12708
12709 /*
12710 * Invert summed value to create the checksum
12711 * Writing new checksum value directly to the boot data
12712 */
12713 boot_data[cur_header + 7] = -csum;
12714
12715 } else if (pcir_header->code_type == 0x03) {
12716
12717 /*
12718 * Modify Device ID to match current adatper
12719 */
12720 *(u16*) pcir_header->device_id = device_id;
12721
12722 }
12723
12724
12725 /*
12726 * Check indicator element to identify if this is the last
12727 * image in the ROM.
12728 */
12729 if (pcir_header->indicator & 0x80)
12730 break;
12731
12732 /*
12733 * Move header pointer up to the next image in the ROM.
12734 */
12735 cur_header += header->size512 * 512;
12736 }
12737 }
12738
12739 /*
12740 * t4_load_boot - download boot flash
12741 * @adapter: the adapter
12742 * @boot_data: the boot image to write
12743 * @boot_addr: offset in flash to write boot_data
12744 * @size: image size
12745 *
12746 * Write the supplied boot image to the card's serial flash.
12747 * The boot image has the following sections: a 28-byte header and the
12748 * boot image.
12749 */
t4_load_boot(struct adapter * adap,u8 * boot_data,unsigned int boot_addr,unsigned int size)12750 int t4_load_boot(struct adapter *adap, u8 *boot_data,
12751 unsigned int boot_addr, unsigned int size)
12752 {
12753 pci_exp_rom_header_t *header;
12754 int pcir_offset ;
12755 pcir_data_t *pcir_header;
12756 int ret, addr;
12757 uint16_t device_id;
12758 unsigned int i, start, len;
12759 unsigned int boot_sector = boot_addr * 1024;
12760
12761 /*
12762 * Make sure the boot image does not exceed its available space.
12763 */
12764 len = 0;
12765 start = t4_flash_loc_start(adap, FLASH_LOC_BOOT_AREA, &len);
12766 if (boot_sector + size > start + len) {
12767 CH_ERR(adap, "boot data is larger than available BOOT area\n");
12768 return -EFBIG;
12769 }
12770
12771 /*
12772 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
12773 * and Boot configuration data sections. These 3 boot sections span
12774 * the entire FLASH_LOC_BOOT_AREA.
12775 */
12776 i = DIV_ROUND_UP(size ? size : len, SF_SEC_SIZE);
12777 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
12778 (boot_sector >> 16) + i - 1);
12779
12780 /*
12781 * If size == 0 then we're simply erasing the FLASH sectors associated
12782 * with the on-adapter option ROM file
12783 */
12784 if (ret || (size == 0))
12785 goto out;
12786
12787 /* Get boot header */
12788 header = (pci_exp_rom_header_t *)boot_data;
12789 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
12790 /* PCIR Data Structure */
12791 pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
12792
12793 /*
12794 * Perform some primitive sanity testing to avoid accidentally
12795 * writing garbage over the boot sectors. We ought to check for
12796 * more but it's not worth it for now ...
12797 */
12798 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
12799 CH_ERR(adap, "boot image too small/large\n");
12800 return -EFBIG;
12801 }
12802
12803 #ifndef CHELSIO_T4_DIAGS
12804 /*
12805 * Check BOOT ROM header signature
12806 */
12807 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
12808 CH_ERR(adap, "Boot image missing signature\n");
12809 return -EINVAL;
12810 }
12811
12812 /*
12813 * Check PCI header signature
12814 */
12815 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
12816 CH_ERR(adap, "PCI header missing signature\n");
12817 return -EINVAL;
12818 }
12819
12820 /*
12821 * Check Vendor ID matches Chelsio ID
12822 */
12823 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
12824 CH_ERR(adap, "Vendor ID missing signature\n");
12825 return -EINVAL;
12826 }
12827 #endif
12828
12829 /*
12830 * Retrieve adapter's device ID
12831 */
12832 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
12833 /* Want to deal with PF 0 so I strip off PF 4 indicator */
12834 device_id = device_id & 0xf0ff;
12835
12836 /*
12837 * Check PCIE Device ID
12838 */
12839 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
12840 /*
12841 * Change the device ID in the Boot BIOS image to match
12842 * the Device ID of the current adapter.
12843 */
12844 modify_device_id(device_id, boot_data);
12845 }
12846
12847 /*
12848 * Skip over the first SF_PAGE_SIZE worth of data and write it after
12849 * we finish copying the rest of the boot image. This will ensure
12850 * that the BIOS boot header will only be written if the boot image
12851 * was written in full.
12852 */
12853 addr = boot_sector;
12854 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
12855 addr += SF_PAGE_SIZE;
12856 boot_data += SF_PAGE_SIZE;
12857 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
12858 if (ret)
12859 goto out;
12860 }
12861
12862 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
12863 (const u8 *)header, 0);
12864
12865 out:
12866 if (ret)
12867 CH_ERR(adap, "boot image download failed, error %d\n", ret);
12868 return ret;
12869 }
12870
12871 /*
12872 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
12873 * @adapter: the adapter
12874 *
12875 * Return the address within the flash where the OptionROM Configuration
12876 * is stored, or an error if the device FLASH is too small to contain
12877 * a OptionROM Configuration.
12878 */
t4_flash_bootcfg_addr(struct adapter * adapter,unsigned int * lenp)12879 static int t4_flash_bootcfg_addr(struct adapter *adapter, unsigned int *lenp)
12880 {
12881 unsigned int len = 0;
12882 const int start = t4_flash_loc_start(adapter, FLASH_LOC_BOOTCFG, &len);
12883
12884 /*
12885 * If the device FLASH isn't large enough to hold a Firmware
12886 * Configuration File, return an error.
12887 */
12888 if (adapter->params.sf_size < start + len)
12889 return -ENOSPC;
12890 if (lenp != NULL)
12891 *lenp = len;
12892 return (start);
12893 }
12894
t4_load_bootcfg(struct adapter * adap,const u8 * cfg_data,unsigned int size)12895 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
12896 {
12897 int ret, i, n, cfg_addr;
12898 unsigned int addr, len;
12899 unsigned int flash_cfg_start_sec;
12900
12901 cfg_addr = t4_flash_bootcfg_addr(adap, &len);
12902 if (cfg_addr < 0)
12903 return cfg_addr;
12904
12905 if (size > len) {
12906 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", len);
12907 return -EFBIG;
12908 }
12909
12910 flash_cfg_start_sec = cfg_addr / SF_SEC_SIZE;
12911 i = DIV_ROUND_UP(len, SF_SEC_SIZE);
12912 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
12913 flash_cfg_start_sec + i - 1);
12914
12915 /*
12916 * If size == 0 then we're simply erasing the FLASH sectors associated
12917 * with the on-adapter OptionROM Configuration File.
12918 */
12919 if (ret || size == 0)
12920 goto out;
12921
12922 /* this will write to the flash up to SF_PAGE_SIZE at a time */
12923 addr = cfg_addr;
12924 for (i = 0; i < size; i += SF_PAGE_SIZE) {
12925 n = min(size - i, SF_PAGE_SIZE);
12926 ret = t4_write_flash(adap, addr, n, cfg_data, 0);
12927 if (ret)
12928 goto out;
12929 addr += SF_PAGE_SIZE;
12930 cfg_data += SF_PAGE_SIZE;
12931 }
12932
12933 out:
12934 if (ret)
12935 CH_ERR(adap, "boot config data %s failed %d\n",
12936 (size == 0 ? "clear" : "download"), ret);
12937 return ret;
12938 }
12939
12940 /**
12941 * t4_set_filter_cfg - set up filter mode/mask and ingress config.
12942 * @adap: the adapter
12943 * @mode: a bitmap selecting which optional filter components to enable
12944 * @mask: a bitmap selecting which components to enable in filter mask
12945 * @vnic_mode: the ingress config/vnic mode setting
12946 *
12947 * Sets the filter mode and mask by selecting the optional components to
12948 * enable in filter tuples. Returns 0 on success and a negative error if
12949 * the requested mode needs more bits than are available for optional
12950 * components. The filter mask must be a subset of the filter mode.
12951 */
t4_set_filter_cfg(struct adapter * adap,int mode,int mask,int vnic_mode)12952 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
12953 {
12954 int i, nbits, rc;
12955 uint32_t param, val;
12956 uint16_t fmode, fmask;
12957 const int maxbits = adap->chip_params->filter_opt_len;
12958 const int nopt = adap->chip_params->filter_num_opt;
12959 int width;
12960
12961 if (mode != -1 || mask != -1) {
12962 if (mode != -1) {
12963 fmode = mode;
12964 nbits = 0;
12965 for (i = 0; i < nopt; i++) {
12966 if (fmode & (1 << i))
12967 nbits += t4_filter_field_width(adap, i);
12968 }
12969 if (nbits > maxbits) {
12970 CH_ERR(adap, "optional fields in the filter "
12971 "mode (0x%x) add up to %d bits "
12972 "(must be <= %db). Remove some fields and "
12973 "try again.\n", fmode, nbits, maxbits);
12974 return -E2BIG;
12975 }
12976
12977 /*
12978 * Hardware < T7 wants the bits to be maxed out. Keep
12979 * setting them until there's no room for more.
12980 */
12981 if (chip_id(adap) < CHELSIO_T7) {
12982 for (i = 0; i < nopt; i++) {
12983 if (fmode & (1 << i))
12984 continue;
12985 width = t4_filter_field_width(adap, i);
12986 if (nbits + width <= maxbits) {
12987 fmode |= 1 << i;
12988 nbits += width;
12989 if (nbits == maxbits)
12990 break;
12991 }
12992 }
12993 }
12994
12995 fmask = fmode & adap->params.tp.filter_mask;
12996 if (fmask != adap->params.tp.filter_mask) {
12997 CH_WARN(adap,
12998 "filter mask will be changed from 0x%x to "
12999 "0x%x to comply with the filter mode (0x%x).\n",
13000 adap->params.tp.filter_mask, fmask, fmode);
13001 }
13002 } else {
13003 fmode = adap->params.tp.filter_mode;
13004 fmask = mask;
13005 if ((fmode | fmask) != fmode) {
13006 CH_ERR(adap,
13007 "filter mask (0x%x) must be a subset of "
13008 "the filter mode (0x%x).\n", fmask, fmode);
13009 return -EINVAL;
13010 }
13011 }
13012
13013 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
13014 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
13015 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
13016 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) |
13017 V_FW_PARAMS_PARAM_FILTER_MASK(fmask);
13018 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m,
13019 &val);
13020 if (rc < 0)
13021 return rc;
13022 }
13023
13024 if (vnic_mode != -1) {
13025 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
13026 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
13027 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
13028 val = vnic_mode;
13029 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m,
13030 &val);
13031 if (rc < 0)
13032 return rc;
13033 }
13034
13035 /* Refresh. */
13036 read_filter_mode_and_ingress_config(adap);
13037
13038 return 0;
13039 }
13040
13041 /**
13042 * t4_clr_port_stats - clear port statistics
13043 * @adap: the adapter
13044 * @idx: the port index
13045 *
13046 * Clear HW statistics for the given port.
13047 */
t4_clr_port_stats(struct adapter * adap,int idx)13048 void t4_clr_port_stats(struct adapter *adap, int idx)
13049 {
13050 struct port_info *pi;
13051 int i, port_id, tx_chan;
13052 u32 bgmap, port_base_addr;
13053
13054 port_id = adap->port_map[idx];
13055 MPASS(port_id >= 0 && port_id <= adap->params.nports);
13056 pi = adap->port[port_id];
13057
13058 for (tx_chan = pi->tx_chan;
13059 tx_chan < pi->tx_chan + adap->params.tp.lb_nchan; tx_chan++) {
13060 port_base_addr = t4_port_reg(adap, tx_chan, 0);
13061
13062 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
13063 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
13064 t4_write_reg(adap, port_base_addr + i, 0);
13065 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
13066 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
13067 t4_write_reg(adap, port_base_addr + i, 0);
13068 }
13069 bgmap = pi->mps_bg_map;
13070 for (i = 0; i < 4; i++)
13071 if (bgmap & (1 << i)) {
13072 t4_write_reg(adap,
13073 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
13074 t4_write_reg(adap,
13075 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
13076 }
13077 }
13078
13079 /**
13080 * t4_i2c_io - read/write I2C data from adapter
13081 * @adap: the adapter
13082 * @port: Port number if per-port device; <0 if not
13083 * @devid: per-port device ID or absolute device ID
13084 * @offset: byte offset into device I2C space
13085 * @len: byte length of I2C space data
13086 * @buf: buffer in which to return I2C data for read
13087 * buffer which holds the I2C data for write
13088 * @write: if true, do a write; else do a read
13089 * Reads/Writes the I2C data from/to the indicated device and location.
13090 */
t4_i2c_io(struct adapter * adap,unsigned int mbox,int port,unsigned int devid,unsigned int offset,unsigned int len,u8 * buf,bool write)13091 int t4_i2c_io(struct adapter *adap, unsigned int mbox,
13092 int port, unsigned int devid,
13093 unsigned int offset, unsigned int len,
13094 u8 *buf, bool write)
13095 {
13096 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
13097 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
13098 int ret = 0;
13099
13100 if (len > I2C_PAGE_SIZE)
13101 return -EINVAL;
13102
13103 /* Dont allow reads that spans multiple pages */
13104 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
13105 return -EINVAL;
13106
13107 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
13108 ldst_cmd.op_to_addrspace =
13109 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
13110 F_FW_CMD_REQUEST |
13111 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) |
13112 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C));
13113 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
13114 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
13115 ldst_cmd.u.i2c.did = devid;
13116
13117 while (len > 0) {
13118 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
13119
13120 ldst_cmd.u.i2c.boffset = offset;
13121 ldst_cmd.u.i2c.blen = i2c_len;
13122
13123 if (write)
13124 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len);
13125
13126 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
13127 write ? NULL : &ldst_rpl);
13128 if (ret)
13129 break;
13130
13131 if (!write)
13132 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
13133 offset += i2c_len;
13134 buf += i2c_len;
13135 len -= i2c_len;
13136 }
13137
13138 return ret;
13139 }
13140
t4_i2c_rd(struct adapter * adap,unsigned int mbox,int port,unsigned int devid,unsigned int offset,unsigned int len,u8 * buf)13141 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
13142 int port, unsigned int devid,
13143 unsigned int offset, unsigned int len,
13144 u8 *buf)
13145 {
13146 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false);
13147 }
13148
t4_i2c_wr(struct adapter * adap,unsigned int mbox,int port,unsigned int devid,unsigned int offset,unsigned int len,u8 * buf)13149 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
13150 int port, unsigned int devid,
13151 unsigned int offset, unsigned int len,
13152 u8 *buf)
13153 {
13154 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true);
13155 }
13156
13157 /**
13158 * t4_sge_ctxt_rd - read an SGE context through FW
13159 * @adap: the adapter
13160 * @mbox: mailbox to use for the FW command
13161 * @cid: the context id
13162 * @ctype: the context type
13163 * @data: where to store the context data
13164 *
13165 * Issues a FW command through the given mailbox to read an SGE context.
13166 */
t4_sge_ctxt_rd(struct adapter * adap,unsigned int mbox,unsigned int cid,enum ctxt_type ctype,u32 * data)13167 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
13168 enum ctxt_type ctype, u32 *data)
13169 {
13170 int ret;
13171 struct fw_ldst_cmd c;
13172
13173 if (ctype == CTXT_EGRESS)
13174 ret = FW_LDST_ADDRSPC_SGE_EGRC;
13175 else if (ctype == CTXT_INGRESS)
13176 ret = FW_LDST_ADDRSPC_SGE_INGC;
13177 else if (ctype == CTXT_FLM)
13178 ret = FW_LDST_ADDRSPC_SGE_FLMC;
13179 else
13180 ret = FW_LDST_ADDRSPC_SGE_CONMC;
13181
13182 memset(&c, 0, sizeof(c));
13183 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
13184 F_FW_CMD_REQUEST | F_FW_CMD_READ |
13185 V_FW_LDST_CMD_ADDRSPACE(ret));
13186 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
13187 c.u.idctxt.physid = cpu_to_be32(cid);
13188
13189 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
13190 if (ret == 0) {
13191 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
13192 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
13193 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
13194 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
13195 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
13196 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
13197 if (chip_id(adap) > CHELSIO_T6)
13198 data[6] = be32_to_cpu(c.u.idctxt.ctxt_data6);
13199 }
13200 return ret;
13201 }
13202
13203 /**
13204 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
13205 * @adap: the adapter
13206 * @cid: the context id
13207 * @ctype: the context type
13208 * @data: where to store the context data
13209 *
13210 * Reads an SGE context directly, bypassing FW. This is only for
13211 * debugging when FW is unavailable.
13212 */
t4_sge_ctxt_rd_bd(struct adapter * adap,unsigned int cid,enum ctxt_type ctype,u32 * data)13213 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
13214 u32 *data)
13215 {
13216 int i, ret;
13217
13218 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
13219 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
13220 if (!ret) {
13221 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
13222 *data++ = t4_read_reg(adap, i);
13223 if (chip_id(adap) > CHELSIO_T6)
13224 *data++ = t4_read_reg(adap, i);
13225 }
13226 return ret;
13227 }
13228
t4_sched_config(struct adapter * adapter,int type,int minmaxen,int sleep_ok)13229 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
13230 int sleep_ok)
13231 {
13232 struct fw_sched_cmd cmd;
13233
13234 memset(&cmd, 0, sizeof(cmd));
13235 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
13236 F_FW_CMD_REQUEST |
13237 F_FW_CMD_WRITE);
13238 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
13239
13240 cmd.u.config.sc = FW_SCHED_SC_CONFIG;
13241 cmd.u.config.type = type;
13242 cmd.u.config.minmaxen = minmaxen;
13243
13244 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
13245 NULL, sleep_ok);
13246 }
13247
t4_sched_params(struct adapter * adapter,int type,int level,int mode,int rateunit,int ratemode,int channel,int cl,int minrate,int maxrate,int weight,int pktsize,int burstsize,int sleep_ok)13248 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
13249 int rateunit, int ratemode, int channel, int cl,
13250 int minrate, int maxrate, int weight, int pktsize,
13251 int burstsize, int sleep_ok)
13252 {
13253 struct fw_sched_cmd cmd;
13254
13255 memset(&cmd, 0, sizeof(cmd));
13256 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
13257 F_FW_CMD_REQUEST |
13258 F_FW_CMD_WRITE);
13259 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
13260
13261 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
13262 cmd.u.params.type = type;
13263 cmd.u.params.level = level;
13264 cmd.u.params.mode = mode;
13265 cmd.u.params.ch = channel;
13266 cmd.u.params.cl = cl;
13267 cmd.u.params.unit = rateunit;
13268 cmd.u.params.rate = ratemode;
13269 cmd.u.params.min = cpu_to_be32(minrate);
13270 cmd.u.params.max = cpu_to_be32(maxrate);
13271 cmd.u.params.weight = cpu_to_be16(weight);
13272 cmd.u.params.pktsize = cpu_to_be16(pktsize);
13273 cmd.u.params.burstsize = cpu_to_be16(burstsize);
13274
13275 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
13276 NULL, sleep_ok);
13277 }
13278
t4_sched_params_ch_rl(struct adapter * adapter,int channel,int ratemode,unsigned int maxrate,int sleep_ok)13279 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
13280 unsigned int maxrate, int sleep_ok)
13281 {
13282 struct fw_sched_cmd cmd;
13283
13284 memset(&cmd, 0, sizeof(cmd));
13285 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
13286 F_FW_CMD_REQUEST |
13287 F_FW_CMD_WRITE);
13288 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
13289
13290 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
13291 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
13292 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
13293 cmd.u.params.ch = channel;
13294 cmd.u.params.rate = ratemode; /* REL or ABS */
13295 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */
13296
13297 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
13298 NULL, sleep_ok);
13299 }
13300
t4_sched_params_cl_wrr(struct adapter * adapter,int channel,int cl,int weight,int sleep_ok)13301 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
13302 int weight, int sleep_ok)
13303 {
13304 struct fw_sched_cmd cmd;
13305
13306 if (weight < 0 || weight > 100)
13307 return -EINVAL;
13308
13309 memset(&cmd, 0, sizeof(cmd));
13310 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
13311 F_FW_CMD_REQUEST |
13312 F_FW_CMD_WRITE);
13313 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
13314
13315 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
13316 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
13317 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
13318 cmd.u.params.ch = channel;
13319 cmd.u.params.cl = cl;
13320 cmd.u.params.weight = cpu_to_be16(weight);
13321
13322 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
13323 NULL, sleep_ok);
13324 }
13325
t4_sched_params_cl_rl_kbps(struct adapter * adapter,int channel,int cl,int mode,unsigned int maxrate,int pktsize,int sleep_ok)13326 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
13327 int mode, unsigned int maxrate, int pktsize, int sleep_ok)
13328 {
13329 struct fw_sched_cmd cmd;
13330
13331 memset(&cmd, 0, sizeof(cmd));
13332 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
13333 F_FW_CMD_REQUEST |
13334 F_FW_CMD_WRITE);
13335 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
13336
13337 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
13338 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
13339 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
13340 cmd.u.params.mode = mode;
13341 cmd.u.params.ch = channel;
13342 cmd.u.params.cl = cl;
13343 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
13344 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
13345 cmd.u.params.max = cpu_to_be32(maxrate);
13346 cmd.u.params.pktsize = cpu_to_be16(pktsize);
13347
13348 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
13349 NULL, sleep_ok);
13350 }
13351
13352 /*
13353 * t4_config_watchdog - configure (enable/disable) a watchdog timer
13354 * @adapter: the adapter
13355 * @mbox: mailbox to use for the FW command
13356 * @pf: the PF owning the queue
13357 * @vf: the VF owning the queue
13358 * @timeout: watchdog timeout in ms
13359 * @action: watchdog timer / action
13360 *
13361 * There are separate watchdog timers for each possible watchdog
13362 * action. Configure one of the watchdog timers by setting a non-zero
13363 * timeout. Disable a watchdog timer by using a timeout of zero.
13364 */
t4_config_watchdog(struct adapter * adapter,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int timeout,unsigned int action)13365 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
13366 unsigned int pf, unsigned int vf,
13367 unsigned int timeout, unsigned int action)
13368 {
13369 struct fw_watchdog_cmd wdog;
13370 unsigned int ticks;
13371
13372 /*
13373 * The watchdog command expects a timeout in units of 10ms so we need
13374 * to convert it here (via rounding) and force a minimum of one 10ms
13375 * "tick" if the timeout is non-zero but the conversion results in 0
13376 * ticks.
13377 */
13378 ticks = (timeout + 5)/10;
13379 if (timeout && !ticks)
13380 ticks = 1;
13381
13382 memset(&wdog, 0, sizeof wdog);
13383 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
13384 F_FW_CMD_REQUEST |
13385 F_FW_CMD_WRITE |
13386 V_FW_PARAMS_CMD_PFN(pf) |
13387 V_FW_PARAMS_CMD_VFN(vf));
13388 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
13389 wdog.timeout = cpu_to_be32(ticks);
13390 wdog.action = cpu_to_be32(action);
13391
13392 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
13393 }
13394
t4_get_devlog_level(struct adapter * adapter,unsigned int * level)13395 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
13396 {
13397 struct fw_devlog_cmd devlog_cmd;
13398 int ret;
13399
13400 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
13401 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
13402 F_FW_CMD_REQUEST | F_FW_CMD_READ);
13403 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
13404 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
13405 sizeof(devlog_cmd), &devlog_cmd);
13406 if (ret)
13407 return ret;
13408
13409 *level = devlog_cmd.level;
13410 return 0;
13411 }
13412
t4_set_devlog_level(struct adapter * adapter,unsigned int level)13413 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
13414 {
13415 struct fw_devlog_cmd devlog_cmd;
13416
13417 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
13418 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
13419 F_FW_CMD_REQUEST |
13420 F_FW_CMD_WRITE);
13421 devlog_cmd.level = level;
13422 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
13423 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
13424 sizeof(devlog_cmd), &devlog_cmd);
13425 }
13426
t4_configure_add_smac(struct adapter * adap)13427 int t4_configure_add_smac(struct adapter *adap)
13428 {
13429 unsigned int param, val;
13430 int ret = 0;
13431
13432 adap->params.smac_add_support = 0;
13433 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
13434 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC));
13435 /* Query FW to check if FW supports adding source mac address
13436 * to TCAM feature or not.
13437 * If FW returns 1, driver can use this feature and driver need to send
13438 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to
13439 * enable adding smac to TCAM.
13440 */
13441 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
13442 if (ret)
13443 return ret;
13444
13445 if (val == 1) {
13446 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
13447 ¶m, &val);
13448 if (!ret)
13449 /* Firmware allows adding explicit TCAM entries.
13450 * Save this internally.
13451 */
13452 adap->params.smac_add_support = 1;
13453 }
13454
13455 return ret;
13456 }
13457
t4_configure_ringbb(struct adapter * adap)13458 int t4_configure_ringbb(struct adapter *adap)
13459 {
13460 unsigned int param, val;
13461 int ret = 0;
13462
13463 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
13464 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE));
13465 /* Query FW to check if FW supports ring switch feature or not.
13466 * If FW returns 1, driver can use this feature and driver need to send
13467 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to
13468 * enable the ring backbone configuration.
13469 */
13470 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
13471 if (ret < 0) {
13472 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n",
13473 ret);
13474 goto out;
13475 }
13476
13477 if (val != 1) {
13478 CH_ERR(adap, "FW doesnot support ringbackbone features\n");
13479 goto out;
13480 }
13481
13482 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
13483 if (ret < 0) {
13484 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n",
13485 ret);
13486 goto out;
13487 }
13488
13489 out:
13490 return ret;
13491 }
13492
13493 /*
13494 * t4_set_vlan_acl - Set a VLAN id for the specified VF
13495 * @adapter: the adapter
13496 * @mbox: mailbox to use for the FW command
13497 * @vf: one of the VFs instantiated by the specified PF
13498 * @vlan: The vlanid to be set
13499 *
13500 */
t4_set_vlan_acl(struct adapter * adap,unsigned int pf,unsigned int vf,u16 vlan)13501 int t4_set_vlan_acl(struct adapter *adap, unsigned int pf, unsigned int vf,
13502 u16 vlan)
13503 {
13504 struct fw_acl_vlan_cmd vlan_cmd;
13505 unsigned int enable;
13506
13507 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0);
13508 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
13509 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) |
13510 F_FW_CMD_REQUEST |
13511 F_FW_CMD_WRITE |
13512 F_FW_CMD_EXEC |
13513 V_FW_ACL_VLAN_CMD_PFN(pf) |
13514 V_FW_ACL_VLAN_CMD_VFN(vf));
13515 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd) |
13516 V_FW_ACL_VLAN_CMD_PMASK(1 << pf));
13517 /* Drop all packets that donot match vlan id */
13518 vlan_cmd.dropnovlan_fm = (enable
13519 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN |
13520 F_FW_ACL_VLAN_CMD_FM)
13521 : 0);
13522 if (enable != 0) {
13523 vlan_cmd.nvlan = 1;
13524 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
13525 }
13526
13527 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
13528 }
13529
13530 /**
13531 * t4_del_mac - Removes the exact-match filter for a MAC address
13532 * @adap: the adapter
13533 * @mbox: mailbox to use for the FW command
13534 * @viid: the VI id
13535 * @addr: the MAC address value
13536 * @smac: if true, delete from only the smac region of MPS
13537 *
13538 * Modifies an exact-match filter and sets it to the new MAC address if
13539 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
13540 * latter case the address is added persistently if @persist is %true.
13541 *
13542 * Returns a negative error number or the index of the filter with the new
13543 * MAC value. Note that this index may differ from @idx.
13544 */
t4_del_mac(struct adapter * adap,unsigned int mbox,unsigned int viid,const u8 * addr,bool smac)13545 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
13546 const u8 *addr, bool smac)
13547 {
13548 int ret;
13549 struct fw_vi_mac_cmd c;
13550 struct fw_vi_mac_exact *p = c.u.exact;
13551 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
13552
13553 memset(&c, 0, sizeof(c));
13554 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
13555 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
13556 V_FW_VI_MAC_CMD_VIID(viid));
13557 c.freemacs_to_len16 = cpu_to_be32(
13558 V_FW_CMD_LEN16(1) |
13559 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
13560
13561 memcpy(p->macaddr, addr, sizeof(p->macaddr));
13562 p->valid_to_idx = cpu_to_be16(
13563 F_FW_VI_MAC_CMD_VALID |
13564 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
13565
13566 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
13567 if (ret == 0) {
13568 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
13569 if (ret < max_mac_addr)
13570 return -ENOMEM;
13571 }
13572
13573 return ret;
13574 }
13575
13576 /**
13577 * t4_add_mac - Adds an exact-match filter for a MAC address
13578 * @adap: the adapter
13579 * @mbox: mailbox to use for the FW command
13580 * @viid: the VI id
13581 * @idx: index of existing filter for old value of MAC address, or -1
13582 * @addr: the new MAC address value
13583 * @persist: whether a new MAC allocation should be persistent
13584 * @add_smt: if true also add the address to the HW SMT
13585 * @smac: if true, update only the smac region of MPS
13586 *
13587 * Modifies an exact-match filter and sets it to the new MAC address if
13588 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
13589 * latter case the address is added persistently if @persist is %true.
13590 *
13591 * Returns a negative error number or the index of the filter with the new
13592 * MAC value. Note that this index may differ from @idx.
13593 */
t4_add_mac(struct adapter * adap,unsigned int mbox,unsigned int viid,int idx,const u8 * addr,bool persist,u8 * smt_idx,bool smac)13594 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
13595 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac)
13596 {
13597 int ret, mode;
13598 struct fw_vi_mac_cmd c;
13599 struct fw_vi_mac_exact *p = c.u.exact;
13600 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
13601
13602 if (idx < 0) /* new allocation */
13603 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
13604 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
13605
13606 memset(&c, 0, sizeof(c));
13607 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
13608 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
13609 V_FW_VI_MAC_CMD_VIID(viid));
13610 c.freemacs_to_len16 = cpu_to_be32(
13611 V_FW_CMD_LEN16(1) |
13612 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
13613 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
13614 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
13615 V_FW_VI_MAC_CMD_IDX(idx));
13616 memcpy(p->macaddr, addr, sizeof(p->macaddr));
13617
13618 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
13619 if (ret == 0) {
13620 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
13621 if (ret >= max_mac_addr)
13622 return -ENOMEM;
13623 if (smt_idx) {
13624 /* Does fw supports returning smt_idx? */
13625 if (adap->params.viid_smt_extn_support)
13626 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
13627 else {
13628 /* In T4/T5, SMT contains 256 SMAC entries
13629 * organized in 128 rows of 2 entries each.
13630 * In T6, SMT contains 256 SMAC entries in
13631 * 256 rows.
13632 */
13633 if (chip_id(adap) <= CHELSIO_T5)
13634 *smt_idx = ((viid & M_FW_VIID_VIN) << 1);
13635 else
13636 *smt_idx = (viid & M_FW_VIID_VIN);
13637 }
13638 }
13639 }
13640
13641 return ret;
13642 }
13643