1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * amd_axi_w1 - AMD 1Wire programmable logic bus host driver
4 *
5 * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
6 */
7
8 #include <linux/atomic.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/types.h>
18 #include <linux/wait.h>
19
20 #include <linux/w1.h>
21
22 /* 1-wire AMD IP definition */
23 #define AXIW1_IPID 0x10ee4453
24 /* Registers offset */
25 #define AXIW1_INST_REG 0x0
26 #define AXIW1_CTRL_REG 0x4
27 #define AXIW1_IRQE_REG 0x8
28 #define AXIW1_STAT_REG 0xC
29 #define AXIW1_DATA_REG 0x10
30 #define AXIW1_IPVER_REG 0x18
31 #define AXIW1_IPID_REG 0x1C
32 /* Instructions */
33 #define AXIW1_INITPRES 0x0800
34 #define AXIW1_READBIT 0x0C00
35 #define AXIW1_WRITEBIT 0x0E00
36 #define AXIW1_READBYTE 0x0D00
37 #define AXIW1_WRITEBYTE 0x0F00
38 /* Status flag masks */
39 #define AXIW1_DONE BIT(0)
40 #define AXIW1_READY BIT(4)
41 #define AXIW1_PRESENCE BIT(31)
42 #define AXIW1_MAJORVER_MASK GENMASK(23, 8)
43 #define AXIW1_MINORVER_MASK GENMASK(7, 0)
44 /* Control flag */
45 #define AXIW1_GO BIT(0)
46 #define AXI_CLEAR 0
47 #define AXI_RESET BIT(31)
48 #define AXIW1_READDATA BIT(0)
49 /* Interrupt Enable */
50 #define AXIW1_READY_IRQ_EN BIT(4)
51 #define AXIW1_DONE_IRQ_EN BIT(0)
52
53 #define AXIW1_TIMEOUT msecs_to_jiffies(100)
54
55 #define DRIVER_NAME "amd_axi_w1"
56
57 struct amd_axi_w1_local {
58 struct device *dev;
59 void __iomem *base_addr;
60 int irq;
61 atomic_t flag; /* Set on IRQ, cleared once serviced */
62 wait_queue_head_t wait_queue;
63 struct w1_bus_master bus_host;
64 };
65
66 /**
67 * amd_axi_w1_wait_irq_interruptible_timeout() - Wait for IRQ with timeout.
68 *
69 * @amd_axi_w1_local: Pointer to device structure
70 * @IRQ: IRQ channel to wait on
71 *
72 * Return: %0 - OK, %-EINTR - Interrupted, %-EBUSY - Timed out
73 */
amd_axi_w1_wait_irq_interruptible_timeout(struct amd_axi_w1_local * amd_axi_w1_local,u32 IRQ)74 static int amd_axi_w1_wait_irq_interruptible_timeout(struct amd_axi_w1_local *amd_axi_w1_local,
75 u32 IRQ)
76 {
77 int ret;
78
79 /* Enable the IRQ requested and wait for flag to indicate it's been triggered */
80 iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG);
81 ret = wait_event_interruptible_timeout(amd_axi_w1_local->wait_queue,
82 atomic_read(&amd_axi_w1_local->flag) != 0,
83 AXIW1_TIMEOUT);
84 if (ret < 0) {
85 dev_err(amd_axi_w1_local->dev, "Wait IRQ Interrupted\n");
86 return -EINTR;
87 }
88
89 if (!ret) {
90 dev_err(amd_axi_w1_local->dev, "Wait IRQ Timeout\n");
91 return -EBUSY;
92 }
93
94 atomic_set(&amd_axi_w1_local->flag, 0);
95 return 0;
96 }
97
98 /**
99 * amd_axi_w1_touch_bit() - Performs the touch-bit function - write a 0 or 1 and reads the level.
100 *
101 * @data: Pointer to device structure
102 * @bit: The level to write
103 *
104 * Return: The level read
105 */
amd_axi_w1_touch_bit(void * data,u8 bit)106 static u8 amd_axi_w1_touch_bit(void *data, u8 bit)
107 {
108 struct amd_axi_w1_local *amd_axi_w1_local = data;
109 u8 val = 0;
110 int rc;
111
112 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
113 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
114 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
115 AXIW1_READY_IRQ_EN);
116 if (rc < 0)
117 return 1; /* Callee doesn't test for error. Return inactive bus state */
118 }
119
120 if (bit)
121 /* Read. Write read Bit command in register 0 */
122 iowrite32(AXIW1_READBIT, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
123 else
124 /* Write. Write tx Bit command in instruction register with bit to transmit */
125 iowrite32(AXIW1_WRITEBIT + (bit & 0x01),
126 amd_axi_w1_local->base_addr + AXIW1_INST_REG);
127
128 /* Write Go signal and clear control reset signal in control register */
129 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
130
131 /* Wait for done signal to be 1 */
132 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
133 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local, AXIW1_DONE_IRQ_EN);
134 if (rc < 0)
135 return 1; /* Callee doesn't test for error. Return inactive bus state */
136 }
137
138 /* If read, Retrieve data from register */
139 if (bit)
140 val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & AXIW1_READDATA);
141
142 /* Clear Go signal in register 1 */
143 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
144
145 return val;
146 }
147
148 /**
149 * amd_axi_w1_read_byte - Performs the read byte function.
150 *
151 * @data: Pointer to device structure
152 * Return: The value read
153 */
amd_axi_w1_read_byte(void * data)154 static u8 amd_axi_w1_read_byte(void *data)
155 {
156 struct amd_axi_w1_local *amd_axi_w1_local = data;
157 u8 val = 0;
158 int rc;
159
160 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
161 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
162 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
163 AXIW1_READY_IRQ_EN);
164 if (rc < 0)
165 return 0xFF; /* Return inactive bus state */
166 }
167
168 /* Write read Byte command in instruction register*/
169 iowrite32(AXIW1_READBYTE, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
170
171 /* Write Go signal and clear control reset signal in control register */
172 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
173
174 /* Wait for done signal to be 1 */
175 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
176 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local, AXIW1_DONE_IRQ_EN);
177 if (rc < 0)
178 return 0xFF; /* Return inactive bus state */
179 }
180
181 /* Retrieve LSB bit in data register to get RX byte */
182 val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & 0x000000FF);
183
184 /* Clear Go signal in control register */
185 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
186
187 return val;
188 }
189
190 /**
191 * amd_axi_w1_write_byte - Performs the write byte function.
192 *
193 * @data: The ds2482 channel pointer
194 * @val: The value to write
195 */
amd_axi_w1_write_byte(void * data,u8 val)196 static void amd_axi_w1_write_byte(void *data, u8 val)
197 {
198 struct amd_axi_w1_local *amd_axi_w1_local = data;
199 int rc;
200
201 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
202 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
203 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
204 AXIW1_READY_IRQ_EN);
205 if (rc < 0)
206 return;
207 }
208
209 /* Write tx Byte command in instruction register with bit to transmit */
210 iowrite32(AXIW1_WRITEBYTE + val, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
211
212 /* Write Go signal and clear control reset signal in register 1 */
213 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
214
215 /* Wait for done signal to be 1 */
216 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
217 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
218 AXIW1_DONE_IRQ_EN);
219 if (rc < 0)
220 return;
221 }
222
223 /* Clear Go signal in control register */
224 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
225 }
226
227 /**
228 * amd_axi_w1_reset_bus() - Issues a reset bus sequence.
229 *
230 * @data: the bus host data struct
231 * Return: 0=Device present, 1=No device present or error
232 */
amd_axi_w1_reset_bus(void * data)233 static u8 amd_axi_w1_reset_bus(void *data)
234 {
235 struct amd_axi_w1_local *amd_axi_w1_local = data;
236 u8 val = 0;
237 int rc;
238
239 /* Reset 1-wire Axi IP */
240 iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
241
242 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
243 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
244 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
245 AXIW1_READY_IRQ_EN);
246 if (rc < 0)
247 return 1; /* Something went wrong with the hardware */
248 }
249 /* Write Initialization command in instruction register */
250 iowrite32(AXIW1_INITPRES, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
251
252 /* Write Go signal and clear control reset signal in register 1 */
253 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
254
255 /* Wait for done signal to be 1 */
256 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
257 rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local, AXIW1_DONE_IRQ_EN);
258 if (rc < 0)
259 return 1; /* Something went wrong with the hardware */
260 }
261 /* Retrieve MSB bit in status register to get failure bit */
262 if ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_PRESENCE) != 0)
263 val = 1;
264
265 /* Clear Go signal in control register */
266 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
267
268 return val;
269 }
270
271 /* Reset the 1-wire AXI IP. Put the IP in reset state and clear registers */
amd_axi_w1_reset(struct amd_axi_w1_local * amd_axi_w1_local)272 static void amd_axi_w1_reset(struct amd_axi_w1_local *amd_axi_w1_local)
273 {
274 iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
275 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
276 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG);
277 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_STAT_REG);
278 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_DATA_REG);
279 }
280
amd_axi_w1_irq(int irq,void * lp)281 static irqreturn_t amd_axi_w1_irq(int irq, void *lp)
282 {
283 struct amd_axi_w1_local *amd_axi_w1_local = lp;
284
285 /* Reset interrupt trigger */
286 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG);
287
288 atomic_set(&amd_axi_w1_local->flag, 1);
289 wake_up_interruptible(&amd_axi_w1_local->wait_queue);
290
291 return IRQ_HANDLED;
292 }
293
amd_axi_w1_probe(struct platform_device * pdev)294 static int amd_axi_w1_probe(struct platform_device *pdev)
295 {
296 struct device *dev = &pdev->dev;
297 struct amd_axi_w1_local *lp;
298 struct clk *clk;
299 u32 ver_major, ver_minor;
300 int val, rc = 0;
301
302 lp = devm_kzalloc(dev, sizeof(*lp), GFP_KERNEL);
303 if (!lp)
304 return -ENOMEM;
305
306 lp->dev = dev;
307 lp->base_addr = devm_platform_ioremap_resource(pdev, 0);
308 if (IS_ERR(lp->base_addr))
309 return PTR_ERR(lp->base_addr);
310
311 lp->irq = platform_get_irq(pdev, 0);
312 if (lp->irq < 0)
313 return lp->irq;
314
315 rc = devm_request_irq(dev, lp->irq, &amd_axi_w1_irq, IRQF_TRIGGER_HIGH, DRIVER_NAME, lp);
316 if (rc)
317 return rc;
318
319 /* Initialize wait queue and flag */
320 init_waitqueue_head(&lp->wait_queue);
321
322 clk = devm_clk_get_enabled(dev, NULL);
323 if (IS_ERR(clk))
324 return PTR_ERR(clk);
325
326 /* Verify IP presence in HW */
327 if (ioread32(lp->base_addr + AXIW1_IPID_REG) != AXIW1_IPID) {
328 dev_err(dev, "AMD 1-wire IP not detected in hardware\n");
329 return -ENODEV;
330 }
331
332 /*
333 * Allow for future driver expansion supporting new hardware features
334 * This driver currently only supports hardware 1.x, but include logic
335 * to detect if a potentially incompatible future version is used
336 * by reading major version ID. It is highly undesirable for new IP versions
337 * to break the API, but this code will at least allow for graceful failure
338 * should that happen. Future new features can be enabled by hardware
339 * incrementing the minor version and augmenting the driver to detect capability
340 * using the minor version number
341 */
342 val = ioread32(lp->base_addr + AXIW1_IPVER_REG);
343 ver_major = FIELD_GET(AXIW1_MAJORVER_MASK, val);
344 ver_minor = FIELD_GET(AXIW1_MINORVER_MASK, val);
345
346 if (ver_major != 1) {
347 dev_err(dev, "AMD AXI W1 host version %u.%u is not supported by this driver",
348 ver_major, ver_minor);
349 return -ENODEV;
350 }
351
352 lp->bus_host.data = lp;
353 lp->bus_host.touch_bit = amd_axi_w1_touch_bit;
354 lp->bus_host.read_byte = amd_axi_w1_read_byte;
355 lp->bus_host.write_byte = amd_axi_w1_write_byte;
356 lp->bus_host.reset_bus = amd_axi_w1_reset_bus;
357
358 amd_axi_w1_reset(lp);
359
360 platform_set_drvdata(pdev, lp);
361 rc = w1_add_master_device(&lp->bus_host);
362 if (rc) {
363 dev_err(dev, "Could not add host device\n");
364 return rc;
365 }
366
367 return 0;
368 }
369
amd_axi_w1_remove(struct platform_device * pdev)370 static void amd_axi_w1_remove(struct platform_device *pdev)
371 {
372 struct amd_axi_w1_local *lp = platform_get_drvdata(pdev);
373
374 w1_remove_master_device(&lp->bus_host);
375 }
376
377 static const struct of_device_id amd_axi_w1_of_match[] = {
378 { .compatible = "amd,axi-1wire-host" },
379 { /* end of list */ },
380 };
381 MODULE_DEVICE_TABLE(of, amd_axi_w1_of_match);
382
383 static struct platform_driver amd_axi_w1_driver = {
384 .probe = amd_axi_w1_probe,
385 .remove = amd_axi_w1_remove,
386 .driver = {
387 .name = DRIVER_NAME,
388 .of_match_table = amd_axi_w1_of_match,
389 },
390 };
391 module_platform_driver(amd_axi_w1_driver);
392
393 MODULE_LICENSE("GPL");
394 MODULE_AUTHOR("Kris Chaplin <kris.chaplin@amd.com>");
395 MODULE_DESCRIPTION("Driver for AMD AXI 1 Wire IP core");
396