1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. 14 */ 15 16 enum fields { 17 RS = 0x001, 18 RT = 0x002, 19 RD = 0x004, 20 RE = 0x008, 21 SIMM = 0x010, 22 UIMM = 0x020, 23 BIMM = 0x040, 24 JIMM = 0x080, 25 FUNC = 0x100, 26 SET = 0x200, 27 SCIMM = 0x400, 28 SIMM9 = 0x800, 29 }; 30 31 #define OP_MASK 0x3f 32 #define OP_SH 26 33 #define RD_MASK 0x1f 34 #define RD_SH 11 35 #define RE_MASK 0x1f 36 #define RE_SH 6 37 #define IMM_MASK 0xffff 38 #define IMM_SH 0 39 #define JIMM_MASK 0x3ffffff 40 #define JIMM_SH 0 41 #define FUNC_MASK 0x3f 42 #define FUNC_SH 0 43 #define SET_MASK 0x7 44 #define SET_SH 0 45 #define SIMM9_SH 7 46 #define SIMM9_MASK 0x1ff 47 48 enum opcode { 49 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, 50 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez, 51 insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1, 52 insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddiv, 53 insn_ddiv_r6, insn_ddivu, insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, 54 insn_dinsu, insn_div, insn_div_r6, insn_divu, insn_divu_r6, insn_dmfc0, 55 insn_dmod, insn_dmodu, insn_dmtc0, insn_dmultu, 56 insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll, 57 insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl, 58 insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins, 59 insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld, 60 insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld, 61 insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, 62 insn_mflo, insn_mod, insn_modu, insn_movn, insn_movz, insn_mtc0, 63 insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, 64 insn_muhu, insn_nor, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, 65 insn_sb, insn_sc, insn_scd, insn_seb, insn_seh, 66 insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll, 67 insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, 68 insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, 69 insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, 70 insn_wsbh, insn_xor, insn_xori, insn_yield, 71 insn_invalid /* insn_invalid must be last */ 72 }; 73 74 struct insn { 75 u32 match; 76 enum fields fields; 77 }; 78 79 static inline u32 build_rs(u32 arg) 80 { 81 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 82 83 return (arg & RS_MASK) << RS_SH; 84 } 85 86 static inline u32 build_rt(u32 arg) 87 { 88 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 89 90 return (arg & RT_MASK) << RT_SH; 91 } 92 93 static inline u32 build_rd(u32 arg) 94 { 95 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 96 97 return (arg & RD_MASK) << RD_SH; 98 } 99 100 static inline u32 build_re(u32 arg) 101 { 102 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 103 104 return (arg & RE_MASK) << RE_SH; 105 } 106 107 static inline u32 build_simm(s32 arg) 108 { 109 WARN(arg > 0x7fff || arg < -0x8000, 110 KERN_WARNING "Micro-assembler field overflow\n"); 111 112 return arg & 0xffff; 113 } 114 115 static inline u32 build_uimm(u32 arg) 116 { 117 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 118 119 return arg & IMM_MASK; 120 } 121 122 static inline u32 build_scimm(u32 arg) 123 { 124 WARN(arg & ~SCIMM_MASK, 125 KERN_WARNING "Micro-assembler field overflow\n"); 126 127 return (arg & SCIMM_MASK) << SCIMM_SH; 128 } 129 130 static inline u32 build_scimm9(s32 arg) 131 { 132 WARN((arg > 0xff || arg < -0x100), 133 KERN_WARNING "Micro-assembler field overflow\n"); 134 135 return (arg & SIMM9_MASK) << SIMM9_SH; 136 } 137 138 static inline u32 build_func(u32 arg) 139 { 140 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 141 142 return arg & FUNC_MASK; 143 } 144 145 static inline u32 build_set(u32 arg) 146 { 147 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 148 149 return arg & SET_MASK; 150 } 151 152 static void build_insn(u32 **buf, enum opcode opc, ...); 153 154 #define I_u1u2u3(op) \ 155 Ip_u1u2u3(op) \ 156 { \ 157 build_insn(buf, insn##op, a, b, c); \ 158 } \ 159 UASM_EXPORT_SYMBOL(uasm_i##op); 160 161 #define I_s3s1s2(op) \ 162 Ip_s3s1s2(op) \ 163 { \ 164 build_insn(buf, insn##op, b, c, a); \ 165 } \ 166 UASM_EXPORT_SYMBOL(uasm_i##op); 167 168 #define I_u2u1u3(op) \ 169 Ip_u2u1u3(op) \ 170 { \ 171 build_insn(buf, insn##op, b, a, c); \ 172 } \ 173 UASM_EXPORT_SYMBOL(uasm_i##op); 174 175 #define I_u3u2u1(op) \ 176 Ip_u3u2u1(op) \ 177 { \ 178 build_insn(buf, insn##op, c, b, a); \ 179 } \ 180 UASM_EXPORT_SYMBOL(uasm_i##op); 181 182 #define I_u3u1u2(op) \ 183 Ip_u3u1u2(op) \ 184 { \ 185 build_insn(buf, insn##op, b, c, a); \ 186 } \ 187 UASM_EXPORT_SYMBOL(uasm_i##op); 188 189 #define I_u1u2s3(op) \ 190 Ip_u1u2s3(op) \ 191 { \ 192 build_insn(buf, insn##op, a, b, c); \ 193 } \ 194 UASM_EXPORT_SYMBOL(uasm_i##op); 195 196 #define I_u2s3u1(op) \ 197 Ip_u2s3u1(op) \ 198 { \ 199 build_insn(buf, insn##op, c, a, b); \ 200 } \ 201 UASM_EXPORT_SYMBOL(uasm_i##op); 202 203 #define I_u2u1s3(op) \ 204 Ip_u2u1s3(op) \ 205 { \ 206 build_insn(buf, insn##op, b, a, c); \ 207 } \ 208 UASM_EXPORT_SYMBOL(uasm_i##op); 209 210 #define I_u2u1msbu3(op) \ 211 Ip_u2u1msbu3(op) \ 212 { \ 213 build_insn(buf, insn##op, b, a, c+d-1, c); \ 214 } \ 215 UASM_EXPORT_SYMBOL(uasm_i##op); 216 217 #define I_u2u1msb32u3(op) \ 218 Ip_u2u1msbu3(op) \ 219 { \ 220 build_insn(buf, insn##op, b, a, c+d-33, c); \ 221 } \ 222 UASM_EXPORT_SYMBOL(uasm_i##op); 223 224 #define I_u2u1msb32msb3(op) \ 225 Ip_u2u1msbu3(op) \ 226 { \ 227 build_insn(buf, insn##op, b, a, c+d-33, c-32); \ 228 } \ 229 UASM_EXPORT_SYMBOL(uasm_i##op); 230 231 #define I_u2u1msbdu3(op) \ 232 Ip_u2u1msbu3(op) \ 233 { \ 234 build_insn(buf, insn##op, b, a, d-1, c); \ 235 } \ 236 UASM_EXPORT_SYMBOL(uasm_i##op); 237 238 #define I_u1u2(op) \ 239 Ip_u1u2(op) \ 240 { \ 241 build_insn(buf, insn##op, a, b); \ 242 } \ 243 UASM_EXPORT_SYMBOL(uasm_i##op); 244 245 #define I_u2u1(op) \ 246 Ip_u1u2(op) \ 247 { \ 248 build_insn(buf, insn##op, b, a); \ 249 } \ 250 UASM_EXPORT_SYMBOL(uasm_i##op); 251 252 #define I_u1s2(op) \ 253 Ip_u1s2(op) \ 254 { \ 255 build_insn(buf, insn##op, a, b); \ 256 } \ 257 UASM_EXPORT_SYMBOL(uasm_i##op); 258 259 #define I_u1(op) \ 260 Ip_u1(op) \ 261 { \ 262 build_insn(buf, insn##op, a); \ 263 } \ 264 UASM_EXPORT_SYMBOL(uasm_i##op); 265 266 #define I_0(op) \ 267 Ip_0(op) \ 268 { \ 269 build_insn(buf, insn##op); \ 270 } \ 271 UASM_EXPORT_SYMBOL(uasm_i##op); 272 273 I_u2u1s3(_addiu) 274 I_u3u1u2(_addu) 275 I_u2u1u3(_andi) 276 I_u3u1u2(_and) 277 I_u1u2s3(_beq) 278 I_u1u2s3(_beql) 279 I_u1s2(_bgez) 280 I_u1s2(_bgezl) 281 I_u1s2(_bgtz) 282 I_u1s2(_blez) 283 I_u1s2(_bltz) 284 I_u1s2(_bltzl) 285 I_u1u2s3(_bne) 286 I_u1(_break) 287 I_u2s3u1(_cache) 288 I_u1u2(_cfc1) 289 I_u2u1(_cfcmsa) 290 I_u1u2(_ctc1) 291 I_u2u1(_ctcmsa) 292 I_u1u2(_ddiv) 293 I_u3u1u2(_ddiv_r6) 294 I_u1u2(_ddivu) 295 I_u3u1u2(_ddivu_r6) 296 I_u1u2u3(_dmfc0) 297 I_u3u1u2(_dmod) 298 I_u3u1u2(_dmodu) 299 I_u1u2u3(_dmtc0) 300 I_u1u2(_dmultu) 301 I_u3u1u2(_dmulu) 302 I_u2u1s3(_daddiu) 303 I_u3u1u2(_daddu) 304 I_u1(_di); 305 I_u1u2(_div) 306 I_u3u1u2(_div_r6) 307 I_u1u2(_divu) 308 I_u3u1u2(_divu_r6) 309 I_u2u1(_dsbh); 310 I_u2u1(_dshd); 311 I_u2u1u3(_dsll) 312 I_u2u1u3(_dsll32) 313 I_u3u2u1(_dsllv) 314 I_u2u1u3(_dsra) 315 I_u2u1u3(_dsra32) 316 I_u3u2u1(_dsrav) 317 I_u2u1u3(_dsrl) 318 I_u2u1u3(_dsrl32) 319 I_u3u2u1(_dsrlv) 320 I_u2u1u3(_drotr) 321 I_u2u1u3(_drotr32) 322 I_u3u1u2(_dsubu) 323 I_0(_eret) 324 I_u2u1msbdu3(_ext) 325 I_u2u1msbu3(_ins) 326 I_u1(_j) 327 I_u1(_jal) 328 I_u2u1(_jalr) 329 I_u1(_jr) 330 I_u2s3u1(_lb) 331 I_u2s3u1(_lbu) 332 I_u2s3u1(_ld) 333 I_u2s3u1(_lh) 334 I_u2s3u1(_lhu) 335 I_u2s3u1(_ll) 336 I_u2s3u1(_lld) 337 I_u1s2(_lui) 338 I_u2s3u1(_lw) 339 I_u2s3u1(_lwu) 340 I_u1u2u3(_mfc0) 341 I_u1u2u3(_mfhc0) 342 I_u3u1u2(_mod) 343 I_u3u1u2(_modu) 344 I_u3u1u2(_movn) 345 I_u3u1u2(_movz) 346 I_u1(_mfhi) 347 I_u1(_mflo) 348 I_u1u2u3(_mtc0) 349 I_u1u2u3(_mthc0) 350 I_u1(_mthi) 351 I_u1(_mtlo) 352 I_u3u1u2(_mul) 353 I_u1u2(_multu) 354 I_u3u1u2(_mulu) 355 I_u3u1u2(_muhu) 356 I_u3u1u2(_nor) 357 I_u3u1u2(_or) 358 I_u2u1u3(_ori) 359 I_0(_rfe) 360 I_u2s3u1(_sb) 361 I_u2s3u1(_sc) 362 I_u2s3u1(_scd) 363 I_u2s3u1(_sd) 364 I_u2u1(_seb) 365 I_u2u1(_seh) 366 I_u3u1u2(_seleqz) 367 I_u3u1u2(_selnez) 368 I_u2s3u1(_sh) 369 I_u2u1u3(_sll) 370 I_u3u2u1(_sllv) 371 I_s3s1s2(_slt) 372 I_u2u1s3(_slti) 373 I_u2u1s3(_sltiu) 374 I_u3u1u2(_sltu) 375 I_u2u1u3(_sra) 376 I_u3u2u1(_srav) 377 I_u2u1u3(_srl) 378 I_u3u2u1(_srlv) 379 I_u2u1u3(_rotr) 380 I_u3u1u2(_subu) 381 I_u2s3u1(_sw) 382 I_u1(_sync) 383 I_0(_tlbp) 384 I_0(_tlbr) 385 I_0(_tlbwi) 386 I_0(_tlbwr) 387 I_u1(_wait); 388 I_u2u1(_wsbh) 389 I_u3u1u2(_xor) 390 I_u2u1u3(_xori) 391 I_u2u1(_yield) 392 I_u2u1msbu3(_dins); 393 I_u2u1msb32u3(_dinsm); 394 I_u2u1msb32msb3(_dinsu); 395 I_u1(_syscall); 396 I_u1u2s3(_bbit0); 397 I_u1u2s3(_bbit1); 398 I_u3u1u2(_lwx) 399 I_u3u1u2(_ldx) 400 I_u1u2(_ldpte) 401 I_u2u1u3(_lddir) 402 403 #ifdef CONFIG_CPU_CAVIUM_OCTEON 404 #include <asm/octeon/octeon.h> 405 void uasm_i_pref(u32 **buf, unsigned int a, signed int b, 406 unsigned int c) 407 { 408 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5) 409 /* 410 * As per erratum Core-14449, replace prefetches 0-4, 411 * 6-24 with 'pref 28'. 412 */ 413 build_insn(buf, insn_pref, c, 28, b); 414 else 415 build_insn(buf, insn_pref, c, a, b); 416 } 417 UASM_EXPORT_SYMBOL(uasm_i_pref); 418 #else 419 I_u2s3u1(_pref) 420 #endif 421 422 /* Handle labels. */ 423 void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 424 { 425 (*lab)->addr = addr; 426 (*lab)->lab = lid; 427 (*lab)++; 428 } 429 UASM_EXPORT_SYMBOL(uasm_build_label); 430 431 int uasm_in_compat_space_p(long addr) 432 { 433 /* Is this address in 32bit compat space? */ 434 return addr == (int)addr; 435 } 436 UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); 437 438 static int uasm_rel_highest(long val) 439 { 440 #ifdef CONFIG_64BIT 441 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 442 #else 443 return 0; 444 #endif 445 } 446 447 static int uasm_rel_higher(long val) 448 { 449 #ifdef CONFIG_64BIT 450 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 451 #else 452 return 0; 453 #endif 454 } 455 456 int uasm_rel_hi(long val) 457 { 458 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 459 } 460 UASM_EXPORT_SYMBOL(uasm_rel_hi); 461 462 int uasm_rel_lo(long val) 463 { 464 return ((val & 0xffff) ^ 0x8000) - 0x8000; 465 } 466 UASM_EXPORT_SYMBOL(uasm_rel_lo); 467 468 void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) 469 { 470 if (!uasm_in_compat_space_p(addr)) { 471 uasm_i_lui(buf, rs, uasm_rel_highest(addr)); 472 if (uasm_rel_higher(addr)) 473 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); 474 if (uasm_rel_hi(addr)) { 475 uasm_i_dsll(buf, rs, rs, 16); 476 uasm_i_daddiu(buf, rs, rs, 477 uasm_rel_hi(addr)); 478 uasm_i_dsll(buf, rs, rs, 16); 479 } else 480 uasm_i_dsll32(buf, rs, rs, 0); 481 } else 482 uasm_i_lui(buf, rs, uasm_rel_hi(addr)); 483 } 484 UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); 485 486 void UASM_i_LA(u32 **buf, unsigned int rs, long addr) 487 { 488 UASM_i_LA_mostly(buf, rs, addr); 489 if (uasm_rel_lo(addr)) { 490 if (!uasm_in_compat_space_p(addr)) 491 uasm_i_daddiu(buf, rs, rs, 492 uasm_rel_lo(addr)); 493 else 494 uasm_i_addiu(buf, rs, rs, 495 uasm_rel_lo(addr)); 496 } 497 } 498 UASM_EXPORT_SYMBOL(UASM_i_LA); 499 500 /* Handle relocations. */ 501 void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) 502 { 503 (*rel)->addr = addr; 504 (*rel)->type = R_MIPS_PC16; 505 (*rel)->lab = lid; 506 (*rel)++; 507 } 508 UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); 509 510 static inline void __resolve_relocs(struct uasm_reloc *rel, 511 struct uasm_label *lab); 512 513 void uasm_resolve_relocs(struct uasm_reloc *rel, 514 struct uasm_label *lab) 515 { 516 struct uasm_label *l; 517 518 for (; rel->lab != UASM_LABEL_INVALID; rel++) 519 for (l = lab; l->lab != UASM_LABEL_INVALID; l++) 520 if (rel->lab == l->lab) 521 __resolve_relocs(rel, l); 522 } 523 UASM_EXPORT_SYMBOL(uasm_resolve_relocs); 524 525 void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, 526 long off) 527 { 528 for (; rel->lab != UASM_LABEL_INVALID; rel++) 529 if (rel->addr >= first && rel->addr < end) 530 rel->addr += off; 531 } 532 UASM_EXPORT_SYMBOL(uasm_move_relocs); 533 534 void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, 535 long off) 536 { 537 for (; lab->lab != UASM_LABEL_INVALID; lab++) 538 if (lab->addr >= first && lab->addr < end) 539 lab->addr += off; 540 } 541 UASM_EXPORT_SYMBOL(uasm_move_labels); 542 543 void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, 544 u32 *first, u32 *end, u32 *target) 545 { 546 long off = (long)(target - first); 547 548 memcpy(target, first, (end - first) * sizeof(u32)); 549 550 uasm_move_relocs(rel, first, end, off); 551 uasm_move_labels(lab, first, end, off); 552 } 553 UASM_EXPORT_SYMBOL(uasm_copy_handler); 554 555 int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) 556 { 557 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 558 if (rel->addr == addr 559 && (rel->type == R_MIPS_PC16 560 || rel->type == R_MIPS_26)) 561 return 1; 562 } 563 564 return 0; 565 } 566 UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); 567 568 /* Convenience functions for labeled branches. */ 569 void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, 570 int lid) 571 { 572 uasm_r_mips_pc16(r, *p, lid); 573 uasm_i_bltz(p, reg, 0); 574 } 575 UASM_EXPORT_SYMBOL(uasm_il_bltz); 576 577 void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) 578 { 579 uasm_r_mips_pc16(r, *p, lid); 580 uasm_i_b(p, 0); 581 } 582 UASM_EXPORT_SYMBOL(uasm_il_b); 583 584 void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1, 585 unsigned int r2, int lid) 586 { 587 uasm_r_mips_pc16(r, *p, lid); 588 uasm_i_beq(p, r1, r2, 0); 589 } 590 UASM_EXPORT_SYMBOL(uasm_il_beq); 591 592 void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, 593 int lid) 594 { 595 uasm_r_mips_pc16(r, *p, lid); 596 uasm_i_beqz(p, reg, 0); 597 } 598 UASM_EXPORT_SYMBOL(uasm_il_beqz); 599 600 void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, 601 int lid) 602 { 603 uasm_r_mips_pc16(r, *p, lid); 604 uasm_i_beqzl(p, reg, 0); 605 } 606 UASM_EXPORT_SYMBOL(uasm_il_beqzl); 607 608 void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 609 unsigned int reg2, int lid) 610 { 611 uasm_r_mips_pc16(r, *p, lid); 612 uasm_i_bne(p, reg1, reg2, 0); 613 } 614 UASM_EXPORT_SYMBOL(uasm_il_bne); 615 616 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, 617 int lid) 618 { 619 uasm_r_mips_pc16(r, *p, lid); 620 uasm_i_bnez(p, reg, 0); 621 } 622 UASM_EXPORT_SYMBOL(uasm_il_bnez); 623 624 void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, 625 int lid) 626 { 627 uasm_r_mips_pc16(r, *p, lid); 628 uasm_i_bgezl(p, reg, 0); 629 } 630 UASM_EXPORT_SYMBOL(uasm_il_bgezl); 631 632 void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, 633 int lid) 634 { 635 uasm_r_mips_pc16(r, *p, lid); 636 uasm_i_bgez(p, reg, 0); 637 } 638 UASM_EXPORT_SYMBOL(uasm_il_bgez); 639 640 void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, 641 unsigned int bit, int lid) 642 { 643 uasm_r_mips_pc16(r, *p, lid); 644 uasm_i_bbit0(p, reg, bit, 0); 645 } 646 UASM_EXPORT_SYMBOL(uasm_il_bbit0); 647 648 void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, 649 unsigned int bit, int lid) 650 { 651 uasm_r_mips_pc16(r, *p, lid); 652 uasm_i_bbit1(p, reg, bit, 0); 653 } 654 UASM_EXPORT_SYMBOL(uasm_il_bbit1); 655