1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * max98095.c -- MAX98095 ALSA SoC Audio driver 4 * 5 * Copyright 2011 Maxim Integrated Products 6 */ 7 8 #include <linux/cleanup.h> 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/pm.h> 15 #include <linux/i2c.h> 16 #include <linux/clk.h> 17 #include <linux/mutex.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <linux/slab.h> 25 #include <asm/div64.h> 26 #include <sound/max98095.h> 27 #include <sound/jack.h> 28 #include "max98095.h" 29 30 enum max98095_type { 31 MAX98095, 32 }; 33 34 struct max98095_cdata { 35 unsigned int rate; 36 unsigned int fmt; 37 int eq_sel; 38 int bq_sel; 39 }; 40 41 struct max98095_priv { 42 struct regmap *regmap; 43 enum max98095_type devtype; 44 struct max98095_pdata *pdata; 45 struct clk *mclk; 46 unsigned int sysclk; 47 struct max98095_cdata dai[3]; 48 const char **eq_texts; 49 const char **bq_texts; 50 struct soc_enum eq_enum; 51 struct soc_enum bq_enum; 52 int eq_textcnt; 53 int bq_textcnt; 54 u8 lin_state; 55 unsigned int mic1pre; 56 unsigned int mic2pre; 57 struct snd_soc_jack *headphone_jack; 58 struct snd_soc_jack *mic_jack; 59 struct mutex lock; 60 }; 61 62 static const struct reg_default max98095_reg_def[] = { 63 { 0xf, 0x00 }, /* 0F */ 64 { 0x10, 0x00 }, /* 10 */ 65 { 0x11, 0x00 }, /* 11 */ 66 { 0x12, 0x00 }, /* 12 */ 67 { 0x13, 0x00 }, /* 13 */ 68 { 0x14, 0x00 }, /* 14 */ 69 { 0x15, 0x00 }, /* 15 */ 70 { 0x16, 0x00 }, /* 16 */ 71 { 0x17, 0x00 }, /* 17 */ 72 { 0x18, 0x00 }, /* 18 */ 73 { 0x19, 0x00 }, /* 19 */ 74 { 0x1a, 0x00 }, /* 1A */ 75 { 0x1b, 0x00 }, /* 1B */ 76 { 0x1c, 0x00 }, /* 1C */ 77 { 0x1d, 0x00 }, /* 1D */ 78 { 0x1e, 0x00 }, /* 1E */ 79 { 0x1f, 0x00 }, /* 1F */ 80 { 0x20, 0x00 }, /* 20 */ 81 { 0x21, 0x00 }, /* 21 */ 82 { 0x22, 0x00 }, /* 22 */ 83 { 0x23, 0x00 }, /* 23 */ 84 { 0x24, 0x00 }, /* 24 */ 85 { 0x25, 0x00 }, /* 25 */ 86 { 0x26, 0x00 }, /* 26 */ 87 { 0x27, 0x00 }, /* 27 */ 88 { 0x28, 0x00 }, /* 28 */ 89 { 0x29, 0x00 }, /* 29 */ 90 { 0x2a, 0x00 }, /* 2A */ 91 { 0x2b, 0x00 }, /* 2B */ 92 { 0x2c, 0x00 }, /* 2C */ 93 { 0x2d, 0x00 }, /* 2D */ 94 { 0x2e, 0x00 }, /* 2E */ 95 { 0x2f, 0x00 }, /* 2F */ 96 { 0x30, 0x00 }, /* 30 */ 97 { 0x31, 0x00 }, /* 31 */ 98 { 0x32, 0x00 }, /* 32 */ 99 { 0x33, 0x00 }, /* 33 */ 100 { 0x34, 0x00 }, /* 34 */ 101 { 0x35, 0x00 }, /* 35 */ 102 { 0x36, 0x00 }, /* 36 */ 103 { 0x37, 0x00 }, /* 37 */ 104 { 0x38, 0x00 }, /* 38 */ 105 { 0x39, 0x00 }, /* 39 */ 106 { 0x3a, 0x00 }, /* 3A */ 107 { 0x3b, 0x00 }, /* 3B */ 108 { 0x3c, 0x00 }, /* 3C */ 109 { 0x3d, 0x00 }, /* 3D */ 110 { 0x3e, 0x00 }, /* 3E */ 111 { 0x3f, 0x00 }, /* 3F */ 112 { 0x40, 0x00 }, /* 40 */ 113 { 0x41, 0x00 }, /* 41 */ 114 { 0x42, 0x00 }, /* 42 */ 115 { 0x43, 0x00 }, /* 43 */ 116 { 0x44, 0x00 }, /* 44 */ 117 { 0x45, 0x00 }, /* 45 */ 118 { 0x46, 0x00 }, /* 46 */ 119 { 0x47, 0x00 }, /* 47 */ 120 { 0x48, 0x00 }, /* 48 */ 121 { 0x49, 0x00 }, /* 49 */ 122 { 0x4a, 0x00 }, /* 4A */ 123 { 0x4b, 0x00 }, /* 4B */ 124 { 0x4c, 0x00 }, /* 4C */ 125 { 0x4d, 0x00 }, /* 4D */ 126 { 0x4e, 0x00 }, /* 4E */ 127 { 0x4f, 0x00 }, /* 4F */ 128 { 0x50, 0x00 }, /* 50 */ 129 { 0x51, 0x00 }, /* 51 */ 130 { 0x52, 0x00 }, /* 52 */ 131 { 0x53, 0x00 }, /* 53 */ 132 { 0x54, 0x00 }, /* 54 */ 133 { 0x55, 0x00 }, /* 55 */ 134 { 0x56, 0x00 }, /* 56 */ 135 { 0x57, 0x00 }, /* 57 */ 136 { 0x58, 0x00 }, /* 58 */ 137 { 0x59, 0x00 }, /* 59 */ 138 { 0x5a, 0x00 }, /* 5A */ 139 { 0x5b, 0x00 }, /* 5B */ 140 { 0x5c, 0x00 }, /* 5C */ 141 { 0x5d, 0x00 }, /* 5D */ 142 { 0x5e, 0x00 }, /* 5E */ 143 { 0x5f, 0x00 }, /* 5F */ 144 { 0x60, 0x00 }, /* 60 */ 145 { 0x61, 0x00 }, /* 61 */ 146 { 0x62, 0x00 }, /* 62 */ 147 { 0x63, 0x00 }, /* 63 */ 148 { 0x64, 0x00 }, /* 64 */ 149 { 0x65, 0x00 }, /* 65 */ 150 { 0x66, 0x00 }, /* 66 */ 151 { 0x67, 0x00 }, /* 67 */ 152 { 0x68, 0x00 }, /* 68 */ 153 { 0x69, 0x00 }, /* 69 */ 154 { 0x6a, 0x00 }, /* 6A */ 155 { 0x6b, 0x00 }, /* 6B */ 156 { 0x6c, 0x00 }, /* 6C */ 157 { 0x6d, 0x00 }, /* 6D */ 158 { 0x6e, 0x00 }, /* 6E */ 159 { 0x6f, 0x00 }, /* 6F */ 160 { 0x70, 0x00 }, /* 70 */ 161 { 0x71, 0x00 }, /* 71 */ 162 { 0x72, 0x00 }, /* 72 */ 163 { 0x73, 0x00 }, /* 73 */ 164 { 0x74, 0x00 }, /* 74 */ 165 { 0x75, 0x00 }, /* 75 */ 166 { 0x76, 0x00 }, /* 76 */ 167 { 0x77, 0x00 }, /* 77 */ 168 { 0x78, 0x00 }, /* 78 */ 169 { 0x79, 0x00 }, /* 79 */ 170 { 0x7a, 0x00 }, /* 7A */ 171 { 0x7b, 0x00 }, /* 7B */ 172 { 0x7c, 0x00 }, /* 7C */ 173 { 0x7d, 0x00 }, /* 7D */ 174 { 0x7e, 0x00 }, /* 7E */ 175 { 0x7f, 0x00 }, /* 7F */ 176 { 0x80, 0x00 }, /* 80 */ 177 { 0x81, 0x00 }, /* 81 */ 178 { 0x82, 0x00 }, /* 82 */ 179 { 0x83, 0x00 }, /* 83 */ 180 { 0x84, 0x00 }, /* 84 */ 181 { 0x85, 0x00 }, /* 85 */ 182 { 0x86, 0x00 }, /* 86 */ 183 { 0x87, 0x00 }, /* 87 */ 184 { 0x88, 0x00 }, /* 88 */ 185 { 0x89, 0x00 }, /* 89 */ 186 { 0x8a, 0x00 }, /* 8A */ 187 { 0x8b, 0x00 }, /* 8B */ 188 { 0x8c, 0x00 }, /* 8C */ 189 { 0x8d, 0x00 }, /* 8D */ 190 { 0x8e, 0x00 }, /* 8E */ 191 { 0x8f, 0x00 }, /* 8F */ 192 { 0x90, 0x00 }, /* 90 */ 193 { 0x91, 0x00 }, /* 91 */ 194 { 0x92, 0x30 }, /* 92 */ 195 { 0x93, 0xF0 }, /* 93 */ 196 { 0x94, 0x00 }, /* 94 */ 197 { 0x95, 0x00 }, /* 95 */ 198 { 0x96, 0x3F }, /* 96 */ 199 { 0x97, 0x00 }, /* 97 */ 200 { 0xff, 0x00 }, /* FF */ 201 }; 202 203 static bool max98095_readable(struct device *dev, unsigned int reg) 204 { 205 switch (reg) { 206 case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS: 207 case M98095_0FF_REV_ID: 208 return true; 209 default: 210 return false; 211 } 212 } 213 214 static bool max98095_writeable(struct device *dev, unsigned int reg) 215 { 216 switch (reg) { 217 case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS: 218 return true; 219 default: 220 return false; 221 } 222 } 223 224 static bool max98095_volatile(struct device *dev, unsigned int reg) 225 { 226 switch (reg) { 227 case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS: 228 case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID: 229 return true; 230 default: 231 return false; 232 } 233 } 234 235 static const struct regmap_config max98095_regmap = { 236 .reg_bits = 8, 237 .val_bits = 8, 238 239 .reg_defaults = max98095_reg_def, 240 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def), 241 .max_register = M98095_0FF_REV_ID, 242 .cache_type = REGCACHE_RBTREE, 243 244 .readable_reg = max98095_readable, 245 .writeable_reg = max98095_writeable, 246 .volatile_reg = max98095_volatile, 247 }; 248 249 /* 250 * Load equalizer DSP coefficient configurations registers 251 */ 252 static void m98095_eq_band(struct snd_soc_component *component, unsigned int dai, 253 unsigned int band, u16 *coefs) 254 { 255 unsigned int eq_reg; 256 unsigned int i; 257 258 if (WARN_ON(band > 4) || 259 WARN_ON(dai > 1)) 260 return; 261 262 /* Load the base register address */ 263 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; 264 265 /* Add the band address offset, note adjustment for word address */ 266 eq_reg += band * (M98095_COEFS_PER_BAND << 1); 267 268 /* Step through the registers and coefs */ 269 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 270 snd_soc_component_write(component, eq_reg++, M98095_BYTE1(coefs[i])); 271 snd_soc_component_write(component, eq_reg++, M98095_BYTE0(coefs[i])); 272 } 273 } 274 275 /* 276 * Load biquad filter coefficient configurations registers 277 */ 278 static void m98095_biquad_band(struct snd_soc_component *component, unsigned int dai, 279 unsigned int band, u16 *coefs) 280 { 281 unsigned int bq_reg; 282 unsigned int i; 283 284 if (WARN_ON(band > 1) || 285 WARN_ON(dai > 1)) 286 return; 287 288 /* Load the base register address */ 289 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; 290 291 /* Add the band address offset, note adjustment for word address */ 292 bq_reg += band * (M98095_COEFS_PER_BAND << 1); 293 294 /* Step through the registers and coefs */ 295 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 296 snd_soc_component_write(component, bq_reg++, M98095_BYTE1(coefs[i])); 297 snd_soc_component_write(component, bq_reg++, M98095_BYTE0(coefs[i])); 298 } 299 } 300 301 static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; 302 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum, 303 M98095_02E_DAI1_FILTERS, 7, 304 max98095_fltr_mode); 305 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum, 306 M98095_038_DAI2_FILTERS, 7, 307 max98095_fltr_mode); 308 309 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; 310 311 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum, 312 M98095_087_CFG_MIC, 0, 313 max98095_extmic_text); 314 315 static const struct snd_kcontrol_new max98095_extmic_mux = 316 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); 317 318 static const char * const max98095_linein_text[] = { "INA", "INB" }; 319 320 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum, 321 M98095_086_CFG_LINE, 6, 322 max98095_linein_text); 323 324 static const struct snd_kcontrol_new max98095_linein_mux = 325 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); 326 327 static const char * const max98095_line_mode_text[] = { 328 "Stereo", "Differential"}; 329 330 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum, 331 M98095_086_CFG_LINE, 7, 332 max98095_line_mode_text); 333 334 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum, 335 M98095_086_CFG_LINE, 4, 336 max98095_line_mode_text); 337 338 static const char * const max98095_dai_fltr[] = { 339 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", 340 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; 341 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum, 342 M98095_02E_DAI1_FILTERS, 0, 343 max98095_dai_fltr); 344 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum, 345 M98095_038_DAI2_FILTERS, 0, 346 max98095_dai_fltr); 347 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum, 348 M98095_042_DAI3_FILTERS, 0, 349 max98095_dai_fltr); 350 351 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, 352 struct snd_ctl_elem_value *ucontrol) 353 { 354 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 355 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 356 unsigned int sel = ucontrol->value.integer.value[0]; 357 358 max98095->mic1pre = sel; 359 snd_soc_component_update_bits(component, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, 360 (1+sel)<<M98095_MICPRE_SHIFT); 361 362 return 0; 363 } 364 365 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, 366 struct snd_ctl_elem_value *ucontrol) 367 { 368 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 369 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 370 371 ucontrol->value.integer.value[0] = max98095->mic1pre; 372 return 0; 373 } 374 375 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, 376 struct snd_ctl_elem_value *ucontrol) 377 { 378 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 379 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 380 unsigned int sel = ucontrol->value.integer.value[0]; 381 382 max98095->mic2pre = sel; 383 snd_soc_component_update_bits(component, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, 384 (1+sel)<<M98095_MICPRE_SHIFT); 385 386 return 0; 387 } 388 389 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, 390 struct snd_ctl_elem_value *ucontrol) 391 { 392 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 393 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 394 395 ucontrol->value.integer.value[0] = max98095->mic2pre; 396 return 0; 397 } 398 399 static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv, 400 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 401 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 402 ); 403 404 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); 405 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); 406 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); 407 408 static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv, 409 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 410 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 411 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 412 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 413 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 414 ); 415 416 static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv, 417 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), 418 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), 419 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), 420 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0) 421 ); 422 423 static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv, 424 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 425 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 426 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 427 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 428 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 429 ); 430 431 static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv, 432 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), 433 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), 434 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0) 435 ); 436 437 static const struct snd_kcontrol_new max98095_snd_controls[] = { 438 439 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, 440 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), 441 442 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, 443 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), 444 445 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, 446 0, 31, 0, max98095_rcv_lout_tlv), 447 448 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, 449 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), 450 451 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, 452 M98095_065_LVL_HP_R, 7, 1, 1), 453 454 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, 455 M98095_068_LVL_SPK_R, 7, 1, 1), 456 457 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), 458 459 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, 460 M98095_063_LVL_LINEOUT2, 7, 1, 1), 461 462 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, 463 max98095_mic_tlv), 464 465 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, 466 max98095_mic_tlv), 467 468 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 469 M98095_05F_LVL_MIC1, 5, 2, 0, 470 max98095_mic1pre_get, max98095_mic1pre_set, 471 max98095_micboost_tlv), 472 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 473 M98095_060_LVL_MIC2, 5, 2, 0, 474 max98095_mic2pre_get, max98095_mic2pre_set, 475 max98095_micboost_tlv), 476 477 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, 478 max98095_lin_tlv), 479 480 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, 481 max98095_adc_tlv), 482 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, 483 max98095_adc_tlv), 484 485 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, 486 max98095_adcboost_tlv), 487 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, 488 max98095_adcboost_tlv), 489 490 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), 491 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), 492 493 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), 494 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), 495 496 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), 497 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), 498 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), 499 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), 500 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), 501 502 SOC_ENUM("Linein Mode", max98095_linein_mode_enum), 503 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), 504 }; 505 506 /* Left speaker mixer switch */ 507 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { 508 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), 509 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), 510 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 511 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 512 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), 513 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), 514 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), 515 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), 516 }; 517 518 /* Right speaker mixer switch */ 519 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { 520 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), 521 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), 522 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 523 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 524 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), 525 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), 526 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), 527 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), 528 }; 529 530 /* Left headphone mixer switch */ 531 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { 532 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), 533 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), 534 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), 535 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), 536 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), 537 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), 538 }; 539 540 /* Right headphone mixer switch */ 541 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { 542 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), 543 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), 544 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), 545 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), 546 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), 547 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), 548 }; 549 550 /* Receiver earpiece mixer switch */ 551 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { 552 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), 553 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), 554 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), 555 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), 556 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), 557 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), 558 }; 559 560 /* Left lineout mixer switch */ 561 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { 562 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), 563 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), 564 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), 565 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), 566 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), 567 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), 568 }; 569 570 /* Right lineout mixer switch */ 571 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { 572 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), 573 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), 574 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), 575 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), 576 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), 577 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), 578 }; 579 580 /* Left ADC mixer switch */ 581 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { 582 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), 583 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), 584 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), 585 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), 586 }; 587 588 /* Right ADC mixer switch */ 589 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { 590 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), 591 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), 592 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), 593 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), 594 }; 595 596 static int max98095_mic_event(struct snd_soc_dapm_widget *w, 597 struct snd_kcontrol *kcontrol, int event) 598 { 599 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 600 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 601 602 switch (event) { 603 case SND_SOC_DAPM_POST_PMU: 604 if (w->reg == M98095_05F_LVL_MIC1) { 605 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 606 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); 607 } else { 608 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 609 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); 610 } 611 break; 612 case SND_SOC_DAPM_POST_PMD: 613 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0); 614 break; 615 default: 616 return -EINVAL; 617 } 618 619 return 0; 620 } 621 622 /* 623 * The line inputs are stereo inputs with the left and right 624 * channels sharing a common PGA power control signal. 625 */ 626 static int max98095_line_pga(struct snd_soc_dapm_widget *w, 627 int event, u8 channel) 628 { 629 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 630 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 631 u8 *state; 632 633 if (WARN_ON(!(channel == 1 || channel == 2))) 634 return -EINVAL; 635 636 state = &max98095->lin_state; 637 638 switch (event) { 639 case SND_SOC_DAPM_POST_PMU: 640 *state |= channel; 641 snd_soc_component_update_bits(component, w->reg, 642 (1 << w->shift), (1 << w->shift)); 643 break; 644 case SND_SOC_DAPM_POST_PMD: 645 *state &= ~channel; 646 if (*state == 0) { 647 snd_soc_component_update_bits(component, w->reg, 648 (1 << w->shift), 0); 649 } 650 break; 651 default: 652 return -EINVAL; 653 } 654 655 return 0; 656 } 657 658 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, 659 struct snd_kcontrol *k, int event) 660 { 661 return max98095_line_pga(w, event, 1); 662 } 663 664 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, 665 struct snd_kcontrol *k, int event) 666 { 667 return max98095_line_pga(w, event, 2); 668 } 669 670 /* 671 * The stereo line out mixer outputs to two stereo line outs. 672 * The 2nd pair has a separate set of enables. 673 */ 674 static int max98095_lineout_event(struct snd_soc_dapm_widget *w, 675 struct snd_kcontrol *kcontrol, int event) 676 { 677 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 678 679 switch (event) { 680 case SND_SOC_DAPM_POST_PMU: 681 snd_soc_component_update_bits(component, w->reg, 682 (1 << (w->shift+2)), (1 << (w->shift+2))); 683 break; 684 case SND_SOC_DAPM_POST_PMD: 685 snd_soc_component_update_bits(component, w->reg, 686 (1 << (w->shift+2)), 0); 687 break; 688 default: 689 return -EINVAL; 690 } 691 692 return 0; 693 } 694 695 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { 696 697 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), 698 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), 699 700 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 701 M98095_091_PWR_EN_OUT, 0, 0), 702 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 703 M98095_091_PWR_EN_OUT, 1, 0), 704 SND_SOC_DAPM_DAC("DACM2", "Aux Playback", 705 M98095_091_PWR_EN_OUT, 2, 0), 706 SND_SOC_DAPM_DAC("DACM3", "Voice Playback", 707 M98095_091_PWR_EN_OUT, 2, 0), 708 709 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, 710 6, 0, NULL, 0), 711 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, 712 7, 0, NULL, 0), 713 714 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, 715 4, 0, NULL, 0), 716 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, 717 5, 0, NULL, 0), 718 719 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, 720 3, 0, NULL, 0), 721 722 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, 723 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 724 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, 725 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 726 727 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 728 &max98095_extmic_mux), 729 730 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, 731 &max98095_linein_mux), 732 733 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 734 &max98095_left_hp_mixer_controls[0], 735 ARRAY_SIZE(max98095_left_hp_mixer_controls)), 736 737 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 738 &max98095_right_hp_mixer_controls[0], 739 ARRAY_SIZE(max98095_right_hp_mixer_controls)), 740 741 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 742 &max98095_left_speaker_mixer_controls[0], 743 ARRAY_SIZE(max98095_left_speaker_mixer_controls)), 744 745 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 746 &max98095_right_speaker_mixer_controls[0], 747 ARRAY_SIZE(max98095_right_speaker_mixer_controls)), 748 749 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, 750 &max98095_mono_rcv_mixer_controls[0], 751 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), 752 753 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, 754 &max98095_left_lineout_mixer_controls[0], 755 ARRAY_SIZE(max98095_left_lineout_mixer_controls)), 756 757 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, 758 &max98095_right_lineout_mixer_controls[0], 759 ARRAY_SIZE(max98095_right_lineout_mixer_controls)), 760 761 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 762 &max98095_left_ADC_mixer_controls[0], 763 ARRAY_SIZE(max98095_left_ADC_mixer_controls)), 764 765 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 766 &max98095_right_ADC_mixer_controls[0], 767 ARRAY_SIZE(max98095_right_ADC_mixer_controls)), 768 769 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, 770 5, 0, NULL, 0, max98095_mic_event, 771 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 772 773 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, 774 5, 0, NULL, 0, max98095_mic_event, 775 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 776 777 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, 778 7, 0, NULL, 0, max98095_pga_in1_event, 779 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 780 781 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, 782 7, 0, NULL, 0, max98095_pga_in2_event, 783 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 784 785 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), 786 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), 787 788 SND_SOC_DAPM_OUTPUT("HPL"), 789 SND_SOC_DAPM_OUTPUT("HPR"), 790 SND_SOC_DAPM_OUTPUT("SPKL"), 791 SND_SOC_DAPM_OUTPUT("SPKR"), 792 SND_SOC_DAPM_OUTPUT("RCV"), 793 SND_SOC_DAPM_OUTPUT("OUT1"), 794 SND_SOC_DAPM_OUTPUT("OUT2"), 795 SND_SOC_DAPM_OUTPUT("OUT3"), 796 SND_SOC_DAPM_OUTPUT("OUT4"), 797 798 SND_SOC_DAPM_INPUT("MIC1"), 799 SND_SOC_DAPM_INPUT("MIC2"), 800 SND_SOC_DAPM_INPUT("INA1"), 801 SND_SOC_DAPM_INPUT("INA2"), 802 SND_SOC_DAPM_INPUT("INB1"), 803 SND_SOC_DAPM_INPUT("INB2"), 804 }; 805 806 static const struct snd_soc_dapm_route max98095_audio_map[] = { 807 /* Left headphone output mixer */ 808 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 809 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 810 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 811 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 812 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, 813 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, 814 815 /* Right headphone output mixer */ 816 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 817 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 818 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 819 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 820 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, 821 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, 822 823 /* Left speaker output mixer */ 824 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 825 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 826 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 827 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 828 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 829 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 830 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, 831 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, 832 833 /* Right speaker output mixer */ 834 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 835 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 836 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 837 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 838 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 839 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 840 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, 841 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, 842 843 /* Earpiece/Receiver output mixer */ 844 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, 845 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, 846 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 847 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 848 {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, 849 {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, 850 851 /* Left Lineout output mixer */ 852 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 853 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 854 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 855 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 856 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, 857 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, 858 859 /* Right lineout output mixer */ 860 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 861 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 862 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 863 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 864 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, 865 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, 866 867 {"HP Left Out", NULL, "Left Headphone Mixer"}, 868 {"HP Right Out", NULL, "Right Headphone Mixer"}, 869 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 870 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 871 {"RCV Mono Out", NULL, "Receiver Mixer"}, 872 {"LINE Left Out", NULL, "Left Lineout Mixer"}, 873 {"LINE Right Out", NULL, "Right Lineout Mixer"}, 874 875 {"HPL", NULL, "HP Left Out"}, 876 {"HPR", NULL, "HP Right Out"}, 877 {"SPKL", NULL, "SPK Left Out"}, 878 {"SPKR", NULL, "SPK Right Out"}, 879 {"RCV", NULL, "RCV Mono Out"}, 880 {"OUT1", NULL, "LINE Left Out"}, 881 {"OUT2", NULL, "LINE Right Out"}, 882 {"OUT3", NULL, "LINE Left Out"}, 883 {"OUT4", NULL, "LINE Right Out"}, 884 885 /* Left ADC input mixer */ 886 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 887 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 888 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, 889 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, 890 891 /* Right ADC input mixer */ 892 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 893 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 894 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, 895 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, 896 897 /* Inputs */ 898 {"ADCL", NULL, "Left ADC Mixer"}, 899 {"ADCR", NULL, "Right ADC Mixer"}, 900 901 {"IN1 Input", NULL, "INA1"}, 902 {"IN2 Input", NULL, "INA2"}, 903 904 {"MIC1 Input", NULL, "MIC1"}, 905 {"MIC2 Input", NULL, "MIC2"}, 906 }; 907 908 /* codec mclk clock divider coefficients */ 909 static const struct { 910 u32 rate; 911 u8 sr; 912 } rate_table[] = { 913 {8000, 0x01}, 914 {11025, 0x02}, 915 {16000, 0x03}, 916 {22050, 0x04}, 917 {24000, 0x05}, 918 {32000, 0x06}, 919 {44100, 0x07}, 920 {48000, 0x08}, 921 {88200, 0x09}, 922 {96000, 0x0A}, 923 }; 924 925 static int rate_value(int rate, u8 *value) 926 { 927 int i; 928 929 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 930 if (rate_table[i].rate >= rate) { 931 *value = rate_table[i].sr; 932 return 0; 933 } 934 } 935 *value = rate_table[0].sr; 936 return -EINVAL; 937 } 938 939 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, 940 struct snd_pcm_hw_params *params, 941 struct snd_soc_dai *dai) 942 { 943 struct snd_soc_component *component = dai->component; 944 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 945 struct max98095_cdata *cdata; 946 unsigned long long ni; 947 unsigned int rate; 948 u8 regval; 949 950 cdata = &max98095->dai[0]; 951 952 rate = params_rate(params); 953 954 switch (params_width(params)) { 955 case 16: 956 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT, 957 M98095_DAI_WS, 0); 958 break; 959 case 24: 960 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT, 961 M98095_DAI_WS, M98095_DAI_WS); 962 break; 963 default: 964 return -EINVAL; 965 } 966 967 if (rate_value(rate, ®val)) 968 return -EINVAL; 969 970 snd_soc_component_update_bits(component, M98095_027_DAI1_CLKMODE, 971 M98095_CLKMODE_MASK, regval); 972 cdata->rate = rate; 973 974 /* Configure NI when operating as master */ 975 if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { 976 if (max98095->sysclk == 0) { 977 dev_err(component->dev, "Invalid system clock frequency\n"); 978 return -EINVAL; 979 } 980 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 981 * (unsigned long long int)rate; 982 do_div(ni, (unsigned long long int)max98095->sysclk); 983 snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI, 984 (ni >> 8) & 0x7F); 985 snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO, 986 ni & 0xFF); 987 } 988 989 /* Update sample rate mode */ 990 if (rate < 50000) 991 snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS, 992 M98095_DAI_DHF, 0); 993 else 994 snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS, 995 M98095_DAI_DHF, M98095_DAI_DHF); 996 997 return 0; 998 } 999 1000 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, 1001 struct snd_pcm_hw_params *params, 1002 struct snd_soc_dai *dai) 1003 { 1004 struct snd_soc_component *component = dai->component; 1005 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1006 struct max98095_cdata *cdata; 1007 unsigned long long ni; 1008 unsigned int rate; 1009 u8 regval; 1010 1011 cdata = &max98095->dai[1]; 1012 1013 rate = params_rate(params); 1014 1015 switch (params_width(params)) { 1016 case 16: 1017 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT, 1018 M98095_DAI_WS, 0); 1019 break; 1020 case 24: 1021 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT, 1022 M98095_DAI_WS, M98095_DAI_WS); 1023 break; 1024 default: 1025 return -EINVAL; 1026 } 1027 1028 if (rate_value(rate, ®val)) 1029 return -EINVAL; 1030 1031 snd_soc_component_update_bits(component, M98095_031_DAI2_CLKMODE, 1032 M98095_CLKMODE_MASK, regval); 1033 cdata->rate = rate; 1034 1035 /* Configure NI when operating as master */ 1036 if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { 1037 if (max98095->sysclk == 0) { 1038 dev_err(component->dev, "Invalid system clock frequency\n"); 1039 return -EINVAL; 1040 } 1041 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1042 * (unsigned long long int)rate; 1043 do_div(ni, (unsigned long long int)max98095->sysclk); 1044 snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI, 1045 (ni >> 8) & 0x7F); 1046 snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO, 1047 ni & 0xFF); 1048 } 1049 1050 /* Update sample rate mode */ 1051 if (rate < 50000) 1052 snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS, 1053 M98095_DAI_DHF, 0); 1054 else 1055 snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS, 1056 M98095_DAI_DHF, M98095_DAI_DHF); 1057 1058 return 0; 1059 } 1060 1061 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, 1062 struct snd_pcm_hw_params *params, 1063 struct snd_soc_dai *dai) 1064 { 1065 struct snd_soc_component *component = dai->component; 1066 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1067 struct max98095_cdata *cdata; 1068 unsigned long long ni; 1069 unsigned int rate; 1070 u8 regval; 1071 1072 cdata = &max98095->dai[2]; 1073 1074 rate = params_rate(params); 1075 1076 switch (params_width(params)) { 1077 case 16: 1078 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT, 1079 M98095_DAI_WS, 0); 1080 break; 1081 case 24: 1082 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT, 1083 M98095_DAI_WS, M98095_DAI_WS); 1084 break; 1085 default: 1086 return -EINVAL; 1087 } 1088 1089 if (rate_value(rate, ®val)) 1090 return -EINVAL; 1091 1092 snd_soc_component_update_bits(component, M98095_03B_DAI3_CLKMODE, 1093 M98095_CLKMODE_MASK, regval); 1094 cdata->rate = rate; 1095 1096 /* Configure NI when operating as master */ 1097 if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { 1098 if (max98095->sysclk == 0) { 1099 dev_err(component->dev, "Invalid system clock frequency\n"); 1100 return -EINVAL; 1101 } 1102 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1103 * (unsigned long long int)rate; 1104 do_div(ni, (unsigned long long int)max98095->sysclk); 1105 snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI, 1106 (ni >> 8) & 0x7F); 1107 snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO, 1108 ni & 0xFF); 1109 } 1110 1111 /* Update sample rate mode */ 1112 if (rate < 50000) 1113 snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS, 1114 M98095_DAI_DHF, 0); 1115 else 1116 snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS, 1117 M98095_DAI_DHF, M98095_DAI_DHF); 1118 1119 return 0; 1120 } 1121 1122 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, 1123 int clk_id, unsigned int freq, int dir) 1124 { 1125 struct snd_soc_component *component = dai->component; 1126 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1127 1128 /* Requested clock frequency is already setup */ 1129 if (freq == max98095->sysclk) 1130 return 0; 1131 1132 if (!IS_ERR(max98095->mclk)) { 1133 freq = clk_round_rate(max98095->mclk, freq); 1134 clk_set_rate(max98095->mclk, freq); 1135 } 1136 1137 /* Setup clocks for slave mode, and using the PLL 1138 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1139 * 0x02 (when master clk is 20MHz to 40MHz).. 1140 * 0x03 (when master clk is 40MHz to 60MHz).. 1141 */ 1142 if ((freq >= 10000000) && (freq < 20000000)) { 1143 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x10); 1144 } else if ((freq >= 20000000) && (freq < 40000000)) { 1145 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x20); 1146 } else if ((freq >= 40000000) && (freq < 60000000)) { 1147 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x30); 1148 } else { 1149 dev_err(component->dev, "Invalid master clock frequency\n"); 1150 return -EINVAL; 1151 } 1152 1153 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1154 1155 max98095->sysclk = freq; 1156 return 0; 1157 } 1158 1159 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1160 unsigned int fmt) 1161 { 1162 struct snd_soc_component *component = codec_dai->component; 1163 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1164 struct max98095_cdata *cdata; 1165 u8 regval = 0; 1166 1167 cdata = &max98095->dai[0]; 1168 1169 if (fmt != cdata->fmt) { 1170 cdata->fmt = fmt; 1171 1172 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1173 case SND_SOC_DAIFMT_CBC_CFC: 1174 /* Consumer mode PLL */ 1175 snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI, 1176 0x80); 1177 snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO, 1178 0x00); 1179 break; 1180 case SND_SOC_DAIFMT_CBP_CFP: 1181 /* Set to provider mode */ 1182 regval |= M98095_DAI_MAS; 1183 break; 1184 default: 1185 dev_err(component->dev, "Clock mode unsupported"); 1186 return -EINVAL; 1187 } 1188 1189 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1190 case SND_SOC_DAIFMT_I2S: 1191 regval |= M98095_DAI_DLY; 1192 break; 1193 case SND_SOC_DAIFMT_LEFT_J: 1194 break; 1195 default: 1196 return -EINVAL; 1197 } 1198 1199 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1200 case SND_SOC_DAIFMT_NB_NF: 1201 break; 1202 case SND_SOC_DAIFMT_NB_IF: 1203 regval |= M98095_DAI_WCI; 1204 break; 1205 case SND_SOC_DAIFMT_IB_NF: 1206 regval |= M98095_DAI_BCI; 1207 break; 1208 case SND_SOC_DAIFMT_IB_IF: 1209 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1210 break; 1211 default: 1212 return -EINVAL; 1213 } 1214 1215 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT, 1216 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1217 M98095_DAI_WCI, regval); 1218 1219 snd_soc_component_write(component, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); 1220 } 1221 1222 return 0; 1223 } 1224 1225 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1226 unsigned int fmt) 1227 { 1228 struct snd_soc_component *component = codec_dai->component; 1229 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1230 struct max98095_cdata *cdata; 1231 u8 regval = 0; 1232 1233 cdata = &max98095->dai[1]; 1234 1235 if (fmt != cdata->fmt) { 1236 cdata->fmt = fmt; 1237 1238 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1239 case SND_SOC_DAIFMT_CBC_CFC: 1240 /* Consumer mode PLL */ 1241 snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI, 1242 0x80); 1243 snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO, 1244 0x00); 1245 break; 1246 case SND_SOC_DAIFMT_CBP_CFP: 1247 /* Set to provider mode */ 1248 regval |= M98095_DAI_MAS; 1249 break; 1250 default: 1251 dev_err(component->dev, "Clock mode unsupported"); 1252 return -EINVAL; 1253 } 1254 1255 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1256 case SND_SOC_DAIFMT_I2S: 1257 regval |= M98095_DAI_DLY; 1258 break; 1259 case SND_SOC_DAIFMT_LEFT_J: 1260 break; 1261 default: 1262 return -EINVAL; 1263 } 1264 1265 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1266 case SND_SOC_DAIFMT_NB_NF: 1267 break; 1268 case SND_SOC_DAIFMT_NB_IF: 1269 regval |= M98095_DAI_WCI; 1270 break; 1271 case SND_SOC_DAIFMT_IB_NF: 1272 regval |= M98095_DAI_BCI; 1273 break; 1274 case SND_SOC_DAIFMT_IB_IF: 1275 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1276 break; 1277 default: 1278 return -EINVAL; 1279 } 1280 1281 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT, 1282 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1283 M98095_DAI_WCI, regval); 1284 1285 snd_soc_component_write(component, M98095_035_DAI2_CLOCK, 1286 M98095_DAI_BSEL64); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, 1293 unsigned int fmt) 1294 { 1295 struct snd_soc_component *component = codec_dai->component; 1296 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1297 struct max98095_cdata *cdata; 1298 u8 regval = 0; 1299 1300 cdata = &max98095->dai[2]; 1301 1302 if (fmt != cdata->fmt) { 1303 cdata->fmt = fmt; 1304 1305 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1306 case SND_SOC_DAIFMT_CBC_CFC: 1307 /* Consumer mode PLL */ 1308 snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI, 1309 0x80); 1310 snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO, 1311 0x00); 1312 break; 1313 case SND_SOC_DAIFMT_CBP_CFP: 1314 /* Set to provider mode */ 1315 regval |= M98095_DAI_MAS; 1316 break; 1317 default: 1318 dev_err(component->dev, "Clock mode unsupported"); 1319 return -EINVAL; 1320 } 1321 1322 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1323 case SND_SOC_DAIFMT_I2S: 1324 regval |= M98095_DAI_DLY; 1325 break; 1326 case SND_SOC_DAIFMT_LEFT_J: 1327 break; 1328 default: 1329 return -EINVAL; 1330 } 1331 1332 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1333 case SND_SOC_DAIFMT_NB_NF: 1334 break; 1335 case SND_SOC_DAIFMT_NB_IF: 1336 regval |= M98095_DAI_WCI; 1337 break; 1338 case SND_SOC_DAIFMT_IB_NF: 1339 regval |= M98095_DAI_BCI; 1340 break; 1341 case SND_SOC_DAIFMT_IB_IF: 1342 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1343 break; 1344 default: 1345 return -EINVAL; 1346 } 1347 1348 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT, 1349 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1350 M98095_DAI_WCI, regval); 1351 1352 snd_soc_component_write(component, M98095_03F_DAI3_CLOCK, 1353 M98095_DAI_BSEL64); 1354 } 1355 1356 return 0; 1357 } 1358 1359 static int max98095_set_bias_level(struct snd_soc_component *component, 1360 enum snd_soc_bias_level level) 1361 { 1362 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1363 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1364 int ret; 1365 1366 switch (level) { 1367 case SND_SOC_BIAS_ON: 1368 break; 1369 1370 case SND_SOC_BIAS_PREPARE: 1371 /* 1372 * SND_SOC_BIAS_PREPARE is called while preparing for a 1373 * transition to ON or away from ON. If current bias_level 1374 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1375 * away from ON. Disable the clock in that case, otherwise 1376 * enable it. 1377 */ 1378 if (IS_ERR(max98095->mclk)) 1379 break; 1380 1381 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_ON) { 1382 clk_disable_unprepare(max98095->mclk); 1383 } else { 1384 ret = clk_prepare_enable(max98095->mclk); 1385 if (ret) 1386 return ret; 1387 } 1388 break; 1389 1390 case SND_SOC_BIAS_STANDBY: 1391 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 1392 ret = regcache_sync(max98095->regmap); 1393 1394 if (ret != 0) { 1395 dev_err(component->dev, "Failed to sync cache: %d\n", ret); 1396 return ret; 1397 } 1398 } 1399 1400 snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN, 1401 M98095_MBEN, M98095_MBEN); 1402 break; 1403 1404 case SND_SOC_BIAS_OFF: 1405 snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN, 1406 M98095_MBEN, 0); 1407 regcache_mark_dirty(max98095->regmap); 1408 break; 1409 } 1410 return 0; 1411 } 1412 1413 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 1414 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1415 1416 static const u64 max98095_selectable_formats = 1417 SND_SOC_POSSIBLE_DAIFMT_I2S | 1418 SND_SOC_POSSIBLE_DAIFMT_LEFT_J | 1419 SND_SOC_POSSIBLE_DAIFMT_NB_NF | 1420 SND_SOC_POSSIBLE_DAIFMT_NB_IF | 1421 SND_SOC_POSSIBLE_DAIFMT_IB_NF | 1422 SND_SOC_POSSIBLE_DAIFMT_IB_IF; 1423 1424 static const struct snd_soc_dai_ops max98095_dai1_ops = { 1425 .set_sysclk = max98095_dai_set_sysclk, 1426 .set_fmt = max98095_dai1_set_fmt, 1427 .hw_params = max98095_dai1_hw_params, 1428 .auto_selectable_formats = &max98095_selectable_formats, 1429 .num_auto_selectable_formats = 1, 1430 }; 1431 1432 static const struct snd_soc_dai_ops max98095_dai2_ops = { 1433 .set_sysclk = max98095_dai_set_sysclk, 1434 .set_fmt = max98095_dai2_set_fmt, 1435 .hw_params = max98095_dai2_hw_params, 1436 .auto_selectable_formats = &max98095_selectable_formats, 1437 .num_auto_selectable_formats = 1, 1438 }; 1439 1440 static const struct snd_soc_dai_ops max98095_dai3_ops = { 1441 .set_sysclk = max98095_dai_set_sysclk, 1442 .set_fmt = max98095_dai3_set_fmt, 1443 .hw_params = max98095_dai3_hw_params, 1444 .auto_selectable_formats = &max98095_selectable_formats, 1445 .num_auto_selectable_formats = 1, 1446 }; 1447 1448 static struct snd_soc_dai_driver max98095_dai[] = { 1449 { 1450 .name = "HiFi", 1451 .playback = { 1452 .stream_name = "HiFi Playback", 1453 .channels_min = 1, 1454 .channels_max = 2, 1455 .rates = MAX98095_RATES, 1456 .formats = MAX98095_FORMATS, 1457 }, 1458 .capture = { 1459 .stream_name = "HiFi Capture", 1460 .channels_min = 1, 1461 .channels_max = 2, 1462 .rates = MAX98095_RATES, 1463 .formats = MAX98095_FORMATS, 1464 }, 1465 .ops = &max98095_dai1_ops, 1466 }, 1467 { 1468 .name = "Aux", 1469 .playback = { 1470 .stream_name = "Aux Playback", 1471 .channels_min = 1, 1472 .channels_max = 1, 1473 .rates = MAX98095_RATES, 1474 .formats = MAX98095_FORMATS, 1475 }, 1476 .ops = &max98095_dai2_ops, 1477 }, 1478 { 1479 .name = "Voice", 1480 .playback = { 1481 .stream_name = "Voice Playback", 1482 .channels_min = 1, 1483 .channels_max = 1, 1484 .rates = MAX98095_RATES, 1485 .formats = MAX98095_FORMATS, 1486 }, 1487 .ops = &max98095_dai3_ops, 1488 } 1489 1490 }; 1491 1492 static int max98095_get_eq_channel(const char *name) 1493 { 1494 if (strcmp(name, "EQ1 Mode") == 0) 1495 return 0; 1496 if (strcmp(name, "EQ2 Mode") == 0) 1497 return 1; 1498 return -EINVAL; 1499 } 1500 1501 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, 1502 struct snd_ctl_elem_value *ucontrol) 1503 { 1504 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1505 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1506 struct max98095_pdata *pdata = max98095->pdata; 1507 int channel = max98095_get_eq_channel(kcontrol->id.name); 1508 struct max98095_cdata *cdata; 1509 unsigned int sel = ucontrol->value.enumerated.item[0]; 1510 struct max98095_eq_cfg *coef_set; 1511 int fs, best, best_val, i; 1512 int regmask, regsave; 1513 1514 if (WARN_ON(channel > 1)) 1515 return -EINVAL; 1516 1517 if (!pdata || !max98095->eq_textcnt) 1518 return 0; 1519 1520 if (sel >= pdata->eq_cfgcnt) 1521 return -EINVAL; 1522 1523 cdata = &max98095->dai[channel]; 1524 cdata->eq_sel = sel; 1525 fs = cdata->rate; 1526 1527 /* Find the selected configuration with nearest sample rate */ 1528 best = 0; 1529 best_val = INT_MAX; 1530 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1531 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && 1532 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1533 best = i; 1534 best_val = abs(pdata->eq_cfg[i].rate - fs); 1535 } 1536 } 1537 1538 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1539 pdata->eq_cfg[best].name, 1540 pdata->eq_cfg[best].rate, fs); 1541 1542 coef_set = &pdata->eq_cfg[best]; 1543 1544 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; 1545 1546 /* Disable filter while configuring, and save current on/off state */ 1547 regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL); 1548 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0); 1549 1550 scoped_guard(mutex, &max98095->lock) { 1551 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, 1552 M98095_SEG, M98095_SEG); 1553 m98095_eq_band(component, channel, 0, coef_set->band1); 1554 m98095_eq_band(component, channel, 1, coef_set->band2); 1555 m98095_eq_band(component, channel, 2, coef_set->band3); 1556 m98095_eq_band(component, channel, 3, coef_set->band4); 1557 m98095_eq_band(component, channel, 4, coef_set->band5); 1558 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, 1559 M98095_SEG, 0); 1560 } 1561 1562 /* Restore the original on/off state */ 1563 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave); 1564 return 0; 1565 } 1566 1567 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, 1568 struct snd_ctl_elem_value *ucontrol) 1569 { 1570 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1571 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1572 int channel = max98095_get_eq_channel(kcontrol->id.name); 1573 struct max98095_cdata *cdata; 1574 1575 cdata = &max98095->dai[channel]; 1576 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1577 1578 return 0; 1579 } 1580 1581 static void max98095_handle_eq_pdata(struct snd_soc_component *component) 1582 { 1583 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1584 struct max98095_pdata *pdata = max98095->pdata; 1585 struct max98095_eq_cfg *cfg; 1586 unsigned int cfgcnt; 1587 int i, j; 1588 const char **t; 1589 int ret; 1590 1591 struct snd_kcontrol_new controls[] = { 1592 SOC_ENUM_EXT("EQ1 Mode", 1593 max98095->eq_enum, 1594 max98095_get_eq_enum, 1595 max98095_put_eq_enum), 1596 SOC_ENUM_EXT("EQ2 Mode", 1597 max98095->eq_enum, 1598 max98095_get_eq_enum, 1599 max98095_put_eq_enum), 1600 }; 1601 1602 cfg = pdata->eq_cfg; 1603 cfgcnt = pdata->eq_cfgcnt; 1604 1605 /* Setup an array of texts for the equalizer enum. 1606 * This is based on Mark Brown's equalizer driver code. 1607 */ 1608 max98095->eq_textcnt = 0; 1609 max98095->eq_texts = NULL; 1610 for (i = 0; i < cfgcnt; i++) { 1611 for (j = 0; j < max98095->eq_textcnt; j++) { 1612 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) 1613 break; 1614 } 1615 1616 if (j != max98095->eq_textcnt) 1617 continue; 1618 1619 /* Expand the array */ 1620 t = krealloc(max98095->eq_texts, 1621 sizeof(char *) * (max98095->eq_textcnt + 1), 1622 GFP_KERNEL); 1623 if (t == NULL) 1624 continue; 1625 1626 /* Store the new entry */ 1627 t[max98095->eq_textcnt] = cfg[i].name; 1628 max98095->eq_textcnt++; 1629 max98095->eq_texts = t; 1630 } 1631 1632 /* Now point the soc_enum to .texts array items */ 1633 max98095->eq_enum.texts = max98095->eq_texts; 1634 max98095->eq_enum.items = max98095->eq_textcnt; 1635 1636 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls)); 1637 if (ret != 0) 1638 dev_err(component->dev, "Failed to add EQ control: %d\n", ret); 1639 } 1640 1641 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; 1642 1643 static int max98095_get_bq_channel(struct snd_soc_component *component, 1644 const char *name) 1645 { 1646 int ret; 1647 1648 ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name); 1649 if (ret < 0) 1650 dev_err(component->dev, "Bad biquad channel name '%s'\n", name); 1651 return ret; 1652 } 1653 1654 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, 1655 struct snd_ctl_elem_value *ucontrol) 1656 { 1657 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1658 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1659 struct max98095_pdata *pdata = max98095->pdata; 1660 int channel = max98095_get_bq_channel(component, kcontrol->id.name); 1661 struct max98095_cdata *cdata; 1662 unsigned int sel = ucontrol->value.enumerated.item[0]; 1663 struct max98095_biquad_cfg *coef_set; 1664 int fs, best, best_val, i; 1665 int regmask, regsave; 1666 1667 if (channel < 0) 1668 return channel; 1669 1670 if (!pdata || !max98095->bq_textcnt) 1671 return 0; 1672 1673 if (sel >= pdata->bq_cfgcnt) 1674 return -EINVAL; 1675 1676 cdata = &max98095->dai[channel]; 1677 cdata->bq_sel = sel; 1678 fs = cdata->rate; 1679 1680 /* Find the selected configuration with nearest sample rate */ 1681 best = 0; 1682 best_val = INT_MAX; 1683 for (i = 0; i < pdata->bq_cfgcnt; i++) { 1684 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && 1685 abs(pdata->bq_cfg[i].rate - fs) < best_val) { 1686 best = i; 1687 best_val = abs(pdata->bq_cfg[i].rate - fs); 1688 } 1689 } 1690 1691 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1692 pdata->bq_cfg[best].name, 1693 pdata->bq_cfg[best].rate, fs); 1694 1695 coef_set = &pdata->bq_cfg[best]; 1696 1697 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; 1698 1699 /* Disable filter while configuring, and save current on/off state */ 1700 regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL); 1701 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0); 1702 1703 scoped_guard(mutex, &max98095->lock) { 1704 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, 1705 M98095_SEG, M98095_SEG); 1706 m98095_biquad_band(component, channel, 0, coef_set->band1); 1707 m98095_biquad_band(component, channel, 1, coef_set->band2); 1708 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, 1709 M98095_SEG, 0); 1710 } 1711 1712 /* Restore the original on/off state */ 1713 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave); 1714 return 0; 1715 } 1716 1717 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, 1718 struct snd_ctl_elem_value *ucontrol) 1719 { 1720 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1721 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1722 int channel = max98095_get_bq_channel(component, kcontrol->id.name); 1723 struct max98095_cdata *cdata; 1724 1725 if (channel < 0) 1726 return channel; 1727 1728 cdata = &max98095->dai[channel]; 1729 ucontrol->value.enumerated.item[0] = cdata->bq_sel; 1730 1731 return 0; 1732 } 1733 1734 static void max98095_handle_bq_pdata(struct snd_soc_component *component) 1735 { 1736 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1737 struct max98095_pdata *pdata = max98095->pdata; 1738 struct max98095_biquad_cfg *cfg; 1739 unsigned int cfgcnt; 1740 int i, j; 1741 const char **t; 1742 int ret; 1743 1744 struct snd_kcontrol_new controls[] = { 1745 SOC_ENUM_EXT((char *)bq_mode_name[0], 1746 max98095->bq_enum, 1747 max98095_get_bq_enum, 1748 max98095_put_bq_enum), 1749 SOC_ENUM_EXT((char *)bq_mode_name[1], 1750 max98095->bq_enum, 1751 max98095_get_bq_enum, 1752 max98095_put_bq_enum), 1753 }; 1754 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); 1755 1756 cfg = pdata->bq_cfg; 1757 cfgcnt = pdata->bq_cfgcnt; 1758 1759 /* Setup an array of texts for the biquad enum. 1760 * This is based on Mark Brown's equalizer driver code. 1761 */ 1762 max98095->bq_textcnt = 0; 1763 max98095->bq_texts = NULL; 1764 for (i = 0; i < cfgcnt; i++) { 1765 for (j = 0; j < max98095->bq_textcnt; j++) { 1766 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) 1767 break; 1768 } 1769 1770 if (j != max98095->bq_textcnt) 1771 continue; 1772 1773 /* Expand the array */ 1774 t = krealloc(max98095->bq_texts, 1775 sizeof(char *) * (max98095->bq_textcnt + 1), 1776 GFP_KERNEL); 1777 if (t == NULL) 1778 continue; 1779 1780 /* Store the new entry */ 1781 t[max98095->bq_textcnt] = cfg[i].name; 1782 max98095->bq_textcnt++; 1783 max98095->bq_texts = t; 1784 } 1785 1786 /* Now point the soc_enum to .texts array items */ 1787 max98095->bq_enum.texts = max98095->bq_texts; 1788 max98095->bq_enum.items = max98095->bq_textcnt; 1789 1790 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls)); 1791 if (ret != 0) 1792 dev_err(component->dev, "Failed to add Biquad control: %d\n", ret); 1793 } 1794 1795 static void max98095_handle_pdata(struct snd_soc_component *component) 1796 { 1797 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1798 struct max98095_pdata *pdata = max98095->pdata; 1799 u8 regval = 0; 1800 1801 if (!pdata) { 1802 dev_dbg(component->dev, "No platform data\n"); 1803 return; 1804 } 1805 1806 /* Configure mic for analog/digital mic mode */ 1807 if (pdata->digmic_left_mode) 1808 regval |= M98095_DIGMIC_L; 1809 1810 if (pdata->digmic_right_mode) 1811 regval |= M98095_DIGMIC_R; 1812 1813 snd_soc_component_write(component, M98095_087_CFG_MIC, regval); 1814 1815 /* Configure equalizers */ 1816 if (pdata->eq_cfgcnt) 1817 max98095_handle_eq_pdata(component); 1818 1819 /* Configure bi-quad filters */ 1820 if (pdata->bq_cfgcnt) 1821 max98095_handle_bq_pdata(component); 1822 } 1823 1824 static irqreturn_t max98095_report_jack(int irq, void *data) 1825 { 1826 struct snd_soc_component *component = data; 1827 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1828 unsigned int value; 1829 int hp_report = 0; 1830 int mic_report = 0; 1831 1832 /* Read the Jack Status Register */ 1833 value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS); 1834 1835 /* If ddone is not set, then detection isn't finished yet */ 1836 if ((value & M98095_DDONE) == 0) 1837 return IRQ_NONE; 1838 1839 /* if hp, check its bit, and if set, clear it */ 1840 if ((value & M98095_HP_IN || value & M98095_LO_IN) && 1841 max98095->headphone_jack) 1842 hp_report |= SND_JACK_HEADPHONE; 1843 1844 /* if mic, check its bit, and if set, clear it */ 1845 if ((value & M98095_MIC_IN) && max98095->mic_jack) 1846 mic_report |= SND_JACK_MICROPHONE; 1847 1848 if (max98095->headphone_jack == max98095->mic_jack) { 1849 snd_soc_jack_report(max98095->headphone_jack, 1850 hp_report | mic_report, 1851 SND_JACK_HEADSET); 1852 } else { 1853 if (max98095->headphone_jack) 1854 snd_soc_jack_report(max98095->headphone_jack, 1855 hp_report, SND_JACK_HEADPHONE); 1856 if (max98095->mic_jack) 1857 snd_soc_jack_report(max98095->mic_jack, 1858 mic_report, SND_JACK_MICROPHONE); 1859 } 1860 1861 return IRQ_HANDLED; 1862 } 1863 1864 static int max98095_jack_detect_enable(struct snd_soc_component *component) 1865 { 1866 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1867 int ret = 0; 1868 int detect_enable = M98095_JDEN; 1869 unsigned int slew = M98095_DEFAULT_SLEW_DELAY; 1870 1871 if (max98095->pdata->jack_detect_pin5en) 1872 detect_enable |= M98095_PIN5EN; 1873 1874 if (max98095->pdata->jack_detect_delay) 1875 slew = max98095->pdata->jack_detect_delay; 1876 1877 ret = snd_soc_component_write(component, M98095_08E_JACK_DC_SLEW, slew); 1878 if (ret < 0) { 1879 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret); 1880 return ret; 1881 } 1882 1883 /* configure auto detection to be enabled */ 1884 ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, detect_enable); 1885 if (ret < 0) { 1886 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret); 1887 return ret; 1888 } 1889 1890 return ret; 1891 } 1892 1893 static int max98095_jack_detect_disable(struct snd_soc_component *component) 1894 { 1895 int ret = 0; 1896 1897 /* configure auto detection to be disabled */ 1898 ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, 0x0); 1899 if (ret < 0) { 1900 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret); 1901 return ret; 1902 } 1903 1904 return ret; 1905 } 1906 1907 int max98095_jack_detect(struct snd_soc_component *component, 1908 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack) 1909 { 1910 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1911 struct i2c_client *client = to_i2c_client(component->dev); 1912 int ret = 0; 1913 1914 max98095->headphone_jack = hp_jack; 1915 max98095->mic_jack = mic_jack; 1916 1917 /* only progress if we have at least 1 jack pointer */ 1918 if (!hp_jack && !mic_jack) 1919 return -EINVAL; 1920 1921 max98095_jack_detect_enable(component); 1922 1923 /* enable interrupts for headphone jack detection */ 1924 ret = snd_soc_component_update_bits(component, M98095_013_JACK_INT_EN, 1925 M98095_IDDONE, M98095_IDDONE); 1926 if (ret < 0) { 1927 dev_err(component->dev, "Failed to cfg jack irqs %d\n", ret); 1928 return ret; 1929 } 1930 1931 max98095_report_jack(client->irq, component); 1932 return 0; 1933 } 1934 EXPORT_SYMBOL_GPL(max98095_jack_detect); 1935 1936 #ifdef CONFIG_PM 1937 static int max98095_suspend(struct snd_soc_component *component) 1938 { 1939 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1940 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1941 1942 if (max98095->headphone_jack || max98095->mic_jack) 1943 max98095_jack_detect_disable(component); 1944 1945 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF); 1946 1947 return 0; 1948 } 1949 1950 static int max98095_resume(struct snd_soc_component *component) 1951 { 1952 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 1953 struct i2c_client *client = to_i2c_client(component->dev); 1954 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1955 1956 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_STANDBY); 1957 1958 if (max98095->headphone_jack || max98095->mic_jack) { 1959 max98095_jack_detect_enable(component); 1960 max98095_report_jack(client->irq, component); 1961 } 1962 1963 return 0; 1964 } 1965 #else 1966 #define max98095_suspend NULL 1967 #define max98095_resume NULL 1968 #endif 1969 1970 static int max98095_reset(struct snd_soc_component *component) 1971 { 1972 int i, ret; 1973 1974 /* Gracefully reset the DSP core and the codec hardware 1975 * in a proper sequence */ 1976 ret = snd_soc_component_write(component, M98095_00F_HOST_CFG, 0); 1977 if (ret < 0) { 1978 dev_err(component->dev, "Failed to reset DSP: %d\n", ret); 1979 return ret; 1980 } 1981 1982 ret = snd_soc_component_write(component, M98095_097_PWR_SYS, 0); 1983 if (ret < 0) { 1984 dev_err(component->dev, "Failed to reset component: %d\n", ret); 1985 return ret; 1986 } 1987 1988 /* Reset to hardware default for registers, as there is not 1989 * a soft reset hardware control register */ 1990 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 1991 ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i)); 1992 if (ret < 0) { 1993 dev_err(component->dev, "Failed to reset: %d\n", ret); 1994 return ret; 1995 } 1996 } 1997 1998 return ret; 1999 } 2000 2001 static int max98095_probe(struct snd_soc_component *component) 2002 { 2003 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 2004 struct max98095_cdata *cdata; 2005 struct i2c_client *client; 2006 int ret = 0; 2007 2008 /* reset the codec, the DSP core, and disable all interrupts */ 2009 max98095_reset(component); 2010 2011 client = to_i2c_client(component->dev); 2012 2013 /* initialize private data */ 2014 2015 max98095->sysclk = (unsigned)-1; 2016 max98095->eq_textcnt = 0; 2017 max98095->bq_textcnt = 0; 2018 2019 cdata = &max98095->dai[0]; 2020 cdata->rate = (unsigned)-1; 2021 cdata->fmt = (unsigned)-1; 2022 cdata->eq_sel = 0; 2023 cdata->bq_sel = 0; 2024 2025 cdata = &max98095->dai[1]; 2026 cdata->rate = (unsigned)-1; 2027 cdata->fmt = (unsigned)-1; 2028 cdata->eq_sel = 0; 2029 cdata->bq_sel = 0; 2030 2031 cdata = &max98095->dai[2]; 2032 cdata->rate = (unsigned)-1; 2033 cdata->fmt = (unsigned)-1; 2034 cdata->eq_sel = 0; 2035 cdata->bq_sel = 0; 2036 2037 max98095->lin_state = 0; 2038 max98095->mic1pre = 0; 2039 max98095->mic2pre = 0; 2040 2041 if (client->irq) { 2042 /* register an audio interrupt */ 2043 ret = request_threaded_irq(client->irq, NULL, 2044 max98095_report_jack, 2045 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | 2046 IRQF_ONESHOT, "max98095", component); 2047 if (ret) { 2048 dev_err(component->dev, "Failed to request IRQ: %d\n", ret); 2049 goto err_access; 2050 } 2051 } 2052 2053 ret = snd_soc_component_read(component, M98095_0FF_REV_ID); 2054 if (ret < 0) { 2055 dev_err(component->dev, "Failure reading hardware revision: %d\n", 2056 ret); 2057 goto err_irq; 2058 } 2059 dev_info(component->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); 2060 2061 snd_soc_component_write(component, M98095_097_PWR_SYS, M98095_PWRSV); 2062 2063 snd_soc_component_write(component, M98095_048_MIX_DAC_LR, 2064 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); 2065 2066 snd_soc_component_write(component, M98095_049_MIX_DAC_M, 2067 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); 2068 2069 snd_soc_component_write(component, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); 2070 snd_soc_component_write(component, M98095_045_CFG_DSP, M98095_DSPNORMAL); 2071 snd_soc_component_write(component, M98095_04E_CFG_HP, M98095_HPNORMAL); 2072 2073 snd_soc_component_write(component, M98095_02C_DAI1_IOCFG, 2074 M98095_S1NORMAL|M98095_SDATA); 2075 2076 snd_soc_component_write(component, M98095_036_DAI2_IOCFG, 2077 M98095_S2NORMAL|M98095_SDATA); 2078 2079 snd_soc_component_write(component, M98095_040_DAI3_IOCFG, 2080 M98095_S3NORMAL|M98095_SDATA); 2081 2082 max98095_handle_pdata(component); 2083 2084 /* take the codec out of the shut down */ 2085 snd_soc_component_update_bits(component, M98095_097_PWR_SYS, M98095_SHDNRUN, 2086 M98095_SHDNRUN); 2087 2088 return 0; 2089 2090 err_irq: 2091 if (client->irq) 2092 free_irq(client->irq, component); 2093 err_access: 2094 return ret; 2095 } 2096 2097 static void max98095_remove(struct snd_soc_component *component) 2098 { 2099 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component); 2100 struct i2c_client *client = to_i2c_client(component->dev); 2101 2102 if (max98095->headphone_jack || max98095->mic_jack) 2103 max98095_jack_detect_disable(component); 2104 2105 if (client->irq) 2106 free_irq(client->irq, component); 2107 } 2108 2109 static const struct snd_soc_component_driver soc_component_dev_max98095 = { 2110 .probe = max98095_probe, 2111 .remove = max98095_remove, 2112 .suspend = max98095_suspend, 2113 .resume = max98095_resume, 2114 .set_bias_level = max98095_set_bias_level, 2115 .controls = max98095_snd_controls, 2116 .num_controls = ARRAY_SIZE(max98095_snd_controls), 2117 .dapm_widgets = max98095_dapm_widgets, 2118 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), 2119 .dapm_routes = max98095_audio_map, 2120 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), 2121 .idle_bias_on = 1, 2122 .use_pmdown_time = 1, 2123 .endianness = 1, 2124 }; 2125 2126 static const struct i2c_device_id max98095_i2c_id[] = { 2127 { .name = "max98095", .driver_data = MAX98095 }, 2128 { } 2129 }; 2130 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); 2131 2132 static int max98095_i2c_probe(struct i2c_client *i2c) 2133 { 2134 struct max98095_priv *max98095; 2135 int ret; 2136 2137 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv), 2138 GFP_KERNEL); 2139 if (max98095 == NULL) 2140 return -ENOMEM; 2141 2142 mutex_init(&max98095->lock); 2143 2144 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap); 2145 if (IS_ERR(max98095->regmap)) { 2146 ret = PTR_ERR(max98095->regmap); 2147 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2148 return ret; 2149 } 2150 2151 max98095->mclk = devm_clk_get(&i2c->dev, "mclk"); 2152 if (IS_ERR(max98095->mclk)) 2153 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER) 2154 return -EPROBE_DEFER; 2155 2156 max98095->devtype = (uintptr_t)i2c_get_match_data(i2c); 2157 i2c_set_clientdata(i2c, max98095); 2158 max98095->pdata = i2c->dev.platform_data; 2159 2160 ret = devm_snd_soc_register_component(&i2c->dev, 2161 &soc_component_dev_max98095, 2162 max98095_dai, ARRAY_SIZE(max98095_dai)); 2163 return ret; 2164 } 2165 2166 #ifdef CONFIG_OF 2167 static const struct of_device_id max98095_of_match[] = { 2168 { .compatible = "maxim,max98095", }, 2169 { } 2170 }; 2171 MODULE_DEVICE_TABLE(of, max98095_of_match); 2172 #endif 2173 2174 static struct i2c_driver max98095_i2c_driver = { 2175 .driver = { 2176 .name = "max98095", 2177 .of_match_table = of_match_ptr(max98095_of_match), 2178 }, 2179 .probe = max98095_i2c_probe, 2180 .id_table = max98095_i2c_id, 2181 }; 2182 2183 module_i2c_driver(max98095_i2c_driver); 2184 2185 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); 2186 MODULE_AUTHOR("Peter Hsiang"); 2187 MODULE_LICENSE("GPL"); 2188