1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm0010.c -- WM0010 DSP Driver 4 * 5 * Copyright 2012 Wolfson Microelectronics PLC. 6 * 7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 9 * Scott Ling <sl@opensource.wolfsonmicro.com> 10 */ 11 12 #include <linux/cleanup.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/interrupt.h> 16 #include <linux/irqreturn.h> 17 #include <linux/init.h> 18 #include <linux/spi/spi.h> 19 #include <linux/firmware.h> 20 #include <linux/delay.h> 21 #include <linux/fs.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/mutex.h> 25 #include <linux/workqueue.h> 26 27 #include <sound/soc.h> 28 #include <sound/wm0010.h> 29 30 #define DEVICE_ID_WM0010 10 31 32 /* We only support v1 of the .dfw INFO record */ 33 #define INFO_VERSION 1 34 35 enum dfw_cmd { 36 DFW_CMD_FUSE = 0x01, 37 DFW_CMD_CODE_HDR, 38 DFW_CMD_CODE_DATA, 39 DFW_CMD_PLL, 40 DFW_CMD_INFO = 0xff 41 }; 42 43 struct dfw_binrec { 44 u8 command; 45 u32 length:24; 46 u32 address; 47 uint8_t data[]; 48 } __packed; 49 50 struct dfw_inforec { 51 u8 info_version; 52 u8 tool_major_version; 53 u8 tool_minor_version; 54 u8 dsp_target; 55 }; 56 57 struct dfw_pllrec { 58 u8 command; 59 u32 length:24; 60 u32 address; 61 u32 clkctrl1; 62 u32 clkctrl2; 63 u32 clkctrl3; 64 u32 ldetctrl; 65 u32 uart_div; 66 u32 spi_div; 67 } __packed; 68 69 static struct pll_clock_map { 70 int max_sysclk; 71 int max_pll_spi_speed; 72 u32 pll_clkctrl1; 73 } pll_clock_map[] = { /* Dividers */ 74 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 75 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 76 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 77 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 78 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 79 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 80 }; 81 82 enum wm0010_state { 83 WM0010_POWER_OFF, 84 WM0010_OUT_OF_RESET, 85 WM0010_BOOTROM, 86 WM0010_STAGE2, 87 WM0010_FIRMWARE, 88 }; 89 90 struct wm0010_priv { 91 struct snd_soc_component *component; 92 93 struct mutex lock; 94 struct device *dev; 95 96 struct wm0010_pdata pdata; 97 98 struct gpio_desc *reset; 99 100 struct regulator_bulk_data core_supplies[2]; 101 struct regulator *dbvdd; 102 103 int sysclk; 104 105 enum wm0010_state state; 106 bool boot_failed; 107 bool ready; 108 bool pll_running; 109 int max_spi_freq; 110 int board_max_spi_speed; 111 u32 pll_clkctrl1; 112 113 spinlock_t irq_lock; 114 int irq; 115 116 struct completion boot_completion; 117 }; 118 119 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 120 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 121 }; 122 123 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 124 { "SDI2 Capture", NULL, "SDI1 Playback" }, 125 { "SDI1 Capture", NULL, "SDI2 Playback" }, 126 127 { "SDI1 Capture", NULL, "CLKIN" }, 128 { "SDI2 Capture", NULL, "CLKIN" }, 129 { "SDI1 Playback", NULL, "CLKIN" }, 130 { "SDI2 Playback", NULL, "CLKIN" }, 131 }; 132 133 static const char *wm0010_state_to_str(enum wm0010_state state) 134 { 135 static const char * const state_to_str[] = { 136 "Power off", 137 "Out of reset", 138 "Boot ROM", 139 "Stage2", 140 "Firmware" 141 }; 142 143 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 144 return "null"; 145 return state_to_str[state]; 146 } 147 148 /* Called with wm0010->lock held */ 149 static void wm0010_halt(struct snd_soc_component *component) 150 { 151 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 152 enum wm0010_state state; 153 154 /* Fetch the wm0010 state */ 155 scoped_guard(spinlock_irqsave, &wm0010->irq_lock) 156 state = wm0010->state; 157 158 switch (state) { 159 case WM0010_POWER_OFF: 160 /* If there's nothing to do, bail out */ 161 return; 162 case WM0010_OUT_OF_RESET: 163 case WM0010_BOOTROM: 164 case WM0010_STAGE2: 165 case WM0010_FIRMWARE: 166 /* Remember to put chip back into reset */ 167 gpiod_set_value_cansleep(wm0010->reset, 1); 168 /* Disable the regulators */ 169 regulator_disable(wm0010->dbvdd); 170 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 171 wm0010->core_supplies); 172 break; 173 } 174 175 scoped_guard(spinlock_irqsave, &wm0010->irq_lock) 176 wm0010->state = WM0010_POWER_OFF; 177 } 178 179 struct wm0010_boot_xfer { 180 struct list_head list; 181 struct snd_soc_component *component; 182 struct completion *done; 183 struct spi_message m; 184 struct spi_transfer t; 185 }; 186 187 /* Called with wm0010->lock held */ 188 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 189 { 190 enum wm0010_state state; 191 192 scoped_guard(spinlock_irqsave, &wm0010->irq_lock) 193 state = wm0010->state; 194 195 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 196 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 197 198 wm0010->boot_failed = true; 199 } 200 201 static void wm0010_boot_xfer_complete(void *data) 202 { 203 struct wm0010_boot_xfer *xfer = data; 204 struct snd_soc_component *component = xfer->component; 205 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 206 u32 *out32 = xfer->t.rx_buf; 207 int i; 208 209 if (xfer->m.status != 0) { 210 dev_err(component->dev, "SPI transfer failed: %d\n", 211 xfer->m.status); 212 wm0010_mark_boot_failure(wm0010); 213 if (xfer->done) 214 complete(xfer->done); 215 return; 216 } 217 218 for (i = 0; i < xfer->t.len / 4; i++) { 219 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]); 220 221 switch (be32_to_cpu(out32[i])) { 222 case 0xe0e0e0e0: 223 dev_err(component->dev, 224 "%d: ROM error reported in stage 2\n", i); 225 wm0010_mark_boot_failure(wm0010); 226 break; 227 228 case 0x55555555: 229 if (wm0010->state < WM0010_STAGE2) 230 break; 231 dev_err(component->dev, 232 "%d: ROM bootloader running in stage 2\n", i); 233 wm0010_mark_boot_failure(wm0010); 234 break; 235 236 case 0x0fed0000: 237 dev_dbg(component->dev, "Stage2 loader running\n"); 238 break; 239 240 case 0x0fed0007: 241 dev_dbg(component->dev, "CODE_HDR packet received\n"); 242 break; 243 244 case 0x0fed0008: 245 dev_dbg(component->dev, "CODE_DATA packet received\n"); 246 break; 247 248 case 0x0fed0009: 249 dev_dbg(component->dev, "Download complete\n"); 250 break; 251 252 case 0x0fed000c: 253 dev_dbg(component->dev, "Application start\n"); 254 break; 255 256 case 0x0fed000e: 257 dev_dbg(component->dev, "PLL packet received\n"); 258 wm0010->pll_running = true; 259 break; 260 261 case 0x0fed0025: 262 dev_err(component->dev, "Device reports image too long\n"); 263 wm0010_mark_boot_failure(wm0010); 264 break; 265 266 case 0x0fed002c: 267 dev_err(component->dev, "Device reports bad SPI packet\n"); 268 wm0010_mark_boot_failure(wm0010); 269 break; 270 271 case 0x0fed0031: 272 dev_err(component->dev, "Device reports SPI read overflow\n"); 273 wm0010_mark_boot_failure(wm0010); 274 break; 275 276 case 0x0fed0032: 277 dev_err(component->dev, "Device reports SPI underclock\n"); 278 wm0010_mark_boot_failure(wm0010); 279 break; 280 281 case 0x0fed0033: 282 dev_err(component->dev, "Device reports bad header packet\n"); 283 wm0010_mark_boot_failure(wm0010); 284 break; 285 286 case 0x0fed0034: 287 dev_err(component->dev, "Device reports invalid packet type\n"); 288 wm0010_mark_boot_failure(wm0010); 289 break; 290 291 case 0x0fed0035: 292 dev_err(component->dev, "Device reports data before header error\n"); 293 wm0010_mark_boot_failure(wm0010); 294 break; 295 296 case 0x0fed0038: 297 dev_err(component->dev, "Device reports invalid PLL packet\n"); 298 break; 299 300 case 0x0fed003a: 301 dev_err(component->dev, "Device reports packet alignment error\n"); 302 wm0010_mark_boot_failure(wm0010); 303 break; 304 305 default: 306 dev_err(component->dev, "Unrecognised return 0x%x\n", 307 be32_to_cpu(out32[i])); 308 wm0010_mark_boot_failure(wm0010); 309 break; 310 } 311 312 if (wm0010->boot_failed) 313 break; 314 } 315 316 if (xfer->done) 317 complete(xfer->done); 318 } 319 320 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 321 { 322 int i; 323 324 for (i = 0; i < len / 8; i++) 325 data_out[i] = swab64(data_in[i]); 326 } 327 328 static int wm0010_firmware_load(const char *name, struct snd_soc_component *component) 329 { 330 struct spi_device *spi = to_spi_device(component->dev); 331 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 332 struct list_head xfer_list; 333 struct wm0010_boot_xfer *xfer; 334 int ret; 335 DECLARE_COMPLETION_ONSTACK(done); 336 const struct dfw_binrec *rec; 337 const struct dfw_inforec *inforec; 338 u64 *img; 339 u8 *out, dsp; 340 u32 len, offset; 341 342 INIT_LIST_HEAD(&xfer_list); 343 344 const struct firmware *fw __free(firmware) = NULL; 345 ret = request_firmware(&fw, name, component->dev); 346 if (ret != 0) { 347 dev_err(component->dev, "Failed to request application(%s): %d\n", 348 name, ret); 349 return ret; 350 } 351 352 rec = (const struct dfw_binrec *)fw->data; 353 inforec = (const struct dfw_inforec *)rec->data; 354 offset = 0; 355 dsp = inforec->dsp_target; 356 wm0010->boot_failed = false; 357 if (WARN_ON(!list_empty(&xfer_list))) 358 return -EINVAL; 359 360 /* First record should be INFO */ 361 if (rec->command != DFW_CMD_INFO) { 362 dev_err(component->dev, "First record not INFO\r\n"); 363 return -EINVAL; 364 } 365 366 if (inforec->info_version != INFO_VERSION) { 367 dev_err(component->dev, 368 "Unsupported version (%02d) of INFO record\r\n", 369 inforec->info_version); 370 return -EINVAL; 371 } 372 373 dev_dbg(component->dev, "Version v%02d INFO record found\r\n", 374 inforec->info_version); 375 376 /* Check it's a DSP file */ 377 if (dsp != DEVICE_ID_WM0010) { 378 dev_err(component->dev, "Not a WM0010 firmware file.\r\n"); 379 return -EINVAL; 380 } 381 382 /* Skip the info record as we don't need to send it */ 383 offset += ((rec->length) + 8); 384 rec = (void *)&rec->data[rec->length]; 385 386 while (offset < fw->size) { 387 dev_dbg(component->dev, 388 "Packet: command %d, data length = 0x%x\r\n", 389 rec->command, rec->length); 390 len = rec->length + 8; 391 392 xfer = kzalloc_obj(*xfer); 393 if (!xfer) { 394 ret = -ENOMEM; 395 goto abort; 396 } 397 398 xfer->component = component; 399 list_add_tail(&xfer->list, &xfer_list); 400 401 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 402 if (!out) { 403 ret = -ENOMEM; 404 goto abort; 405 } 406 xfer->t.rx_buf = out; 407 408 img = kzalloc(len, GFP_KERNEL | GFP_DMA); 409 if (!img) { 410 ret = -ENOMEM; 411 goto abort; 412 } 413 xfer->t.tx_buf = img; 414 415 byte_swap_64((u64 *)&rec->command, img, len); 416 417 spi_message_init(&xfer->m); 418 xfer->m.complete = wm0010_boot_xfer_complete; 419 xfer->m.context = xfer; 420 xfer->t.len = len; 421 xfer->t.bits_per_word = 8; 422 423 if (!wm0010->pll_running) { 424 xfer->t.speed_hz = wm0010->sysclk / 6; 425 } else { 426 xfer->t.speed_hz = wm0010->max_spi_freq; 427 428 if (wm0010->board_max_spi_speed && 429 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 430 xfer->t.speed_hz = wm0010->board_max_spi_speed; 431 } 432 433 /* Store max usable spi frequency for later use */ 434 wm0010->max_spi_freq = xfer->t.speed_hz; 435 436 spi_message_add_tail(&xfer->t, &xfer->m); 437 438 offset += ((rec->length) + 8); 439 rec = (void *)&rec->data[rec->length]; 440 441 if (offset >= fw->size) { 442 dev_dbg(component->dev, "All transfers scheduled\n"); 443 xfer->done = &done; 444 } 445 446 ret = spi_async(spi, &xfer->m); 447 if (ret != 0) { 448 dev_err(component->dev, "Write failed: %d\n", ret); 449 goto abort; 450 } 451 452 if (wm0010->boot_failed) { 453 dev_dbg(component->dev, "Boot fail!\n"); 454 ret = -EINVAL; 455 goto abort; 456 } 457 } 458 459 wait_for_completion(&done); 460 461 ret = 0; 462 463 abort: 464 while (!list_empty(&xfer_list)) { 465 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 466 list); 467 kfree(xfer->t.rx_buf); 468 kfree(xfer->t.tx_buf); 469 list_del(&xfer->list); 470 kfree(xfer); 471 } 472 473 return ret; 474 } 475 476 static int wm0010_stage2_load(struct snd_soc_component *component) 477 { 478 struct spi_device *spi = to_spi_device(component->dev); 479 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 480 struct spi_message m; 481 struct spi_transfer t; 482 int i; 483 int ret = 0; 484 485 const struct firmware *fw __free(firmware) = NULL; 486 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev); 487 if (ret != 0) { 488 dev_err(component->dev, "Failed to request stage2 loader: %d\n", 489 ret); 490 return ret; 491 } 492 493 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 494 495 /* Copy to local buffer first as vmalloc causes problems for dma */ 496 u32 *img __free(kfree) = 497 kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA); 498 if (!img) 499 return -ENOMEM; 500 501 u8 *out __free(kfree) = 502 kzalloc(fw->size, GFP_KERNEL | GFP_DMA); 503 if (!out) 504 return -ENOMEM; 505 506 spi_message_init(&m); 507 memset(&t, 0, sizeof(t)); 508 t.rx_buf = out; 509 t.tx_buf = img; 510 t.len = fw->size; 511 t.bits_per_word = 8; 512 t.speed_hz = wm0010->sysclk / 10; 513 spi_message_add_tail(&t, &m); 514 515 dev_dbg(component->dev, "Starting initial download at %dHz\n", 516 t.speed_hz); 517 518 ret = spi_sync(spi, &m); 519 if (ret != 0) { 520 dev_err(component->dev, "Initial download failed: %d\n", ret); 521 return ret; 522 } 523 524 /* Look for errors from the boot ROM */ 525 for (i = 0; i < fw->size; i++) { 526 if (out[i] != 0x55) { 527 dev_err(component->dev, "Boot ROM error: %x in %d\n", 528 out[i], i); 529 wm0010_mark_boot_failure(wm0010); 530 return -EBUSY; 531 } 532 } 533 534 return 0; 535 } 536 537 static int wm0010_boot(struct snd_soc_component *component) 538 { 539 struct spi_device *spi = to_spi_device(component->dev); 540 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 541 unsigned long flags; 542 int ret; 543 struct spi_message m; 544 struct spi_transfer t; 545 struct dfw_pllrec pll_rec; 546 u32 *p, len; 547 u64 *img_swap; 548 u8 *out; 549 int i; 550 551 spin_lock_irqsave(&wm0010->irq_lock, flags); 552 if (wm0010->state != WM0010_POWER_OFF) 553 dev_warn(wm0010->dev, "DSP already powered up!\n"); 554 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 555 556 if (wm0010->sysclk > 26000000) { 557 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n"); 558 ret = -ECANCELED; 559 goto err; 560 } 561 562 mutex_lock(&wm0010->lock); 563 wm0010->pll_running = false; 564 565 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 566 567 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 568 wm0010->core_supplies); 569 if (ret != 0) { 570 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 571 ret); 572 mutex_unlock(&wm0010->lock); 573 goto err; 574 } 575 576 ret = regulator_enable(wm0010->dbvdd); 577 if (ret != 0) { 578 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 579 goto err_core; 580 } 581 582 /* Release reset */ 583 gpiod_set_value_cansleep(wm0010->reset, 0); 584 spin_lock_irqsave(&wm0010->irq_lock, flags); 585 wm0010->state = WM0010_OUT_OF_RESET; 586 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 587 588 if (!wait_for_completion_timeout(&wm0010->boot_completion, 589 msecs_to_jiffies(20))) 590 dev_err(component->dev, "Failed to get interrupt from DSP\n"); 591 592 spin_lock_irqsave(&wm0010->irq_lock, flags); 593 wm0010->state = WM0010_BOOTROM; 594 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 595 596 ret = wm0010_stage2_load(component); 597 if (ret) 598 goto abort; 599 600 if (!wait_for_completion_timeout(&wm0010->boot_completion, 601 msecs_to_jiffies(20))) 602 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n"); 603 604 spin_lock_irqsave(&wm0010->irq_lock, flags); 605 wm0010->state = WM0010_STAGE2; 606 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 607 608 /* Only initialise PLL if max_spi_freq initialised */ 609 if (wm0010->max_spi_freq) { 610 611 /* Initialise a PLL record */ 612 memset(&pll_rec, 0, sizeof(pll_rec)); 613 pll_rec.command = DFW_CMD_PLL; 614 pll_rec.length = (sizeof(pll_rec) - 8); 615 616 /* On wm0010 only the CLKCTRL1 value is used */ 617 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 618 619 ret = -ENOMEM; 620 len = pll_rec.length + 8; 621 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 622 if (!out) 623 goto abort; 624 625 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA); 626 if (!img_swap) 627 goto abort_out; 628 629 /* We need to re-order for 0010 */ 630 byte_swap_64((u64 *)&pll_rec, img_swap, len); 631 632 spi_message_init(&m); 633 memset(&t, 0, sizeof(t)); 634 t.rx_buf = out; 635 t.tx_buf = img_swap; 636 t.len = len; 637 t.bits_per_word = 8; 638 t.speed_hz = wm0010->sysclk / 6; 639 spi_message_add_tail(&t, &m); 640 641 ret = spi_sync(spi, &m); 642 if (ret) { 643 dev_err(component->dev, "First PLL write failed: %d\n", ret); 644 goto abort_swap; 645 } 646 647 /* Use a second send of the message to get the return status */ 648 ret = spi_sync(spi, &m); 649 if (ret) { 650 dev_err(component->dev, "Second PLL write failed: %d\n", ret); 651 goto abort_swap; 652 } 653 654 p = (u32 *)out; 655 656 /* Look for PLL active code from the DSP */ 657 for (i = 0; i < len / 4; i++) { 658 if (*p == 0x0e00ed0f) { 659 dev_dbg(component->dev, "PLL packet received\n"); 660 wm0010->pll_running = true; 661 break; 662 } 663 p++; 664 } 665 666 kfree(img_swap); 667 kfree(out); 668 } else 669 dev_dbg(component->dev, "Not enabling DSP PLL."); 670 671 ret = wm0010_firmware_load("wm0010.dfw", component); 672 673 if (ret != 0) 674 goto abort; 675 676 spin_lock_irqsave(&wm0010->irq_lock, flags); 677 wm0010->state = WM0010_FIRMWARE; 678 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 679 680 mutex_unlock(&wm0010->lock); 681 682 return 0; 683 684 abort_swap: 685 kfree(img_swap); 686 abort_out: 687 kfree(out); 688 abort: 689 /* Put the chip back into reset */ 690 wm0010_halt(component); 691 mutex_unlock(&wm0010->lock); 692 return ret; 693 694 err_core: 695 mutex_unlock(&wm0010->lock); 696 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 697 wm0010->core_supplies); 698 err: 699 return ret; 700 } 701 702 static int wm0010_set_bias_level(struct snd_soc_component *component, 703 enum snd_soc_bias_level level) 704 { 705 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 706 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 707 708 switch (level) { 709 case SND_SOC_BIAS_ON: 710 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_PREPARE) 711 wm0010_boot(component); 712 break; 713 case SND_SOC_BIAS_PREPARE: 714 break; 715 case SND_SOC_BIAS_STANDBY: 716 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_PREPARE) { 717 scoped_guard(mutex, &wm0010->lock) 718 wm0010_halt(component); 719 } 720 break; 721 case SND_SOC_BIAS_OFF: 722 break; 723 } 724 725 return 0; 726 } 727 728 static int wm0010_set_sysclk(struct snd_soc_component *component, int source, 729 int clk_id, unsigned int freq, int dir) 730 { 731 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 732 unsigned int i; 733 734 wm0010->sysclk = freq; 735 736 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 737 wm0010->max_spi_freq = 0; 738 } else { 739 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 740 if (freq >= pll_clock_map[i].max_sysclk) { 741 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 742 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 743 break; 744 } 745 } 746 747 return 0; 748 } 749 750 static int wm0010_probe(struct snd_soc_component *component); 751 752 static const struct snd_soc_component_driver soc_component_dev_wm0010 = { 753 .probe = wm0010_probe, 754 .set_bias_level = wm0010_set_bias_level, 755 .set_sysclk = wm0010_set_sysclk, 756 .dapm_widgets = wm0010_dapm_widgets, 757 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 758 .dapm_routes = wm0010_dapm_routes, 759 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 760 .use_pmdown_time = 1, 761 .endianness = 1, 762 }; 763 764 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 765 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 766 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 767 SNDRV_PCM_FMTBIT_S32_LE) 768 769 static struct snd_soc_dai_driver wm0010_dai[] = { 770 { 771 .name = "wm0010-sdi1", 772 .playback = { 773 .stream_name = "SDI1 Playback", 774 .channels_min = 1, 775 .channels_max = 2, 776 .rates = WM0010_RATES, 777 .formats = WM0010_FORMATS, 778 }, 779 .capture = { 780 .stream_name = "SDI1 Capture", 781 .channels_min = 1, 782 .channels_max = 2, 783 .rates = WM0010_RATES, 784 .formats = WM0010_FORMATS, 785 }, 786 }, 787 { 788 .name = "wm0010-sdi2", 789 .playback = { 790 .stream_name = "SDI2 Playback", 791 .channels_min = 1, 792 .channels_max = 2, 793 .rates = WM0010_RATES, 794 .formats = WM0010_FORMATS, 795 }, 796 .capture = { 797 .stream_name = "SDI2 Capture", 798 .channels_min = 1, 799 .channels_max = 2, 800 .rates = WM0010_RATES, 801 .formats = WM0010_FORMATS, 802 }, 803 }, 804 }; 805 806 static irqreturn_t wm0010_irq(int irq, void *data) 807 { 808 struct wm0010_priv *wm0010 = data; 809 810 switch (wm0010->state) { 811 case WM0010_OUT_OF_RESET: 812 case WM0010_BOOTROM: 813 case WM0010_STAGE2: 814 scoped_guard(spinlock, &wm0010->irq_lock) 815 complete(&wm0010->boot_completion); 816 return IRQ_HANDLED; 817 default: 818 return IRQ_NONE; 819 } 820 821 return IRQ_NONE; 822 } 823 824 static int wm0010_probe(struct snd_soc_component *component) 825 { 826 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 827 828 wm0010->component = component; 829 830 return 0; 831 } 832 833 static int wm0010_spi_probe(struct spi_device *spi) 834 { 835 int ret; 836 int trigger; 837 int irq; 838 struct wm0010_priv *wm0010; 839 840 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 841 GFP_KERNEL); 842 if (!wm0010) 843 return -ENOMEM; 844 845 mutex_init(&wm0010->lock); 846 spin_lock_init(&wm0010->irq_lock); 847 848 spi_set_drvdata(spi, wm0010); 849 wm0010->dev = &spi->dev; 850 851 if (dev_get_platdata(&spi->dev)) 852 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 853 sizeof(wm0010->pdata)); 854 855 init_completion(&wm0010->boot_completion); 856 857 wm0010->core_supplies[0].supply = "AVDD"; 858 wm0010->core_supplies[1].supply = "DCVDD"; 859 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 860 wm0010->core_supplies); 861 if (ret != 0) { 862 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 863 ret); 864 return ret; 865 } 866 867 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 868 if (IS_ERR(wm0010->dbvdd)) { 869 ret = PTR_ERR(wm0010->dbvdd); 870 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 871 return ret; 872 } 873 874 wm0010->reset = devm_gpiod_get(wm0010->dev, "reset", GPIOD_OUT_HIGH); 875 if (IS_ERR(wm0010->reset)) 876 return dev_err_probe(wm0010->dev, PTR_ERR(wm0010->reset), 877 "could not get RESET GPIO\n"); 878 gpiod_set_consumer_name(wm0010->reset, "wm0010 reset"); 879 880 wm0010->state = WM0010_POWER_OFF; 881 882 irq = spi->irq; 883 if (wm0010->pdata.irq_flags) 884 trigger = wm0010->pdata.irq_flags; 885 else 886 trigger = IRQF_TRIGGER_FALLING; 887 trigger |= IRQF_ONESHOT; 888 889 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger, 890 "wm0010", wm0010); 891 if (ret) { 892 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 893 irq, ret); 894 return ret; 895 } 896 wm0010->irq = irq; 897 898 ret = irq_set_irq_wake(irq, 1); 899 if (ret) { 900 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", 901 irq, ret); 902 goto free_irq; 903 } 904 905 if (spi->max_speed_hz) 906 wm0010->board_max_spi_speed = spi->max_speed_hz; 907 else 908 wm0010->board_max_spi_speed = 0; 909 910 ret = devm_snd_soc_register_component(&spi->dev, 911 &soc_component_dev_wm0010, wm0010_dai, 912 ARRAY_SIZE(wm0010_dai)); 913 if (ret < 0) 914 goto disable_irq_wake; 915 916 return 0; 917 918 disable_irq_wake: 919 irq_set_irq_wake(wm0010->irq, 0); 920 921 free_irq: 922 if (wm0010->irq) 923 free_irq(wm0010->irq, wm0010); 924 925 return ret; 926 } 927 928 static void wm0010_spi_remove(struct spi_device *spi) 929 { 930 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 931 932 gpiod_set_value_cansleep(wm0010->reset, 1); 933 934 irq_set_irq_wake(wm0010->irq, 0); 935 936 if (wm0010->irq) 937 free_irq(wm0010->irq, wm0010); 938 } 939 940 static struct spi_driver wm0010_spi_driver = { 941 .driver = { 942 .name = "wm0010", 943 }, 944 .probe = wm0010_spi_probe, 945 .remove = wm0010_spi_remove, 946 }; 947 948 module_spi_driver(wm0010_spi_driver); 949 950 MODULE_DESCRIPTION("ASoC WM0010 driver"); 951 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 952 MODULE_LICENSE("GPL"); 953 954 MODULE_FIRMWARE("wm0010.dfw"); 955 MODULE_FIRMWARE("wm0010_stage2.bin"); 956