1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44 #include <net/addrconf.h>
45
46 #include <rdma/ib_verbs.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_umem.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_mad.h>
51 #include <rdma/ib_cache.h>
52 #include <rdma/uverbs_ioctl.h>
53 #include <linux/hashtable.h>
54
55 #include "roce_hsi.h"
56 #include "qplib_res.h"
57 #include "qplib_sp.h"
58 #include "qplib_fp.h"
59 #include "qplib_rcfw.h"
60
61 #include "bnxt_re.h"
62 #include "ib_verbs.h"
63 #include "debugfs.h"
64
65 #include <rdma/uverbs_types.h>
66 #include <rdma/uverbs_std_types.h>
67
68 #include <rdma/ib_user_ioctl_cmds.h>
69
70 #define UVERBS_MODULE_NAME bnxt_re
71 #include <rdma/uverbs_named_ioctl.h>
72
73 #include <rdma/bnxt_re-abi.h>
74
__from_ib_access_flags(int iflags)75 static int __from_ib_access_flags(int iflags)
76 {
77 int qflags = 0;
78
79 if (iflags & IB_ACCESS_LOCAL_WRITE)
80 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
81 if (iflags & IB_ACCESS_REMOTE_READ)
82 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
83 if (iflags & IB_ACCESS_REMOTE_WRITE)
84 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
85 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
86 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
87 if (iflags & IB_ACCESS_MW_BIND)
88 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
89 if (iflags & IB_ZERO_BASED)
90 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
91 if (iflags & IB_ACCESS_ON_DEMAND)
92 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
93 return qflags;
94 };
95
__to_ib_access_flags(int qflags)96 static int __to_ib_access_flags(int qflags)
97 {
98 int iflags = 0;
99
100 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
101 iflags |= IB_ACCESS_LOCAL_WRITE;
102 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
103 iflags |= IB_ACCESS_REMOTE_WRITE;
104 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
105 iflags |= IB_ACCESS_REMOTE_READ;
106 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
107 iflags |= IB_ACCESS_REMOTE_ATOMIC;
108 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
109 iflags |= IB_ACCESS_MW_BIND;
110 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
111 iflags |= IB_ZERO_BASED;
112 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
113 iflags |= IB_ACCESS_ON_DEMAND;
114 return iflags;
115 }
116
__qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx * cctx,int iflags)117 static u8 __qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx *cctx, int iflags)
118 {
119 u8 qflags = 0;
120
121 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
122 /* For Wh+ */
123 return (u8)__from_ib_access_flags(iflags);
124
125 /* For P5, P7 and later chips */
126 if (iflags & IB_ACCESS_LOCAL_WRITE)
127 qflags |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
128 if (iflags & IB_ACCESS_REMOTE_WRITE)
129 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
130 if (iflags & IB_ACCESS_REMOTE_READ)
131 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
132 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
133 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC;
134
135 return qflags;
136 }
137
__qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx * cctx,u8 qflags)138 static int __qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx *cctx, u8 qflags)
139 {
140 int iflags = 0;
141
142 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
143 /* For Wh+ */
144 return __to_ib_access_flags(qflags);
145
146 /* For P5, P7 and later chips */
147 if (qflags & CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE)
148 iflags |= IB_ACCESS_LOCAL_WRITE;
149 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE)
150 iflags |= IB_ACCESS_REMOTE_WRITE;
151 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_READ)
152 iflags |= IB_ACCESS_REMOTE_READ;
153 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC)
154 iflags |= IB_ACCESS_REMOTE_ATOMIC;
155
156 return iflags;
157 }
158
bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev * rdev,struct bnxt_qplib_mrw * qplib_mr)159 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev,
160 struct bnxt_qplib_mrw *qplib_mr)
161 {
162 if (_is_relaxed_ordering_supported(rdev->dev_attr->dev_cap_flags2) &&
163 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev))
164 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO;
165 }
166
bnxt_re_build_sgl(struct ib_sge * ib_sg_list,struct bnxt_qplib_sge * sg_list,int num)167 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
168 struct bnxt_qplib_sge *sg_list, int num)
169 {
170 int i, total = 0;
171
172 for (i = 0; i < num; i++) {
173 sg_list[i].addr = ib_sg_list[i].addr;
174 sg_list[i].lkey = ib_sg_list[i].lkey;
175 sg_list[i].size = ib_sg_list[i].length;
176 total += sg_list[i].size;
177 }
178 return total;
179 }
180
181 /* Device */
bnxt_re_query_device(struct ib_device * ibdev,struct ib_device_attr * ib_attr,struct ib_udata * udata)182 int bnxt_re_query_device(struct ib_device *ibdev,
183 struct ib_device_attr *ib_attr,
184 struct ib_udata *udata)
185 {
186 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
187 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
188
189 memset(ib_attr, 0, sizeof(*ib_attr));
190 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
191 min(sizeof(dev_attr->fw_ver),
192 sizeof(ib_attr->fw_ver)));
193 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid,
194 rdev->netdev->dev_addr);
195 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
196 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED;
197
198 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
199 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
200 ib_attr->hw_ver = rdev->en_dev->pdev->revision;
201 ib_attr->max_qp = dev_attr->max_qp;
202 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
203 ib_attr->device_cap_flags =
204 IB_DEVICE_CURR_QP_STATE_MOD
205 | IB_DEVICE_RC_RNR_NAK_GEN
206 | IB_DEVICE_SHUTDOWN_PORT
207 | IB_DEVICE_SYS_IMAGE_GUID
208 | IB_DEVICE_RESIZE_MAX_WR
209 | IB_DEVICE_PORT_ACTIVE_EVENT
210 | IB_DEVICE_N_NOTIFY_CQ
211 | IB_DEVICE_MEM_WINDOW
212 | IB_DEVICE_MEM_WINDOW_TYPE_2B
213 | IB_DEVICE_MEM_MGT_EXTENSIONS;
214 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
215 ib_attr->max_send_sge = dev_attr->max_qp_sges;
216 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
217 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
218 ib_attr->max_cq = dev_attr->max_cq;
219 ib_attr->max_cqe = dev_attr->max_cq_wqes;
220 ib_attr->max_mr = dev_attr->max_mr;
221 ib_attr->max_pd = dev_attr->max_pd;
222 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
223 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
224 ib_attr->atomic_cap = IB_ATOMIC_NONE;
225 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
226 if (dev_attr->is_atomic) {
227 ib_attr->atomic_cap = IB_ATOMIC_GLOB;
228 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
229 }
230
231 ib_attr->max_ee_rd_atom = 0;
232 ib_attr->max_res_rd_atom = 0;
233 ib_attr->max_ee_init_rd_atom = 0;
234 ib_attr->max_ee = 0;
235 ib_attr->max_rdd = 0;
236 ib_attr->max_mw = dev_attr->max_mw;
237 ib_attr->max_raw_ipv6_qp = 0;
238 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
239 ib_attr->max_mcast_grp = 0;
240 ib_attr->max_mcast_qp_attach = 0;
241 ib_attr->max_total_mcast_qp_attach = 0;
242 ib_attr->max_ah = dev_attr->max_ah;
243
244 ib_attr->max_srq = dev_attr->max_srq;
245 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
246 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
247
248 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
249
250 ib_attr->max_pkeys = 1;
251 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
252 return 0;
253 }
254
bnxt_re_modify_device(struct ib_device * ibdev,int device_modify_mask,struct ib_device_modify * device_modify)255 int bnxt_re_modify_device(struct ib_device *ibdev,
256 int device_modify_mask,
257 struct ib_device_modify *device_modify)
258 {
259 ibdev_dbg(ibdev, "Modify device with mask 0x%x", device_modify_mask);
260
261 if (device_modify_mask & ~IB_DEVICE_MODIFY_NODE_DESC)
262 return -EOPNOTSUPP;
263
264 if (!(device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC))
265 return 0;
266
267 memcpy(ibdev->node_desc, device_modify->node_desc, IB_DEVICE_NODE_DESC_MAX);
268 return 0;
269 }
270
271 /* Port */
bnxt_re_query_port(struct ib_device * ibdev,u32 port_num,struct ib_port_attr * port_attr)272 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
273 struct ib_port_attr *port_attr)
274 {
275 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
276 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
277 int rc;
278
279 memset(port_attr, 0, sizeof(*port_attr));
280
281 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
282 port_attr->state = IB_PORT_ACTIVE;
283 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
284 } else {
285 port_attr->state = IB_PORT_DOWN;
286 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
287 }
288 port_attr->max_mtu = IB_MTU_4096;
289 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
290 port_attr->gid_tbl_len = dev_attr->max_sgid;
291 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
292 IB_PORT_DEVICE_MGMT_SUP |
293 IB_PORT_VENDOR_CLASS_SUP;
294 port_attr->ip_gids = true;
295
296 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
297 port_attr->bad_pkey_cntr = 0;
298 port_attr->qkey_viol_cntr = 0;
299 port_attr->pkey_tbl_len = dev_attr->max_pkey;
300 port_attr->lid = 0;
301 port_attr->sm_lid = 0;
302 port_attr->lmc = 0;
303 port_attr->max_vl_num = 4;
304 port_attr->sm_sl = 0;
305 port_attr->subnet_timeout = 0;
306 port_attr->init_type_reply = 0;
307 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed,
308 &port_attr->active_width);
309
310 return rc;
311 }
312
bnxt_re_get_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)313 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
314 struct ib_port_immutable *immutable)
315 {
316 struct ib_port_attr port_attr;
317
318 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
319 return -EINVAL;
320
321 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
322 immutable->gid_tbl_len = port_attr.gid_tbl_len;
323 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
324 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
325 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
326 return 0;
327 }
328
bnxt_re_query_fw_str(struct ib_device * ibdev,char * str)329 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
330 {
331 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
332
333 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
334 rdev->dev_attr->fw_ver[0], rdev->dev_attr->fw_ver[1],
335 rdev->dev_attr->fw_ver[2], rdev->dev_attr->fw_ver[3]);
336 }
337
bnxt_re_query_pkey(struct ib_device * ibdev,u32 port_num,u16 index,u16 * pkey)338 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
339 u16 index, u16 *pkey)
340 {
341 if (index > 0)
342 return -EINVAL;
343
344 *pkey = IB_DEFAULT_PKEY_FULL;
345
346 return 0;
347 }
348
bnxt_re_query_gid(struct ib_device * ibdev,u32 port_num,int index,union ib_gid * gid)349 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
350 int index, union ib_gid *gid)
351 {
352 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
353 int rc;
354
355 /* Ignore port_num */
356 memset(gid, 0, sizeof(*gid));
357 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
358 &rdev->qplib_res.sgid_tbl, index,
359 (struct bnxt_qplib_gid *)gid);
360 return rc;
361 }
362
bnxt_re_del_gid(const struct ib_gid_attr * attr,void ** context)363 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
364 {
365 int rc = 0;
366 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
367 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
368 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
369 struct bnxt_qplib_gid *gid_to_del;
370 u16 vlan_id = 0xFFFF;
371
372 /* Delete the entry from the hardware */
373 ctx = *context;
374 if (!ctx)
375 return -EINVAL;
376
377 if (sgid_tbl && sgid_tbl->active) {
378 if (ctx->idx >= sgid_tbl->max)
379 return -EINVAL;
380 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
381 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
382 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
383 * or via the ib_unregister_device path. In the former case QP1
384 * may not be destroyed yet, in which case just return as FW
385 * needs that entry to be present and will fail it's deletion.
386 * We could get invoked again after QP1 is destroyed OR get an
387 * ADD_GID call with a different GID value for the same index
388 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
389 */
390 if (ctx->idx == 0 &&
391 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
392 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
393 ibdev_dbg(&rdev->ibdev,
394 "Trying to delete GID0 while QP1 is alive\n");
395 return -EFAULT;
396 }
397 ctx->refcnt--;
398 if (!ctx->refcnt) {
399 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
400 vlan_id, true);
401 if (rc) {
402 ibdev_err(&rdev->ibdev,
403 "Failed to remove GID: %#x", rc);
404 } else {
405 ctx_tbl = sgid_tbl->ctx;
406 ctx_tbl[ctx->idx] = NULL;
407 kfree(ctx);
408 }
409 }
410 } else {
411 return -EINVAL;
412 }
413 return rc;
414 }
415
bnxt_re_add_gid(const struct ib_gid_attr * attr,void ** context)416 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
417 {
418 int rc;
419 u32 tbl_idx = 0;
420 u16 vlan_id = 0xFFFF;
421 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
422 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
423 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
424
425 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
426 if (rc)
427 return rc;
428
429 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
430 rdev->qplib_res.netdev->dev_addr,
431 vlan_id, true, &tbl_idx);
432 if (rc == -EALREADY) {
433 ctx_tbl = sgid_tbl->ctx;
434 ctx_tbl[tbl_idx]->refcnt++;
435 *context = ctx_tbl[tbl_idx];
436 return 0;
437 }
438
439 if (rc < 0) {
440 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
441 return rc;
442 }
443
444 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
445 if (!ctx)
446 return -ENOMEM;
447 ctx_tbl = sgid_tbl->ctx;
448 ctx->idx = tbl_idx;
449 ctx->refcnt = 1;
450 ctx_tbl[tbl_idx] = ctx;
451 *context = ctx;
452
453 return rc;
454 }
455
bnxt_re_get_link_layer(struct ib_device * ibdev,u32 port_num)456 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
457 u32 port_num)
458 {
459 return IB_LINK_LAYER_ETHERNET;
460 }
461
462 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
463
bnxt_re_create_fence_wqe(struct bnxt_re_pd * pd)464 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
465 {
466 struct bnxt_re_fence_data *fence = &pd->fence;
467 struct ib_mr *ib_mr = &fence->mr->ib_mr;
468 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
469 struct bnxt_re_dev *rdev = pd->rdev;
470
471 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
472 return;
473
474 memset(wqe, 0, sizeof(*wqe));
475 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
476 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
477 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
478 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
479 wqe->bind.zero_based = false;
480 wqe->bind.parent_l_key = ib_mr->lkey;
481 wqe->bind.va = (u64)(unsigned long)fence->va;
482 wqe->bind.length = fence->size;
483 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
484 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
485
486 /* Save the initial rkey in fence structure for now;
487 * wqe->bind.r_key will be set at (re)bind time.
488 */
489 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
490 }
491
bnxt_re_bind_fence_mw(struct bnxt_qplib_qp * qplib_qp)492 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
493 {
494 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
495 qplib_qp);
496 struct ib_pd *ib_pd = qp->ib_qp.pd;
497 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
498 struct bnxt_re_fence_data *fence = &pd->fence;
499 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
500 struct bnxt_qplib_swqe wqe;
501 int rc;
502
503 memcpy(&wqe, fence_wqe, sizeof(wqe));
504 wqe.bind.r_key = fence->bind_rkey;
505 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
506
507 ibdev_dbg(&qp->rdev->ibdev,
508 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
509 wqe.bind.r_key, qp->qplib_qp.id, pd);
510 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
511 if (rc) {
512 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
513 return rc;
514 }
515 bnxt_qplib_post_send_db(&qp->qplib_qp);
516
517 return rc;
518 }
519
bnxt_re_destroy_fence_mr(struct bnxt_re_pd * pd)520 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
521 {
522 struct bnxt_re_fence_data *fence = &pd->fence;
523 struct bnxt_re_dev *rdev = pd->rdev;
524 struct device *dev = &rdev->en_dev->pdev->dev;
525 struct bnxt_re_mr *mr = fence->mr;
526
527 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
528 return;
529
530 if (fence->mw) {
531 bnxt_re_dealloc_mw(fence->mw);
532 fence->mw = NULL;
533 }
534 if (mr) {
535 if (mr->ib_mr.rkey)
536 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
537 true);
538 if (mr->ib_mr.lkey)
539 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
540 kfree(mr);
541 fence->mr = NULL;
542 }
543 if (fence->dma_addr) {
544 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
545 DMA_BIDIRECTIONAL);
546 fence->dma_addr = 0;
547 }
548 }
549
bnxt_re_create_fence_mr(struct bnxt_re_pd * pd)550 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
551 {
552 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
553 struct bnxt_re_fence_data *fence = &pd->fence;
554 struct bnxt_re_dev *rdev = pd->rdev;
555 struct device *dev = &rdev->en_dev->pdev->dev;
556 struct bnxt_re_mr *mr = NULL;
557 dma_addr_t dma_addr = 0;
558 struct ib_mw *mw;
559 int rc;
560
561 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
562 return 0;
563
564 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
565 DMA_BIDIRECTIONAL);
566 rc = dma_mapping_error(dev, dma_addr);
567 if (rc) {
568 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
569 rc = -EIO;
570 fence->dma_addr = 0;
571 goto fail;
572 }
573 fence->dma_addr = dma_addr;
574
575 /* Allocate a MR */
576 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
577 if (!mr) {
578 rc = -ENOMEM;
579 goto fail;
580 }
581 fence->mr = mr;
582 mr->rdev = rdev;
583 mr->qplib_mr.pd = &pd->qplib_pd;
584 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
585 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
586 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) {
587 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
588 if (rc) {
589 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
590 goto fail;
591 }
592
593 /* Register MR */
594 mr->ib_mr.lkey = mr->qplib_mr.lkey;
595 } else {
596 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
597 }
598 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
599 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
600 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
601 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE);
602 if (rc) {
603 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
604 goto fail;
605 }
606 mr->ib_mr.rkey = mr->qplib_mr.rkey;
607
608 /* Create a fence MW only for kernel consumers */
609 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
610 if (IS_ERR(mw)) {
611 ibdev_err(&rdev->ibdev,
612 "Failed to create fence-MW for PD: %p\n", pd);
613 rc = PTR_ERR(mw);
614 goto fail;
615 }
616 fence->mw = mw;
617
618 bnxt_re_create_fence_wqe(pd);
619 return 0;
620
621 fail:
622 bnxt_re_destroy_fence_mr(pd);
623 return rc;
624 }
625
626 static struct bnxt_re_user_mmap_entry*
bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext * uctx,u64 mem_offset,enum bnxt_re_mmap_flag mmap_flag,u64 * offset)627 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset,
628 enum bnxt_re_mmap_flag mmap_flag, u64 *offset)
629 {
630 struct bnxt_re_user_mmap_entry *entry;
631 int ret;
632
633 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
634 if (!entry)
635 return NULL;
636
637 entry->mem_offset = mem_offset;
638 entry->mmap_flag = mmap_flag;
639 entry->uctx = uctx;
640
641 switch (mmap_flag) {
642 case BNXT_RE_MMAP_SH_PAGE:
643 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx,
644 &entry->rdma_entry, PAGE_SIZE, 0);
645 break;
646 case BNXT_RE_MMAP_UC_DB:
647 case BNXT_RE_MMAP_WC_DB:
648 case BNXT_RE_MMAP_DBR_BAR:
649 case BNXT_RE_MMAP_DBR_PAGE:
650 case BNXT_RE_MMAP_TOGGLE_PAGE:
651 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx,
652 &entry->rdma_entry, PAGE_SIZE);
653 break;
654 default:
655 ret = -EINVAL;
656 break;
657 }
658
659 if (ret) {
660 kfree(entry);
661 return NULL;
662 }
663 if (offset)
664 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
665
666 return entry;
667 }
668
669 /* Protection Domains */
bnxt_re_dealloc_pd(struct ib_pd * ib_pd,struct ib_udata * udata)670 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
671 {
672 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
673 struct bnxt_re_dev *rdev = pd->rdev;
674
675 if (udata) {
676 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
677 pd->pd_db_mmap = NULL;
678 }
679
680 bnxt_re_destroy_fence_mr(pd);
681
682 if (pd->qplib_pd.id) {
683 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res,
684 &rdev->qplib_res.pd_tbl,
685 &pd->qplib_pd))
686 atomic_dec(&rdev->stats.res.pd_count);
687 }
688 return 0;
689 }
690
bnxt_re_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)691 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
692 {
693 struct ib_device *ibdev = ibpd->device;
694 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
695 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
696 udata, struct bnxt_re_ucontext, ib_uctx);
697 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
698 struct bnxt_re_user_mmap_entry *entry = NULL;
699 u32 active_pds;
700 int rc = 0;
701
702 pd->rdev = rdev;
703 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) {
704 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
705 rc = -ENOMEM;
706 goto fail;
707 }
708
709 if (udata) {
710 struct bnxt_re_pd_resp resp = {};
711
712 if (!ucntx->dpi.dbr) {
713 /* Allocate DPI in alloc_pd to avoid failing of
714 * ibv_devinfo and family of application when DPIs
715 * are depleted.
716 */
717 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res,
718 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) {
719 rc = -ENOMEM;
720 goto dbfail;
721 }
722 }
723
724 resp.pdid = pd->qplib_pd.id;
725 /* Still allow mapping this DBR to the new user PD. */
726 resp.dpi = ucntx->dpi.dpi;
727
728 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr,
729 BNXT_RE_MMAP_UC_DB, &resp.dbr);
730
731 if (!entry) {
732 rc = -ENOMEM;
733 goto dbfail;
734 }
735
736 pd->pd_db_mmap = &entry->rdma_entry;
737
738 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
739 if (rc) {
740 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
741 rc = -EFAULT;
742 goto dbfail;
743 }
744 }
745
746 if (!udata)
747 if (bnxt_re_create_fence_mr(pd))
748 ibdev_warn(&rdev->ibdev,
749 "Failed to create Fence-MR\n");
750 active_pds = atomic_inc_return(&rdev->stats.res.pd_count);
751 if (active_pds > rdev->stats.res.pd_watermark)
752 rdev->stats.res.pd_watermark = active_pds;
753
754 return 0;
755 dbfail:
756 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
757 &pd->qplib_pd);
758 fail:
759 return rc;
760 }
761
762 /* Address Handles */
bnxt_re_destroy_ah(struct ib_ah * ib_ah,u32 flags)763 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
764 {
765 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
766 struct bnxt_re_dev *rdev = ah->rdev;
767 bool block = true;
768 int rc;
769
770 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE);
771 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block);
772 if (BNXT_RE_CHECK_RC(rc)) {
773 if (rc == -ETIMEDOUT)
774 rc = 0;
775 else
776 goto fail;
777 }
778 atomic_dec(&rdev->stats.res.ah_count);
779 fail:
780 return rc;
781 }
782
bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)783 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
784 {
785 u8 nw_type;
786
787 switch (ntype) {
788 case RDMA_NETWORK_IPV4:
789 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
790 break;
791 case RDMA_NETWORK_IPV6:
792 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
793 break;
794 default:
795 nw_type = CMDQ_CREATE_AH_TYPE_V1;
796 break;
797 }
798 return nw_type;
799 }
800
bnxt_re_create_ah(struct ib_ah * ib_ah,struct rdma_ah_init_attr * init_attr,struct ib_udata * udata)801 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
802 struct ib_udata *udata)
803 {
804 struct ib_pd *ib_pd = ib_ah->pd;
805 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
806 struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
807 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
808 struct bnxt_re_dev *rdev = pd->rdev;
809 const struct ib_gid_attr *sgid_attr;
810 struct bnxt_re_gid_ctx *ctx;
811 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
812 u32 active_ahs;
813 u8 nw_type;
814 int rc;
815
816 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
817 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
818 return -EINVAL;
819 }
820
821 ah->rdev = rdev;
822 ah->qplib_ah.pd = &pd->qplib_pd;
823
824 /* Supply the configuration for the HW */
825 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
826 sizeof(union ib_gid));
827 sgid_attr = grh->sgid_attr;
828 /* Get the HW context of the GID. The reference
829 * of GID table entry is already taken by the caller.
830 */
831 ctx = rdma_read_gid_hw_context(sgid_attr);
832 ah->qplib_ah.sgid_index = ctx->idx;
833 ah->qplib_ah.host_sgid_index = grh->sgid_index;
834 ah->qplib_ah.traffic_class = grh->traffic_class;
835 ah->qplib_ah.flow_label = grh->flow_label;
836 ah->qplib_ah.hop_limit = grh->hop_limit;
837 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
838
839 /* Get network header type for this GID */
840 nw_type = rdma_gid_attr_network_type(sgid_attr);
841 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
842
843 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
844 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
845 !(init_attr->flags &
846 RDMA_CREATE_AH_SLEEPABLE));
847 if (rc) {
848 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
849 return rc;
850 }
851
852 /* Write AVID to shared page. */
853 if (udata) {
854 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
855 udata, struct bnxt_re_ucontext, ib_uctx);
856 unsigned long flag;
857 u32 *wrptr;
858
859 spin_lock_irqsave(&uctx->sh_lock, flag);
860 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
861 *wrptr = ah->qplib_ah.id;
862 wmb(); /* make sure cache is updated. */
863 spin_unlock_irqrestore(&uctx->sh_lock, flag);
864 }
865 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count);
866 if (active_ahs > rdev->stats.res.ah_watermark)
867 rdev->stats.res.ah_watermark = active_ahs;
868
869 return 0;
870 }
871
bnxt_re_query_ah(struct ib_ah * ib_ah,struct rdma_ah_attr * ah_attr)872 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
873 {
874 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
875
876 ah_attr->type = ib_ah->type;
877 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
878 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
879 rdma_ah_set_grh(ah_attr, NULL, 0,
880 ah->qplib_ah.host_sgid_index,
881 0, ah->qplib_ah.traffic_class);
882 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
883 rdma_ah_set_port_num(ah_attr, 1);
884 rdma_ah_set_static_rate(ah_attr, 0);
885 return 0;
886 }
887
bnxt_re_lock_cqs(struct bnxt_re_qp * qp)888 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
889 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
890 {
891 unsigned long flags;
892
893 spin_lock_irqsave(&qp->scq->cq_lock, flags);
894 if (qp->rcq != qp->scq)
895 spin_lock(&qp->rcq->cq_lock);
896 else
897 __acquire(&qp->rcq->cq_lock);
898
899 return flags;
900 }
901
bnxt_re_unlock_cqs(struct bnxt_re_qp * qp,unsigned long flags)902 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
903 unsigned long flags)
904 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
905 {
906 if (qp->rcq != qp->scq)
907 spin_unlock(&qp->rcq->cq_lock);
908 else
909 __release(&qp->rcq->cq_lock);
910 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
911 }
912
bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp * qp)913 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
914 {
915 struct bnxt_re_qp *gsi_sqp;
916 struct bnxt_re_ah *gsi_sah;
917 struct bnxt_re_dev *rdev;
918 int rc;
919
920 rdev = qp->rdev;
921 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
922 gsi_sah = rdev->gsi_ctx.gsi_sah;
923
924 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
925 bnxt_qplib_destroy_ah(&rdev->qplib_res,
926 &gsi_sah->qplib_ah,
927 true);
928 atomic_dec(&rdev->stats.res.ah_count);
929 bnxt_qplib_clean_qp(&qp->qplib_qp);
930
931 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
932 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
933 if (rc) {
934 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
935 goto fail;
936 }
937 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
938
939 /* remove from active qp list */
940 mutex_lock(&rdev->qp_lock);
941 list_del(&gsi_sqp->list);
942 mutex_unlock(&rdev->qp_lock);
943 atomic_dec(&rdev->stats.res.qp_count);
944
945 kfree(rdev->gsi_ctx.sqp_tbl);
946 kfree(gsi_sah);
947 kfree(gsi_sqp);
948 rdev->gsi_ctx.gsi_sqp = NULL;
949 rdev->gsi_ctx.gsi_sah = NULL;
950 rdev->gsi_ctx.sqp_tbl = NULL;
951
952 return 0;
953 fail:
954 return rc;
955 }
956
957 /* Queue Pairs */
bnxt_re_destroy_qp(struct ib_qp * ib_qp,struct ib_udata * udata)958 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
959 {
960 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
961 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
962 struct bnxt_re_dev *rdev = qp->rdev;
963 struct bnxt_qplib_nq *scq_nq = NULL;
964 struct bnxt_qplib_nq *rcq_nq = NULL;
965 unsigned int flags;
966 int rc;
967
968 bnxt_re_debug_rem_qpinfo(rdev, qp);
969
970 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
971
972 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
973 if (rc)
974 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
975
976 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
977 flags = bnxt_re_lock_cqs(qp);
978 bnxt_qplib_clean_qp(&qp->qplib_qp);
979 bnxt_re_unlock_cqs(qp, flags);
980 }
981
982 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
983
984 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
985 bnxt_re_destroy_gsi_sqp(qp);
986
987 mutex_lock(&rdev->qp_lock);
988 list_del(&qp->list);
989 mutex_unlock(&rdev->qp_lock);
990 atomic_dec(&rdev->stats.res.qp_count);
991 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC)
992 atomic_dec(&rdev->stats.res.rc_qp_count);
993 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD)
994 atomic_dec(&rdev->stats.res.ud_qp_count);
995
996 ib_umem_release(qp->rumem);
997 ib_umem_release(qp->sumem);
998
999 /* Flush all the entries of notification queue associated with
1000 * given qp.
1001 */
1002 scq_nq = qplib_qp->scq->nq;
1003 rcq_nq = qplib_qp->rcq->nq;
1004 bnxt_re_synchronize_nq(scq_nq);
1005 if (scq_nq != rcq_nq)
1006 bnxt_re_synchronize_nq(rcq_nq);
1007
1008 return 0;
1009 }
1010
__from_ib_qp_type(enum ib_qp_type type)1011 static u8 __from_ib_qp_type(enum ib_qp_type type)
1012 {
1013 switch (type) {
1014 case IB_QPT_GSI:
1015 return CMDQ_CREATE_QP1_TYPE_GSI;
1016 case IB_QPT_RC:
1017 return CMDQ_CREATE_QP_TYPE_RC;
1018 case IB_QPT_UD:
1019 return CMDQ_CREATE_QP_TYPE_UD;
1020 default:
1021 return IB_QPT_MAX;
1022 }
1023 }
1024
bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp * qplqp,int rsge,int max)1025 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
1026 int rsge, int max)
1027 {
1028 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
1029 rsge = max;
1030 return bnxt_re_get_rwqe_size(rsge);
1031 }
1032
bnxt_re_get_wqe_size(int ilsize,int nsge)1033 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
1034 {
1035 u16 wqe_size, calc_ils;
1036
1037 wqe_size = bnxt_re_get_swqe_size(nsge);
1038 if (ilsize) {
1039 calc_ils = sizeof(struct sq_send_hdr) + ilsize;
1040 wqe_size = max_t(u16, calc_ils, wqe_size);
1041 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
1042 }
1043 return wqe_size;
1044 }
1045
bnxt_re_setup_swqe_size(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)1046 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
1047 struct ib_qp_init_attr *init_attr)
1048 {
1049 struct bnxt_qplib_dev_attr *dev_attr;
1050 struct bnxt_qplib_qp *qplqp;
1051 struct bnxt_re_dev *rdev;
1052 struct bnxt_qplib_q *sq;
1053 int align, ilsize;
1054
1055 rdev = qp->rdev;
1056 qplqp = &qp->qplib_qp;
1057 sq = &qplqp->sq;
1058 dev_attr = rdev->dev_attr;
1059
1060 align = sizeof(struct sq_send_hdr);
1061 ilsize = ALIGN(init_attr->cap.max_inline_data, align);
1062
1063 /* For gen p4 and gen p5 fixed wqe compatibility mode
1064 * wqe size is fixed to 128 bytes - ie 6 SGEs
1065 */
1066 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) {
1067 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE);
1068 sq->max_sge = BNXT_STATIC_MAX_SGE;
1069 } else {
1070 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
1071 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
1072 return -EINVAL;
1073 }
1074
1075 if (init_attr->cap.max_inline_data) {
1076 qplqp->max_inline_data = sq->wqe_size -
1077 sizeof(struct sq_send_hdr);
1078 init_attr->cap.max_inline_data = qplqp->max_inline_data;
1079 }
1080
1081 return 0;
1082 }
1083
bnxt_re_init_user_qp(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_qp * qp,struct bnxt_re_ucontext * cntx,struct bnxt_re_qp_req * ureq)1084 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
1085 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx,
1086 struct bnxt_re_qp_req *ureq)
1087 {
1088 struct bnxt_qplib_qp *qplib_qp;
1089 int bytes = 0, psn_sz;
1090 struct ib_umem *umem;
1091 int psn_nume;
1092
1093 qplib_qp = &qp->qplib_qp;
1094
1095 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
1096 /* Consider mapping PSN search memory only for RC QPs. */
1097 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
1098 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
1099 sizeof(struct sq_psn_search_ext) :
1100 sizeof(struct sq_psn_search);
1101 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) {
1102 psn_nume = ureq->sq_slots;
1103 } else {
1104 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
1105 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
1106 sizeof(struct bnxt_qplib_sge));
1107 }
1108 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
1109 psn_nume = roundup_pow_of_two(psn_nume);
1110 bytes += (psn_nume * psn_sz);
1111 }
1112
1113 bytes = PAGE_ALIGN(bytes);
1114 umem = ib_umem_get(&rdev->ibdev, ureq->qpsva, bytes,
1115 IB_ACCESS_LOCAL_WRITE);
1116 if (IS_ERR(umem))
1117 return PTR_ERR(umem);
1118
1119 qp->sumem = umem;
1120 qplib_qp->sq.sg_info.umem = umem;
1121 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
1122 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
1123 qplib_qp->qp_handle = ureq->qp_handle;
1124
1125 if (!qp->qplib_qp.srq) {
1126 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
1127 bytes = PAGE_ALIGN(bytes);
1128 umem = ib_umem_get(&rdev->ibdev, ureq->qprva, bytes,
1129 IB_ACCESS_LOCAL_WRITE);
1130 if (IS_ERR(umem))
1131 goto rqfail;
1132 qp->rumem = umem;
1133 qplib_qp->rq.sg_info.umem = umem;
1134 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
1135 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
1136 }
1137
1138 qplib_qp->dpi = &cntx->dpi;
1139 return 0;
1140 rqfail:
1141 ib_umem_release(qp->sumem);
1142 qp->sumem = NULL;
1143 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
1144
1145 return PTR_ERR(umem);
1146 }
1147
bnxt_re_create_shadow_qp_ah(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1148 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
1149 (struct bnxt_re_pd *pd,
1150 struct bnxt_qplib_res *qp1_res,
1151 struct bnxt_qplib_qp *qp1_qp)
1152 {
1153 struct bnxt_re_dev *rdev = pd->rdev;
1154 struct bnxt_re_ah *ah;
1155 union ib_gid sgid;
1156 int rc;
1157
1158 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
1159 if (!ah)
1160 return NULL;
1161
1162 ah->rdev = rdev;
1163 ah->qplib_ah.pd = &pd->qplib_pd;
1164
1165 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
1166 if (rc)
1167 goto fail;
1168
1169 /* supply the dgid data same as sgid */
1170 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
1171 sizeof(union ib_gid));
1172 ah->qplib_ah.sgid_index = 0;
1173
1174 ah->qplib_ah.traffic_class = 0;
1175 ah->qplib_ah.flow_label = 0;
1176 ah->qplib_ah.hop_limit = 1;
1177 ah->qplib_ah.sl = 0;
1178 /* Have DMAC same as SMAC */
1179 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1180
1181 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1182 if (rc) {
1183 ibdev_err(&rdev->ibdev,
1184 "Failed to allocate HW AH for Shadow QP");
1185 goto fail;
1186 }
1187 atomic_inc(&rdev->stats.res.ah_count);
1188
1189 return ah;
1190
1191 fail:
1192 kfree(ah);
1193 return NULL;
1194 }
1195
bnxt_re_create_shadow_qp(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1196 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1197 (struct bnxt_re_pd *pd,
1198 struct bnxt_qplib_res *qp1_res,
1199 struct bnxt_qplib_qp *qp1_qp)
1200 {
1201 struct bnxt_re_dev *rdev = pd->rdev;
1202 struct bnxt_re_qp *qp;
1203 int rc;
1204
1205 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1206 if (!qp)
1207 return NULL;
1208
1209 qp->rdev = rdev;
1210
1211 /* Initialize the shadow QP structure from the QP1 values */
1212 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1213
1214 qp->qplib_qp.pd = &pd->qplib_pd;
1215 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1216 qp->qplib_qp.type = IB_QPT_UD;
1217
1218 qp->qplib_qp.max_inline_data = 0;
1219 qp->qplib_qp.sig_type = true;
1220
1221 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1222 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1223 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1224 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe;
1225 qp->qplib_qp.sq.max_sge = 2;
1226 /* Q full delta can be 1 since it is internal QP */
1227 qp->qplib_qp.sq.q_full_delta = 1;
1228 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1229 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1230
1231 qp->qplib_qp.scq = qp1_qp->scq;
1232 qp->qplib_qp.rcq = qp1_qp->rcq;
1233
1234 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1235 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1236 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe;
1237 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1238 /* Q full delta can be 1 since it is internal QP */
1239 qp->qplib_qp.rq.q_full_delta = 1;
1240 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1241 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1242
1243 qp->qplib_qp.mtu = qp1_qp->mtu;
1244
1245 qp->qplib_qp.sq_hdr_buf_size = 0;
1246 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1247 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1248
1249 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1250 if (rc)
1251 goto fail;
1252
1253 spin_lock_init(&qp->sq_lock);
1254 INIT_LIST_HEAD(&qp->list);
1255 mutex_lock(&rdev->qp_lock);
1256 list_add_tail(&qp->list, &rdev->qp_list);
1257 atomic_inc(&rdev->stats.res.qp_count);
1258 mutex_unlock(&rdev->qp_lock);
1259 return qp;
1260 fail:
1261 kfree(qp);
1262 return NULL;
1263 }
1264
bnxt_re_init_rq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx)1265 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1266 struct ib_qp_init_attr *init_attr,
1267 struct bnxt_re_ucontext *uctx)
1268 {
1269 struct bnxt_qplib_dev_attr *dev_attr;
1270 struct bnxt_qplib_qp *qplqp;
1271 struct bnxt_re_dev *rdev;
1272 struct bnxt_qplib_q *rq;
1273 int entries;
1274
1275 rdev = qp->rdev;
1276 qplqp = &qp->qplib_qp;
1277 rq = &qplqp->rq;
1278 dev_attr = rdev->dev_attr;
1279
1280 if (init_attr->srq) {
1281 struct bnxt_re_srq *srq;
1282
1283 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1284 qplqp->srq = &srq->qplib_srq;
1285 rq->max_wqe = 0;
1286 } else {
1287 rq->max_sge = init_attr->cap.max_recv_sge;
1288 if (rq->max_sge > dev_attr->max_qp_sges)
1289 rq->max_sge = dev_attr->max_qp_sges;
1290 init_attr->cap.max_recv_sge = rq->max_sge;
1291 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1292 dev_attr->max_qp_sges);
1293 /* Allocate 1 more than what's provided so posting max doesn't
1294 * mean empty.
1295 */
1296 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx);
1297 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1298 rq->max_sw_wqe = rq->max_wqe;
1299 rq->q_full_delta = 0;
1300 rq->sg_info.pgsize = PAGE_SIZE;
1301 rq->sg_info.pgshft = PAGE_SHIFT;
1302 }
1303
1304 return 0;
1305 }
1306
bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp * qp)1307 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1308 {
1309 struct bnxt_qplib_dev_attr *dev_attr;
1310 struct bnxt_qplib_qp *qplqp;
1311 struct bnxt_re_dev *rdev;
1312
1313 rdev = qp->rdev;
1314 qplqp = &qp->qplib_qp;
1315 dev_attr = rdev->dev_attr;
1316
1317 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1318 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1319 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1320 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1321 qplqp->rq.max_sge = 6;
1322 }
1323 }
1324
bnxt_re_init_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx,struct bnxt_re_qp_req * ureq)1325 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1326 struct ib_qp_init_attr *init_attr,
1327 struct bnxt_re_ucontext *uctx,
1328 struct bnxt_re_qp_req *ureq)
1329 {
1330 struct bnxt_qplib_dev_attr *dev_attr;
1331 struct bnxt_qplib_qp *qplqp;
1332 struct bnxt_re_dev *rdev;
1333 struct bnxt_qplib_q *sq;
1334 int diff = 0;
1335 int entries;
1336 int rc;
1337
1338 rdev = qp->rdev;
1339 qplqp = &qp->qplib_qp;
1340 sq = &qplqp->sq;
1341 dev_attr = rdev->dev_attr;
1342
1343 sq->max_sge = init_attr->cap.max_send_sge;
1344 entries = init_attr->cap.max_send_wr;
1345 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) {
1346 sq->max_wqe = ureq->sq_slots;
1347 sq->max_sw_wqe = ureq->sq_slots;
1348 sq->wqe_size = sizeof(struct sq_sge);
1349 } else {
1350 if (sq->max_sge > dev_attr->max_qp_sges) {
1351 sq->max_sge = dev_attr->max_qp_sges;
1352 init_attr->cap.max_send_sge = sq->max_sge;
1353 }
1354
1355 rc = bnxt_re_setup_swqe_size(qp, init_attr);
1356 if (rc)
1357 return rc;
1358
1359 /* Allocate 128 + 1 more than what's provided */
1360 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1361 0 : BNXT_QPLIB_RESERVED_QP_WRS;
1362 entries = bnxt_re_init_depth(entries + diff + 1, uctx);
1363 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1364 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
1365 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true);
1366 else
1367 sq->max_sw_wqe = sq->max_wqe;
1368
1369 }
1370 sq->q_full_delta = diff + 1;
1371 /*
1372 * Reserving one slot for Phantom WQE. Application can
1373 * post one extra entry in this case. But allowing this to avoid
1374 * unexpected Queue full condition
1375 */
1376 qplqp->sq.q_full_delta -= 1;
1377 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1378 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1379
1380 return 0;
1381 }
1382
bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx)1383 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1384 struct ib_qp_init_attr *init_attr,
1385 struct bnxt_re_ucontext *uctx)
1386 {
1387 struct bnxt_qplib_dev_attr *dev_attr;
1388 struct bnxt_qplib_qp *qplqp;
1389 struct bnxt_re_dev *rdev;
1390 int entries;
1391
1392 rdev = qp->rdev;
1393 qplqp = &qp->qplib_qp;
1394 dev_attr = rdev->dev_attr;
1395
1396 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1397 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx);
1398 qplqp->sq.max_wqe = min_t(u32, entries,
1399 dev_attr->max_qp_wqes + 1);
1400 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1401 init_attr->cap.max_send_wr;
1402 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1403 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1404 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1405 }
1406 }
1407
bnxt_re_init_qp_type(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr)1408 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1409 struct ib_qp_init_attr *init_attr)
1410 {
1411 struct bnxt_qplib_chip_ctx *chip_ctx;
1412 int qptype;
1413
1414 chip_ctx = rdev->chip_ctx;
1415
1416 qptype = __from_ib_qp_type(init_attr->qp_type);
1417 if (qptype == IB_QPT_MAX) {
1418 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1419 qptype = -EOPNOTSUPP;
1420 goto out;
1421 }
1422
1423 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) &&
1424 init_attr->qp_type == IB_QPT_GSI)
1425 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1426 out:
1427 return qptype;
1428 }
1429
bnxt_re_init_qp_attr(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx,struct bnxt_re_qp_req * ureq)1430 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1431 struct ib_qp_init_attr *init_attr,
1432 struct bnxt_re_ucontext *uctx,
1433 struct bnxt_re_qp_req *ureq)
1434 {
1435 struct bnxt_qplib_dev_attr *dev_attr;
1436 struct bnxt_qplib_qp *qplqp;
1437 struct bnxt_re_dev *rdev;
1438 struct bnxt_re_cq *cq;
1439 int rc = 0, qptype;
1440
1441 rdev = qp->rdev;
1442 qplqp = &qp->qplib_qp;
1443 dev_attr = rdev->dev_attr;
1444
1445 /* Setup misc params */
1446 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1447 qplqp->pd = &pd->qplib_pd;
1448 qplqp->qp_handle = (u64)qplqp;
1449 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1450 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
1451 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1452 if (qptype < 0) {
1453 rc = qptype;
1454 goto out;
1455 }
1456 qplqp->type = (u8)qptype;
1457 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx);
1458 if (init_attr->qp_type == IB_QPT_RC) {
1459 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1460 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1461 }
1462 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1463 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1464 if (init_attr->create_flags) {
1465 ibdev_dbg(&rdev->ibdev,
1466 "QP create flags 0x%x not supported",
1467 init_attr->create_flags);
1468 return -EOPNOTSUPP;
1469 }
1470
1471 /* Setup CQs */
1472 if (init_attr->send_cq) {
1473 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1474 qplqp->scq = &cq->qplib_cq;
1475 qp->scq = cq;
1476 }
1477
1478 if (init_attr->recv_cq) {
1479 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1480 qplqp->rcq = &cq->qplib_cq;
1481 qp->rcq = cq;
1482 }
1483
1484 /* Setup RQ/SRQ */
1485 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx);
1486 if (rc)
1487 goto out;
1488 if (init_attr->qp_type == IB_QPT_GSI)
1489 bnxt_re_adjust_gsi_rq_attr(qp);
1490
1491 /* Setup SQ */
1492 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq);
1493 if (rc)
1494 goto out;
1495 if (init_attr->qp_type == IB_QPT_GSI)
1496 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx);
1497
1498 if (uctx) /* This will update DPI and qp_handle */
1499 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq);
1500 out:
1501 return rc;
1502 }
1503
bnxt_re_create_shadow_gsi(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd)1504 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1505 struct bnxt_re_pd *pd)
1506 {
1507 struct bnxt_re_sqp_entries *sqp_tbl;
1508 struct bnxt_re_dev *rdev;
1509 struct bnxt_re_qp *sqp;
1510 struct bnxt_re_ah *sah;
1511 int rc = 0;
1512
1513 rdev = qp->rdev;
1514 /* Create a shadow QP to handle the QP1 traffic */
1515 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl),
1516 GFP_KERNEL);
1517 if (!sqp_tbl)
1518 return -ENOMEM;
1519 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1520
1521 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1522 if (!sqp) {
1523 rc = -ENODEV;
1524 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1525 goto out;
1526 }
1527 rdev->gsi_ctx.gsi_sqp = sqp;
1528
1529 sqp->rcq = qp->rcq;
1530 sqp->scq = qp->scq;
1531 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1532 &qp->qplib_qp);
1533 if (!sah) {
1534 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1535 &sqp->qplib_qp);
1536 rc = -ENODEV;
1537 ibdev_err(&rdev->ibdev,
1538 "Failed to create AH entry for ShadowQP");
1539 goto out;
1540 }
1541 rdev->gsi_ctx.gsi_sah = sah;
1542
1543 return 0;
1544 out:
1545 kfree(sqp_tbl);
1546 return rc;
1547 }
1548
bnxt_re_create_gsi_qp(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr)1549 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1550 struct ib_qp_init_attr *init_attr)
1551 {
1552 struct bnxt_re_dev *rdev;
1553 struct bnxt_qplib_qp *qplqp;
1554 int rc;
1555
1556 rdev = qp->rdev;
1557 qplqp = &qp->qplib_qp;
1558
1559 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1560 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1561
1562 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1563 if (rc) {
1564 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1565 goto out;
1566 }
1567
1568 rc = bnxt_re_create_shadow_gsi(qp, pd);
1569 out:
1570 return rc;
1571 }
1572
bnxt_re_test_qp_limits(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr,struct bnxt_qplib_dev_attr * dev_attr)1573 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1574 struct ib_qp_init_attr *init_attr,
1575 struct bnxt_qplib_dev_attr *dev_attr)
1576 {
1577 bool rc = true;
1578
1579 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1580 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1581 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1582 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1583 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1584 ibdev_err(&rdev->ibdev,
1585 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1586 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1587 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1588 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1589 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1590 init_attr->cap.max_inline_data,
1591 dev_attr->max_inline_data);
1592 rc = false;
1593 }
1594 return rc;
1595 }
1596
bnxt_re_create_qp(struct ib_qp * ib_qp,struct ib_qp_init_attr * qp_init_attr,struct ib_udata * udata)1597 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,
1598 struct ib_udata *udata)
1599 {
1600 struct bnxt_qplib_dev_attr *dev_attr;
1601 struct bnxt_re_ucontext *uctx;
1602 struct bnxt_re_qp_req ureq;
1603 struct bnxt_re_dev *rdev;
1604 struct bnxt_re_pd *pd;
1605 struct bnxt_re_qp *qp;
1606 struct ib_pd *ib_pd;
1607 u32 active_qps;
1608 int rc;
1609
1610 ib_pd = ib_qp->pd;
1611 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1612 rdev = pd->rdev;
1613 dev_attr = rdev->dev_attr;
1614 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1615
1616 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1617 if (udata)
1618 if (ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))))
1619 return -EFAULT;
1620
1621 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1622 if (!rc) {
1623 rc = -EINVAL;
1624 goto fail;
1625 }
1626
1627 qp->rdev = rdev;
1628 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq);
1629 if (rc)
1630 goto fail;
1631
1632 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1633 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) {
1634 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1635 if (rc == -ENODEV)
1636 goto qp_destroy;
1637 if (rc)
1638 goto fail;
1639 } else {
1640 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1641 if (rc) {
1642 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1643 goto free_umem;
1644 }
1645 if (udata) {
1646 struct bnxt_re_qp_resp resp;
1647
1648 resp.qpid = qp->qplib_qp.id;
1649 resp.rsvd = 0;
1650 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1651 if (rc) {
1652 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1653 goto qp_destroy;
1654 }
1655 }
1656 }
1657
1658 qp->ib_qp.qp_num = qp->qplib_qp.id;
1659 if (qp_init_attr->qp_type == IB_QPT_GSI)
1660 rdev->gsi_ctx.gsi_qp = qp;
1661 spin_lock_init(&qp->sq_lock);
1662 spin_lock_init(&qp->rq_lock);
1663 INIT_LIST_HEAD(&qp->list);
1664 mutex_lock(&rdev->qp_lock);
1665 list_add_tail(&qp->list, &rdev->qp_list);
1666 mutex_unlock(&rdev->qp_lock);
1667 active_qps = atomic_inc_return(&rdev->stats.res.qp_count);
1668 if (active_qps > rdev->stats.res.qp_watermark)
1669 rdev->stats.res.qp_watermark = active_qps;
1670 if (qp_init_attr->qp_type == IB_QPT_RC) {
1671 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count);
1672 if (active_qps > rdev->stats.res.rc_qp_watermark)
1673 rdev->stats.res.rc_qp_watermark = active_qps;
1674 } else if (qp_init_attr->qp_type == IB_QPT_UD) {
1675 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count);
1676 if (active_qps > rdev->stats.res.ud_qp_watermark)
1677 rdev->stats.res.ud_qp_watermark = active_qps;
1678 }
1679 bnxt_re_debug_add_qpinfo(rdev, qp);
1680
1681 return 0;
1682 qp_destroy:
1683 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1684 free_umem:
1685 ib_umem_release(qp->rumem);
1686 ib_umem_release(qp->sumem);
1687 fail:
1688 return rc;
1689 }
1690
__from_ib_qp_state(enum ib_qp_state state)1691 static u8 __from_ib_qp_state(enum ib_qp_state state)
1692 {
1693 switch (state) {
1694 case IB_QPS_RESET:
1695 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1696 case IB_QPS_INIT:
1697 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1698 case IB_QPS_RTR:
1699 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1700 case IB_QPS_RTS:
1701 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1702 case IB_QPS_SQD:
1703 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1704 case IB_QPS_SQE:
1705 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1706 case IB_QPS_ERR:
1707 default:
1708 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1709 }
1710 }
1711
__to_ib_qp_state(u8 state)1712 static enum ib_qp_state __to_ib_qp_state(u8 state)
1713 {
1714 switch (state) {
1715 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1716 return IB_QPS_RESET;
1717 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1718 return IB_QPS_INIT;
1719 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1720 return IB_QPS_RTR;
1721 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1722 return IB_QPS_RTS;
1723 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1724 return IB_QPS_SQD;
1725 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1726 return IB_QPS_SQE;
1727 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1728 default:
1729 return IB_QPS_ERR;
1730 }
1731 }
1732
__from_ib_mtu(enum ib_mtu mtu)1733 static u32 __from_ib_mtu(enum ib_mtu mtu)
1734 {
1735 switch (mtu) {
1736 case IB_MTU_256:
1737 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1738 case IB_MTU_512:
1739 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1740 case IB_MTU_1024:
1741 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1742 case IB_MTU_2048:
1743 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1744 case IB_MTU_4096:
1745 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1746 default:
1747 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1748 }
1749 }
1750
__to_ib_mtu(u32 mtu)1751 static enum ib_mtu __to_ib_mtu(u32 mtu)
1752 {
1753 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1754 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1755 return IB_MTU_256;
1756 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1757 return IB_MTU_512;
1758 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1759 return IB_MTU_1024;
1760 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1761 return IB_MTU_2048;
1762 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1763 return IB_MTU_4096;
1764 default:
1765 return IB_MTU_2048;
1766 }
1767 }
1768
1769 /* Shared Receive Queues */
bnxt_re_destroy_srq(struct ib_srq * ib_srq,struct ib_udata * udata)1770 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1771 {
1772 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1773 ib_srq);
1774 struct bnxt_re_dev *rdev = srq->rdev;
1775 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1776 struct bnxt_qplib_nq *nq = NULL;
1777
1778 if (qplib_srq->cq)
1779 nq = qplib_srq->cq->nq;
1780 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1781 free_page((unsigned long)srq->uctx_srq_page);
1782 hash_del(&srq->hash_entry);
1783 }
1784 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1785 ib_umem_release(srq->umem);
1786 atomic_dec(&rdev->stats.res.srq_count);
1787 if (nq)
1788 nq->budget--;
1789 return 0;
1790 }
1791
bnxt_re_init_user_srq(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_srq * srq,struct ib_udata * udata)1792 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1793 struct bnxt_re_pd *pd,
1794 struct bnxt_re_srq *srq,
1795 struct ib_udata *udata)
1796 {
1797 struct bnxt_re_srq_req ureq;
1798 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1799 struct ib_umem *umem;
1800 int bytes = 0;
1801 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1802 udata, struct bnxt_re_ucontext, ib_uctx);
1803
1804 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1805 return -EFAULT;
1806
1807 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1808 bytes = PAGE_ALIGN(bytes);
1809 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1810 IB_ACCESS_LOCAL_WRITE);
1811 if (IS_ERR(umem))
1812 return PTR_ERR(umem);
1813
1814 srq->umem = umem;
1815 qplib_srq->sg_info.umem = umem;
1816 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1817 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1818 qplib_srq->srq_handle = ureq.srq_handle;
1819 qplib_srq->dpi = &cntx->dpi;
1820
1821 return 0;
1822 }
1823
bnxt_re_create_srq(struct ib_srq * ib_srq,struct ib_srq_init_attr * srq_init_attr,struct ib_udata * udata)1824 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1825 struct ib_srq_init_attr *srq_init_attr,
1826 struct ib_udata *udata)
1827 {
1828 struct bnxt_qplib_dev_attr *dev_attr;
1829 struct bnxt_qplib_nq *nq = NULL;
1830 struct bnxt_re_ucontext *uctx;
1831 struct bnxt_re_dev *rdev;
1832 struct bnxt_re_srq *srq;
1833 struct bnxt_re_pd *pd;
1834 struct ib_pd *ib_pd;
1835 u32 active_srqs;
1836 int rc, entries;
1837
1838 ib_pd = ib_srq->pd;
1839 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1840 rdev = pd->rdev;
1841 dev_attr = rdev->dev_attr;
1842 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1843
1844 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1845 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1846 rc = -EINVAL;
1847 goto exit;
1848 }
1849
1850 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1851 rc = -EOPNOTSUPP;
1852 goto exit;
1853 }
1854
1855 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1856 srq->rdev = rdev;
1857 srq->qplib_srq.pd = &pd->qplib_pd;
1858 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1859 /* Allocate 1 more than what's provided so posting max doesn't
1860 * mean empty
1861 */
1862 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx);
1863 if (entries > dev_attr->max_srq_wqes + 1)
1864 entries = dev_attr->max_srq_wqes + 1;
1865 srq->qplib_srq.max_wqe = entries;
1866
1867 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1868 /* 128 byte wqe size for SRQ . So use max sges */
1869 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1870 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1871 srq->srq_limit = srq_init_attr->attr.srq_limit;
1872 srq->qplib_srq.eventq_hw_ring_id = rdev->nqr->nq[0].ring_id;
1873 srq->qplib_srq.sg_info.pgsize = PAGE_SIZE;
1874 srq->qplib_srq.sg_info.pgshft = PAGE_SHIFT;
1875 nq = &rdev->nqr->nq[0];
1876
1877 if (udata) {
1878 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1879 if (rc)
1880 goto fail;
1881 }
1882
1883 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1884 if (rc) {
1885 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1886 goto fail;
1887 }
1888
1889 if (udata) {
1890 struct bnxt_re_srq_resp resp = {};
1891
1892 resp.srqid = srq->qplib_srq.id;
1893 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1894 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id);
1895 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL);
1896 if (!srq->uctx_srq_page) {
1897 rc = -ENOMEM;
1898 goto fail;
1899 }
1900 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT;
1901 }
1902 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1903 if (rc) {
1904 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1905 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1906 &srq->qplib_srq);
1907 goto fail;
1908 }
1909 }
1910 if (nq)
1911 nq->budget++;
1912 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count);
1913 if (active_srqs > rdev->stats.res.srq_watermark)
1914 rdev->stats.res.srq_watermark = active_srqs;
1915 spin_lock_init(&srq->lock);
1916
1917 return 0;
1918
1919 fail:
1920 ib_umem_release(srq->umem);
1921 exit:
1922 return rc;
1923 }
1924
bnxt_re_modify_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)1925 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1926 enum ib_srq_attr_mask srq_attr_mask,
1927 struct ib_udata *udata)
1928 {
1929 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1930 ib_srq);
1931 struct bnxt_re_dev *rdev = srq->rdev;
1932 int rc;
1933
1934 switch (srq_attr_mask) {
1935 case IB_SRQ_MAX_WR:
1936 /* SRQ resize is not supported */
1937 return -EINVAL;
1938 case IB_SRQ_LIMIT:
1939 /* Change the SRQ threshold */
1940 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1941 return -EINVAL;
1942
1943 srq->qplib_srq.threshold = srq_attr->srq_limit;
1944 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1945 if (rc) {
1946 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1947 return rc;
1948 }
1949 /* On success, update the shadow */
1950 srq->srq_limit = srq_attr->srq_limit;
1951 /* No need to Build and send response back to udata */
1952 return 0;
1953 default:
1954 ibdev_err(&rdev->ibdev,
1955 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1956 return -EINVAL;
1957 }
1958 }
1959
bnxt_re_query_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr)1960 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1961 {
1962 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1963 ib_srq);
1964 struct bnxt_re_srq tsrq;
1965 struct bnxt_re_dev *rdev = srq->rdev;
1966 int rc;
1967
1968 /* Get live SRQ attr */
1969 tsrq.qplib_srq.id = srq->qplib_srq.id;
1970 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1971 if (rc) {
1972 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1973 return rc;
1974 }
1975 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1976 srq_attr->max_sge = srq->qplib_srq.max_sge;
1977 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1978
1979 return 0;
1980 }
1981
bnxt_re_post_srq_recv(struct ib_srq * ib_srq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)1982 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1983 const struct ib_recv_wr **bad_wr)
1984 {
1985 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1986 ib_srq);
1987 struct bnxt_qplib_swqe wqe;
1988 unsigned long flags;
1989 int rc = 0;
1990
1991 spin_lock_irqsave(&srq->lock, flags);
1992 while (wr) {
1993 /* Transcribe each ib_recv_wr to qplib_swqe */
1994 wqe.num_sge = wr->num_sge;
1995 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1996 wqe.wr_id = wr->wr_id;
1997 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1998
1999 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
2000 if (rc) {
2001 *bad_wr = wr;
2002 break;
2003 }
2004 wr = wr->next;
2005 }
2006 spin_unlock_irqrestore(&srq->lock, flags);
2007
2008 return rc;
2009 }
bnxt_re_modify_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp1_qp,int qp_attr_mask)2010 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
2011 struct bnxt_re_qp *qp1_qp,
2012 int qp_attr_mask)
2013 {
2014 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
2015 int rc;
2016
2017 if (qp_attr_mask & IB_QP_STATE) {
2018 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2019 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
2020 }
2021 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2022 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2023 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
2024 }
2025
2026 if (qp_attr_mask & IB_QP_QKEY) {
2027 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2028 /* Using a Random QKEY */
2029 qp->qplib_qp.qkey = 0x81818181;
2030 }
2031 if (qp_attr_mask & IB_QP_SQ_PSN) {
2032 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2033 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
2034 }
2035
2036 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2037 if (rc)
2038 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
2039 return rc;
2040 }
2041
bnxt_re_modify_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_udata * udata)2042 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2043 int qp_attr_mask, struct ib_udata *udata)
2044 {
2045 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2046 struct bnxt_re_dev *rdev = qp->rdev;
2047 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
2048 enum ib_qp_state curr_qp_state, new_qp_state;
2049 int rc, entries;
2050 unsigned int flags;
2051 u8 nw_type;
2052
2053 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
2054 return -EOPNOTSUPP;
2055
2056 qp->qplib_qp.modify_flags = 0;
2057 if (qp_attr_mask & IB_QP_STATE) {
2058 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
2059 new_qp_state = qp_attr->qp_state;
2060 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
2061 ib_qp->qp_type, qp_attr_mask)) {
2062 ibdev_err(&rdev->ibdev,
2063 "Invalid attribute mask: %#x specified ",
2064 qp_attr_mask);
2065 ibdev_err(&rdev->ibdev,
2066 "for qpn: %#x type: %#x",
2067 ib_qp->qp_num, ib_qp->qp_type);
2068 ibdev_err(&rdev->ibdev,
2069 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
2070 curr_qp_state, new_qp_state);
2071 return -EINVAL;
2072 }
2073 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2074 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
2075
2076 if (!qp->sumem &&
2077 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
2078 ibdev_dbg(&rdev->ibdev,
2079 "Move QP = %p to flush list\n", qp);
2080 flags = bnxt_re_lock_cqs(qp);
2081 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
2082 bnxt_re_unlock_cqs(qp, flags);
2083 }
2084 if (!qp->sumem &&
2085 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
2086 ibdev_dbg(&rdev->ibdev,
2087 "Move QP = %p out of flush list\n", qp);
2088 flags = bnxt_re_lock_cqs(qp);
2089 bnxt_qplib_clean_qp(&qp->qplib_qp);
2090 bnxt_re_unlock_cqs(qp, flags);
2091 }
2092 }
2093 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
2094 qp->qplib_qp.modify_flags |=
2095 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
2096 qp->qplib_qp.en_sqd_async_notify = true;
2097 }
2098 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
2099 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
2100 qp->qplib_qp.access =
2101 __qp_access_flags_from_ib(qp->qplib_qp.cctx,
2102 qp_attr->qp_access_flags);
2103 /* LOCAL_WRITE access must be set to allow RC receive */
2104 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
2105 }
2106 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2107 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2108 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
2109 }
2110 if (qp_attr_mask & IB_QP_QKEY) {
2111 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2112 qp->qplib_qp.qkey = qp_attr->qkey;
2113 }
2114 if (qp_attr_mask & IB_QP_AV) {
2115 const struct ib_global_route *grh =
2116 rdma_ah_read_grh(&qp_attr->ah_attr);
2117 const struct ib_gid_attr *sgid_attr;
2118 struct bnxt_re_gid_ctx *ctx;
2119
2120 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
2121 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
2122 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
2123 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
2124 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
2125 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
2126 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
2127 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
2128 sizeof(qp->qplib_qp.ah.dgid.data));
2129 qp->qplib_qp.ah.flow_label = grh->flow_label;
2130 sgid_attr = grh->sgid_attr;
2131 /* Get the HW context of the GID. The reference
2132 * of GID table entry is already taken by the caller.
2133 */
2134 ctx = rdma_read_gid_hw_context(sgid_attr);
2135 qp->qplib_qp.ah.sgid_index = ctx->idx;
2136 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
2137 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
2138 qp->qplib_qp.ah.traffic_class = grh->traffic_class >> 2;
2139 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
2140 ether_addr_copy(qp->qplib_qp.ah.dmac,
2141 qp_attr->ah_attr.roce.dmac);
2142
2143 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
2144 &qp->qplib_qp.smac[0]);
2145 if (rc)
2146 return rc;
2147
2148 nw_type = rdma_gid_attr_network_type(sgid_attr);
2149 switch (nw_type) {
2150 case RDMA_NETWORK_IPV4:
2151 qp->qplib_qp.nw_type =
2152 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
2153 break;
2154 case RDMA_NETWORK_IPV6:
2155 qp->qplib_qp.nw_type =
2156 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
2157 break;
2158 default:
2159 qp->qplib_qp.nw_type =
2160 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
2161 break;
2162 }
2163 }
2164
2165 if (qp_attr->qp_state == IB_QPS_RTR) {
2166 enum ib_mtu qpmtu;
2167
2168 qpmtu = iboe_get_mtu(rdev->netdev->mtu);
2169 if (qp_attr_mask & IB_QP_PATH_MTU) {
2170 if (ib_mtu_enum_to_int(qp_attr->path_mtu) >
2171 ib_mtu_enum_to_int(qpmtu))
2172 return -EINVAL;
2173 qpmtu = qp_attr->path_mtu;
2174 }
2175
2176 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
2177 qp->qplib_qp.path_mtu = __from_ib_mtu(qpmtu);
2178 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qpmtu);
2179 }
2180
2181 if (qp_attr_mask & IB_QP_TIMEOUT) {
2182 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
2183 qp->qplib_qp.timeout = qp_attr->timeout;
2184 }
2185 if (qp_attr_mask & IB_QP_RETRY_CNT) {
2186 qp->qplib_qp.modify_flags |=
2187 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
2188 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
2189 }
2190 if (qp_attr_mask & IB_QP_RNR_RETRY) {
2191 qp->qplib_qp.modify_flags |=
2192 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
2193 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
2194 }
2195 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
2196 qp->qplib_qp.modify_flags |=
2197 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
2198 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
2199 }
2200 if (qp_attr_mask & IB_QP_RQ_PSN) {
2201 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
2202 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
2203 }
2204 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2205 qp->qplib_qp.modify_flags |=
2206 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
2207 /* Cap the max_rd_atomic to device max */
2208 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
2209 dev_attr->max_qp_rd_atom);
2210 }
2211 if (qp_attr_mask & IB_QP_SQ_PSN) {
2212 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2213 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
2214 }
2215 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2216 if (qp_attr->max_dest_rd_atomic >
2217 dev_attr->max_qp_init_rd_atom) {
2218 ibdev_err(&rdev->ibdev,
2219 "max_dest_rd_atomic requested%d is > dev_max%d",
2220 qp_attr->max_dest_rd_atomic,
2221 dev_attr->max_qp_init_rd_atom);
2222 return -EINVAL;
2223 }
2224
2225 qp->qplib_qp.modify_flags |=
2226 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
2227 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
2228 }
2229 if (qp_attr_mask & IB_QP_CAP) {
2230 struct bnxt_re_ucontext *uctx =
2231 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
2232
2233 qp->qplib_qp.modify_flags |=
2234 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2235 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2236 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2237 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2238 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2239 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2240 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2241 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2242 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2243 (qp_attr->cap.max_inline_data >=
2244 dev_attr->max_inline_data)) {
2245 ibdev_err(&rdev->ibdev,
2246 "Create QP failed - max exceeded");
2247 return -EINVAL;
2248 }
2249 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx);
2250 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2251 dev_attr->max_qp_wqes + 1);
2252 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2253 qp_attr->cap.max_send_wr;
2254 /*
2255 * Reserving one slot for Phantom WQE. Some application can
2256 * post one extra entry in this case. Allowing this to avoid
2257 * unexpected Queue full condition
2258 */
2259 qp->qplib_qp.sq.q_full_delta -= 1;
2260 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2261 if (qp->qplib_qp.rq.max_wqe) {
2262 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx);
2263 qp->qplib_qp.rq.max_wqe =
2264 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2265 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe;
2266 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2267 qp_attr->cap.max_recv_wr;
2268 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2269 } else {
2270 /* SRQ was used prior, just ignore the RQ caps */
2271 }
2272 }
2273 if (qp_attr_mask & IB_QP_DEST_QPN) {
2274 qp->qplib_qp.modify_flags |=
2275 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2276 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2277 }
2278 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2279 if (rc) {
2280 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2281 return rc;
2282 }
2283 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2284 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2285 return rc;
2286 }
2287
bnxt_re_query_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)2288 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2289 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2290 {
2291 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2292 struct bnxt_re_dev *rdev = qp->rdev;
2293 struct bnxt_qplib_qp *qplib_qp;
2294 int rc;
2295
2296 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2297 if (!qplib_qp)
2298 return -ENOMEM;
2299
2300 qplib_qp->id = qp->qplib_qp.id;
2301 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2302
2303 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2304 if (rc) {
2305 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2306 goto out;
2307 }
2308 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2309 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2310 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2311 qp_attr->qp_access_flags = __qp_access_flags_to_ib(qp->qplib_qp.cctx,
2312 qplib_qp->access);
2313 qp_attr->pkey_index = qplib_qp->pkey_index;
2314 qp_attr->qkey = qplib_qp->qkey;
2315 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2316 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2317 qplib_qp->ah.host_sgid_index,
2318 qplib_qp->ah.hop_limit,
2319 qplib_qp->ah.traffic_class);
2320 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2321 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2322 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2323 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2324 qp_attr->timeout = qplib_qp->timeout;
2325 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2326 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2327 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2328 qp_attr->port_num = __to_ib_port_num(qplib_qp->port_id);
2329 qp_attr->rq_psn = qplib_qp->rq.psn;
2330 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2331 qp_attr->sq_psn = qplib_qp->sq.psn;
2332 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2333 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2334 IB_SIGNAL_REQ_WR;
2335 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2336
2337 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2338 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2339 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2340 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2341 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2342 qp_init_attr->cap = qp_attr->cap;
2343
2344 out:
2345 kfree(qplib_qp);
2346 return rc;
2347 }
2348
2349 /* Routine for sending QP1 packets for RoCE V1 an V2
2350 */
bnxt_re_build_qp1_send_v2(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2351 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2352 const struct ib_send_wr *wr,
2353 struct bnxt_qplib_swqe *wqe,
2354 int payload_size)
2355 {
2356 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2357 ib_ah);
2358 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2359 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2360 struct bnxt_qplib_sge sge;
2361 u8 nw_type;
2362 u16 ether_type;
2363 union ib_gid dgid;
2364 bool is_eth = false;
2365 bool is_vlan = false;
2366 bool is_grh = false;
2367 bool is_udp = false;
2368 u8 ip_version = 0;
2369 u16 vlan_id = 0xFFFF;
2370 void *buf;
2371 int i, rc;
2372
2373 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2374
2375 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2376 if (rc)
2377 return rc;
2378
2379 /* Get network header type for this GID */
2380 nw_type = rdma_gid_attr_network_type(sgid_attr);
2381 switch (nw_type) {
2382 case RDMA_NETWORK_IPV4:
2383 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2384 break;
2385 case RDMA_NETWORK_IPV6:
2386 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2387 break;
2388 default:
2389 nw_type = BNXT_RE_ROCE_V1_PACKET;
2390 break;
2391 }
2392 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2393 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2394 if (is_udp) {
2395 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2396 ip_version = 4;
2397 ether_type = ETH_P_IP;
2398 } else {
2399 ip_version = 6;
2400 ether_type = ETH_P_IPV6;
2401 }
2402 is_grh = false;
2403 } else {
2404 ether_type = ETH_P_IBOE;
2405 is_grh = true;
2406 }
2407
2408 is_eth = true;
2409 is_vlan = vlan_id && (vlan_id < 0x1000);
2410
2411 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2412 ip_version, is_udp, 0, &qp->qp1_hdr);
2413
2414 /* ETH */
2415 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2416 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2417
2418 /* For vlan, check the sgid for vlan existence */
2419
2420 if (!is_vlan) {
2421 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2422 } else {
2423 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2424 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2425 }
2426
2427 if (is_grh || (ip_version == 6)) {
2428 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2429 sizeof(sgid_attr->gid));
2430 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2431 sizeof(sgid_attr->gid));
2432 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2433 }
2434
2435 if (ip_version == 4) {
2436 qp->qp1_hdr.ip4.tos = 0;
2437 qp->qp1_hdr.ip4.id = 0;
2438 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2439 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2440
2441 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2442 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2443 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2444 }
2445
2446 if (is_udp) {
2447 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2448 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2449 qp->qp1_hdr.udp.csum = 0;
2450 }
2451
2452 /* BTH */
2453 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2454 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2455 qp->qp1_hdr.immediate_present = 1;
2456 } else {
2457 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2458 }
2459 if (wr->send_flags & IB_SEND_SOLICITED)
2460 qp->qp1_hdr.bth.solicited_event = 1;
2461 /* pad_count */
2462 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2463
2464 /* P_key for QP1 is for all members */
2465 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2466 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2467 qp->qp1_hdr.bth.ack_req = 0;
2468 qp->send_psn++;
2469 qp->send_psn &= BTH_PSN_MASK;
2470 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2471 /* DETH */
2472 /* Use the priviledged Q_Key for QP1 */
2473 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2474 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2475
2476 /* Pack the QP1 to the transmit buffer */
2477 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2478 if (buf) {
2479 ib_ud_header_pack(&qp->qp1_hdr, buf);
2480 for (i = wqe->num_sge; i; i--) {
2481 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2482 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2483 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2484 }
2485
2486 /*
2487 * Max Header buf size for IPV6 RoCE V2 is 86,
2488 * which is same as the QP1 SQ header buffer.
2489 * Header buf size for IPV4 RoCE V2 can be 66.
2490 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2491 * Subtract 20 bytes from QP1 SQ header buf size
2492 */
2493 if (is_udp && ip_version == 4)
2494 sge.size -= 20;
2495 /*
2496 * Max Header buf size for RoCE V1 is 78.
2497 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2498 * Subtract 8 bytes from QP1 SQ header buf size
2499 */
2500 if (!is_udp)
2501 sge.size -= 8;
2502
2503 /* Subtract 4 bytes for non vlan packets */
2504 if (!is_vlan)
2505 sge.size -= 4;
2506
2507 wqe->sg_list[0].addr = sge.addr;
2508 wqe->sg_list[0].lkey = sge.lkey;
2509 wqe->sg_list[0].size = sge.size;
2510 wqe->num_sge++;
2511
2512 } else {
2513 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2514 rc = -ENOMEM;
2515 }
2516 return rc;
2517 }
2518
2519 /* For the MAD layer, it only provides the recv SGE the size of
2520 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2521 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2522 * receive packet (334 bytes) with no VLAN and then copy the GRH
2523 * and the MAD datagram out to the provided SGE.
2524 */
bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp * qp,const struct ib_recv_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2525 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2526 const struct ib_recv_wr *wr,
2527 struct bnxt_qplib_swqe *wqe,
2528 int payload_size)
2529 {
2530 struct bnxt_re_sqp_entries *sqp_entry;
2531 struct bnxt_qplib_sge ref, sge;
2532 struct bnxt_re_dev *rdev;
2533 u32 rq_prod_index;
2534
2535 rdev = qp->rdev;
2536
2537 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2538
2539 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2540 return -ENOMEM;
2541
2542 /* Create 1 SGE to receive the entire
2543 * ethernet packet
2544 */
2545 /* Save the reference from ULP */
2546 ref.addr = wqe->sg_list[0].addr;
2547 ref.lkey = wqe->sg_list[0].lkey;
2548 ref.size = wqe->sg_list[0].size;
2549
2550 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2551
2552 /* SGE 1 */
2553 wqe->sg_list[0].addr = sge.addr;
2554 wqe->sg_list[0].lkey = sge.lkey;
2555 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2556 sge.size -= wqe->sg_list[0].size;
2557
2558 sqp_entry->sge.addr = ref.addr;
2559 sqp_entry->sge.lkey = ref.lkey;
2560 sqp_entry->sge.size = ref.size;
2561 /* Store the wrid for reporting completion */
2562 sqp_entry->wrid = wqe->wr_id;
2563 /* change the wqe->wrid to table index */
2564 wqe->wr_id = rq_prod_index;
2565 return 0;
2566 }
2567
is_ud_qp(struct bnxt_re_qp * qp)2568 static int is_ud_qp(struct bnxt_re_qp *qp)
2569 {
2570 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2571 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2572 }
2573
bnxt_re_build_send_wqe(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2574 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2575 const struct ib_send_wr *wr,
2576 struct bnxt_qplib_swqe *wqe)
2577 {
2578 struct bnxt_re_ah *ah = NULL;
2579
2580 if (is_ud_qp(qp)) {
2581 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2582 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2583 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2584 wqe->send.avid = ah->qplib_ah.id;
2585 }
2586 switch (wr->opcode) {
2587 case IB_WR_SEND:
2588 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2589 break;
2590 case IB_WR_SEND_WITH_IMM:
2591 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2592 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data);
2593 break;
2594 case IB_WR_SEND_WITH_INV:
2595 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2596 wqe->send.inv_key = wr->ex.invalidate_rkey;
2597 break;
2598 default:
2599 return -EINVAL;
2600 }
2601 if (wr->send_flags & IB_SEND_SIGNALED)
2602 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2603 if (wr->send_flags & IB_SEND_FENCE)
2604 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2605 if (wr->send_flags & IB_SEND_SOLICITED)
2606 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2607 if (wr->send_flags & IB_SEND_INLINE)
2608 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2609
2610 return 0;
2611 }
2612
bnxt_re_build_rdma_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2613 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2614 struct bnxt_qplib_swqe *wqe)
2615 {
2616 switch (wr->opcode) {
2617 case IB_WR_RDMA_WRITE:
2618 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2619 break;
2620 case IB_WR_RDMA_WRITE_WITH_IMM:
2621 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2622 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data);
2623 break;
2624 case IB_WR_RDMA_READ:
2625 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2626 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2627 break;
2628 default:
2629 return -EINVAL;
2630 }
2631 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2632 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2633 if (wr->send_flags & IB_SEND_SIGNALED)
2634 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2635 if (wr->send_flags & IB_SEND_FENCE)
2636 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2637 if (wr->send_flags & IB_SEND_SOLICITED)
2638 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2639 if (wr->send_flags & IB_SEND_INLINE)
2640 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2641
2642 return 0;
2643 }
2644
bnxt_re_build_atomic_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2645 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2646 struct bnxt_qplib_swqe *wqe)
2647 {
2648 switch (wr->opcode) {
2649 case IB_WR_ATOMIC_CMP_AND_SWP:
2650 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2651 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2652 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2653 break;
2654 case IB_WR_ATOMIC_FETCH_AND_ADD:
2655 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2656 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2657 break;
2658 default:
2659 return -EINVAL;
2660 }
2661 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2662 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2663 if (wr->send_flags & IB_SEND_SIGNALED)
2664 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2665 if (wr->send_flags & IB_SEND_FENCE)
2666 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2667 if (wr->send_flags & IB_SEND_SOLICITED)
2668 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2669 return 0;
2670 }
2671
bnxt_re_build_inv_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2672 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2673 struct bnxt_qplib_swqe *wqe)
2674 {
2675 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2676 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2677
2678 if (wr->send_flags & IB_SEND_SIGNALED)
2679 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2680 if (wr->send_flags & IB_SEND_SOLICITED)
2681 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2682
2683 return 0;
2684 }
2685
bnxt_re_build_reg_wqe(const struct ib_reg_wr * wr,struct bnxt_qplib_swqe * wqe)2686 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2687 struct bnxt_qplib_swqe *wqe)
2688 {
2689 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2690 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2691 int access = wr->access;
2692
2693 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2694 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2695 wqe->frmr.page_list = mr->pages;
2696 wqe->frmr.page_list_len = mr->npages;
2697 wqe->frmr.levels = qplib_frpl->hwq.level;
2698 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2699
2700 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2701 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2702
2703 if (access & IB_ACCESS_LOCAL_WRITE)
2704 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2705 if (access & IB_ACCESS_REMOTE_READ)
2706 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2707 if (access & IB_ACCESS_REMOTE_WRITE)
2708 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2709 if (access & IB_ACCESS_REMOTE_ATOMIC)
2710 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2711 if (access & IB_ACCESS_MW_BIND)
2712 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2713
2714 wqe->frmr.l_key = wr->key;
2715 wqe->frmr.length = wr->mr->length;
2716 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K);
2717 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K);
2718 wqe->frmr.va = wr->mr->iova;
2719 return 0;
2720 }
2721
bnxt_re_copy_inline_data(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2722 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2723 const struct ib_send_wr *wr,
2724 struct bnxt_qplib_swqe *wqe)
2725 {
2726 /* Copy the inline data to the data field */
2727 u8 *in_data;
2728 u32 i, sge_len;
2729 void *sge_addr;
2730
2731 in_data = wqe->inline_data;
2732 for (i = 0; i < wr->num_sge; i++) {
2733 sge_addr = (void *)(unsigned long)
2734 wr->sg_list[i].addr;
2735 sge_len = wr->sg_list[i].length;
2736
2737 if ((sge_len + wqe->inline_len) >
2738 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2739 ibdev_err(&rdev->ibdev,
2740 "Inline data size requested > supported value");
2741 return -EINVAL;
2742 }
2743 sge_len = wr->sg_list[i].length;
2744
2745 memcpy(in_data, sge_addr, sge_len);
2746 in_data += wr->sg_list[i].length;
2747 wqe->inline_len += wr->sg_list[i].length;
2748 }
2749 return wqe->inline_len;
2750 }
2751
bnxt_re_copy_wr_payload(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2752 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2753 const struct ib_send_wr *wr,
2754 struct bnxt_qplib_swqe *wqe)
2755 {
2756 int payload_sz = 0;
2757
2758 if (wr->send_flags & IB_SEND_INLINE)
2759 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2760 else
2761 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2762 wqe->num_sge);
2763
2764 return payload_sz;
2765 }
2766
bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp * qp)2767 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2768 {
2769 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2770 qp->ib_qp.qp_type == IB_QPT_GSI ||
2771 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2772 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2773 int qp_attr_mask;
2774 struct ib_qp_attr qp_attr;
2775
2776 qp_attr_mask = IB_QP_STATE;
2777 qp_attr.qp_state = IB_QPS_RTS;
2778 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2779 qp->qplib_qp.wqe_cnt = 0;
2780 }
2781 }
2782
bnxt_re_post_send_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_send_wr * wr)2783 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2784 struct bnxt_re_qp *qp,
2785 const struct ib_send_wr *wr)
2786 {
2787 int rc = 0, payload_sz = 0;
2788 unsigned long flags;
2789
2790 spin_lock_irqsave(&qp->sq_lock, flags);
2791 while (wr) {
2792 struct bnxt_qplib_swqe wqe = {};
2793
2794 /* Common */
2795 wqe.num_sge = wr->num_sge;
2796 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2797 ibdev_err(&rdev->ibdev,
2798 "Limit exceeded for Send SGEs");
2799 rc = -EINVAL;
2800 goto bad;
2801 }
2802
2803 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2804 if (payload_sz < 0) {
2805 rc = -EINVAL;
2806 goto bad;
2807 }
2808 wqe.wr_id = wr->wr_id;
2809
2810 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2811
2812 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2813 if (!rc)
2814 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2815 bad:
2816 if (rc) {
2817 ibdev_err(&rdev->ibdev,
2818 "Post send failed opcode = %#x rc = %d",
2819 wr->opcode, rc);
2820 break;
2821 }
2822 wr = wr->next;
2823 }
2824 bnxt_qplib_post_send_db(&qp->qplib_qp);
2825 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2826 bnxt_ud_qp_hw_stall_workaround(qp);
2827 spin_unlock_irqrestore(&qp->sq_lock, flags);
2828 return rc;
2829 }
2830
bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe * wqe)2831 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe)
2832 {
2833 /* Need unconditional fence for non-wire memory opcode
2834 * to work as expected.
2835 */
2836 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV ||
2837 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR ||
2838 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR ||
2839 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW)
2840 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2841 }
2842
bnxt_re_post_send(struct ib_qp * ib_qp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)2843 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2844 const struct ib_send_wr **bad_wr)
2845 {
2846 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2847 struct bnxt_qplib_swqe wqe;
2848 int rc = 0, payload_sz = 0;
2849 unsigned long flags;
2850
2851 spin_lock_irqsave(&qp->sq_lock, flags);
2852 while (wr) {
2853 /* House keeping */
2854 memset(&wqe, 0, sizeof(wqe));
2855
2856 /* Common */
2857 wqe.num_sge = wr->num_sge;
2858 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2859 ibdev_err(&qp->rdev->ibdev,
2860 "Limit exceeded for Send SGEs");
2861 rc = -EINVAL;
2862 goto bad;
2863 }
2864
2865 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2866 if (payload_sz < 0) {
2867 rc = -EINVAL;
2868 goto bad;
2869 }
2870 wqe.wr_id = wr->wr_id;
2871
2872 switch (wr->opcode) {
2873 case IB_WR_SEND:
2874 case IB_WR_SEND_WITH_IMM:
2875 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2876 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2877 payload_sz);
2878 if (rc)
2879 goto bad;
2880 wqe.rawqp1.lflags |=
2881 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2882 }
2883 switch (wr->send_flags) {
2884 case IB_SEND_IP_CSUM:
2885 wqe.rawqp1.lflags |=
2886 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2887 break;
2888 default:
2889 break;
2890 }
2891 fallthrough;
2892 case IB_WR_SEND_WITH_INV:
2893 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2894 break;
2895 case IB_WR_RDMA_WRITE:
2896 case IB_WR_RDMA_WRITE_WITH_IMM:
2897 case IB_WR_RDMA_READ:
2898 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2899 break;
2900 case IB_WR_ATOMIC_CMP_AND_SWP:
2901 case IB_WR_ATOMIC_FETCH_AND_ADD:
2902 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2903 break;
2904 case IB_WR_RDMA_READ_WITH_INV:
2905 ibdev_err(&qp->rdev->ibdev,
2906 "RDMA Read with Invalidate is not supported");
2907 rc = -EINVAL;
2908 goto bad;
2909 case IB_WR_LOCAL_INV:
2910 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2911 break;
2912 case IB_WR_REG_MR:
2913 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2914 break;
2915 default:
2916 /* Unsupported WRs */
2917 ibdev_err(&qp->rdev->ibdev,
2918 "WR (%#x) is not supported", wr->opcode);
2919 rc = -EINVAL;
2920 goto bad;
2921 }
2922 if (!rc) {
2923 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2924 bnxt_re_legacy_set_uc_fence(&wqe);
2925 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2926 }
2927 bad:
2928 if (rc) {
2929 ibdev_err(&qp->rdev->ibdev,
2930 "post_send failed op:%#x qps = %#x rc = %d\n",
2931 wr->opcode, qp->qplib_qp.state, rc);
2932 *bad_wr = wr;
2933 break;
2934 }
2935 wr = wr->next;
2936 }
2937 bnxt_qplib_post_send_db(&qp->qplib_qp);
2938 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2939 bnxt_ud_qp_hw_stall_workaround(qp);
2940 spin_unlock_irqrestore(&qp->sq_lock, flags);
2941
2942 return rc;
2943 }
2944
bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_recv_wr * wr)2945 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2946 struct bnxt_re_qp *qp,
2947 const struct ib_recv_wr *wr)
2948 {
2949 struct bnxt_qplib_swqe wqe;
2950 int rc = 0;
2951
2952 while (wr) {
2953 /* House keeping */
2954 memset(&wqe, 0, sizeof(wqe));
2955
2956 /* Common */
2957 wqe.num_sge = wr->num_sge;
2958 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2959 ibdev_err(&rdev->ibdev,
2960 "Limit exceeded for Receive SGEs");
2961 rc = -EINVAL;
2962 break;
2963 }
2964 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2965 wqe.wr_id = wr->wr_id;
2966 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2967
2968 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2969 if (rc)
2970 break;
2971
2972 wr = wr->next;
2973 }
2974 if (!rc)
2975 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2976 return rc;
2977 }
2978
bnxt_re_post_recv(struct ib_qp * ib_qp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)2979 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2980 const struct ib_recv_wr **bad_wr)
2981 {
2982 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2983 struct bnxt_qplib_swqe wqe;
2984 int rc = 0, payload_sz = 0;
2985 unsigned long flags;
2986 u32 count = 0;
2987
2988 spin_lock_irqsave(&qp->rq_lock, flags);
2989 while (wr) {
2990 /* House keeping */
2991 memset(&wqe, 0, sizeof(wqe));
2992
2993 /* Common */
2994 wqe.num_sge = wr->num_sge;
2995 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2996 ibdev_err(&qp->rdev->ibdev,
2997 "Limit exceeded for Receive SGEs");
2998 rc = -EINVAL;
2999 *bad_wr = wr;
3000 break;
3001 }
3002
3003 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
3004 wr->num_sge);
3005 wqe.wr_id = wr->wr_id;
3006 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
3007
3008 if (ib_qp->qp_type == IB_QPT_GSI &&
3009 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
3010 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
3011 payload_sz);
3012 if (!rc)
3013 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
3014 if (rc) {
3015 *bad_wr = wr;
3016 break;
3017 }
3018
3019 /* Ring DB if the RQEs posted reaches a threshold value */
3020 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
3021 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3022 count = 0;
3023 }
3024
3025 wr = wr->next;
3026 }
3027
3028 if (count)
3029 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3030
3031 spin_unlock_irqrestore(&qp->rq_lock, flags);
3032
3033 return rc;
3034 }
3035
bnxt_re_get_nq(struct bnxt_re_dev * rdev)3036 static struct bnxt_qplib_nq *bnxt_re_get_nq(struct bnxt_re_dev *rdev)
3037 {
3038 int min, indx;
3039
3040 mutex_lock(&rdev->nqr->load_lock);
3041 for (indx = 0, min = 0; indx < (rdev->nqr->num_msix - 1); indx++) {
3042 if (rdev->nqr->nq[min].load > rdev->nqr->nq[indx].load)
3043 min = indx;
3044 }
3045 rdev->nqr->nq[min].load++;
3046 mutex_unlock(&rdev->nqr->load_lock);
3047
3048 return &rdev->nqr->nq[min];
3049 }
3050
bnxt_re_put_nq(struct bnxt_re_dev * rdev,struct bnxt_qplib_nq * nq)3051 static void bnxt_re_put_nq(struct bnxt_re_dev *rdev, struct bnxt_qplib_nq *nq)
3052 {
3053 mutex_lock(&rdev->nqr->load_lock);
3054 nq->load--;
3055 mutex_unlock(&rdev->nqr->load_lock);
3056 }
3057
3058 /* Completion Queues */
bnxt_re_destroy_cq(struct ib_cq * ib_cq,struct ib_udata * udata)3059 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
3060 {
3061 struct bnxt_qplib_chip_ctx *cctx;
3062 struct bnxt_qplib_nq *nq;
3063 struct bnxt_re_dev *rdev;
3064 struct bnxt_re_cq *cq;
3065
3066 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3067 rdev = cq->rdev;
3068 nq = cq->qplib_cq.nq;
3069 cctx = rdev->chip_ctx;
3070
3071 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3072 free_page((unsigned long)cq->uctx_cq_page);
3073 hash_del(&cq->hash_entry);
3074 }
3075 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3076
3077 bnxt_re_put_nq(rdev, nq);
3078 ib_umem_release(cq->umem);
3079
3080 atomic_dec(&rdev->stats.res.cq_count);
3081 nq->budget--;
3082 kfree(cq->cql);
3083 return 0;
3084 }
3085
bnxt_re_create_cq(struct ib_cq * ibcq,const struct ib_cq_init_attr * attr,struct uverbs_attr_bundle * attrs)3086 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
3087 struct uverbs_attr_bundle *attrs)
3088 {
3089 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3090 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
3091 struct ib_udata *udata = &attrs->driver_udata;
3092 struct bnxt_re_ucontext *uctx =
3093 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3094 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
3095 struct bnxt_qplib_chip_ctx *cctx;
3096 int cqe = attr->cqe;
3097 int rc, entries;
3098 u32 active_cqs;
3099
3100 if (attr->flags)
3101 return -EOPNOTSUPP;
3102
3103 /* Validate CQ fields */
3104 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3105 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
3106 return -EINVAL;
3107 }
3108
3109 cq->rdev = rdev;
3110 cctx = rdev->chip_ctx;
3111 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
3112
3113 entries = bnxt_re_init_depth(cqe + 1, uctx);
3114 if (entries > dev_attr->max_cq_wqes + 1)
3115 entries = dev_attr->max_cq_wqes + 1;
3116
3117 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3118 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3119 if (udata) {
3120 struct bnxt_re_cq_req req;
3121 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3122 rc = -EFAULT;
3123 goto fail;
3124 }
3125
3126 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3127 entries * sizeof(struct cq_base),
3128 IB_ACCESS_LOCAL_WRITE);
3129 if (IS_ERR(cq->umem)) {
3130 rc = PTR_ERR(cq->umem);
3131 goto fail;
3132 }
3133 cq->qplib_cq.sg_info.umem = cq->umem;
3134 cq->qplib_cq.dpi = &uctx->dpi;
3135 } else {
3136 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
3137 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
3138 GFP_KERNEL);
3139 if (!cq->cql) {
3140 rc = -ENOMEM;
3141 goto fail;
3142 }
3143
3144 cq->qplib_cq.dpi = &rdev->dpi_privileged;
3145 }
3146 cq->qplib_cq.max_wqe = entries;
3147 cq->qplib_cq.coalescing = &rdev->cq_coalescing;
3148 cq->qplib_cq.nq = bnxt_re_get_nq(rdev);
3149 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id;
3150
3151 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
3152 if (rc) {
3153 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
3154 goto fail;
3155 }
3156
3157 cq->ib_cq.cqe = entries;
3158 cq->cq_period = cq->qplib_cq.period;
3159
3160 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count);
3161 if (active_cqs > rdev->stats.res.cq_watermark)
3162 rdev->stats.res.cq_watermark = active_cqs;
3163 spin_lock_init(&cq->cq_lock);
3164
3165 if (udata) {
3166 struct bnxt_re_cq_resp resp = {};
3167
3168 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3169 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id);
3170 /* Allocate a page */
3171 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL);
3172 if (!cq->uctx_cq_page) {
3173 rc = -ENOMEM;
3174 goto c2fail;
3175 }
3176 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT;
3177 }
3178 resp.cqid = cq->qplib_cq.id;
3179 resp.tail = cq->qplib_cq.hwq.cons;
3180 resp.phase = cq->qplib_cq.period;
3181 resp.rsvd = 0;
3182 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
3183 if (rc) {
3184 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
3185 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3186 goto free_mem;
3187 }
3188 }
3189
3190 return 0;
3191
3192 free_mem:
3193 free_page((unsigned long)cq->uctx_cq_page);
3194 c2fail:
3195 ib_umem_release(cq->umem);
3196 fail:
3197 kfree(cq->cql);
3198 return rc;
3199 }
3200
bnxt_re_resize_cq_complete(struct bnxt_re_cq * cq)3201 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq)
3202 {
3203 struct bnxt_re_dev *rdev = cq->rdev;
3204
3205 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq);
3206
3207 cq->qplib_cq.max_wqe = cq->resize_cqe;
3208 if (cq->resize_umem) {
3209 ib_umem_release(cq->umem);
3210 cq->umem = cq->resize_umem;
3211 cq->resize_umem = NULL;
3212 cq->resize_cqe = 0;
3213 }
3214 }
3215
bnxt_re_resize_cq(struct ib_cq * ibcq,int cqe,struct ib_udata * udata)3216 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata)
3217 {
3218 struct bnxt_qplib_sg_info sg_info = {};
3219 struct bnxt_qplib_dpi *orig_dpi = NULL;
3220 struct bnxt_qplib_dev_attr *dev_attr;
3221 struct bnxt_re_ucontext *uctx = NULL;
3222 struct bnxt_re_resize_cq_req req;
3223 struct bnxt_re_dev *rdev;
3224 struct bnxt_re_cq *cq;
3225 int rc, entries;
3226
3227 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3228 rdev = cq->rdev;
3229 dev_attr = rdev->dev_attr;
3230 if (!ibcq->uobject) {
3231 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported");
3232 return -EOPNOTSUPP;
3233 }
3234
3235 if (cq->resize_umem) {
3236 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy",
3237 cq->qplib_cq.id);
3238 return -EBUSY;
3239 }
3240
3241 /* Check the requested cq depth out of supported depth */
3242 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3243 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d",
3244 cq->qplib_cq.id, cqe);
3245 return -EINVAL;
3246 }
3247
3248 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3249 entries = bnxt_re_init_depth(cqe + 1, uctx);
3250 if (entries > dev_attr->max_cq_wqes + 1)
3251 entries = dev_attr->max_cq_wqes + 1;
3252
3253 /* uverbs consumer */
3254 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3255 rc = -EFAULT;
3256 goto fail;
3257 }
3258
3259 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3260 entries * sizeof(struct cq_base),
3261 IB_ACCESS_LOCAL_WRITE);
3262 if (IS_ERR(cq->resize_umem)) {
3263 rc = PTR_ERR(cq->resize_umem);
3264 cq->resize_umem = NULL;
3265 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n",
3266 __func__, rc);
3267 goto fail;
3268 }
3269 cq->resize_cqe = entries;
3270 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info));
3271 orig_dpi = cq->qplib_cq.dpi;
3272
3273 cq->qplib_cq.sg_info.umem = cq->resize_umem;
3274 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3275 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3276 cq->qplib_cq.dpi = &uctx->dpi;
3277
3278 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries);
3279 if (rc) {
3280 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!",
3281 cq->qplib_cq.id);
3282 goto fail;
3283 }
3284
3285 cq->ib_cq.cqe = cq->resize_cqe;
3286 atomic_inc(&rdev->stats.res.resize_count);
3287
3288 return 0;
3289
3290 fail:
3291 if (cq->resize_umem) {
3292 ib_umem_release(cq->resize_umem);
3293 cq->resize_umem = NULL;
3294 cq->resize_cqe = 0;
3295 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info));
3296 cq->qplib_cq.dpi = orig_dpi;
3297 }
3298 return rc;
3299 }
3300
__req_to_ib_wc_status(u8 qstatus)3301 static u8 __req_to_ib_wc_status(u8 qstatus)
3302 {
3303 switch (qstatus) {
3304 case CQ_REQ_STATUS_OK:
3305 return IB_WC_SUCCESS;
3306 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
3307 return IB_WC_BAD_RESP_ERR;
3308 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
3309 return IB_WC_LOC_LEN_ERR;
3310 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
3311 return IB_WC_LOC_QP_OP_ERR;
3312 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
3313 return IB_WC_LOC_PROT_ERR;
3314 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
3315 return IB_WC_GENERAL_ERR;
3316 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
3317 return IB_WC_REM_INV_REQ_ERR;
3318 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
3319 return IB_WC_REM_ACCESS_ERR;
3320 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
3321 return IB_WC_REM_OP_ERR;
3322 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
3323 return IB_WC_RNR_RETRY_EXC_ERR;
3324 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
3325 return IB_WC_RETRY_EXC_ERR;
3326 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
3327 return IB_WC_WR_FLUSH_ERR;
3328 default:
3329 return IB_WC_GENERAL_ERR;
3330 }
3331 return 0;
3332 }
3333
__rawqp1_to_ib_wc_status(u8 qstatus)3334 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
3335 {
3336 switch (qstatus) {
3337 case CQ_RES_RAWETH_QP1_STATUS_OK:
3338 return IB_WC_SUCCESS;
3339 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
3340 return IB_WC_LOC_ACCESS_ERR;
3341 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
3342 return IB_WC_LOC_LEN_ERR;
3343 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
3344 return IB_WC_LOC_PROT_ERR;
3345 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
3346 return IB_WC_LOC_QP_OP_ERR;
3347 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
3348 return IB_WC_GENERAL_ERR;
3349 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
3350 return IB_WC_WR_FLUSH_ERR;
3351 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
3352 return IB_WC_WR_FLUSH_ERR;
3353 default:
3354 return IB_WC_GENERAL_ERR;
3355 }
3356 }
3357
__rc_to_ib_wc_status(u8 qstatus)3358 static u8 __rc_to_ib_wc_status(u8 qstatus)
3359 {
3360 switch (qstatus) {
3361 case CQ_RES_RC_STATUS_OK:
3362 return IB_WC_SUCCESS;
3363 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
3364 return IB_WC_LOC_ACCESS_ERR;
3365 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
3366 return IB_WC_LOC_LEN_ERR;
3367 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
3368 return IB_WC_LOC_PROT_ERR;
3369 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
3370 return IB_WC_LOC_QP_OP_ERR;
3371 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
3372 return IB_WC_GENERAL_ERR;
3373 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
3374 return IB_WC_REM_INV_REQ_ERR;
3375 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
3376 return IB_WC_WR_FLUSH_ERR;
3377 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
3378 return IB_WC_WR_FLUSH_ERR;
3379 default:
3380 return IB_WC_GENERAL_ERR;
3381 }
3382 }
3383
bnxt_re_process_req_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3384 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3385 {
3386 switch (cqe->type) {
3387 case BNXT_QPLIB_SWQE_TYPE_SEND:
3388 wc->opcode = IB_WC_SEND;
3389 break;
3390 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3391 wc->opcode = IB_WC_SEND;
3392 wc->wc_flags |= IB_WC_WITH_IMM;
3393 break;
3394 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3395 wc->opcode = IB_WC_SEND;
3396 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3397 break;
3398 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3399 wc->opcode = IB_WC_RDMA_WRITE;
3400 break;
3401 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3402 wc->opcode = IB_WC_RDMA_WRITE;
3403 wc->wc_flags |= IB_WC_WITH_IMM;
3404 break;
3405 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3406 wc->opcode = IB_WC_RDMA_READ;
3407 break;
3408 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3409 wc->opcode = IB_WC_COMP_SWAP;
3410 break;
3411 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3412 wc->opcode = IB_WC_FETCH_ADD;
3413 break;
3414 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3415 wc->opcode = IB_WC_LOCAL_INV;
3416 break;
3417 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3418 wc->opcode = IB_WC_REG_MR;
3419 break;
3420 default:
3421 wc->opcode = IB_WC_SEND;
3422 break;
3423 }
3424
3425 wc->status = __req_to_ib_wc_status(cqe->status);
3426 }
3427
bnxt_re_check_packet_type(u16 raweth_qp1_flags,u16 raweth_qp1_flags2)3428 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3429 u16 raweth_qp1_flags2)
3430 {
3431 bool is_ipv6 = false, is_ipv4 = false;
3432
3433 /* raweth_qp1_flags Bit 9-6 indicates itype */
3434 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3435 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3436 return -1;
3437
3438 if (raweth_qp1_flags2 &
3439 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3440 raweth_qp1_flags2 &
3441 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3442 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3443 (raweth_qp1_flags2 &
3444 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3445 (is_ipv6 = true) : (is_ipv4 = true);
3446 return ((is_ipv6) ?
3447 BNXT_RE_ROCEV2_IPV6_PACKET :
3448 BNXT_RE_ROCEV2_IPV4_PACKET);
3449 } else {
3450 return BNXT_RE_ROCE_V1_PACKET;
3451 }
3452 }
3453
bnxt_re_to_ib_nw_type(int nw_type)3454 static int bnxt_re_to_ib_nw_type(int nw_type)
3455 {
3456 u8 nw_hdr_type = 0xFF;
3457
3458 switch (nw_type) {
3459 case BNXT_RE_ROCE_V1_PACKET:
3460 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3461 break;
3462 case BNXT_RE_ROCEV2_IPV4_PACKET:
3463 nw_hdr_type = RDMA_NETWORK_IPV4;
3464 break;
3465 case BNXT_RE_ROCEV2_IPV6_PACKET:
3466 nw_hdr_type = RDMA_NETWORK_IPV6;
3467 break;
3468 }
3469 return nw_hdr_type;
3470 }
3471
bnxt_re_is_loopback_packet(struct bnxt_re_dev * rdev,void * rq_hdr_buf)3472 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3473 void *rq_hdr_buf)
3474 {
3475 u8 *tmp_buf = NULL;
3476 struct ethhdr *eth_hdr;
3477 u16 eth_type;
3478 bool rc = false;
3479
3480 tmp_buf = (u8 *)rq_hdr_buf;
3481 /*
3482 * If dest mac is not same as I/F mac, this could be a
3483 * loopback address or multicast address, check whether
3484 * it is a loopback packet
3485 */
3486 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3487 tmp_buf += 4;
3488 /* Check the ether type */
3489 eth_hdr = (struct ethhdr *)tmp_buf;
3490 eth_type = ntohs(eth_hdr->h_proto);
3491 switch (eth_type) {
3492 case ETH_P_IBOE:
3493 rc = true;
3494 break;
3495 case ETH_P_IP:
3496 case ETH_P_IPV6: {
3497 u32 len;
3498 struct udphdr *udp_hdr;
3499
3500 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3501 sizeof(struct ipv6hdr));
3502 tmp_buf += sizeof(struct ethhdr) + len;
3503 udp_hdr = (struct udphdr *)tmp_buf;
3504 if (ntohs(udp_hdr->dest) ==
3505 ROCE_V2_UDP_DPORT)
3506 rc = true;
3507 break;
3508 }
3509 default:
3510 break;
3511 }
3512 }
3513
3514 return rc;
3515 }
3516
bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp * gsi_qp,struct bnxt_qplib_cqe * cqe)3517 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3518 struct bnxt_qplib_cqe *cqe)
3519 {
3520 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3521 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3522 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3523 dma_addr_t shrq_hdr_buf_map;
3524 struct ib_sge s_sge[2] = {};
3525 struct ib_sge r_sge[2] = {};
3526 struct bnxt_re_ah *gsi_sah;
3527 struct ib_recv_wr rwr = {};
3528 dma_addr_t rq_hdr_buf_map;
3529 struct ib_ud_wr udwr = {};
3530 struct ib_send_wr *swr;
3531 u32 skip_bytes = 0;
3532 int pkt_type = 0;
3533 void *rq_hdr_buf;
3534 u32 offset = 0;
3535 u32 tbl_idx;
3536 int rc;
3537
3538 swr = &udwr.wr;
3539 tbl_idx = cqe->wr_id;
3540
3541 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3542 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3543 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3544 tbl_idx);
3545
3546 /* Shadow QP header buffer */
3547 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3548 tbl_idx);
3549 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3550
3551 /* Store this cqe */
3552 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3553 sqp_entry->qp1_qp = gsi_qp;
3554
3555 /* Find packet type from the cqe */
3556
3557 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3558 cqe->raweth_qp1_flags2);
3559 if (pkt_type < 0) {
3560 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3561 return -EINVAL;
3562 }
3563
3564 /* Adjust the offset for the user buffer and post in the rq */
3565
3566 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3567 offset = 20;
3568
3569 /*
3570 * QP1 loopback packet has 4 bytes of internal header before
3571 * ether header. Skip these four bytes.
3572 */
3573 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3574 skip_bytes = 4;
3575
3576 /* First send SGE . Skip the ether header*/
3577 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3578 + skip_bytes;
3579 s_sge[0].lkey = 0xFFFFFFFF;
3580 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3581 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3582
3583 /* Second Send SGE */
3584 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3585 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3586 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3587 s_sge[1].addr += 8;
3588 s_sge[1].lkey = 0xFFFFFFFF;
3589 s_sge[1].length = 256;
3590
3591 /* First recv SGE */
3592
3593 r_sge[0].addr = shrq_hdr_buf_map;
3594 r_sge[0].lkey = 0xFFFFFFFF;
3595 r_sge[0].length = 40;
3596
3597 r_sge[1].addr = sqp_entry->sge.addr + offset;
3598 r_sge[1].lkey = sqp_entry->sge.lkey;
3599 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3600
3601 /* Create receive work request */
3602 rwr.num_sge = 2;
3603 rwr.sg_list = r_sge;
3604 rwr.wr_id = tbl_idx;
3605 rwr.next = NULL;
3606
3607 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3608 if (rc) {
3609 ibdev_err(&rdev->ibdev,
3610 "Failed to post Rx buffers to shadow QP");
3611 return -ENOMEM;
3612 }
3613
3614 swr->num_sge = 2;
3615 swr->sg_list = s_sge;
3616 swr->wr_id = tbl_idx;
3617 swr->opcode = IB_WR_SEND;
3618 swr->next = NULL;
3619 gsi_sah = rdev->gsi_ctx.gsi_sah;
3620 udwr.ah = &gsi_sah->ib_ah;
3621 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3622 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3623
3624 /* post data received in the send queue */
3625 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3626 }
3627
bnxt_re_process_res_rawqp1_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3628 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3629 struct bnxt_qplib_cqe *cqe)
3630 {
3631 wc->opcode = IB_WC_RECV;
3632 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3633 wc->wc_flags |= IB_WC_GRH;
3634 }
3635
bnxt_re_check_if_vlan_valid(struct bnxt_re_dev * rdev,u16 vlan_id)3636 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3637 u16 vlan_id)
3638 {
3639 /*
3640 * Check if the vlan is configured in the host. If not configured, it
3641 * can be a transparent VLAN. So dont report the vlan id.
3642 */
3643 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3644 htons(ETH_P_8021Q), vlan_id))
3645 return false;
3646 return true;
3647 }
3648
bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe * orig_cqe,u16 * vid,u8 * sl)3649 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3650 u16 *vid, u8 *sl)
3651 {
3652 bool ret = false;
3653 u32 metadata;
3654 u16 tpid;
3655
3656 metadata = orig_cqe->raweth_qp1_metadata;
3657 if (orig_cqe->raweth_qp1_flags2 &
3658 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3659 tpid = ((metadata &
3660 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3661 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3662 if (tpid == ETH_P_8021Q) {
3663 *vid = metadata &
3664 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3665 *sl = (metadata &
3666 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3667 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3668 ret = true;
3669 }
3670 }
3671
3672 return ret;
3673 }
3674
bnxt_re_process_res_rc_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3675 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3676 struct bnxt_qplib_cqe *cqe)
3677 {
3678 wc->opcode = IB_WC_RECV;
3679 wc->status = __rc_to_ib_wc_status(cqe->status);
3680
3681 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3682 wc->wc_flags |= IB_WC_WITH_IMM;
3683 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3684 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3685 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3686 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3687 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3688 }
3689
bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp * gsi_sqp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3690 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3691 struct ib_wc *wc,
3692 struct bnxt_qplib_cqe *cqe)
3693 {
3694 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3695 struct bnxt_re_qp *gsi_qp = NULL;
3696 struct bnxt_qplib_cqe *orig_cqe = NULL;
3697 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3698 int nw_type;
3699 u32 tbl_idx;
3700 u16 vlan_id;
3701 u8 sl;
3702
3703 tbl_idx = cqe->wr_id;
3704
3705 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3706 gsi_qp = sqp_entry->qp1_qp;
3707 orig_cqe = &sqp_entry->cqe;
3708
3709 wc->wr_id = sqp_entry->wrid;
3710 wc->byte_len = orig_cqe->length;
3711 wc->qp = &gsi_qp->ib_qp;
3712
3713 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata);
3714 wc->src_qp = orig_cqe->src_qp;
3715 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3716 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3717 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3718 wc->vlan_id = vlan_id;
3719 wc->sl = sl;
3720 wc->wc_flags |= IB_WC_WITH_VLAN;
3721 }
3722 }
3723 wc->port_num = 1;
3724 wc->vendor_err = orig_cqe->status;
3725
3726 wc->opcode = IB_WC_RECV;
3727 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3728 wc->wc_flags |= IB_WC_GRH;
3729
3730 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3731 orig_cqe->raweth_qp1_flags2);
3732 if (nw_type >= 0) {
3733 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3734 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3735 }
3736 }
3737
bnxt_re_process_res_ud_wc(struct bnxt_re_qp * qp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3738 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3739 struct ib_wc *wc,
3740 struct bnxt_qplib_cqe *cqe)
3741 {
3742 struct bnxt_re_dev *rdev;
3743 u16 vlan_id = 0;
3744 u8 nw_type;
3745
3746 rdev = qp->rdev;
3747 wc->opcode = IB_WC_RECV;
3748 wc->status = __rc_to_ib_wc_status(cqe->status);
3749
3750 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3751 wc->wc_flags |= IB_WC_WITH_IMM;
3752 /* report only on GSI QP for Thor */
3753 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3754 wc->wc_flags |= IB_WC_GRH;
3755 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3756 wc->wc_flags |= IB_WC_WITH_SMAC;
3757 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3758 vlan_id = (cqe->cfa_meta & 0xFFF);
3759 }
3760 /* Mark only if vlan_id is non zero */
3761 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3762 wc->vlan_id = vlan_id;
3763 wc->wc_flags |= IB_WC_WITH_VLAN;
3764 }
3765 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3766 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3767 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3768 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3769 }
3770
3771 }
3772
send_phantom_wqe(struct bnxt_re_qp * qp)3773 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3774 {
3775 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3776 unsigned long flags;
3777 int rc;
3778
3779 spin_lock_irqsave(&qp->sq_lock, flags);
3780
3781 rc = bnxt_re_bind_fence_mw(lib_qp);
3782 if (!rc) {
3783 lib_qp->sq.phantom_wqe_cnt++;
3784 ibdev_dbg(&qp->rdev->ibdev,
3785 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3786 lib_qp->id, lib_qp->sq.hwq.prod,
3787 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3788 lib_qp->sq.phantom_wqe_cnt);
3789 }
3790
3791 spin_unlock_irqrestore(&qp->sq_lock, flags);
3792 return rc;
3793 }
3794
bnxt_re_poll_cq(struct ib_cq * ib_cq,int num_entries,struct ib_wc * wc)3795 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3796 {
3797 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3798 struct bnxt_re_qp *qp, *sh_qp;
3799 struct bnxt_qplib_cqe *cqe;
3800 int i, ncqe, budget;
3801 struct bnxt_qplib_q *sq;
3802 struct bnxt_qplib_qp *lib_qp;
3803 u32 tbl_idx;
3804 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3805 unsigned long flags;
3806
3807 /* User CQ; the only processing we do is to
3808 * complete any pending CQ resize operation.
3809 */
3810 if (cq->umem) {
3811 if (cq->resize_umem)
3812 bnxt_re_resize_cq_complete(cq);
3813 return 0;
3814 }
3815
3816 spin_lock_irqsave(&cq->cq_lock, flags);
3817 budget = min_t(u32, num_entries, cq->max_cql);
3818 num_entries = budget;
3819 if (!cq->cql) {
3820 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3821 goto exit;
3822 }
3823 cqe = &cq->cql[0];
3824 while (budget) {
3825 lib_qp = NULL;
3826 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3827 if (lib_qp) {
3828 sq = &lib_qp->sq;
3829 if (sq->send_phantom) {
3830 qp = container_of(lib_qp,
3831 struct bnxt_re_qp, qplib_qp);
3832 if (send_phantom_wqe(qp) == -ENOMEM)
3833 ibdev_err(&cq->rdev->ibdev,
3834 "Phantom failed! Scheduled to send again\n");
3835 else
3836 sq->send_phantom = false;
3837 }
3838 }
3839 if (ncqe < budget)
3840 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3841 cqe + ncqe,
3842 budget - ncqe);
3843
3844 if (!ncqe)
3845 break;
3846
3847 for (i = 0; i < ncqe; i++, cqe++) {
3848 /* Transcribe each qplib_wqe back to ib_wc */
3849 memset(wc, 0, sizeof(*wc));
3850
3851 wc->wr_id = cqe->wr_id;
3852 wc->byte_len = cqe->length;
3853 qp = container_of
3854 ((struct bnxt_qplib_qp *)
3855 (unsigned long)(cqe->qp_handle),
3856 struct bnxt_re_qp, qplib_qp);
3857 wc->qp = &qp->ib_qp;
3858 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3859 wc->ex.imm_data = cpu_to_be32(cqe->immdata);
3860 else
3861 wc->ex.invalidate_rkey = cqe->invrkey;
3862 wc->src_qp = cqe->src_qp;
3863 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3864 wc->port_num = 1;
3865 wc->vendor_err = cqe->status;
3866
3867 switch (cqe->opcode) {
3868 case CQ_BASE_CQE_TYPE_REQ:
3869 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3870 if (sh_qp &&
3871 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3872 /* Handle this completion with
3873 * the stored completion
3874 */
3875 memset(wc, 0, sizeof(*wc));
3876 continue;
3877 }
3878 bnxt_re_process_req_wc(wc, cqe);
3879 break;
3880 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3881 if (!cqe->status) {
3882 int rc = 0;
3883
3884 rc = bnxt_re_process_raw_qp_pkt_rx
3885 (qp, cqe);
3886 if (!rc) {
3887 memset(wc, 0, sizeof(*wc));
3888 continue;
3889 }
3890 cqe->status = -1;
3891 }
3892 /* Errors need not be looped back.
3893 * But change the wr_id to the one
3894 * stored in the table
3895 */
3896 tbl_idx = cqe->wr_id;
3897 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3898 wc->wr_id = sqp_entry->wrid;
3899 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3900 break;
3901 case CQ_BASE_CQE_TYPE_RES_RC:
3902 bnxt_re_process_res_rc_wc(wc, cqe);
3903 break;
3904 case CQ_BASE_CQE_TYPE_RES_UD:
3905 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3906 if (sh_qp &&
3907 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3908 /* Handle this completion with
3909 * the stored completion
3910 */
3911 if (cqe->status) {
3912 continue;
3913 } else {
3914 bnxt_re_process_res_shadow_qp_wc
3915 (qp, wc, cqe);
3916 break;
3917 }
3918 }
3919 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3920 break;
3921 default:
3922 ibdev_err(&cq->rdev->ibdev,
3923 "POLL CQ : type 0x%x not handled",
3924 cqe->opcode);
3925 continue;
3926 }
3927 wc++;
3928 budget--;
3929 }
3930 }
3931 exit:
3932 spin_unlock_irqrestore(&cq->cq_lock, flags);
3933 return num_entries - budget;
3934 }
3935
bnxt_re_req_notify_cq(struct ib_cq * ib_cq,enum ib_cq_notify_flags ib_cqn_flags)3936 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3937 enum ib_cq_notify_flags ib_cqn_flags)
3938 {
3939 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3940 int type = 0, rc = 0;
3941 unsigned long flags;
3942
3943 spin_lock_irqsave(&cq->cq_lock, flags);
3944 /* Trigger on the very next completion */
3945 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3946 type = DBC_DBC_TYPE_CQ_ARMALL;
3947 /* Trigger on the next solicited completion */
3948 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3949 type = DBC_DBC_TYPE_CQ_ARMSE;
3950
3951 /* Poll to see if there are missed events */
3952 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3953 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3954 rc = 1;
3955 goto exit;
3956 }
3957 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3958
3959 exit:
3960 spin_unlock_irqrestore(&cq->cq_lock, flags);
3961 return rc;
3962 }
3963
3964 /* Memory Regions */
bnxt_re_get_dma_mr(struct ib_pd * ib_pd,int mr_access_flags)3965 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3966 {
3967 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3968 struct bnxt_re_dev *rdev = pd->rdev;
3969 struct bnxt_re_mr *mr;
3970 u32 active_mrs;
3971 int rc;
3972
3973 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3974 if (!mr)
3975 return ERR_PTR(-ENOMEM);
3976
3977 mr->rdev = rdev;
3978 mr->qplib_mr.pd = &pd->qplib_pd;
3979 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
3980 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3981
3982 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
3983 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
3984
3985 /* Allocate and register 0 as the address */
3986 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3987 if (rc)
3988 goto fail;
3989
3990 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3991 mr->qplib_mr.total_size = -1; /* Infinte length */
3992 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
3993 PAGE_SIZE);
3994 if (rc)
3995 goto fail_mr;
3996
3997 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3998 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3999 IB_ACCESS_REMOTE_ATOMIC))
4000 mr->ib_mr.rkey = mr->ib_mr.lkey;
4001 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4002 if (active_mrs > rdev->stats.res.mr_watermark)
4003 rdev->stats.res.mr_watermark = active_mrs;
4004
4005 return &mr->ib_mr;
4006
4007 fail_mr:
4008 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4009 fail:
4010 kfree(mr);
4011 return ERR_PTR(rc);
4012 }
4013
bnxt_re_dereg_mr(struct ib_mr * ib_mr,struct ib_udata * udata)4014 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
4015 {
4016 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4017 struct bnxt_re_dev *rdev = mr->rdev;
4018 int rc;
4019
4020 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4021 if (rc) {
4022 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
4023 return rc;
4024 }
4025
4026 if (mr->pages) {
4027 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
4028 &mr->qplib_frpl);
4029 kfree(mr->pages);
4030 mr->npages = 0;
4031 mr->pages = NULL;
4032 }
4033 ib_umem_release(mr->ib_umem);
4034
4035 kfree(mr);
4036 atomic_dec(&rdev->stats.res.mr_count);
4037 return rc;
4038 }
4039
bnxt_re_set_page(struct ib_mr * ib_mr,u64 addr)4040 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
4041 {
4042 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4043
4044 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
4045 return -ENOMEM;
4046
4047 mr->pages[mr->npages++] = addr;
4048 return 0;
4049 }
4050
bnxt_re_map_mr_sg(struct ib_mr * ib_mr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)4051 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
4052 unsigned int *sg_offset)
4053 {
4054 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4055
4056 mr->npages = 0;
4057 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
4058 }
4059
bnxt_re_alloc_mr(struct ib_pd * ib_pd,enum ib_mr_type type,u32 max_num_sg)4060 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
4061 u32 max_num_sg)
4062 {
4063 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4064 struct bnxt_re_dev *rdev = pd->rdev;
4065 struct bnxt_re_mr *mr = NULL;
4066 u32 active_mrs;
4067 int rc;
4068
4069 if (type != IB_MR_TYPE_MEM_REG) {
4070 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
4071 return ERR_PTR(-EINVAL);
4072 }
4073 if (max_num_sg > MAX_PBL_LVL_1_PGS)
4074 return ERR_PTR(-EINVAL);
4075
4076 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
4077 if (!mr)
4078 return ERR_PTR(-ENOMEM);
4079
4080 mr->rdev = rdev;
4081 mr->qplib_mr.pd = &pd->qplib_pd;
4082 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR;
4083 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
4084
4085 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4086 if (rc)
4087 goto bail;
4088
4089 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4090 mr->ib_mr.rkey = mr->ib_mr.lkey;
4091
4092 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
4093 if (!mr->pages) {
4094 rc = -ENOMEM;
4095 goto fail;
4096 }
4097 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
4098 &mr->qplib_frpl, max_num_sg);
4099 if (rc) {
4100 ibdev_err(&rdev->ibdev,
4101 "Failed to allocate HW FR page list");
4102 goto fail_mr;
4103 }
4104
4105 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4106 if (active_mrs > rdev->stats.res.mr_watermark)
4107 rdev->stats.res.mr_watermark = active_mrs;
4108 return &mr->ib_mr;
4109
4110 fail_mr:
4111 kfree(mr->pages);
4112 fail:
4113 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4114 bail:
4115 kfree(mr);
4116 return ERR_PTR(rc);
4117 }
4118
bnxt_re_alloc_mw(struct ib_pd * ib_pd,enum ib_mw_type type,struct ib_udata * udata)4119 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
4120 struct ib_udata *udata)
4121 {
4122 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4123 struct bnxt_re_dev *rdev = pd->rdev;
4124 struct bnxt_re_mw *mw;
4125 u32 active_mws;
4126 int rc;
4127
4128 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
4129 if (!mw)
4130 return ERR_PTR(-ENOMEM);
4131 mw->rdev = rdev;
4132 mw->qplib_mw.pd = &pd->qplib_pd;
4133
4134 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
4135 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
4136 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
4137 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
4138 if (rc) {
4139 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
4140 goto fail;
4141 }
4142 mw->ib_mw.rkey = mw->qplib_mw.rkey;
4143
4144 active_mws = atomic_inc_return(&rdev->stats.res.mw_count);
4145 if (active_mws > rdev->stats.res.mw_watermark)
4146 rdev->stats.res.mw_watermark = active_mws;
4147 return &mw->ib_mw;
4148
4149 fail:
4150 kfree(mw);
4151 return ERR_PTR(rc);
4152 }
4153
bnxt_re_dealloc_mw(struct ib_mw * ib_mw)4154 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
4155 {
4156 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
4157 struct bnxt_re_dev *rdev = mw->rdev;
4158 int rc;
4159
4160 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
4161 if (rc) {
4162 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
4163 return rc;
4164 }
4165
4166 kfree(mw);
4167 atomic_dec(&rdev->stats.res.mw_count);
4168 return rc;
4169 }
4170
__bnxt_re_user_reg_mr(struct ib_pd * ib_pd,u64 length,u64 virt_addr,int mr_access_flags,struct ib_umem * umem)4171 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr,
4172 int mr_access_flags, struct ib_umem *umem)
4173 {
4174 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4175 struct bnxt_re_dev *rdev = pd->rdev;
4176 unsigned long page_size;
4177 struct bnxt_re_mr *mr;
4178 int umem_pgs, rc;
4179 u32 active_mrs;
4180
4181 if (length > BNXT_RE_MAX_MR_SIZE) {
4182 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
4183 length, BNXT_RE_MAX_MR_SIZE);
4184 return ERR_PTR(-ENOMEM);
4185 }
4186
4187 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr);
4188 if (!page_size) {
4189 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
4190 return ERR_PTR(-EINVAL);
4191 }
4192
4193 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
4194 if (!mr)
4195 return ERR_PTR(-ENOMEM);
4196
4197 mr->rdev = rdev;
4198 mr->qplib_mr.pd = &pd->qplib_pd;
4199 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
4200 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
4201
4202 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) {
4203 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4204 if (rc) {
4205 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc);
4206 rc = -EIO;
4207 goto free_mr;
4208 }
4209 /* The fixed portion of the rkey is the same as the lkey */
4210 mr->ib_mr.rkey = mr->qplib_mr.rkey;
4211 } else {
4212 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
4213 }
4214 mr->ib_umem = umem;
4215 mr->qplib_mr.va = virt_addr;
4216 mr->qplib_mr.total_size = length;
4217
4218 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
4219 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
4220
4221 umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
4222 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
4223 umem_pgs, page_size);
4224 if (rc) {
4225 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc);
4226 rc = -EIO;
4227 goto free_mrw;
4228 }
4229
4230 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4231 mr->ib_mr.rkey = mr->qplib_mr.lkey;
4232 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4233 if (active_mrs > rdev->stats.res.mr_watermark)
4234 rdev->stats.res.mr_watermark = active_mrs;
4235
4236 return &mr->ib_mr;
4237
4238 free_mrw:
4239 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4240 free_mr:
4241 kfree(mr);
4242 return ERR_PTR(rc);
4243 }
4244
bnxt_re_reg_user_mr(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int mr_access_flags,struct ib_udata * udata)4245 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
4246 u64 virt_addr, int mr_access_flags,
4247 struct ib_udata *udata)
4248 {
4249 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4250 struct bnxt_re_dev *rdev = pd->rdev;
4251 struct ib_umem *umem;
4252 struct ib_mr *ib_mr;
4253
4254 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
4255 if (IS_ERR(umem))
4256 return ERR_CAST(umem);
4257
4258 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4259 if (IS_ERR(ib_mr))
4260 ib_umem_release(umem);
4261 return ib_mr;
4262 }
4263
bnxt_re_reg_user_mr_dmabuf(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int fd,int mr_access_flags,struct uverbs_attr_bundle * attrs)4264 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start,
4265 u64 length, u64 virt_addr, int fd,
4266 int mr_access_flags,
4267 struct uverbs_attr_bundle *attrs)
4268 {
4269 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4270 struct bnxt_re_dev *rdev = pd->rdev;
4271 struct ib_umem_dmabuf *umem_dmabuf;
4272 struct ib_umem *umem;
4273 struct ib_mr *ib_mr;
4274
4275 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length,
4276 fd, mr_access_flags);
4277 if (IS_ERR(umem_dmabuf))
4278 return ERR_CAST(umem_dmabuf);
4279
4280 umem = &umem_dmabuf->umem;
4281
4282 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4283 if (IS_ERR(ib_mr))
4284 ib_umem_release(umem);
4285 return ib_mr;
4286 }
4287
bnxt_re_alloc_ucontext(struct ib_ucontext * ctx,struct ib_udata * udata)4288 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
4289 {
4290 struct ib_device *ibdev = ctx->device;
4291 struct bnxt_re_ucontext *uctx =
4292 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
4293 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
4294 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
4295 struct bnxt_re_user_mmap_entry *entry;
4296 struct bnxt_re_uctx_resp resp = {};
4297 struct bnxt_re_uctx_req ureq = {};
4298 u32 chip_met_rev_num = 0;
4299 int rc;
4300
4301 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
4302
4303 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
4304 ibdev_dbg(ibdev, " is different from the device %d ",
4305 BNXT_RE_ABI_VERSION);
4306 return -EPERM;
4307 }
4308
4309 uctx->rdev = rdev;
4310
4311 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
4312 if (!uctx->shpg) {
4313 rc = -ENOMEM;
4314 goto fail;
4315 }
4316 spin_lock_init(&uctx->sh_lock);
4317
4318 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
4319 chip_met_rev_num = rdev->chip_ctx->chip_num;
4320 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
4321 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
4322 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
4323 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
4324 resp.chip_id0 = chip_met_rev_num;
4325 /*Temp, Use xa_alloc instead */
4326 resp.dev_id = rdev->en_dev->pdev->devfn;
4327 resp.max_qp = rdev->qplib_ctx.qpc_count;
4328 resp.pg_size = PAGE_SIZE;
4329 resp.cqe_sz = sizeof(struct cq_base);
4330 resp.max_cqd = dev_attr->max_cq_wqes;
4331
4332 if (rdev->chip_ctx->modes.db_push)
4333 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED;
4334
4335 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL);
4336 if (!entry) {
4337 rc = -ENOMEM;
4338 goto cfail;
4339 }
4340 uctx->shpage_mmap = &entry->rdma_entry;
4341 if (rdev->pacing.dbr_pacing)
4342 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;
4343
4344 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
4345 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED;
4346
4347 if (udata->inlen >= sizeof(ureq)) {
4348 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)));
4349 if (rc)
4350 goto cfail;
4351 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) {
4352 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;
4353 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED;
4354 }
4355 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) {
4356 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
4357 resp.mode = rdev->chip_ctx->modes.wqe_mode;
4358 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
4359 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED;
4360 }
4361 }
4362
4363 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
4364 if (rc) {
4365 ibdev_err(ibdev, "Failed to copy user context");
4366 rc = -EFAULT;
4367 goto cfail;
4368 }
4369
4370 return 0;
4371 cfail:
4372 free_page((unsigned long)uctx->shpg);
4373 uctx->shpg = NULL;
4374 fail:
4375 return rc;
4376 }
4377
bnxt_re_dealloc_ucontext(struct ib_ucontext * ib_uctx)4378 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
4379 {
4380 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4381 struct bnxt_re_ucontext,
4382 ib_uctx);
4383
4384 struct bnxt_re_dev *rdev = uctx->rdev;
4385
4386 rdma_user_mmap_entry_remove(uctx->shpage_mmap);
4387 uctx->shpage_mmap = NULL;
4388 if (uctx->shpg)
4389 free_page((unsigned long)uctx->shpg);
4390
4391 if (uctx->dpi.dbr) {
4392 /* Free DPI only if this is the first PD allocated by the
4393 * application and mark the context dpi as NULL
4394 */
4395 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi);
4396 uctx->dpi.dbr = NULL;
4397 }
4398 }
4399
bnxt_re_search_for_cq(struct bnxt_re_dev * rdev,u32 cq_id)4400 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id)
4401 {
4402 struct bnxt_re_cq *cq = NULL, *tmp_cq;
4403
4404 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) {
4405 if (tmp_cq->qplib_cq.id == cq_id) {
4406 cq = tmp_cq;
4407 break;
4408 }
4409 }
4410 return cq;
4411 }
4412
bnxt_re_search_for_srq(struct bnxt_re_dev * rdev,u32 srq_id)4413 static struct bnxt_re_srq *bnxt_re_search_for_srq(struct bnxt_re_dev *rdev, u32 srq_id)
4414 {
4415 struct bnxt_re_srq *srq = NULL, *tmp_srq;
4416
4417 hash_for_each_possible(rdev->srq_hash, tmp_srq, hash_entry, srq_id) {
4418 if (tmp_srq->qplib_srq.id == srq_id) {
4419 srq = tmp_srq;
4420 break;
4421 }
4422 }
4423 return srq;
4424 }
4425
4426 /* Helper function to mmap the virtual memory from user app */
bnxt_re_mmap(struct ib_ucontext * ib_uctx,struct vm_area_struct * vma)4427 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
4428 {
4429 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4430 struct bnxt_re_ucontext,
4431 ib_uctx);
4432 struct bnxt_re_user_mmap_entry *bnxt_entry;
4433 struct rdma_user_mmap_entry *rdma_entry;
4434 int ret = 0;
4435 u64 pfn;
4436
4437 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma);
4438 if (!rdma_entry)
4439 return -EINVAL;
4440
4441 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4442 rdma_entry);
4443
4444 switch (bnxt_entry->mmap_flag) {
4445 case BNXT_RE_MMAP_WC_DB:
4446 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4447 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4448 pgprot_writecombine(vma->vm_page_prot),
4449 rdma_entry);
4450 break;
4451 case BNXT_RE_MMAP_UC_DB:
4452 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4453 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4454 pgprot_noncached(vma->vm_page_prot),
4455 rdma_entry);
4456 break;
4457 case BNXT_RE_MMAP_SH_PAGE:
4458 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg));
4459 break;
4460 case BNXT_RE_MMAP_DBR_BAR:
4461 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4462 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4463 pgprot_noncached(vma->vm_page_prot),
4464 rdma_entry);
4465 break;
4466 case BNXT_RE_MMAP_DBR_PAGE:
4467 case BNXT_RE_MMAP_TOGGLE_PAGE:
4468 /* Driver doesn't expect write access for user space */
4469 if (vma->vm_flags & VM_WRITE)
4470 ret = -EFAULT;
4471 else
4472 ret = vm_insert_page(vma, vma->vm_start,
4473 virt_to_page((void *)bnxt_entry->mem_offset));
4474 break;
4475 default:
4476 ret = -EINVAL;
4477 break;
4478 }
4479
4480 rdma_user_mmap_entry_put(rdma_entry);
4481 return ret;
4482 }
4483
bnxt_re_mmap_free(struct rdma_user_mmap_entry * rdma_entry)4484 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
4485 {
4486 struct bnxt_re_user_mmap_entry *bnxt_entry;
4487
4488 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4489 rdma_entry);
4490
4491 kfree(bnxt_entry);
4492 }
4493
UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)4494 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs)
4495 {
4496 struct bnxt_re_ucontext *uctx;
4497
4498 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4499 bnxt_re_pacing_alert(uctx->rdev);
4500 return 0;
4501 }
4502
UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)4503 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs)
4504 {
4505 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4506 enum bnxt_re_alloc_page_type alloc_type;
4507 struct bnxt_re_user_mmap_entry *entry;
4508 enum bnxt_re_mmap_flag mmap_flag;
4509 struct bnxt_qplib_chip_ctx *cctx;
4510 struct bnxt_re_ucontext *uctx;
4511 struct bnxt_re_dev *rdev;
4512 u64 mmap_offset;
4513 u32 length;
4514 u32 dpi;
4515 u64 addr;
4516 int err;
4517
4518 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4519 if (IS_ERR(uctx))
4520 return PTR_ERR(uctx);
4521
4522 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE);
4523 if (err)
4524 return err;
4525
4526 rdev = uctx->rdev;
4527 cctx = rdev->chip_ctx;
4528
4529 switch (alloc_type) {
4530 case BNXT_RE_ALLOC_WC_PAGE:
4531 if (cctx->modes.db_push) {
4532 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi,
4533 uctx, BNXT_QPLIB_DPI_TYPE_WC))
4534 return -ENOMEM;
4535 length = PAGE_SIZE;
4536 dpi = uctx->wcdpi.dpi;
4537 addr = (u64)uctx->wcdpi.umdbr;
4538 mmap_flag = BNXT_RE_MMAP_WC_DB;
4539 } else {
4540 return -EINVAL;
4541 }
4542
4543 break;
4544 case BNXT_RE_ALLOC_DBR_BAR_PAGE:
4545 length = PAGE_SIZE;
4546 addr = (u64)rdev->pacing.dbr_bar_addr;
4547 mmap_flag = BNXT_RE_MMAP_DBR_BAR;
4548 break;
4549
4550 case BNXT_RE_ALLOC_DBR_PAGE:
4551 length = PAGE_SIZE;
4552 addr = (u64)rdev->pacing.dbr_page;
4553 mmap_flag = BNXT_RE_MMAP_DBR_PAGE;
4554 break;
4555
4556 default:
4557 return -EOPNOTSUPP;
4558 }
4559
4560 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset);
4561 if (!entry)
4562 return -ENOMEM;
4563
4564 uobj->object = entry;
4565 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4566 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4567 &mmap_offset, sizeof(mmap_offset));
4568 if (err)
4569 return err;
4570
4571 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4572 &length, sizeof(length));
4573 if (err)
4574 return err;
4575
4576 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI,
4577 &dpi, sizeof(length));
4578 if (err)
4579 return err;
4580
4581 return 0;
4582 }
4583
alloc_page_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)4584 static int alloc_page_obj_cleanup(struct ib_uobject *uobject,
4585 enum rdma_remove_reason why,
4586 struct uverbs_attr_bundle *attrs)
4587 {
4588 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4589 struct bnxt_re_ucontext *uctx = entry->uctx;
4590
4591 switch (entry->mmap_flag) {
4592 case BNXT_RE_MMAP_WC_DB:
4593 if (uctx && uctx->wcdpi.dbr) {
4594 struct bnxt_re_dev *rdev = uctx->rdev;
4595
4596 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi);
4597 uctx->wcdpi.dbr = NULL;
4598 }
4599 break;
4600 case BNXT_RE_MMAP_DBR_BAR:
4601 case BNXT_RE_MMAP_DBR_PAGE:
4602 break;
4603 default:
4604 goto exit;
4605 }
4606 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4607 exit:
4608 return 0;
4609 }
4610
4611 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE,
4612 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE,
4613 BNXT_RE_OBJECT_ALLOC_PAGE,
4614 UVERBS_ACCESS_NEW,
4615 UA_MANDATORY),
4616 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE,
4617 enum bnxt_re_alloc_page_type,
4618 UA_MANDATORY),
4619 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4620 UVERBS_ATTR_TYPE(u64),
4621 UA_MANDATORY),
4622 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4623 UVERBS_ATTR_TYPE(u32),
4624 UA_MANDATORY),
4625 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI,
4626 UVERBS_ATTR_TYPE(u32),
4627 UA_MANDATORY));
4628
4629 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE,
4630 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE,
4631 BNXT_RE_OBJECT_ALLOC_PAGE,
4632 UVERBS_ACCESS_DESTROY,
4633 UA_MANDATORY));
4634
4635 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE,
4636 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup),
4637 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE),
4638 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE));
4639
4640 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV);
4641
4642 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV,
4643 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV));
4644
4645 /* Toggle MEM */
UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)4646 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs)
4647 {
4648 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4649 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;
4650 enum bnxt_re_get_toggle_mem_type res_type;
4651 struct bnxt_re_user_mmap_entry *entry;
4652 struct bnxt_re_ucontext *uctx;
4653 struct ib_ucontext *ib_uctx;
4654 struct bnxt_re_dev *rdev;
4655 struct bnxt_re_srq *srq;
4656 u32 length = PAGE_SIZE;
4657 struct bnxt_re_cq *cq;
4658 u64 mem_offset;
4659 u32 offset = 0;
4660 u64 addr = 0;
4661 u32 res_id;
4662 int err;
4663
4664 ib_uctx = ib_uverbs_get_ucontext(attrs);
4665 if (IS_ERR(ib_uctx))
4666 return PTR_ERR(ib_uctx);
4667
4668 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE);
4669 if (err)
4670 return err;
4671
4672 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
4673 rdev = uctx->rdev;
4674 err = uverbs_copy_from(&res_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID);
4675 if (err)
4676 return err;
4677
4678 switch (res_type) {
4679 case BNXT_RE_CQ_TOGGLE_MEM:
4680 cq = bnxt_re_search_for_cq(rdev, res_id);
4681 if (!cq)
4682 return -EINVAL;
4683
4684 addr = (u64)cq->uctx_cq_page;
4685 break;
4686 case BNXT_RE_SRQ_TOGGLE_MEM:
4687 srq = bnxt_re_search_for_srq(rdev, res_id);
4688 if (!srq)
4689 return -EINVAL;
4690
4691 addr = (u64)srq->uctx_srq_page;
4692 break;
4693
4694 default:
4695 return -EOPNOTSUPP;
4696 }
4697
4698 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset);
4699 if (!entry)
4700 return -ENOMEM;
4701
4702 uobj->object = entry;
4703 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4704 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4705 &mem_offset, sizeof(mem_offset));
4706 if (err)
4707 return err;
4708
4709 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4710 &length, sizeof(length));
4711 if (err)
4712 return err;
4713
4714 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4715 &offset, sizeof(length));
4716 if (err)
4717 return err;
4718
4719 return 0;
4720 }
4721
get_toggle_mem_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)4722 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject,
4723 enum rdma_remove_reason why,
4724 struct uverbs_attr_bundle *attrs)
4725 {
4726 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4727
4728 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4729 return 0;
4730 }
4731
4732 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM,
4733 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE,
4734 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4735 UVERBS_ACCESS_NEW,
4736 UA_MANDATORY),
4737 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE,
4738 enum bnxt_re_get_toggle_mem_type,
4739 UA_MANDATORY),
4740 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID,
4741 UVERBS_ATTR_TYPE(u32),
4742 UA_MANDATORY),
4743 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4744 UVERBS_ATTR_TYPE(u64),
4745 UA_MANDATORY),
4746 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4747 UVERBS_ATTR_TYPE(u32),
4748 UA_MANDATORY),
4749 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4750 UVERBS_ATTR_TYPE(u32),
4751 UA_MANDATORY));
4752
4753 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,
4754 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE,
4755 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4756 UVERBS_ACCESS_DESTROY,
4757 UA_MANDATORY));
4758
4759 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4760 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup),
4761 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM),
4762 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM));
4763
4764 const struct uapi_definition bnxt_re_uapi_defs[] = {
4765 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE),
4766 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV),
4767 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM),
4768 {}
4769 };
4770