1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2015 Glider bvba
6 *
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
8 *
9 * Copyright (C) 2013 Ideas On Board SPRL
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_clock.h>
25 #include <linux/pm_domain.h>
26 #include <linux/psci.h>
27 #include <linux/reset-controller.h>
28 #include <linux/slab.h>
29 #include <linux/string_choices.h>
30
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
35
36 #ifdef DEBUG
37 #define WARN_DEBUG(x) WARN_ON(x)
38 #else
39 #define WARN_DEBUG(x) do { } while (0)
40 #endif
41
42 #define RZT2H_RESET_REG_READ_COUNT 7
43
44 /*
45 * Module Standby and Software Reset register offsets.
46 *
47 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
48 * R-Car Gen2, R-Car Gen3, and RZ/G1.
49 * These are NOT valid for R-Car Gen1 and RZ/A1!
50 */
51
52 /*
53 * Module Stop Status Register offsets
54 */
55
56 static const u16 mstpsr[] = {
57 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
58 0x9A0, 0x9A4, 0x9A8, 0x9AC,
59 };
60
61 static const u16 mstpsr_for_gen4[] = {
62 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
63 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
64 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
65 0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74,
66 };
67
68 /*
69 * System Module Stop Control Register offsets
70 */
71
72 static const u16 smstpcr[] = {
73 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
74 0x990, 0x994, 0x998, 0x99C,
75 };
76
77 static const u16 mstpcr_for_gen4[] = {
78 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
79 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
80 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
81 0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74,
82 };
83
84 /*
85 * Module Stop Control Register (RZ/T2H)
86 * RZ/T2H has 2 registers blocks,
87 * Bit 12 is used to differentiate them
88 */
89
90 #define RZT2H_MSTPCR_BLOCK_SHIFT 12
91 #define RZT2H_MSTPCR_OFFSET_MASK GENMASK(11, 0)
92 #define RZT2H_MSTPCR(block, offset) (((block) << RZT2H_MSTPCR_BLOCK_SHIFT) | \
93 ((offset) & RZT2H_MSTPCR_OFFSET_MASK))
94
95 #define RZT2H_MSTPCR_BLOCK(x) ((x) >> RZT2H_MSTPCR_BLOCK_SHIFT)
96 #define RZT2H_MSTPCR_OFFSET(x) ((x) & RZT2H_MSTPCR_OFFSET_MASK)
97
98 static const u16 mstpcr_for_rzt2h[] = {
99 RZT2H_MSTPCR(0, 0x300), /* MSTPCRA */
100 RZT2H_MSTPCR(0, 0x304), /* MSTPCRB */
101 RZT2H_MSTPCR(0, 0x308), /* MSTPCRC */
102 RZT2H_MSTPCR(0, 0x30c), /* MSTPCRD */
103 RZT2H_MSTPCR(0, 0x310), /* MSTPCRE */
104 0,
105 RZT2H_MSTPCR(1, 0x318), /* MSTPCRG */
106 0,
107 RZT2H_MSTPCR(1, 0x320), /* MSTPCRI */
108 RZT2H_MSTPCR(0, 0x324), /* MSTPCRJ */
109 RZT2H_MSTPCR(0, 0x328), /* MSTPCRK */
110 RZT2H_MSTPCR(0, 0x32c), /* MSTPCRL */
111 RZT2H_MSTPCR(0, 0x330), /* MSTPCRM */
112 RZT2H_MSTPCR(1, 0x334), /* MSTPCRN */
113 };
114
115 /*
116 * Standby Control Register offsets (RZ/A)
117 * Base address is FRQCR register
118 */
119
120 static const u16 stbcr[] = {
121 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
122 0x424, 0x428, 0x42C,
123 };
124
125 /*
126 * Software Reset Register offsets
127 */
128
129 static const u16 srcr[] = {
130 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
131 0x920, 0x924, 0x928, 0x92C,
132 };
133
134 static const u16 srcr_for_gen4[] = {
135 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
136 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
137 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
138 0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74,
139 };
140
141 static const u16 mrcr_for_rzt2h[] = {
142 0x240, /* MRCTLA */
143 0x244, /* Reserved */
144 0x248, /* Reserved */
145 0x24C, /* Reserved */
146 0x250, /* MRCTLE */
147 0x254, /* Reserved */
148 0x258, /* Reserved */
149 0x25C, /* Reserved */
150 0x260, /* MRCTLI */
151 0x264, /* Reserved */
152 0x268, /* Reserved */
153 0x26C, /* Reserved */
154 0x270, /* MRCTLM */
155 };
156
157 /*
158 * Software Reset Clearing Register offsets
159 */
160
161 static const u16 srstclr[] = {
162 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
163 0x960, 0x964, 0x968, 0x96C,
164 };
165
166 static const u16 srstclr_for_gen4[] = {
167 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
168 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
169 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
170 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4,
171 };
172
173 /**
174 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
175 * and Software Reset Private Data
176 *
177 * @pub: Data passed to clock registration callback
178 * @rcdev: Optional reset controller entity
179 * @dev: CPG/MSSR device
180 * @reg_layout: CPG/MSSR register layout
181 * @np: Device node in DT for this CPG/MSSR module
182 * @num_core_clks: Number of Core Clocks in clks[]
183 * @num_mod_clks: Number of Module Clocks in clks[]
184 * @last_dt_core_clk: ID of the last Core Clock exported to DT
185 * @status_regs: Pointer to status registers array
186 * @control_regs: Pointer to control registers array
187 * @reset_regs: Pointer to reset registers array
188 * @reset_clear_regs: Pointer to reset clearing registers array
189 * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control
190 * [].val: Saved values of SMSTPCR[]
191 * @reserved_ids: Temporary used, reserved id list
192 * @num_reserved_ids: Temporary used, number of reserved id list
193 * @clks: Array containing all Core and Module Clocks
194 */
195 struct cpg_mssr_priv {
196 struct cpg_mssr_pub pub;
197 #ifdef CONFIG_RESET_CONTROLLER
198 struct reset_controller_dev rcdev;
199 #endif
200 struct device *dev;
201 enum clk_reg_layout reg_layout;
202 struct device_node *np;
203
204 unsigned int num_core_clks;
205 unsigned int num_mod_clks;
206 unsigned int last_dt_core_clk;
207
208 const u16 *status_regs;
209 const u16 *control_regs;
210 const u16 *reset_regs;
211 const u16 *reset_clear_regs;
212 struct {
213 u32 mask;
214 u32 val;
215 } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)];
216
217 unsigned int *reserved_ids;
218 unsigned int num_reserved_ids;
219
220 struct clk *clks[];
221 };
222
223 static struct cpg_mssr_priv *cpg_mssr_priv;
224
225 /**
226 * struct mstp_clock - MSTP gating clock
227 * @hw: handle between common and hardware-specific interfaces
228 * @index: MSTP clock number
229 * @priv: CPG/MSSR private data
230 */
231 struct mstp_clock {
232 struct clk_hw hw;
233 u32 index;
234 struct cpg_mssr_priv *priv;
235 };
236
237 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
238
cpg_rzt2h_mstp_read(struct cpg_mssr_priv * priv,u16 offset)239 static u32 cpg_rzt2h_mstp_read(struct cpg_mssr_priv *priv, u16 offset)
240 {
241 void __iomem *base =
242 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
243
244 return readl(base + RZT2H_MSTPCR_OFFSET(offset));
245 }
246
cpg_rzt2h_mstp_write(struct cpg_mssr_priv * priv,u16 offset,u32 value)247 static void cpg_rzt2h_mstp_write(struct cpg_mssr_priv *priv, u16 offset, u32 value)
248 {
249 void __iomem *base =
250 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
251
252 writel(value, base + RZT2H_MSTPCR_OFFSET(offset));
253 }
254
cpg_rzt2h_mstp_delay(u32 idx,bool bit_valid)255 static void cpg_rzt2h_mstp_delay(u32 idx, bool bit_valid)
256 {
257 unsigned int mask = bit_valid ? GENMASK(31, 0) : GENMASK(31, 5);
258
259 if (idx == (MOD_CLK_PACK(1204) & mask)) {
260 /* LCDC needs 100 dummy reads, or 142us */
261 udelay(142);
262 } else if (idx == (MOD_CLK_PACK(605) & mask)) {
263 /* RTC needs 300 dummy reads, or 428us */
264 udelay(428);
265 } else {
266 /* default 7 dummy reads, or 10us */
267 udelay(10);
268 }
269 }
270
cpg_mstp_clock_endisable(struct clk_hw * hw,bool enable)271 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
272 {
273 struct mstp_clock *clock = to_mstp_clock(hw);
274 struct cpg_mssr_priv *priv = clock->priv;
275 unsigned int reg = clock->index / 32;
276 unsigned int bit = clock->index % 32;
277 struct device *dev = priv->dev;
278 u32 bitmask = BIT(bit);
279 unsigned long flags;
280 u32 value;
281 int error;
282
283 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
284 str_on_off(enable));
285 spin_lock_irqsave(&priv->pub.rmw_lock, flags);
286
287 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
288 value = readb(priv->pub.base0 + priv->control_regs[reg]);
289 if (enable)
290 value &= ~bitmask;
291 else
292 value |= bitmask;
293 writeb(value, priv->pub.base0 + priv->control_regs[reg]);
294
295 /* dummy read to ensure write has completed */
296 readb(priv->pub.base0 + priv->control_regs[reg]);
297 barrier_data(priv->pub.base0 + priv->control_regs[reg]);
298
299 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
300 value = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
301
302 if (enable)
303 value &= ~bitmask;
304 else
305 value |= bitmask;
306
307 cpg_rzt2h_mstp_write(priv, priv->control_regs[reg], value);
308 } else {
309 value = readl(priv->pub.base0 + priv->control_regs[reg]);
310 if (enable)
311 value &= ~bitmask;
312 else
313 value |= bitmask;
314 writel(value, priv->pub.base0 + priv->control_regs[reg]);
315 }
316
317 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
318
319 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
320 return 0;
321
322 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
323 /*
324 * For the RZ/T2H case, it is necessary to perform a read-back after
325 * accessing the MSTPCRm register and to dummy-read any register of
326 * the IP at least seven times. Instead of memory-mapping the IP
327 * register, we simply add a delay after the read operation.
328 */
329 cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
330 cpg_rzt2h_mstp_delay(clock->index, true);
331 return 0;
332 }
333
334 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
335 value, !(value & bitmask), 0, 10);
336 if (error)
337 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
338 priv->pub.base0 + priv->control_regs[reg], bit);
339
340 return error;
341 }
342
cpg_mstp_clock_enable(struct clk_hw * hw)343 static int cpg_mstp_clock_enable(struct clk_hw *hw)
344 {
345 return cpg_mstp_clock_endisable(hw, true);
346 }
347
cpg_mstp_clock_disable(struct clk_hw * hw)348 static void cpg_mstp_clock_disable(struct clk_hw *hw)
349 {
350 cpg_mstp_clock_endisable(hw, false);
351 }
352
cpg_mstp_clock_is_enabled(struct clk_hw * hw)353 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
354 {
355 struct mstp_clock *clock = to_mstp_clock(hw);
356 struct cpg_mssr_priv *priv = clock->priv;
357 unsigned int reg = clock->index / 32;
358 u32 value;
359
360 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
361 value = readb(priv->pub.base0 + priv->control_regs[reg]);
362 else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
363 value = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
364 else
365 value = readl(priv->pub.base0 + priv->status_regs[reg]);
366
367 return !(value & BIT(clock->index % 32));
368 }
369
370 static const struct clk_ops cpg_mstp_clock_ops = {
371 .enable = cpg_mstp_clock_enable,
372 .disable = cpg_mstp_clock_disable,
373 .is_enabled = cpg_mstp_clock_is_enabled,
374 };
375
376 static
cpg_mssr_clk_src_twocell_get(struct of_phandle_args * clkspec,void * data)377 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
378 void *data)
379 {
380 unsigned int clkidx = clkspec->args[1];
381 struct cpg_mssr_priv *priv = data;
382 struct device *dev = priv->dev;
383 unsigned int idx;
384 const char *type;
385 struct clk *clk;
386 int range_check;
387
388 if (clkspec->args_count != 2)
389 return ERR_PTR(-EINVAL);
390
391 switch (clkspec->args[0]) {
392 case CPG_CORE:
393 type = "core";
394 if (clkidx > priv->last_dt_core_clk) {
395 dev_err(dev, "Invalid %s clock index %u\n", type,
396 clkidx);
397 return ERR_PTR(-EINVAL);
398 }
399 clk = priv->clks[clkidx];
400 break;
401
402 case CPG_MOD:
403 type = "module";
404 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
405 idx = MOD_CLK_PACK_10(clkidx);
406 range_check = 7 - (clkidx % 10);
407 } else {
408 idx = MOD_CLK_PACK(clkidx);
409 range_check = 31 - (clkidx % 100);
410 }
411 if (range_check < 0 || idx >= priv->num_mod_clks) {
412 dev_err(dev, "Invalid %s clock index %u\n", type,
413 clkidx);
414 return ERR_PTR(-EINVAL);
415 }
416 clk = priv->clks[priv->num_core_clks + idx];
417 break;
418
419 default:
420 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
421 return ERR_PTR(-EINVAL);
422 }
423
424 if (IS_ERR(clk))
425 dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx,
426 PTR_ERR(clk));
427 else
428 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
429 clkspec->args[0], clkspec->args[1], clk,
430 clk_get_rate(clk));
431 return clk;
432 }
433
cpg_mssr_register_core_clk(const struct cpg_core_clk * core,const struct cpg_mssr_info * info,struct cpg_mssr_priv * priv)434 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
435 const struct cpg_mssr_info *info,
436 struct cpg_mssr_priv *priv)
437 {
438 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
439 struct device *dev = priv->dev;
440 unsigned int id = core->id, div = core->div;
441 const char *parent_name;
442
443 WARN_DEBUG(id >= priv->num_core_clks);
444 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
445
446 switch (core->type) {
447 case CLK_TYPE_IN:
448 clk = of_clk_get_by_name(priv->np, core->name);
449 break;
450
451 case CLK_TYPE_FF:
452 case CLK_TYPE_DIV6P1:
453 case CLK_TYPE_DIV6_RO:
454 WARN_DEBUG(core->parent >= priv->num_core_clks);
455 parent = priv->pub.clks[core->parent];
456 if (IS_ERR(parent)) {
457 clk = parent;
458 goto fail;
459 }
460
461 parent_name = __clk_get_name(parent);
462
463 if (core->type == CLK_TYPE_DIV6_RO)
464 /* Multiply with the DIV6 register value */
465 div *= (readl(priv->pub.base0 + core->offset) & 0x3f) + 1;
466
467 if (core->type == CLK_TYPE_DIV6P1) {
468 clk = cpg_div6_register(core->name, 1, &parent_name,
469 priv->pub.base0 + core->offset,
470 &priv->pub.notifiers);
471 } else {
472 clk = clk_register_fixed_factor(NULL, core->name,
473 parent_name, 0,
474 core->mult, div);
475 }
476 break;
477
478 case CLK_TYPE_FR:
479 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
480 core->mult);
481 break;
482
483 default:
484 if (info->cpg_clk_register)
485 clk = info->cpg_clk_register(dev, core, info,
486 &priv->pub);
487 else
488 dev_err(dev, "%s has unsupported core clock type %u\n",
489 core->name, core->type);
490 break;
491 }
492
493 if (IS_ERR(clk))
494 goto fail;
495
496 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
497 priv->pub.clks[id] = clk;
498 return;
499
500 fail:
501 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
502 core->name, PTR_ERR(clk));
503 }
504
cpg_mssr_register_mod_clk(const struct mssr_mod_clk * mod,const struct cpg_mssr_info * info,struct cpg_mssr_priv * priv)505 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
506 const struct cpg_mssr_info *info,
507 struct cpg_mssr_priv *priv)
508 {
509 struct mstp_clock *clock = NULL;
510 struct device *dev = priv->dev;
511 unsigned int id = mod->id;
512 struct clk_init_data init = {};
513 struct clk *parent, *clk;
514 const char *parent_name;
515 unsigned int i;
516
517 WARN_DEBUG(id < priv->num_core_clks);
518 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
519 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
520 WARN_DEBUG(PTR_ERR(priv->pub.clks[id]) != -ENOENT);
521
522 if (!mod->name) {
523 /* Skip NULLified clock */
524 return;
525 }
526
527 parent = priv->pub.clks[mod->parent];
528 if (IS_ERR(parent)) {
529 clk = parent;
530 goto fail;
531 }
532
533 clock = kzalloc_obj(*clock);
534 if (!clock) {
535 clk = ERR_PTR(-ENOMEM);
536 goto fail;
537 }
538
539 init.name = mod->name;
540 init.ops = &cpg_mstp_clock_ops;
541 init.flags = CLK_SET_RATE_PARENT;
542 parent_name = __clk_get_name(parent);
543 init.parent_names = &parent_name;
544 init.num_parents = 1;
545
546 clock->index = id - priv->num_core_clks;
547 clock->priv = priv;
548 clock->hw.init = &init;
549
550 for (i = 0; i < info->num_crit_mod_clks; i++)
551 if (id == info->crit_mod_clks[i] &&
552 cpg_mstp_clock_is_enabled(&clock->hw)) {
553 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
554 mod->name);
555 init.flags |= CLK_IS_CRITICAL;
556 break;
557 }
558
559 /*
560 * Ignore reserved device.
561 * see
562 * cpg_mssr_reserved_init()
563 */
564 for (i = 0; i < priv->num_reserved_ids; i++) {
565 if (id == priv->reserved_ids[i]) {
566 dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name);
567 init.flags |= CLK_IGNORE_UNUSED;
568 break;
569 }
570 }
571
572 clk = clk_register(NULL, &clock->hw);
573 if (IS_ERR(clk))
574 goto fail;
575
576 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
577 priv->clks[id] = clk;
578 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
579 return;
580
581 fail:
582 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
583 mod->name, PTR_ERR(clk));
584 kfree(clock);
585 }
586
587 struct cpg_mssr_clk_domain {
588 struct generic_pm_domain genpd;
589 unsigned int num_core_pm_clks;
590 unsigned int core_pm_clks[] __counted_by(num_core_pm_clks);
591 };
592
593 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
594
cpg_mssr_is_pm_clk(const struct of_phandle_args * clkspec,struct cpg_mssr_clk_domain * pd)595 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
596 struct cpg_mssr_clk_domain *pd)
597 {
598 unsigned int i;
599
600 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
601 return false;
602
603 switch (clkspec->args[0]) {
604 case CPG_CORE:
605 for (i = 0; i < pd->num_core_pm_clks; i++)
606 if (clkspec->args[1] == pd->core_pm_clks[i])
607 return true;
608 return false;
609
610 case CPG_MOD:
611 return true;
612
613 default:
614 return false;
615 }
616 }
617
cpg_mssr_attach_dev(struct generic_pm_domain * unused,struct device * dev)618 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
619 {
620 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
621 struct device_node *np = dev->of_node;
622 struct of_phandle_args clkspec;
623 struct clk *clk;
624 int i = 0;
625 int error;
626
627 if (!pd) {
628 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
629 return -EPROBE_DEFER;
630 }
631
632 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
633 &clkspec)) {
634 if (cpg_mssr_is_pm_clk(&clkspec, pd))
635 goto found;
636
637 of_node_put(clkspec.np);
638 i++;
639 }
640
641 return 0;
642
643 found:
644 clk = of_clk_get_from_provider(&clkspec);
645 of_node_put(clkspec.np);
646
647 if (IS_ERR(clk))
648 return PTR_ERR(clk);
649
650 error = pm_clk_create(dev);
651 if (error)
652 goto fail_put;
653
654 error = pm_clk_add_clk(dev, clk);
655 if (error)
656 goto fail_destroy;
657
658 return 0;
659
660 fail_destroy:
661 pm_clk_destroy(dev);
662 fail_put:
663 clk_put(clk);
664 return error;
665 }
666
cpg_mssr_detach_dev(struct generic_pm_domain * unused,struct device * dev)667 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
668 {
669 if (!pm_clk_no_clocks(dev))
670 pm_clk_destroy(dev);
671 }
672
cpg_mssr_genpd_remove(void * data)673 static void cpg_mssr_genpd_remove(void *data)
674 {
675 pm_genpd_remove(data);
676 }
677
cpg_mssr_add_clk_domain(struct device * dev,const unsigned int * core_pm_clks,unsigned int num_core_pm_clks)678 static int __init cpg_mssr_add_clk_domain(struct device *dev,
679 const unsigned int *core_pm_clks,
680 unsigned int num_core_pm_clks)
681 {
682 struct device_node *np = dev->of_node;
683 struct generic_pm_domain *genpd;
684 struct cpg_mssr_clk_domain *pd;
685 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
686 int ret;
687
688 pd = devm_kzalloc(dev, struct_size(pd, core_pm_clks, num_core_pm_clks), GFP_KERNEL);
689 if (!pd)
690 return -ENOMEM;
691
692 pd->num_core_pm_clks = num_core_pm_clks;
693 memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
694
695 genpd = &pd->genpd;
696 genpd->name = np->name;
697 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
698 GENPD_FLAG_ACTIVE_WAKEUP;
699 genpd->attach_dev = cpg_mssr_attach_dev;
700 genpd->detach_dev = cpg_mssr_detach_dev;
701 ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
702 if (ret)
703 return ret;
704
705 ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd);
706 if (ret)
707 return ret;
708
709 cpg_mssr_clk_domain = pd;
710
711 return of_genpd_add_provider_simple(np, genpd);
712 }
713
714 #ifdef CONFIG_RESET_CONTROLLER
715
716 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
717
cpg_mssr_reset_operate(struct reset_controller_dev * rcdev,const char * func,bool set,unsigned long id)718 static int cpg_mssr_reset_operate(struct reset_controller_dev *rcdev,
719 const char *func, bool set, unsigned long id)
720 {
721 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
722 unsigned int reg = id / 32;
723 unsigned int bit = id % 32;
724 const u16 off = set ? priv->reset_regs[reg] : priv->reset_clear_regs[reg];
725 u32 bitmask = BIT(bit);
726
727 if (func)
728 dev_dbg(priv->dev, "%s %u%02u\n", func, reg, bit);
729
730 writel(bitmask, priv->pub.base0 + off);
731 readl(priv->pub.base0 + off);
732 barrier_data(priv->pub.base0 + off);
733
734 return 0;
735 }
736
cpg_mssr_reset(struct reset_controller_dev * rcdev,unsigned long id)737 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
738 unsigned long id)
739 {
740 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
741
742 /* Reset module */
743 cpg_mssr_reset_operate(rcdev, "reset", true, id);
744
745 /*
746 * On R-Car Gen4, delay after SRCR has been written is 1ms.
747 * On older SoCs, delay after SRCR has been written is 35us
748 * (one cycle of the RCLK clock @ ca. 32 kHz).
749 */
750 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
751 usleep_range(1000, 2000);
752 else
753 usleep_range(35, 1000);
754
755 /* Release module from reset state */
756 return cpg_mssr_reset_operate(rcdev, NULL, false, id);
757 }
758
cpg_mssr_assert(struct reset_controller_dev * rcdev,unsigned long id)759 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
760 {
761 return cpg_mssr_reset_operate(rcdev, "assert", true, id);
762 }
763
cpg_mssr_deassert(struct reset_controller_dev * rcdev,unsigned long id)764 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
765 unsigned long id)
766 {
767 return cpg_mssr_reset_operate(rcdev, "deassert", false, id);
768 }
769
cpg_mssr_status(struct reset_controller_dev * rcdev,unsigned long id)770 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
771 unsigned long id)
772 {
773 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
774 unsigned int reg = id / 32;
775 unsigned int bit = id % 32;
776 u32 bitmask = BIT(bit);
777
778 return !!(readl(priv->pub.base0 + priv->reset_regs[reg]) & bitmask);
779 }
780
cpg_mrcr_set_reset_state(struct reset_controller_dev * rcdev,unsigned long id,bool set)781 static int cpg_mrcr_set_reset_state(struct reset_controller_dev *rcdev,
782 unsigned long id, bool set)
783 {
784 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
785 unsigned int reg = id / 32;
786 unsigned int bit = id % 32;
787 u32 bitmask = BIT(bit);
788 void __iomem *reg_addr;
789 unsigned long flags;
790 unsigned int i;
791 u32 val;
792
793 dev_dbg(priv->dev, "%s %u%02u\n", set ? "assert" : "deassert", reg, bit);
794
795 spin_lock_irqsave(&priv->pub.rmw_lock, flags);
796
797 reg_addr = priv->pub.base0 + priv->reset_regs[reg];
798 /* Read current value and modify */
799 val = readl(reg_addr);
800 if (set)
801 val |= bitmask;
802 else
803 val &= ~bitmask;
804 writel(val, reg_addr);
805
806 /*
807 * For secure processing after release from a module reset, one must
808 * perform multiple dummy reads of the same register.
809 */
810 for (i = 0; !set && i < RZT2H_RESET_REG_READ_COUNT; i++)
811 readl(reg_addr);
812
813 /* Verify the operation */
814 val = readl(reg_addr);
815
816 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
817
818 if (set == !(bitmask & val)) {
819 dev_err(priv->dev, "Reset register %u%02u operation failed\n", reg, bit);
820 return -EIO;
821 }
822
823 return 0;
824 }
825
cpg_mrcr_reset(struct reset_controller_dev * rcdev,unsigned long id)826 static int cpg_mrcr_reset(struct reset_controller_dev *rcdev, unsigned long id)
827 {
828 int ret;
829
830 ret = cpg_mrcr_set_reset_state(rcdev, id, true);
831 if (ret)
832 return ret;
833
834 return cpg_mrcr_set_reset_state(rcdev, id, false);
835 }
836
cpg_mrcr_assert(struct reset_controller_dev * rcdev,unsigned long id)837 static int cpg_mrcr_assert(struct reset_controller_dev *rcdev, unsigned long id)
838 {
839 return cpg_mrcr_set_reset_state(rcdev, id, true);
840 }
841
cpg_mrcr_deassert(struct reset_controller_dev * rcdev,unsigned long id)842 static int cpg_mrcr_deassert(struct reset_controller_dev *rcdev, unsigned long id)
843 {
844 return cpg_mrcr_set_reset_state(rcdev, id, false);
845 }
846
847 static const struct reset_control_ops cpg_mssr_reset_ops = {
848 .reset = cpg_mssr_reset,
849 .assert = cpg_mssr_assert,
850 .deassert = cpg_mssr_deassert,
851 .status = cpg_mssr_status,
852 };
853
854 static const struct reset_control_ops cpg_mrcr_reset_ops = {
855 .reset = cpg_mrcr_reset,
856 .assert = cpg_mrcr_assert,
857 .deassert = cpg_mrcr_deassert,
858 .status = cpg_mssr_status,
859 };
860
cpg_mssr_reset_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)861 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
862 const struct of_phandle_args *reset_spec)
863 {
864 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
865 unsigned int unpacked = reset_spec->args[0];
866 unsigned int idx = MOD_CLK_PACK(unpacked);
867
868 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
869 dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
870 return -EINVAL;
871 }
872
873 return idx;
874 }
875
cpg_mssr_reset_controller_register(struct cpg_mssr_priv * priv)876 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
877 {
878 /*
879 * RZ/T2H (and family) has the Module Reset Control Registers
880 * which allows control resets of certain modules.
881 * The number of resets is not equal to the number of module clocks.
882 */
883 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
884 priv->rcdev.ops = &cpg_mrcr_reset_ops;
885 priv->rcdev.nr_resets = ARRAY_SIZE(mrcr_for_rzt2h) * 32;
886 } else {
887 priv->rcdev.ops = &cpg_mssr_reset_ops;
888 priv->rcdev.nr_resets = priv->num_mod_clks;
889 }
890
891 priv->rcdev.of_node = priv->dev->of_node;
892 priv->rcdev.of_reset_n_cells = 1;
893 priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
894
895 return devm_reset_controller_register(priv->dev, &priv->rcdev);
896 }
897
898 #else /* !CONFIG_RESET_CONTROLLER */
cpg_mssr_reset_controller_register(struct cpg_mssr_priv * priv)899 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
900 {
901 return 0;
902 }
903 #endif /* !CONFIG_RESET_CONTROLLER */
904
905 static const struct of_device_id cpg_mssr_match[] = {
906 #ifdef CONFIG_CLK_R7S9210
907 {
908 .compatible = "renesas,r7s9210-cpg-mssr",
909 .data = &r7s9210_cpg_mssr_info,
910 },
911 #endif
912 #ifdef CONFIG_CLK_R8A7742
913 {
914 .compatible = "renesas,r8a7742-cpg-mssr",
915 .data = &r8a7742_cpg_mssr_info,
916 },
917 #endif
918 #ifdef CONFIG_CLK_R8A7743
919 {
920 .compatible = "renesas,r8a7743-cpg-mssr",
921 .data = &r8a7743_cpg_mssr_info,
922 },
923 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
924 {
925 .compatible = "renesas,r8a7744-cpg-mssr",
926 .data = &r8a7743_cpg_mssr_info,
927 },
928 #endif
929 #ifdef CONFIG_CLK_R8A7745
930 {
931 .compatible = "renesas,r8a7745-cpg-mssr",
932 .data = &r8a7745_cpg_mssr_info,
933 },
934 #endif
935 #ifdef CONFIG_CLK_R8A77470
936 {
937 .compatible = "renesas,r8a77470-cpg-mssr",
938 .data = &r8a77470_cpg_mssr_info,
939 },
940 #endif
941 #ifdef CONFIG_CLK_R8A774A1
942 {
943 .compatible = "renesas,r8a774a1-cpg-mssr",
944 .data = &r8a774a1_cpg_mssr_info,
945 },
946 #endif
947 #ifdef CONFIG_CLK_R8A774B1
948 {
949 .compatible = "renesas,r8a774b1-cpg-mssr",
950 .data = &r8a774b1_cpg_mssr_info,
951 },
952 #endif
953 #ifdef CONFIG_CLK_R8A774C0
954 {
955 .compatible = "renesas,r8a774c0-cpg-mssr",
956 .data = &r8a774c0_cpg_mssr_info,
957 },
958 #endif
959 #ifdef CONFIG_CLK_R8A774E1
960 {
961 .compatible = "renesas,r8a774e1-cpg-mssr",
962 .data = &r8a774e1_cpg_mssr_info,
963 },
964 #endif
965 #ifdef CONFIG_CLK_R8A7790
966 {
967 .compatible = "renesas,r8a7790-cpg-mssr",
968 .data = &r8a7790_cpg_mssr_info,
969 },
970 #endif
971 #ifdef CONFIG_CLK_R8A7791
972 {
973 .compatible = "renesas,r8a7791-cpg-mssr",
974 .data = &r8a7791_cpg_mssr_info,
975 },
976 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
977 {
978 .compatible = "renesas,r8a7793-cpg-mssr",
979 .data = &r8a7791_cpg_mssr_info,
980 },
981 #endif
982 #ifdef CONFIG_CLK_R8A7792
983 {
984 .compatible = "renesas,r8a7792-cpg-mssr",
985 .data = &r8a7792_cpg_mssr_info,
986 },
987 #endif
988 #ifdef CONFIG_CLK_R8A7794
989 {
990 .compatible = "renesas,r8a7794-cpg-mssr",
991 .data = &r8a7794_cpg_mssr_info,
992 },
993 #endif
994 #ifdef CONFIG_CLK_R8A7795
995 {
996 .compatible = "renesas,r8a7795-cpg-mssr",
997 .data = &r8a7795_cpg_mssr_info,
998 },
999 #endif
1000 #ifdef CONFIG_CLK_R8A77960
1001 {
1002 .compatible = "renesas,r8a7796-cpg-mssr",
1003 .data = &r8a7796_cpg_mssr_info,
1004 },
1005 #endif
1006 #ifdef CONFIG_CLK_R8A77961
1007 {
1008 .compatible = "renesas,r8a77961-cpg-mssr",
1009 .data = &r8a7796_cpg_mssr_info,
1010 },
1011 #endif
1012 #ifdef CONFIG_CLK_R8A77965
1013 {
1014 .compatible = "renesas,r8a77965-cpg-mssr",
1015 .data = &r8a77965_cpg_mssr_info,
1016 },
1017 #endif
1018 #ifdef CONFIG_CLK_R8A77970
1019 {
1020 .compatible = "renesas,r8a77970-cpg-mssr",
1021 .data = &r8a77970_cpg_mssr_info,
1022 },
1023 #endif
1024 #ifdef CONFIG_CLK_R8A77980
1025 {
1026 .compatible = "renesas,r8a77980-cpg-mssr",
1027 .data = &r8a77980_cpg_mssr_info,
1028 },
1029 #endif
1030 #ifdef CONFIG_CLK_R8A77990
1031 {
1032 .compatible = "renesas,r8a77990-cpg-mssr",
1033 .data = &r8a77990_cpg_mssr_info,
1034 },
1035 #endif
1036 #ifdef CONFIG_CLK_R8A77995
1037 {
1038 .compatible = "renesas,r8a77995-cpg-mssr",
1039 .data = &r8a77995_cpg_mssr_info,
1040 },
1041 #endif
1042 #ifdef CONFIG_CLK_R8A779A0
1043 {
1044 .compatible = "renesas,r8a779a0-cpg-mssr",
1045 .data = &r8a779a0_cpg_mssr_info,
1046 },
1047 #endif
1048 #ifdef CONFIG_CLK_R8A779F0
1049 {
1050 .compatible = "renesas,r8a779f0-cpg-mssr",
1051 .data = &r8a779f0_cpg_mssr_info,
1052 },
1053 #endif
1054 #ifdef CONFIG_CLK_R8A779G0
1055 {
1056 .compatible = "renesas,r8a779g0-cpg-mssr",
1057 .data = &r8a779g0_cpg_mssr_info,
1058 },
1059 #endif
1060 #ifdef CONFIG_CLK_R8A779H0
1061 {
1062 .compatible = "renesas,r8a779h0-cpg-mssr",
1063 .data = &r8a779h0_cpg_mssr_info,
1064 },
1065 #endif
1066 #ifdef CONFIG_CLK_R9A09G077
1067 {
1068 .compatible = "renesas,r9a09g077-cpg-mssr",
1069 .data = &r9a09g077_cpg_mssr_info,
1070 },
1071 #endif
1072 #ifdef CONFIG_CLK_R9A09G087
1073 {
1074 .compatible = "renesas,r9a09g087-cpg-mssr",
1075 .data = &r9a09g077_cpg_mssr_info,
1076 },
1077 #endif
1078 { /* sentinel */ }
1079 };
1080
cpg_mssr_del_clk_provider(void * data)1081 static void cpg_mssr_del_clk_provider(void *data)
1082 {
1083 of_clk_del_provider(data);
1084 }
1085
1086 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
cpg_mssr_suspend_noirq(struct device * dev)1087 static int cpg_mssr_suspend_noirq(struct device *dev)
1088 {
1089 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
1090 unsigned int reg;
1091
1092 /* This is the best we can do to check for the presence of PSCI */
1093 if (!psci_ops.cpu_suspend)
1094 return 0;
1095
1096 /* Save module registers with bits under our control */
1097 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
1098 u32 val;
1099
1100 if (!priv->smstpcr_saved[reg].mask)
1101 continue;
1102
1103 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1104 val = readb(priv->pub.base0 + priv->control_regs[reg]);
1105 else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
1106 val = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
1107 else
1108 val = readl(priv->pub.base0 + priv->control_regs[reg]);
1109
1110 priv->smstpcr_saved[reg].val = val;
1111 }
1112
1113 /* Save core clocks */
1114 raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_SUSPEND, NULL);
1115
1116 return 0;
1117 }
1118
cpg_mssr_resume_noirq(struct device * dev)1119 static int cpg_mssr_resume_noirq(struct device *dev)
1120 {
1121 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
1122 unsigned int reg;
1123 u32 mask, oldval, newval;
1124 int error;
1125
1126 /* This is the best we can do to check for the presence of PSCI */
1127 if (!psci_ops.cpu_suspend)
1128 return 0;
1129
1130 /* Restore core clocks */
1131 raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_RESUME, NULL);
1132
1133 /* Restore module clocks */
1134 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
1135 mask = priv->smstpcr_saved[reg].mask;
1136 if (!mask)
1137 continue;
1138
1139 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1140 oldval = readb(priv->pub.base0 + priv->control_regs[reg]);
1141 else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
1142 oldval = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
1143 else
1144 oldval = readl(priv->pub.base0 + priv->control_regs[reg]);
1145 newval = oldval & ~mask;
1146 newval |= priv->smstpcr_saved[reg].val & mask;
1147 if (newval == oldval)
1148 continue;
1149
1150 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
1151 writeb(newval, priv->pub.base0 + priv->control_regs[reg]);
1152 /* dummy read to ensure write has completed */
1153 readb(priv->pub.base0 + priv->control_regs[reg]);
1154 barrier_data(priv->pub.base0 + priv->control_regs[reg]);
1155 continue;
1156 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
1157 cpg_rzt2h_mstp_write(priv, priv->control_regs[reg], newval);
1158 /* See cpg_mstp_clock_endisable() on why this is necessary. */
1159 cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
1160 cpg_rzt2h_mstp_delay(reg * 32, false);
1161 continue;
1162 } else
1163 writel(newval, priv->pub.base0 + priv->control_regs[reg]);
1164
1165 /* Wait until enabled clocks are really enabled */
1166 mask &= ~priv->smstpcr_saved[reg].val;
1167 if (!mask)
1168 continue;
1169
1170 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
1171 oldval, !(oldval & mask), 0, 10);
1172 if (error)
1173 dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,
1174 oldval & mask);
1175 }
1176
1177 return 0;
1178 }
1179
1180 static const struct dev_pm_ops cpg_mssr_pm = {
1181 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
1182 cpg_mssr_resume_noirq)
1183 };
1184 #define DEV_PM_OPS &cpg_mssr_pm
1185 #else
1186 #define DEV_PM_OPS NULL
1187 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
1188
cpg_mssr_reserved_exit(struct cpg_mssr_priv * priv)1189 static void __init cpg_mssr_reserved_exit(struct cpg_mssr_priv *priv)
1190 {
1191 kfree(priv->reserved_ids);
1192 }
1193
cpg_mssr_reserved_init(struct cpg_mssr_priv * priv,const struct cpg_mssr_info * info)1194 static int __init cpg_mssr_reserved_init(struct cpg_mssr_priv *priv,
1195 const struct cpg_mssr_info *info)
1196 {
1197 struct device_node *soc __free(device_node) = of_find_node_by_path("/soc");
1198 struct device_node *node;
1199 uint32_t args[MAX_PHANDLE_ARGS];
1200 unsigned int *ids = NULL;
1201 unsigned int num = 0;
1202
1203 /*
1204 * Because clk_disable_unused() will disable all unused clocks, the device which is assigned
1205 * to a non-Linux system will be disabled when Linux is booted.
1206 *
1207 * To avoid such situation, renesas-cpg-mssr assumes the device which has
1208 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag
1209 * to its CPG_MOD clocks.
1210 * see also
1211 * cpg_mssr_register_mod_clk()
1212 *
1213 * scif5: serial@e6f30000 {
1214 * ...
1215 * => clocks = <&cpg CPG_MOD 202>,
1216 * <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1217 * <&scif_clk>;
1218 * ...
1219 * status = "reserved";
1220 * };
1221 */
1222 for_each_reserved_child_of_node(soc, node) {
1223 struct of_phandle_iterator it;
1224 int rc;
1225
1226 of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) {
1227 int idx;
1228 unsigned int *new_ids;
1229
1230 if (it.node != priv->np)
1231 continue;
1232
1233 if (of_phandle_iterator_args(&it, args, MAX_PHANDLE_ARGS) != 2)
1234 continue;
1235
1236 if (args[0] != CPG_MOD)
1237 continue;
1238
1239 new_ids = krealloc_array(ids, (num + 1), sizeof(*ids), GFP_KERNEL);
1240 if (!new_ids) {
1241 of_node_put(it.node);
1242 kfree(ids);
1243 return -ENOMEM;
1244 }
1245 ids = new_ids;
1246
1247 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1248 idx = MOD_CLK_PACK_10(args[1]); /* for DEF_MOD_STB() */
1249 else
1250 idx = MOD_CLK_PACK(args[1]); /* for DEF_MOD() */
1251
1252 ids[num] = info->num_total_core_clks + idx;
1253
1254 num++;
1255 }
1256 }
1257
1258 priv->num_reserved_ids = num;
1259 priv->reserved_ids = ids;
1260
1261 return 0;
1262 }
1263
cpg_mssr_common_init(struct device * dev,struct device_node * np,const struct cpg_mssr_info * info)1264 static int __init cpg_mssr_common_init(struct device *dev,
1265 struct device_node *np,
1266 const struct cpg_mssr_info *info)
1267 {
1268 struct cpg_mssr_priv *priv;
1269 unsigned int nclks, i;
1270 int error;
1271
1272 if (info->init) {
1273 error = info->init(dev);
1274 if (error)
1275 return error;
1276 }
1277
1278 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
1279 priv = kzalloc_flex(*priv, clks, nclks);
1280 if (!priv)
1281 return -ENOMEM;
1282
1283 priv->pub.clks = priv->clks;
1284 priv->np = np;
1285 priv->dev = dev;
1286 spin_lock_init(&priv->pub.rmw_lock);
1287
1288 priv->pub.base0 = of_iomap(np, 0);
1289 if (!priv->pub.base0) {
1290 error = -ENOMEM;
1291 goto out_err;
1292 }
1293 if (info->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
1294 priv->pub.base1 = of_iomap(np, 1);
1295 if (!priv->pub.base1) {
1296 error = -ENOMEM;
1297 goto out_err;
1298 }
1299 }
1300
1301 priv->num_core_clks = info->num_total_core_clks;
1302 priv->num_mod_clks = info->num_hw_mod_clks;
1303 priv->last_dt_core_clk = info->last_dt_core_clk;
1304 RAW_INIT_NOTIFIER_HEAD(&priv->pub.notifiers);
1305 priv->reg_layout = info->reg_layout;
1306 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
1307 priv->status_regs = mstpsr;
1308 priv->control_regs = smstpcr;
1309 priv->reset_regs = srcr;
1310 priv->reset_clear_regs = srstclr;
1311 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
1312 priv->control_regs = stbcr;
1313 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
1314 priv->control_regs = mstpcr_for_rzt2h;
1315 priv->reset_regs = mrcr_for_rzt2h;
1316 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
1317 priv->status_regs = mstpsr_for_gen4;
1318 priv->control_regs = mstpcr_for_gen4;
1319 priv->reset_regs = srcr_for_gen4;
1320 priv->reset_clear_regs = srstclr_for_gen4;
1321 } else {
1322 error = -EINVAL;
1323 goto out_err;
1324 }
1325
1326 for (i = 0; i < nclks; i++)
1327 priv->pub.clks[i] = ERR_PTR(-ENOENT);
1328
1329 error = cpg_mssr_reserved_init(priv, info);
1330 if (error)
1331 goto out_err;
1332
1333 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
1334 if (error)
1335 goto reserve_err;
1336
1337 cpg_mssr_priv = priv;
1338
1339 return 0;
1340
1341 reserve_err:
1342 cpg_mssr_reserved_exit(priv);
1343 out_err:
1344 if (priv->pub.base0)
1345 iounmap(priv->pub.base0);
1346 if (priv->pub.base1)
1347 iounmap(priv->pub.base1);
1348 kfree(priv);
1349
1350 return error;
1351 }
1352
cpg_mssr_early_init(struct device_node * np,const struct cpg_mssr_info * info)1353 void __init cpg_mssr_early_init(struct device_node *np,
1354 const struct cpg_mssr_info *info)
1355 {
1356 int error;
1357 int i;
1358
1359 error = cpg_mssr_common_init(NULL, np, info);
1360 if (error)
1361 return;
1362
1363 for (i = 0; i < info->num_early_core_clks; i++)
1364 cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1365 cpg_mssr_priv);
1366
1367 for (i = 0; i < info->num_early_mod_clks; i++)
1368 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1369 cpg_mssr_priv);
1370
1371 }
1372
cpg_mssr_probe(struct platform_device * pdev)1373 static int __init cpg_mssr_probe(struct platform_device *pdev)
1374 {
1375 struct device *dev = &pdev->dev;
1376 struct device_node *np = dev->of_node;
1377 const struct cpg_mssr_info *info;
1378 struct cpg_mssr_priv *priv;
1379 unsigned int i;
1380 int error;
1381
1382 info = of_device_get_match_data(dev);
1383
1384 if (!cpg_mssr_priv) {
1385 error = cpg_mssr_common_init(dev, dev->of_node, info);
1386 if (error)
1387 return error;
1388 }
1389
1390 priv = cpg_mssr_priv;
1391 priv->dev = dev;
1392 dev_set_drvdata(dev, priv);
1393
1394 for (i = 0; i < info->num_core_clks; i++)
1395 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
1396
1397 for (i = 0; i < info->num_mod_clks; i++)
1398 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
1399
1400 error = devm_add_action_or_reset(dev,
1401 cpg_mssr_del_clk_provider,
1402 np);
1403 if (error)
1404 goto reserve_exit;
1405
1406 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
1407 info->num_core_pm_clks);
1408 if (error)
1409 goto reserve_exit;
1410
1411 /* Reset Controller not supported for Standby Control SoCs */
1412 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1413 goto reserve_exit;
1414
1415 error = cpg_mssr_reset_controller_register(priv);
1416
1417 reserve_exit:
1418 cpg_mssr_reserved_exit(priv);
1419
1420 return error;
1421 }
1422
1423 static struct platform_driver cpg_mssr_driver = {
1424 .driver = {
1425 .name = "renesas-cpg-mssr",
1426 .of_match_table = cpg_mssr_match,
1427 .pm = DEV_PM_OPS,
1428 },
1429 };
1430
cpg_mssr_init(void)1431 static int __init cpg_mssr_init(void)
1432 {
1433 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1434 }
1435
1436 subsys_initcall(cpg_mssr_init);
1437
mssr_mod_nullify(struct mssr_mod_clk * mod_clks,unsigned int num_mod_clks,const unsigned int * clks,unsigned int n)1438 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1439 unsigned int num_mod_clks,
1440 const unsigned int *clks, unsigned int n)
1441 {
1442 unsigned int i, j;
1443
1444 for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1445 if (mod_clks[i].id == clks[j]) {
1446 mod_clks[i].name = NULL;
1447 j++;
1448 }
1449 }
1450
1451 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
1452