1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4 #include <linux/cleanup.h>
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/clk.h>
11 #include <linux/of_clk.h>
12 #include <linux/clk-provider.h>
13 #include <sound/soc.h>
14 #include <sound/soc-dapm.h>
15 #include <linux/pm_clock.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/of_platform.h>
18 #include <sound/tlv.h>
19
20 #include "lpass-macro-common.h"
21 #include "lpass-wsa-macro.h"
22
23 #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
24 #define CDC_WSA_MCLK_EN_MASK BIT(0)
25 #define CDC_WSA_MCLK_ENABLE BIT(0)
26 #define CDC_WSA_MCLK_DISABLE 0
27 #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
28 #define CDC_WSA_FS_CNT_EN_MASK BIT(0)
29 #define CDC_WSA_FS_CNT_ENABLE BIT(0)
30 #define CDC_WSA_FS_CNT_DISABLE 0
31 #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008)
32 #define CDC_WSA_SWR_CLK_EN_MASK BIT(0)
33 #define CDC_WSA_SWR_CLK_ENABLE BIT(0)
34 #define CDC_WSA_SWR_RST_EN_MASK BIT(1)
35 #define CDC_WSA_SWR_RST_ENABLE BIT(1)
36 #define CDC_WSA_SWR_RST_DISABLE 0
37 #define CDC_WSA_TOP_TOP_CFG0 (0x0080)
38 #define CDC_WSA_TOP_TOP_CFG1 (0x0084)
39 #define CDC_WSA_TOP_FREQ_MCLK (0x0088)
40 #define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C)
41 #define CDC_WSA_TOP_DEBUG_EN0 (0x0090)
42 #define CDC_WSA_TOP_DEBUG_EN1 (0x0094)
43 #define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098)
44 #define CDC_WSA_TOP_RX_I2S_CTL (0x009C)
45 #define CDC_WSA_TOP_TX_I2S_CTL (0x00A0)
46 #define CDC_WSA_TOP_I2S_CLK (0x00A4)
47 #define CDC_WSA_TOP_I2S_RESET (0x00A8)
48 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (0x0100)
49 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (0x0104)
50 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (0x0108)
51 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (0x010C)
52 #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110)
53 #define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3)
54 #define CDC_WSA_RX_MIX_TX1_SEL_SHFT 3
55 #define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0)
56 #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114)
57 #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118)
58 #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244)
59 #define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5)
60 #define CDC_WSA_TX_SPKR_PROT_RESET BIT(5)
61 #define CDC_WSA_TX_SPKR_PROT_NO_RESET 0
62 #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4)
63 #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE BIT(4)
64 #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0
65 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0)
66 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0
67 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K 1
68 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K 2
69 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K 3
70 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K 4
71 #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248)
72 #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264)
73 #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268)
74 #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL (0x0284)
75 #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (0x0288)
76 #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL (0x02A4)
77 #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (0x02A8)
78 #define CDC_WSA_INTR_CTRL_CFG (0x0340)
79 #define CDC_WSA_INTR_CTRL_CLR_COMMIT (0x0344)
80 #define CDC_WSA_INTR_CTRL_PIN1_MASK0 (0x0360)
81 #define CDC_WSA_INTR_CTRL_PIN1_STATUS0 (0x0368)
82 #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (0x0370)
83 #define CDC_WSA_INTR_CTRL_PIN2_MASK0 (0x0380)
84 #define CDC_WSA_INTR_CTRL_PIN2_STATUS0 (0x0388)
85 #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (0x0390)
86 #define CDC_WSA_INTR_CTRL_LEVEL0 (0x03C0)
87 #define CDC_WSA_INTR_CTRL_BYPASS0 (0x03C8)
88 #define CDC_WSA_INTR_CTRL_SET0 (0x03D0)
89 #define CDC_WSA_RX0_RX_PATH_CTL (0x0400)
90 #define CDC_WSA_RX_PATH_CLK_EN_MASK BIT(5)
91 #define CDC_WSA_RX_PATH_CLK_ENABLE BIT(5)
92 #define CDC_WSA_RX_PATH_CLK_DISABLE 0
93 #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK BIT(4)
94 #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE BIT(4)
95 #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE 0
96 #define CDC_WSA_RX0_RX_PATH_CFG0 (0x0404)
97 #define CDC_WSA_RX_PATH_COMP_EN_MASK BIT(1)
98 #define CDC_WSA_RX_PATH_COMP_ENABLE BIT(1)
99 #define CDC_WSA_RX_PATH_HD2_EN_MASK BIT(2)
100 #define CDC_WSA_RX_PATH_HD2_ENABLE BIT(2)
101 #define CDC_WSA_RX_PATH_SPKR_RATE_MASK BIT(3)
102 #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 BIT(3)
103 #define CDC_WSA_RX0_RX_PATH_CFG1 (0x0408)
104 #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK BIT(0)
105 #define CDC_WSA_RX_PATH_SMART_BST_ENABLE BIT(0)
106 #define CDC_WSA_RX_PATH_SMART_BST_DISABLE 0
107 #define CDC_WSA_RX0_RX_PATH_CFG2 (0x040C)
108 #define CDC_WSA_RX0_RX_PATH_CFG3 (0x0410)
109 #define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0)
110 #define CDC_WSA_RX0_RX_VOL_CTL (0x0414)
111 #define CDC_WSA_RX0_RX_PATH_MIX_CTL (0x0418)
112 #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK BIT(5)
113 #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE BIT(5)
114 #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE 0
115 #define CDC_WSA_RX0_RX_PATH_MIX_CFG (0x041C)
116 #define CDC_WSA_RX0_RX_VOL_MIX_CTL (0x0420)
117 #define CDC_WSA_RX0_RX_PATH_SEC0 (0x0424)
118 #define CDC_WSA_RX0_RX_PATH_SEC1 (0x0428)
119 #define CDC_WSA_RX_PGA_HALF_DB_MASK BIT(0)
120 #define CDC_WSA_RX_PGA_HALF_DB_ENABLE BIT(0)
121 #define CDC_WSA_RX_PGA_HALF_DB_DISABLE 0
122 #define CDC_WSA_RX0_RX_PATH_SEC2 (0x042C)
123 #define CDC_WSA_RX0_RX_PATH_SEC3 (0x0430)
124 #define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0)
125 #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2)
126 #define CDC_WSA_RX0_RX_PATH_SEC5 (0x0438)
127 #define CDC_WSA_RX0_RX_PATH_SEC6 (0x043C)
128 #define CDC_WSA_RX0_RX_PATH_SEC7 (0x0440)
129 #define CDC_WSA_RX0_RX_PATH_MIX_SEC0 (0x0444)
130 #define CDC_WSA_RX0_RX_PATH_MIX_SEC1 (0x0448)
131 #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (0x044C)
132 #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK BIT(0)
133 #define CDC_WSA_RX_DSMDEM_CLK_ENABLE BIT(0)
134 #define CDC_WSA_RX1_RX_PATH_CTL (0x0480)
135 #define CDC_WSA_RX1_RX_PATH_CFG0 (0x0484)
136 #define CDC_WSA_RX1_RX_PATH_CFG1 (0x0488)
137 #define CDC_WSA_RX1_RX_PATH_CFG2 (0x048C)
138 #define CDC_WSA_RX1_RX_PATH_CFG3 (0x0490)
139 #define CDC_WSA_RX1_RX_VOL_CTL (0x0494)
140 #define CDC_WSA_RX1_RX_PATH_MIX_CTL (0x0498)
141 #define CDC_WSA_RX1_RX_PATH_MIX_CFG (0x049C)
142 #define CDC_WSA_RX1_RX_VOL_MIX_CTL (0x04A0)
143 #define CDC_WSA_RX1_RX_PATH_SEC0 (0x04A4)
144 #define CDC_WSA_RX1_RX_PATH_SEC1 (0x04A8)
145 #define CDC_WSA_RX1_RX_PATH_SEC2 (0x04AC)
146 #define CDC_WSA_RX1_RX_PATH_SEC3 (0x04B0)
147 #define CDC_WSA_RX1_RX_PATH_SEC5 (0x04B8)
148 #define CDC_WSA_RX1_RX_PATH_SEC6 (0x04BC)
149 #define CDC_WSA_RX1_RX_PATH_SEC7 (0x04C0)
150 #define CDC_WSA_RX1_RX_PATH_MIX_SEC0 (0x04C4)
151 #define CDC_WSA_RX1_RX_PATH_MIX_SEC1 (0x04C8)
152 #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (0x04CC)
153 #define CDC_WSA_BOOST0_BOOST_PATH_CTL (0x0500)
154 #define CDC_WSA_BOOST_PATH_CLK_EN_MASK BIT(4)
155 #define CDC_WSA_BOOST_PATH_CLK_ENABLE BIT(4)
156 #define CDC_WSA_BOOST_PATH_CLK_DISABLE 0
157 #define CDC_WSA_BOOST0_BOOST_CTL (0x0504)
158 #define CDC_WSA_BOOST0_BOOST_CFG1 (0x0508)
159 #define CDC_WSA_BOOST0_BOOST_CFG2 (0x050C)
160 #define CDC_WSA_BOOST1_BOOST_PATH_CTL (0x0540)
161 #define CDC_WSA_BOOST1_BOOST_CTL (0x0544)
162 #define CDC_WSA_BOOST1_BOOST_CFG1 (0x0548)
163 #define CDC_WSA_BOOST1_BOOST_CFG2 (0x054C)
164 #define CDC_WSA_COMPANDER0_CTL0 (0x0580)
165 #define CDC_WSA_COMPANDER_CLK_EN_MASK BIT(0)
166 #define CDC_WSA_COMPANDER_CLK_ENABLE BIT(0)
167 #define CDC_WSA_COMPANDER_SOFT_RST_MASK BIT(1)
168 #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE BIT(1)
169 #define CDC_WSA_COMPANDER_HALT_MASK BIT(2)
170 #define CDC_WSA_COMPANDER_HALT BIT(2)
171 #define CDC_WSA_COMPANDER0_CTL1 (0x0584)
172 #define CDC_WSA_COMPANDER0_CTL2 (0x0588)
173 #define CDC_WSA_COMPANDER0_CTL3 (0x058C)
174 #define CDC_WSA_COMPANDER0_CTL4 (0x0590)
175 #define CDC_WSA_COMPANDER0_CTL5 (0x0594)
176 #define CDC_WSA_COMPANDER0_CTL6 (0x0598)
177 #define CDC_WSA_COMPANDER0_CTL7 (0x059C)
178 /* CDC_WSA_COMPANDER1_CTLx and CDC_WSA_SOFTCLIPx differ per LPASS codec versions */
179 #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL (0x0680)
180 #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK BIT(0)
181 #define CDC_WSA_EC_HQ_EC_CLK_ENABLE BIT(0)
182 #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (0x0684)
183 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1)
184 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K BIT(3)
185 #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL (0x06C0)
186 #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (0x06C4)
187 #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (0x0700)
188 #define CDC_WSA_SPLINE_ASRC0_CTL0 (0x0704)
189 #define CDC_WSA_SPLINE_ASRC0_CTL1 (0x0708)
190 #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL (0x070C)
191 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB (0x0710)
192 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB (0x0714)
193 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB (0x0718)
194 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB (0x071C)
195 #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (0x0720)
196 #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (0x0740)
197 #define CDC_WSA_SPLINE_ASRC1_CTL0 (0x0744)
198 #define CDC_WSA_SPLINE_ASRC1_CTL1 (0x0748)
199 #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL (0x074C)
200 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750)
201 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754)
202 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758)
203 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C)
204 #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760)
205 #define WSA_MAX_OFFSET (0x0760)
206
207 /* LPASS codec version <=2.4 register offsets */
208 #define CDC_WSA_COMPANDER1_CTL0 (0x05C0)
209 #define CDC_WSA_COMPANDER1_CTL1 (0x05C4)
210 #define CDC_WSA_COMPANDER1_CTL2 (0x05C8)
211 #define CDC_WSA_COMPANDER1_CTL3 (0x05CC)
212 #define CDC_WSA_COMPANDER1_CTL4 (0x05D0)
213 #define CDC_WSA_COMPANDER1_CTL5 (0x05D4)
214 #define CDC_WSA_COMPANDER1_CTL6 (0x05D8)
215 #define CDC_WSA_COMPANDER1_CTL7 (0x05DC)
216 #define CDC_WSA_SOFTCLIP0_CRC (0x0600)
217 #define CDC_WSA_SOFTCLIP_CLK_EN_MASK BIT(0)
218 #define CDC_WSA_SOFTCLIP_CLK_ENABLE BIT(0)
219 #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0604)
220 #define CDC_WSA_SOFTCLIP_EN_MASK BIT(0)
221 #define CDC_WSA_SOFTCLIP_ENABLE BIT(0)
222 #define CDC_WSA_SOFTCLIP1_CRC (0x0640)
223 #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0644)
224
225 /* LPASS codec version >=2.5 register offsets */
226 #define CDC_WSA_TOP_FS_UNGATE (0x00AC)
227 #define CDC_WSA_TOP_GRP_SEL (0x00B0)
228 #define CDC_WSA_TOP_FS_UNGATE2 (0x00DC)
229 #define CDC_2_5_WSA_COMPANDER0_CTL8 (0x05A0)
230 #define CDC_2_5_WSA_COMPANDER0_CTL9 (0x05A4)
231 #define CDC_2_5_WSA_COMPANDER0_CTL10 (0x05A8)
232 #define CDC_2_5_WSA_COMPANDER0_CTL11 (0x05AC)
233 #define CDC_2_5_WSA_COMPANDER0_CTL12 (0x05B0)
234 #define CDC_2_5_WSA_COMPANDER0_CTL13 (0x05B4)
235 #define CDC_2_5_WSA_COMPANDER0_CTL14 (0x05B8)
236 #define CDC_2_5_WSA_COMPANDER0_CTL15 (0x05BC)
237 #define CDC_2_5_WSA_COMPANDER0_CTL16 (0x05C0)
238 #define CDC_2_5_WSA_COMPANDER0_CTL17 (0x05C4)
239 #define CDC_2_5_WSA_COMPANDER0_CTL18 (0x05C8)
240 #define CDC_2_5_WSA_COMPANDER0_CTL19 (0x05CC)
241 #define CDC_2_5_WSA_COMPANDER1_CTL0 (0x05E0)
242 #define CDC_2_5_WSA_COMPANDER1_CTL1 (0x05E4)
243 #define CDC_2_5_WSA_COMPANDER1_CTL2 (0x05E8)
244 #define CDC_2_5_WSA_COMPANDER1_CTL3 (0x05EC)
245 #define CDC_2_5_WSA_COMPANDER1_CTL4 (0x05F0)
246 #define CDC_2_5_WSA_COMPANDER1_CTL5 (0x05F4)
247 #define CDC_2_5_WSA_COMPANDER1_CTL6 (0x05F8)
248 #define CDC_2_5_WSA_COMPANDER1_CTL7 (0x05FC)
249 #define CDC_2_5_WSA_COMPANDER1_CTL8 (0x0600)
250 #define CDC_2_5_WSA_COMPANDER1_CTL9 (0x0604)
251 #define CDC_2_5_WSA_COMPANDER1_CTL10 (0x0608)
252 #define CDC_2_5_WSA_COMPANDER1_CTL11 (0x060C)
253 #define CDC_2_5_WSA_COMPANDER1_CTL12 (0x0610)
254 #define CDC_2_5_WSA_COMPANDER1_CTL13 (0x0614)
255 #define CDC_2_5_WSA_COMPANDER1_CTL14 (0x0618)
256 #define CDC_2_5_WSA_COMPANDER1_CTL15 (0x061C)
257 #define CDC_2_5_WSA_COMPANDER1_CTL16 (0x0620)
258 #define CDC_2_5_WSA_COMPANDER1_CTL17 (0x0624)
259 #define CDC_2_5_WSA_COMPANDER1_CTL18 (0x0628)
260 #define CDC_2_5_WSA_COMPANDER1_CTL19 (0x062C)
261 #define CDC_2_5_WSA_SOFTCLIP0_CRC (0x0640)
262 #define CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0644)
263 #define CDC_2_5_WSA_SOFTCLIP1_CRC (0x0660)
264 #define CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0664)
265
266 #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
267 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
268 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
269 #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\
270 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
271 #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
272 SNDRV_PCM_FMTBIT_S24_LE |\
273 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
274
275 #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
276 SNDRV_PCM_RATE_48000)
277 #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
278 SNDRV_PCM_FMTBIT_S24_LE |\
279 SNDRV_PCM_FMTBIT_S24_3LE)
280
281 #define NUM_INTERPOLATORS 2
282 #define WSA_NUM_CLKS_MAX 5
283 #define WSA_MACRO_MCLK_FREQ 19200000
284 #define WSA_MACRO_MUX_CFG_OFFSET 0x8
285 #define WSA_MACRO_MUX_CFG1_OFFSET 0x4
286 #define WSA_MACRO_RX_PATH_OFFSET 0x80
287 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10
288 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C
289 #define WSA_MACRO_FS_RATE_MASK 0x0F
290 #define WSA_MACRO_EC_MIX_TX0_MASK 0x03
291 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18
292 #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2
293
294 enum {
295 WSA_MACRO_GAIN_OFFSET_M1P5_DB,
296 WSA_MACRO_GAIN_OFFSET_0_DB,
297 };
298 enum {
299 WSA_MACRO_RX0 = 0,
300 WSA_MACRO_RX1,
301 WSA_MACRO_RX_MIX0,
302 WSA_MACRO_RX_MIX1,
303 WSA_MACRO_RX_MAX,
304 };
305
306 enum {
307 WSA_MACRO_TX0 = 0,
308 WSA_MACRO_TX1,
309 WSA_MACRO_TX_MAX,
310 };
311
312 enum {
313 WSA_MACRO_EC0_MUX = 0,
314 WSA_MACRO_EC1_MUX,
315 WSA_MACRO_EC_MUX_MAX,
316 };
317
318 enum {
319 WSA_MACRO_COMP1, /* SPK_L */
320 WSA_MACRO_COMP2, /* SPK_R */
321 WSA_MACRO_COMP_MAX
322 };
323
324 enum {
325 WSA_MACRO_SOFTCLIP0, /* RX0 */
326 WSA_MACRO_SOFTCLIP1, /* RX1 */
327 WSA_MACRO_SOFTCLIP_MAX
328 };
329
330 enum {
331 INTn_1_INP_SEL_ZERO = 0,
332 INTn_1_INP_SEL_RX0,
333 INTn_1_INP_SEL_RX1,
334 INTn_1_INP_SEL_RX2,
335 INTn_1_INP_SEL_RX3,
336 INTn_1_INP_SEL_DEC0,
337 INTn_1_INP_SEL_DEC1,
338 };
339
340 enum {
341 INTn_2_INP_SEL_ZERO = 0,
342 INTn_2_INP_SEL_RX0,
343 INTn_2_INP_SEL_RX1,
344 INTn_2_INP_SEL_RX2,
345 INTn_2_INP_SEL_RX3,
346 };
347
348 struct interp_sample_rate {
349 int sample_rate;
350 int rate_val;
351 };
352
353 static struct interp_sample_rate int_prim_sample_rate_val[] = {
354 {8000, 0x0}, /* 8K */
355 {16000, 0x1}, /* 16K */
356 {24000, -EINVAL},/* 24K */
357 {32000, 0x3}, /* 32K */
358 {48000, 0x4}, /* 48K */
359 {96000, 0x5}, /* 96K */
360 {192000, 0x6}, /* 192K */
361 {384000, 0x7}, /* 384K */
362 {44100, 0x8}, /* 44.1K */
363 };
364
365 static struct interp_sample_rate int_mix_sample_rate_val[] = {
366 {48000, 0x4}, /* 48K */
367 {96000, 0x5}, /* 96K */
368 {192000, 0x6}, /* 192K */
369 };
370
371 /* Matches also rx_mux_text */
372 enum {
373 WSA_MACRO_AIF1_PB,
374 WSA_MACRO_AIF_MIX1_PB,
375 WSA_MACRO_AIF_VI,
376 WSA_MACRO_AIF_ECHO,
377 WSA_MACRO_MAX_DAIS,
378 };
379
380 /**
381 * struct wsa_reg_layout - Register layout differences
382 * @rx_intx_1_mix_inp0_sel_mask: register mask for RX_INTX_1_MIX_INP0_SEL_MASK
383 * @rx_intx_1_mix_inp1_sel_mask: register mask for RX_INTX_1_MIX_INP1_SEL_MASK
384 * @rx_intx_1_mix_inp2_sel_mask: register mask for RX_INTX_1_MIX_INP2_SEL_MASK
385 * @rx_intx_2_sel_mask: register mask for RX_INTX_2_SEL_MASK
386 * @compander1_reg_offset: offset between compander registers (compander1 - compander0)
387 * @softclip0_reg_base: base address of softclip0 register
388 * @softclip1_reg_offset: offset between compander registers (softclip1 - softclip0)
389 */
390 struct wsa_reg_layout {
391 unsigned int rx_intx_1_mix_inp0_sel_mask;
392 unsigned int rx_intx_1_mix_inp1_sel_mask;
393 unsigned int rx_intx_1_mix_inp2_sel_mask;
394 unsigned int rx_intx_2_sel_mask;
395 unsigned int compander1_reg_offset;
396 unsigned int softclip0_reg_base;
397 unsigned int softclip1_reg_offset;
398 };
399
400 struct wsa_macro {
401 struct device *dev;
402 int comp_enabled[WSA_MACRO_COMP_MAX];
403 int ec_hq[WSA_MACRO_RX1 + 1];
404 u16 prim_int_users[WSA_MACRO_RX1 + 1];
405 u16 wsa_mclk_users;
406 enum lpass_codec_version codec_version;
407 const struct wsa_reg_layout *reg_layout;
408 unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS];
409 unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS];
410 int rx_port_value[WSA_MACRO_RX_MAX];
411 int ear_spkr_gain;
412 int spkr_gain_offset;
413 int spkr_mode;
414 u32 pcm_rate_vi;
415 int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX];
416 int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX];
417 struct regmap *regmap;
418 struct clk *mclk;
419 struct clk *npl;
420 struct clk *macro;
421 struct clk *dcodec;
422 struct clk *fsgen;
423 struct clk_hw hw;
424 };
425 #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw)
426
427 static const struct wsa_reg_layout wsa_codec_v2_1 = {
428 .rx_intx_1_mix_inp0_sel_mask = GENMASK(2, 0),
429 .rx_intx_1_mix_inp1_sel_mask = GENMASK(5, 3),
430 .rx_intx_1_mix_inp2_sel_mask = GENMASK(5, 3),
431 .rx_intx_2_sel_mask = GENMASK(2, 0),
432 .compander1_reg_offset = 0x40,
433 .softclip0_reg_base = 0x600,
434 .softclip1_reg_offset = 0x40,
435 };
436
437 static const struct wsa_reg_layout wsa_codec_v2_5 = {
438 .rx_intx_1_mix_inp0_sel_mask = GENMASK(3, 0),
439 .rx_intx_1_mix_inp1_sel_mask = GENMASK(7, 4),
440 .rx_intx_1_mix_inp2_sel_mask = GENMASK(7, 4),
441 .rx_intx_2_sel_mask = GENMASK(3, 0),
442 .compander1_reg_offset = 0x60,
443 .softclip0_reg_base = 0x640,
444 .softclip1_reg_offset = 0x20,
445 };
446
447 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
448
449 static const char *const rx_text_v2_1[] = {
450 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1"
451 };
452
453 static const char *const rx_text_v2_5[] = {
454 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5", "RX6", "RX7", "RX8", "DEC0", "DEC1"
455 };
456
457 static const char *const rx_mix_text_v2_1[] = {
458 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1"
459 };
460
461 static const char *const rx_mix_text_v2_5[] = {
462 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5", "RX6", "RX7", "RX8"
463 };
464
465 static const char *const rx_mix_ec_text[] = {
466 "ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
467 };
468
469 /* Order must match WSA_MACRO_MAX_DAIS enum (offset by 1) */
470 static const char *const rx_mux_text[] = {
471 "ZERO", "AIF1_PB", "AIF_MIX1_PB"
472 };
473
474 static const char *const rx_sidetone_mix_text[] = {
475 "ZERO", "SRC0"
476 };
477
478 static const char * const wsa_macro_ear_spkr_pa_gain_text[] = {
479 "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB",
480 "G_4_DB", "G_5_DB", "G_6_DB"
481 };
482
483 static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum,
484 wsa_macro_ear_spkr_pa_gain_text);
485
486 /* RX INT0 */
487 static const struct soc_enum rx0_prim_inp0_chain_enum_v2_1 =
488 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
489 0, 7, rx_text_v2_1);
490
491 static const struct soc_enum rx0_prim_inp1_chain_enum_v2_1 =
492 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
493 3, 7, rx_text_v2_1);
494
495 static const struct soc_enum rx0_prim_inp2_chain_enum_v2_1 =
496 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
497 3, 7, rx_text_v2_1);
498
499 static const struct soc_enum rx0_mix_chain_enum_v2_1 =
500 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
501 0, 5, rx_mix_text_v2_1);
502
503 static const struct soc_enum rx0_prim_inp0_chain_enum_v2_5 =
504 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
505 0, 12, rx_text_v2_5);
506
507 static const struct soc_enum rx0_prim_inp1_chain_enum_v2_5 =
508 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
509 4, 12, rx_text_v2_5);
510
511 static const struct soc_enum rx0_prim_inp2_chain_enum_v2_5 =
512 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
513 4, 12, rx_text_v2_5);
514
515 static const struct soc_enum rx0_mix_chain_enum_v2_5 =
516 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
517 0, 10, rx_mix_text_v2_5);
518
519 static const struct soc_enum rx0_sidetone_mix_enum =
520 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
521
522 static const struct snd_kcontrol_new rx0_prim_inp0_mux_v2_1 =
523 SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum_v2_1);
524
525 static const struct snd_kcontrol_new rx0_prim_inp1_mux_v2_1 =
526 SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum_v2_1);
527
528 static const struct snd_kcontrol_new rx0_prim_inp2_mux_v2_1 =
529 SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum_v2_1);
530
531 static const struct snd_kcontrol_new rx0_mix_mux_v2_1 =
532 SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum_v2_1);
533
534 static const struct snd_kcontrol_new rx0_prim_inp0_mux_v2_5 =
535 SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum_v2_5);
536
537 static const struct snd_kcontrol_new rx0_prim_inp1_mux_v2_5 =
538 SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum_v2_5);
539
540 static const struct snd_kcontrol_new rx0_prim_inp2_mux_v2_5 =
541 SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum_v2_5);
542
543 static const struct snd_kcontrol_new rx0_mix_mux_v2_5 =
544 SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum_v2_5);
545
546 static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
547 SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
548
549 /* RX INT1 */
550 static const struct soc_enum rx1_prim_inp0_chain_enum_v2_1 =
551 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
552 0, 7, rx_text_v2_1);
553
554 static const struct soc_enum rx1_prim_inp1_chain_enum_v2_1 =
555 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
556 3, 7, rx_text_v2_1);
557
558 static const struct soc_enum rx1_prim_inp2_chain_enum_v2_1 =
559 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
560 3, 7, rx_text_v2_1);
561
562 static const struct soc_enum rx1_mix_chain_enum_v2_1 =
563 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
564 0, 5, rx_mix_text_v2_1);
565
566 static const struct soc_enum rx1_prim_inp0_chain_enum_v2_5 =
567 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
568 0, 12, rx_text_v2_5);
569
570 static const struct soc_enum rx1_prim_inp1_chain_enum_v2_5 =
571 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
572 4, 12, rx_text_v2_5);
573
574 static const struct soc_enum rx1_prim_inp2_chain_enum_v2_5 =
575 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
576 4, 12, rx_text_v2_5);
577
578 static const struct soc_enum rx1_mix_chain_enum_v2_5 =
579 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
580 0, 10, rx_mix_text_v2_5);
581
582 static const struct snd_kcontrol_new rx1_prim_inp0_mux_v2_1 =
583 SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum_v2_1);
584
585 static const struct snd_kcontrol_new rx1_prim_inp1_mux_v2_1 =
586 SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum_v2_1);
587
588 static const struct snd_kcontrol_new rx1_prim_inp2_mux_v2_1 =
589 SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum_v2_1);
590
591 static const struct snd_kcontrol_new rx1_mix_mux_v2_1 =
592 SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum_v2_1);
593
594 static const struct snd_kcontrol_new rx1_prim_inp0_mux_v2_5 =
595 SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum_v2_5);
596
597 static const struct snd_kcontrol_new rx1_prim_inp1_mux_v2_5 =
598 SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum_v2_5);
599
600 static const struct snd_kcontrol_new rx1_prim_inp2_mux_v2_5 =
601 SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum_v2_5);
602
603 static const struct snd_kcontrol_new rx1_mix_mux_v2_5 =
604 SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum_v2_5);
605
606 static const struct soc_enum rx_mix_ec0_enum =
607 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
608 0, 3, rx_mix_ec_text);
609
610 static const struct soc_enum rx_mix_ec1_enum =
611 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
612 3, 3, rx_mix_ec_text);
613
614 static const struct snd_kcontrol_new rx_mix_ec0_mux =
615 SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
616
617 static const struct snd_kcontrol_new rx_mix_ec1_mux =
618 SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
619
620 static const struct reg_default wsa_defaults[] = {
621 /* WSA Macro */
622 { CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
623 { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
624 { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
625 { CDC_WSA_TOP_TOP_CFG0, 0x00},
626 { CDC_WSA_TOP_TOP_CFG1, 0x00},
627 { CDC_WSA_TOP_FREQ_MCLK, 0x00},
628 { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
629 { CDC_WSA_TOP_DEBUG_EN0, 0x00},
630 { CDC_WSA_TOP_DEBUG_EN1, 0x00},
631 { CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
632 { CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
633 { CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
634 { CDC_WSA_TOP_I2S_CLK, 0x02},
635 { CDC_WSA_TOP_I2S_RESET, 0x00},
636 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
637 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
638 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
639 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
640 { CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
641 { CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
642 { CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
643 { CDC_WSA_INTR_CTRL_CFG, 0x00},
644 { CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
645 { CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
646 { CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
647 { CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
648 { CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
649 { CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
650 { CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
651 { CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
652 { CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
653 { CDC_WSA_INTR_CTRL_SET0, 0x00},
654 { CDC_WSA_RX0_RX_PATH_CTL, 0x04},
655 { CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
656 { CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
657 { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
658 { CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
659 { CDC_WSA_RX0_RX_VOL_CTL, 0x00},
660 { CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
661 { CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
662 { CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
663 { CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
664 { CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
665 { CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
666 { CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
667 { CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
668 { CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
669 { CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
670 { CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
671 { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
672 { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
673 { CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
674 { CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
675 { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
676 { CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
677 { CDC_WSA_RX1_RX_VOL_CTL, 0x00},
678 { CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
679 { CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
680 { CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
681 { CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
682 { CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
683 { CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
684 { CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
685 { CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
686 { CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
687 { CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
688 { CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
689 { CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
690 { CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
691 { CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
692 { CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
693 { CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
694 { CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
695 { CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
696 { CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
697 { CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
698 { CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
699 { CDC_WSA_COMPANDER0_CTL0, 0x60},
700 { CDC_WSA_COMPANDER0_CTL1, 0xDB},
701 { CDC_WSA_COMPANDER0_CTL2, 0xFF},
702 { CDC_WSA_COMPANDER0_CTL3, 0x35},
703 { CDC_WSA_COMPANDER0_CTL4, 0xFF},
704 { CDC_WSA_COMPANDER0_CTL5, 0x00},
705 { CDC_WSA_COMPANDER0_CTL6, 0x01},
706 { CDC_WSA_COMPANDER0_CTL7, 0x28},
707 { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
708 { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
709 { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
710 { CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
711 { CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
712 { CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
713 { CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
714 { CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
715 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
716 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
717 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
718 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
719 { CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
720 { CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
721 { CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
722 { CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
723 { CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
724 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
725 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
726 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
727 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
728 { CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
729 };
730
731 static const struct reg_default wsa_defaults_v2_1[] = {
732 { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
733 { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
734 { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
735 { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
736 { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
737 { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
738 { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
739 { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
740 { CDC_WSA_COMPANDER1_CTL0, 0x60},
741 { CDC_WSA_COMPANDER1_CTL1, 0xDB},
742 { CDC_WSA_COMPANDER1_CTL2, 0xFF},
743 { CDC_WSA_COMPANDER1_CTL3, 0x35},
744 { CDC_WSA_COMPANDER1_CTL4, 0xFF},
745 { CDC_WSA_COMPANDER1_CTL5, 0x00},
746 { CDC_WSA_COMPANDER1_CTL6, 0x01},
747 { CDC_WSA_COMPANDER1_CTL7, 0x28},
748 { CDC_WSA_SOFTCLIP0_CRC, 0x00},
749 { CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
750 { CDC_WSA_SOFTCLIP1_CRC, 0x00},
751 { CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
752 };
753
754 static const struct reg_default wsa_defaults_v2_5[] = {
755 { CDC_WSA_TOP_FS_UNGATE, 0xFF},
756 { CDC_WSA_TOP_GRP_SEL, 0x08},
757 { CDC_WSA_TOP_FS_UNGATE2, 0x1F},
758 { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x04},
759 { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x02},
760 { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x04},
761 { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x02},
762 { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x04},
763 { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x02},
764 { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x04},
765 { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x02},
766 { CDC_2_5_WSA_COMPANDER0_CTL8, 0x00},
767 { CDC_2_5_WSA_COMPANDER0_CTL9, 0x00},
768 { CDC_2_5_WSA_COMPANDER0_CTL10, 0x06},
769 { CDC_2_5_WSA_COMPANDER0_CTL11, 0x12},
770 { CDC_2_5_WSA_COMPANDER0_CTL12, 0x1E},
771 { CDC_2_5_WSA_COMPANDER0_CTL13, 0x24},
772 { CDC_2_5_WSA_COMPANDER0_CTL14, 0x24},
773 { CDC_2_5_WSA_COMPANDER0_CTL15, 0x24},
774 { CDC_2_5_WSA_COMPANDER0_CTL16, 0x00},
775 { CDC_2_5_WSA_COMPANDER0_CTL17, 0x24},
776 { CDC_2_5_WSA_COMPANDER0_CTL18, 0x2A},
777 { CDC_2_5_WSA_COMPANDER0_CTL19, 0x16},
778 { CDC_2_5_WSA_COMPANDER1_CTL0, 0x60},
779 { CDC_2_5_WSA_COMPANDER1_CTL1, 0xDB},
780 { CDC_2_5_WSA_COMPANDER1_CTL2, 0xFF},
781 { CDC_2_5_WSA_COMPANDER1_CTL3, 0x35},
782 { CDC_2_5_WSA_COMPANDER1_CTL4, 0xFF},
783 { CDC_2_5_WSA_COMPANDER1_CTL5, 0x00},
784 { CDC_2_5_WSA_COMPANDER1_CTL6, 0x01},
785 { CDC_2_5_WSA_COMPANDER1_CTL7, 0x28},
786 { CDC_2_5_WSA_COMPANDER1_CTL8, 0x00},
787 { CDC_2_5_WSA_COMPANDER1_CTL9, 0x00},
788 { CDC_2_5_WSA_COMPANDER1_CTL10, 0x06},
789 { CDC_2_5_WSA_COMPANDER1_CTL11, 0x12},
790 { CDC_2_5_WSA_COMPANDER1_CTL12, 0x1E},
791 { CDC_2_5_WSA_COMPANDER1_CTL13, 0x24},
792 { CDC_2_5_WSA_COMPANDER1_CTL14, 0x24},
793 { CDC_2_5_WSA_COMPANDER1_CTL15, 0x24},
794 { CDC_2_5_WSA_COMPANDER1_CTL16, 0x00},
795 { CDC_2_5_WSA_COMPANDER1_CTL17, 0x24},
796 { CDC_2_5_WSA_COMPANDER1_CTL18, 0x2A},
797 { CDC_2_5_WSA_COMPANDER1_CTL19, 0x16},
798 { CDC_2_5_WSA_SOFTCLIP0_CRC, 0x00},
799 { CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
800 { CDC_2_5_WSA_SOFTCLIP1_CRC, 0x00},
801 { CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
802 };
803
wsa_is_wronly_register(struct device * dev,unsigned int reg)804 static bool wsa_is_wronly_register(struct device *dev,
805 unsigned int reg)
806 {
807 switch (reg) {
808 case CDC_WSA_INTR_CTRL_CLR_COMMIT:
809 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
810 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
811 return true;
812 }
813
814 return false;
815 }
816
wsa_is_rw_register_v2_1(struct device * dev,unsigned int reg)817 static bool wsa_is_rw_register_v2_1(struct device *dev, unsigned int reg)
818 {
819 switch (reg) {
820 case CDC_WSA_COMPANDER1_CTL0:
821 case CDC_WSA_COMPANDER1_CTL1:
822 case CDC_WSA_COMPANDER1_CTL2:
823 case CDC_WSA_COMPANDER1_CTL3:
824 case CDC_WSA_COMPANDER1_CTL4:
825 case CDC_WSA_COMPANDER1_CTL5:
826 case CDC_WSA_COMPANDER1_CTL7:
827 case CDC_WSA_SOFTCLIP0_CRC:
828 case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
829 case CDC_WSA_SOFTCLIP1_CRC:
830 case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
831 return true;
832 }
833
834 return false;
835 }
836
wsa_is_rw_register_v2_5(struct device * dev,unsigned int reg)837 static bool wsa_is_rw_register_v2_5(struct device *dev, unsigned int reg)
838 {
839 switch (reg) {
840 case CDC_WSA_TOP_FS_UNGATE:
841 case CDC_WSA_TOP_GRP_SEL:
842 case CDC_WSA_TOP_FS_UNGATE2:
843 case CDC_2_5_WSA_COMPANDER0_CTL8:
844 case CDC_2_5_WSA_COMPANDER0_CTL9:
845 case CDC_2_5_WSA_COMPANDER0_CTL10:
846 case CDC_2_5_WSA_COMPANDER0_CTL11:
847 case CDC_2_5_WSA_COMPANDER0_CTL12:
848 case CDC_2_5_WSA_COMPANDER0_CTL13:
849 case CDC_2_5_WSA_COMPANDER0_CTL14:
850 case CDC_2_5_WSA_COMPANDER0_CTL15:
851 case CDC_2_5_WSA_COMPANDER0_CTL16:
852 case CDC_2_5_WSA_COMPANDER0_CTL17:
853 case CDC_2_5_WSA_COMPANDER0_CTL18:
854 case CDC_2_5_WSA_COMPANDER0_CTL19:
855 case CDC_2_5_WSA_COMPANDER1_CTL0:
856 case CDC_2_5_WSA_COMPANDER1_CTL1:
857 case CDC_2_5_WSA_COMPANDER1_CTL2:
858 case CDC_2_5_WSA_COMPANDER1_CTL3:
859 case CDC_2_5_WSA_COMPANDER1_CTL4:
860 case CDC_2_5_WSA_COMPANDER1_CTL5:
861 case CDC_2_5_WSA_COMPANDER1_CTL7:
862 case CDC_2_5_WSA_COMPANDER1_CTL8:
863 case CDC_2_5_WSA_COMPANDER1_CTL9:
864 case CDC_2_5_WSA_COMPANDER1_CTL10:
865 case CDC_2_5_WSA_COMPANDER1_CTL11:
866 case CDC_2_5_WSA_COMPANDER1_CTL12:
867 case CDC_2_5_WSA_COMPANDER1_CTL13:
868 case CDC_2_5_WSA_COMPANDER1_CTL14:
869 case CDC_2_5_WSA_COMPANDER1_CTL15:
870 case CDC_2_5_WSA_COMPANDER1_CTL16:
871 case CDC_2_5_WSA_COMPANDER1_CTL17:
872 case CDC_2_5_WSA_COMPANDER1_CTL18:
873 case CDC_2_5_WSA_COMPANDER1_CTL19:
874 case CDC_2_5_WSA_SOFTCLIP0_CRC:
875 case CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
876 case CDC_2_5_WSA_SOFTCLIP1_CRC:
877 case CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
878 return true;
879 }
880
881 return false;
882 }
883
wsa_is_rw_register(struct device * dev,unsigned int reg)884 static bool wsa_is_rw_register(struct device *dev, unsigned int reg)
885 {
886 struct wsa_macro *wsa = dev_get_drvdata(dev);
887
888 switch (reg) {
889 case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL:
890 case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL:
891 case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL:
892 case CDC_WSA_TOP_TOP_CFG0:
893 case CDC_WSA_TOP_TOP_CFG1:
894 case CDC_WSA_TOP_FREQ_MCLK:
895 case CDC_WSA_TOP_DEBUG_BUS_SEL:
896 case CDC_WSA_TOP_DEBUG_EN0:
897 case CDC_WSA_TOP_DEBUG_EN1:
898 case CDC_WSA_TOP_DEBUG_DSM_LB:
899 case CDC_WSA_TOP_RX_I2S_CTL:
900 case CDC_WSA_TOP_TX_I2S_CTL:
901 case CDC_WSA_TOP_I2S_CLK:
902 case CDC_WSA_TOP_I2S_RESET:
903 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0:
904 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1:
905 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0:
906 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1:
907 case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0:
908 case CDC_WSA_RX_INP_MUX_RX_EC_CFG0:
909 case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0:
910 case CDC_WSA_TX0_SPKR_PROT_PATH_CTL:
911 case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0:
912 case CDC_WSA_TX1_SPKR_PROT_PATH_CTL:
913 case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0:
914 case CDC_WSA_TX2_SPKR_PROT_PATH_CTL:
915 case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0:
916 case CDC_WSA_TX3_SPKR_PROT_PATH_CTL:
917 case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0:
918 case CDC_WSA_INTR_CTRL_CFG:
919 case CDC_WSA_INTR_CTRL_PIN1_MASK0:
920 case CDC_WSA_INTR_CTRL_PIN2_MASK0:
921 case CDC_WSA_INTR_CTRL_LEVEL0:
922 case CDC_WSA_INTR_CTRL_BYPASS0:
923 case CDC_WSA_INTR_CTRL_SET0:
924 case CDC_WSA_RX0_RX_PATH_CTL:
925 case CDC_WSA_RX0_RX_PATH_CFG0:
926 case CDC_WSA_RX0_RX_PATH_CFG1:
927 case CDC_WSA_RX0_RX_PATH_CFG2:
928 case CDC_WSA_RX0_RX_PATH_CFG3:
929 case CDC_WSA_RX0_RX_VOL_CTL:
930 case CDC_WSA_RX0_RX_PATH_MIX_CTL:
931 case CDC_WSA_RX0_RX_PATH_MIX_CFG:
932 case CDC_WSA_RX0_RX_VOL_MIX_CTL:
933 case CDC_WSA_RX0_RX_PATH_SEC0:
934 case CDC_WSA_RX0_RX_PATH_SEC1:
935 case CDC_WSA_RX0_RX_PATH_SEC2:
936 case CDC_WSA_RX0_RX_PATH_SEC3:
937 case CDC_WSA_RX0_RX_PATH_SEC5:
938 case CDC_WSA_RX0_RX_PATH_SEC6:
939 case CDC_WSA_RX0_RX_PATH_SEC7:
940 case CDC_WSA_RX0_RX_PATH_MIX_SEC0:
941 case CDC_WSA_RX0_RX_PATH_MIX_SEC1:
942 case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL:
943 case CDC_WSA_RX1_RX_PATH_CTL:
944 case CDC_WSA_RX1_RX_PATH_CFG0:
945 case CDC_WSA_RX1_RX_PATH_CFG1:
946 case CDC_WSA_RX1_RX_PATH_CFG2:
947 case CDC_WSA_RX1_RX_PATH_CFG3:
948 case CDC_WSA_RX1_RX_VOL_CTL:
949 case CDC_WSA_RX1_RX_PATH_MIX_CTL:
950 case CDC_WSA_RX1_RX_PATH_MIX_CFG:
951 case CDC_WSA_RX1_RX_VOL_MIX_CTL:
952 case CDC_WSA_RX1_RX_PATH_SEC0:
953 case CDC_WSA_RX1_RX_PATH_SEC1:
954 case CDC_WSA_RX1_RX_PATH_SEC2:
955 case CDC_WSA_RX1_RX_PATH_SEC3:
956 case CDC_WSA_RX1_RX_PATH_SEC5:
957 case CDC_WSA_RX1_RX_PATH_SEC6:
958 case CDC_WSA_RX1_RX_PATH_SEC7:
959 case CDC_WSA_RX1_RX_PATH_MIX_SEC0:
960 case CDC_WSA_RX1_RX_PATH_MIX_SEC1:
961 case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL:
962 case CDC_WSA_BOOST0_BOOST_PATH_CTL:
963 case CDC_WSA_BOOST0_BOOST_CTL:
964 case CDC_WSA_BOOST0_BOOST_CFG1:
965 case CDC_WSA_BOOST0_BOOST_CFG2:
966 case CDC_WSA_BOOST1_BOOST_PATH_CTL:
967 case CDC_WSA_BOOST1_BOOST_CTL:
968 case CDC_WSA_BOOST1_BOOST_CFG1:
969 case CDC_WSA_BOOST1_BOOST_CFG2:
970 case CDC_WSA_COMPANDER0_CTL0:
971 case CDC_WSA_COMPANDER0_CTL1:
972 case CDC_WSA_COMPANDER0_CTL2:
973 case CDC_WSA_COMPANDER0_CTL3:
974 case CDC_WSA_COMPANDER0_CTL4:
975 case CDC_WSA_COMPANDER0_CTL5:
976 case CDC_WSA_COMPANDER0_CTL7:
977 case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL:
978 case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0:
979 case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL:
980 case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0:
981 case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL:
982 case CDC_WSA_SPLINE_ASRC0_CTL0:
983 case CDC_WSA_SPLINE_ASRC0_CTL1:
984 case CDC_WSA_SPLINE_ASRC0_FIFO_CTL:
985 case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL:
986 case CDC_WSA_SPLINE_ASRC1_CTL0:
987 case CDC_WSA_SPLINE_ASRC1_CTL1:
988 case CDC_WSA_SPLINE_ASRC1_FIFO_CTL:
989 return true;
990 }
991
992 if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5)
993 return wsa_is_rw_register_v2_5(dev, reg);
994
995 return wsa_is_rw_register_v2_1(dev, reg);
996 }
997
wsa_is_writeable_register(struct device * dev,unsigned int reg)998 static bool wsa_is_writeable_register(struct device *dev, unsigned int reg)
999 {
1000 bool ret;
1001
1002 ret = wsa_is_rw_register(dev, reg);
1003 if (!ret)
1004 return wsa_is_wronly_register(dev, reg);
1005
1006 return ret;
1007 }
1008
wsa_is_readable_register_v2_1(struct device * dev,unsigned int reg)1009 static bool wsa_is_readable_register_v2_1(struct device *dev, unsigned int reg)
1010 {
1011 switch (reg) {
1012 case CDC_WSA_COMPANDER1_CTL6:
1013 return true;
1014 }
1015
1016 return wsa_is_rw_register(dev, reg);
1017 }
1018
wsa_is_readable_register_v2_5(struct device * dev,unsigned int reg)1019 static bool wsa_is_readable_register_v2_5(struct device *dev, unsigned int reg)
1020 {
1021 switch (reg) {
1022 case CDC_2_5_WSA_COMPANDER1_CTL6:
1023 return true;
1024 }
1025
1026 return wsa_is_rw_register(dev, reg);
1027 }
1028
wsa_is_readable_register(struct device * dev,unsigned int reg)1029 static bool wsa_is_readable_register(struct device *dev, unsigned int reg)
1030 {
1031 struct wsa_macro *wsa = dev_get_drvdata(dev);
1032
1033 switch (reg) {
1034 case CDC_WSA_INTR_CTRL_CLR_COMMIT:
1035 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
1036 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
1037 case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
1038 case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
1039 case CDC_WSA_COMPANDER0_CTL6:
1040 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
1041 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
1042 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
1043 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
1044 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
1045 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
1046 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
1047 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
1048 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
1049 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
1050 return true;
1051 }
1052
1053 if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5)
1054 return wsa_is_readable_register_v2_5(dev, reg);
1055
1056 return wsa_is_readable_register_v2_1(dev, reg);
1057 }
1058
wsa_is_volatile_register_v2_1(struct device * dev,unsigned int reg)1059 static bool wsa_is_volatile_register_v2_1(struct device *dev, unsigned int reg)
1060 {
1061 switch (reg) {
1062 case CDC_WSA_COMPANDER1_CTL6:
1063 return true;
1064 }
1065
1066 return false;
1067 }
1068
wsa_is_volatile_register_v2_5(struct device * dev,unsigned int reg)1069 static bool wsa_is_volatile_register_v2_5(struct device *dev, unsigned int reg)
1070 {
1071 switch (reg) {
1072 case CDC_2_5_WSA_COMPANDER1_CTL6:
1073 return true;
1074 }
1075
1076 return false;
1077 }
1078
wsa_is_volatile_register(struct device * dev,unsigned int reg)1079 static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)
1080 {
1081 struct wsa_macro *wsa = dev_get_drvdata(dev);
1082
1083 /* Update volatile list for rx/tx macros */
1084 switch (reg) {
1085 case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
1086 case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
1087 case CDC_WSA_COMPANDER0_CTL6:
1088 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
1089 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
1090 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
1091 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
1092 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
1093 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
1094 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
1095 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
1096 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
1097 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
1098 return true;
1099 }
1100
1101 if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5)
1102 return wsa_is_volatile_register_v2_5(dev, reg);
1103
1104 return wsa_is_volatile_register_v2_1(dev, reg);
1105 }
1106
1107 static const struct regmap_config wsa_regmap_config = {
1108 .name = "wsa_macro",
1109 .reg_bits = 16,
1110 .val_bits = 32, /* 8 but with 32 bit read/write */
1111 .reg_stride = 4,
1112 .cache_type = REGCACHE_FLAT,
1113 /* .reg_defaults and .num_reg_defaults set in probe() */
1114 .max_register = WSA_MAX_OFFSET,
1115 .writeable_reg = wsa_is_writeable_register,
1116 .volatile_reg = wsa_is_volatile_register,
1117 .readable_reg = wsa_is_readable_register,
1118 };
1119
1120 /**
1121 * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost
1122 * settings based on speaker mode.
1123 *
1124 * @component: codec instance
1125 * @mode: Indicates speaker configuration mode.
1126 *
1127 * Returns 0 on success or -EINVAL on error.
1128 */
wsa_macro_set_spkr_mode(struct snd_soc_component * component,int mode)1129 int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode)
1130 {
1131 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1132
1133 wsa->spkr_mode = mode;
1134
1135 switch (mode) {
1136 case WSA_MACRO_SPKR_MODE_1:
1137 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00);
1138 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00);
1139 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
1140 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00);
1141 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44);
1142 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44);
1143 break;
1144 default:
1145 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
1146 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80);
1147 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
1148 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01);
1149 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58);
1150 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58);
1151 break;
1152 }
1153 return 0;
1154 }
1155 EXPORT_SYMBOL(wsa_macro_set_spkr_mode);
1156
wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 int_prim_fs_rate_reg_val,u32 sample_rate)1157 static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1158 u8 int_prim_fs_rate_reg_val,
1159 u32 sample_rate)
1160 {
1161 u8 int_1_mix1_inp;
1162 u32 j, port;
1163 u16 int_mux_cfg0, int_mux_cfg1;
1164 u16 int_fs_reg;
1165 u8 inp0_sel, inp1_sel, inp2_sel;
1166 struct snd_soc_component *component = dai->component;
1167 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1168
1169 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
1170 int_1_mix1_inp = port;
1171 int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0;
1172
1173 /*
1174 * Loop through all interpolator MUX inputs and find out
1175 * to which interpolator input, the cdc_dma rx port
1176 * is connected
1177 */
1178 for (j = 0; j < NUM_INTERPOLATORS; j++) {
1179 int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET;
1180 inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1181 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask);
1182 inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1183 wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask);
1184 inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
1185 wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask);
1186
1187 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1188 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1189 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
1190 int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL +
1191 WSA_MACRO_RX_PATH_OFFSET * j;
1192 /* sample_rate is in Hz */
1193 snd_soc_component_update_bits(component, int_fs_reg,
1194 WSA_MACRO_FS_RATE_MASK,
1195 int_prim_fs_rate_reg_val);
1196 }
1197 int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET;
1198 }
1199 }
1200
1201 return 0;
1202 }
1203
wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai * dai,u8 int_mix_fs_rate_reg_val,u32 sample_rate)1204 static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1205 u8 int_mix_fs_rate_reg_val,
1206 u32 sample_rate)
1207 {
1208 u8 int_2_inp;
1209 u32 j, port;
1210 u16 int_mux_cfg1, int_fs_reg;
1211 u8 int_mux_cfg1_val;
1212 struct snd_soc_component *component = dai->component;
1213 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1214
1215 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
1216 int_2_inp = port;
1217
1218 int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;
1219 for (j = 0; j < NUM_INTERPOLATORS; j++) {
1220 int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
1221 wsa->reg_layout->rx_intx_2_sel_mask);
1222
1223 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
1224 int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL +
1225 WSA_MACRO_RX_PATH_OFFSET * j;
1226
1227 snd_soc_component_update_bits(component,
1228 int_fs_reg,
1229 WSA_MACRO_FS_RATE_MASK,
1230 int_mix_fs_rate_reg_val);
1231 }
1232 int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET;
1233 }
1234 }
1235 return 0;
1236 }
1237
wsa_macro_set_interpolator_rate(struct snd_soc_dai * dai,u32 sample_rate)1238 static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai,
1239 u32 sample_rate)
1240 {
1241 int rate_val = 0;
1242 int i, ret;
1243
1244 /* set mixing path rate */
1245 for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
1246 if (sample_rate == int_mix_sample_rate_val[i].sample_rate) {
1247 rate_val = int_mix_sample_rate_val[i].rate_val;
1248 break;
1249 }
1250 }
1251 if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0))
1252 goto prim_rate;
1253
1254 ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate);
1255 if (ret < 0)
1256 return ret;
1257 prim_rate:
1258 /* set primary path sample rate */
1259 for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
1260 if (sample_rate == int_prim_sample_rate_val[i].sample_rate) {
1261 rate_val = int_prim_sample_rate_val[i].rate_val;
1262 break;
1263 }
1264 }
1265 if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0))
1266 return -EINVAL;
1267
1268 ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate);
1269
1270 return ret;
1271 }
1272
wsa_macro_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1273 static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
1274 struct snd_pcm_hw_params *params,
1275 struct snd_soc_dai *dai)
1276 {
1277 struct snd_soc_component *component = dai->component;
1278 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1279 int ret;
1280
1281 switch (substream->stream) {
1282 case SNDRV_PCM_STREAM_PLAYBACK:
1283 ret = wsa_macro_set_interpolator_rate(dai, params_rate(params));
1284 if (ret) {
1285 dev_err(component->dev,
1286 "%s: cannot set sample rate: %u\n",
1287 __func__, params_rate(params));
1288 return ret;
1289 }
1290 break;
1291 case SNDRV_PCM_STREAM_CAPTURE:
1292 if (dai->id == WSA_MACRO_AIF_VI)
1293 wsa->pcm_rate_vi = params_rate(params);
1294
1295 break;
1296 default:
1297 break;
1298 }
1299 return 0;
1300 }
1301
wsa_macro_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1302 static int wsa_macro_get_channel_map(const struct snd_soc_dai *dai,
1303 unsigned int *tx_num, unsigned int *tx_slot,
1304 unsigned int *rx_num, unsigned int *rx_slot)
1305 {
1306 struct snd_soc_component *component = dai->component;
1307 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1308 u16 val, mask = 0, cnt = 0, temp;
1309
1310 switch (dai->id) {
1311 case WSA_MACRO_AIF_VI:
1312 *tx_slot = wsa->active_ch_mask[dai->id];
1313 *tx_num = wsa->active_ch_cnt[dai->id];
1314 break;
1315 case WSA_MACRO_AIF1_PB:
1316 case WSA_MACRO_AIF_MIX1_PB:
1317 for_each_set_bit(temp, &wsa->active_ch_mask[dai->id],
1318 WSA_MACRO_RX_MAX) {
1319 mask |= (1 << temp);
1320 if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT)
1321 break;
1322 }
1323 if (mask & 0x0C)
1324 mask = mask >> 0x2;
1325 *rx_slot = mask;
1326 *rx_num = cnt;
1327 break;
1328 case WSA_MACRO_AIF_ECHO:
1329 val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
1330 if (val & WSA_MACRO_EC_MIX_TX1_MASK) {
1331 mask |= 0x2;
1332 cnt++;
1333 }
1334 if (val & WSA_MACRO_EC_MIX_TX0_MASK) {
1335 mask |= 0x1;
1336 cnt++;
1337 }
1338 *tx_slot = mask;
1339 *tx_num = cnt;
1340 break;
1341 default:
1342 dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1343 break;
1344 }
1345 return 0;
1346 }
1347
1348 static const struct snd_soc_dai_ops wsa_macro_dai_ops = {
1349 .hw_params = wsa_macro_hw_params,
1350 .get_channel_map = wsa_macro_get_channel_map,
1351 };
1352
1353 static struct snd_soc_dai_driver wsa_macro_dai[] = {
1354 {
1355 .name = "wsa_macro_rx1",
1356 .id = WSA_MACRO_AIF1_PB,
1357 .playback = {
1358 .stream_name = "WSA_AIF1 Playback",
1359 .rates = WSA_MACRO_RX_RATES,
1360 .formats = WSA_MACRO_RX_FORMATS,
1361 .rate_max = 384000,
1362 .rate_min = 8000,
1363 .channels_min = 1,
1364 .channels_max = 2,
1365 },
1366 .ops = &wsa_macro_dai_ops,
1367 },
1368 {
1369 .name = "wsa_macro_rx_mix",
1370 .id = WSA_MACRO_AIF_MIX1_PB,
1371 .playback = {
1372 .stream_name = "WSA_AIF_MIX1 Playback",
1373 .rates = WSA_MACRO_RX_MIX_RATES,
1374 .formats = WSA_MACRO_RX_FORMATS,
1375 .rate_max = 192000,
1376 .rate_min = 48000,
1377 .channels_min = 1,
1378 .channels_max = 2,
1379 },
1380 .ops = &wsa_macro_dai_ops,
1381 },
1382 {
1383 .name = "wsa_macro_vifeedback",
1384 .id = WSA_MACRO_AIF_VI,
1385 .capture = {
1386 .stream_name = "WSA_AIF_VI Capture",
1387 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
1388 .formats = WSA_MACRO_RX_FORMATS,
1389 .rate_max = 48000,
1390 .rate_min = 8000,
1391 .channels_min = 1,
1392 .channels_max = 4,
1393 },
1394 .ops = &wsa_macro_dai_ops,
1395 },
1396 {
1397 .name = "wsa_macro_echo",
1398 .id = WSA_MACRO_AIF_ECHO,
1399 .capture = {
1400 .stream_name = "WSA_AIF_ECHO Capture",
1401 .rates = WSA_MACRO_ECHO_RATES,
1402 .formats = WSA_MACRO_ECHO_FORMATS,
1403 .rate_max = 48000,
1404 .rate_min = 8000,
1405 .channels_min = 1,
1406 .channels_max = 2,
1407 },
1408 .ops = &wsa_macro_dai_ops,
1409 },
1410 };
1411
wsa_macro_mclk_enable(struct wsa_macro * wsa,bool mclk_enable)1412 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
1413 {
1414 struct regmap *regmap = wsa->regmap;
1415
1416 if (mclk_enable) {
1417 if (wsa->wsa_mclk_users == 0) {
1418 regcache_mark_dirty(regmap);
1419 regcache_sync(regmap);
1420 /* 9.6MHz MCLK, set value 0x00 if other frequency */
1421 regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01);
1422 regmap_update_bits(regmap,
1423 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1424 CDC_WSA_MCLK_EN_MASK,
1425 CDC_WSA_MCLK_ENABLE);
1426 regmap_update_bits(regmap,
1427 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1428 CDC_WSA_FS_CNT_EN_MASK,
1429 CDC_WSA_FS_CNT_ENABLE);
1430 }
1431 wsa->wsa_mclk_users++;
1432 } else {
1433 if (wsa->wsa_mclk_users <= 0) {
1434 dev_err(wsa->dev, "clock already disabled\n");
1435 wsa->wsa_mclk_users = 0;
1436 return;
1437 }
1438 wsa->wsa_mclk_users--;
1439 if (wsa->wsa_mclk_users == 0) {
1440 regmap_update_bits(regmap,
1441 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1442 CDC_WSA_FS_CNT_EN_MASK,
1443 CDC_WSA_FS_CNT_DISABLE);
1444 regmap_update_bits(regmap,
1445 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1446 CDC_WSA_MCLK_EN_MASK,
1447 CDC_WSA_MCLK_DISABLE);
1448 }
1449 }
1450 }
1451
wsa_macro_enable_disable_vi_sense(struct snd_soc_component * component,bool enable,u32 tx_reg0,u32 tx_reg1,u32 val)1452 static void wsa_macro_enable_disable_vi_sense(struct snd_soc_component *component, bool enable,
1453 u32 tx_reg0, u32 tx_reg1, u32 val)
1454 {
1455 if (enable) {
1456 /* Enable V&I sensing */
1457 snd_soc_component_update_bits(component, tx_reg0,
1458 CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1459 CDC_WSA_TX_SPKR_PROT_RESET);
1460 snd_soc_component_update_bits(component, tx_reg1,
1461 CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1462 CDC_WSA_TX_SPKR_PROT_RESET);
1463 snd_soc_component_update_bits(component, tx_reg0,
1464 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1465 val);
1466 snd_soc_component_update_bits(component, tx_reg1,
1467 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1468 val);
1469 snd_soc_component_update_bits(component, tx_reg0,
1470 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1471 CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1472 snd_soc_component_update_bits(component, tx_reg1,
1473 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1474 CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1475 snd_soc_component_update_bits(component, tx_reg0,
1476 CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1477 CDC_WSA_TX_SPKR_PROT_NO_RESET);
1478 snd_soc_component_update_bits(component, tx_reg1,
1479 CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1480 CDC_WSA_TX_SPKR_PROT_NO_RESET);
1481 } else {
1482 snd_soc_component_update_bits(component, tx_reg0,
1483 CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1484 CDC_WSA_TX_SPKR_PROT_RESET);
1485 snd_soc_component_update_bits(component, tx_reg1,
1486 CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1487 CDC_WSA_TX_SPKR_PROT_RESET);
1488 snd_soc_component_update_bits(component, tx_reg0,
1489 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1490 CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1491 snd_soc_component_update_bits(component, tx_reg1,
1492 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1493 CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1494 }
1495 }
1496
wsa_macro_enable_disable_vi_feedback(struct snd_soc_component * component,bool enable,u32 rate)1497 static void wsa_macro_enable_disable_vi_feedback(struct snd_soc_component *component,
1498 bool enable, u32 rate)
1499 {
1500 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1501
1502 if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1503 wsa_macro_enable_disable_vi_sense(component, enable,
1504 CDC_WSA_TX0_SPKR_PROT_PATH_CTL,
1505 CDC_WSA_TX1_SPKR_PROT_PATH_CTL, rate);
1506
1507 if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1508 wsa_macro_enable_disable_vi_sense(component, enable,
1509 CDC_WSA_TX2_SPKR_PROT_PATH_CTL,
1510 CDC_WSA_TX3_SPKR_PROT_PATH_CTL, rate);
1511 }
1512
wsa_macro_mclk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1513 static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
1514 struct snd_kcontrol *kcontrol, int event)
1515 {
1516 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1517 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1518
1519 wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
1520 return 0;
1521 }
1522
wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1523 static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
1524 struct snd_kcontrol *kcontrol,
1525 int event)
1526 {
1527 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1528 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1529 u32 rate_val;
1530
1531 switch (wsa->pcm_rate_vi) {
1532 case 8000:
1533 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K;
1534 break;
1535 case 16000:
1536 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K;
1537 break;
1538 case 24000:
1539 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K;
1540 break;
1541 case 32000:
1542 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K;
1543 break;
1544 case 48000:
1545 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K;
1546 break;
1547 default:
1548 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K;
1549 break;
1550 }
1551
1552 switch (event) {
1553 case SND_SOC_DAPM_POST_PMU:
1554 /* Enable V&I sensing */
1555 wsa_macro_enable_disable_vi_feedback(component, true, rate_val);
1556 break;
1557 case SND_SOC_DAPM_POST_PMD:
1558 /* Disable V&I sensing */
1559 wsa_macro_enable_disable_vi_feedback(component, false, rate_val);
1560 break;
1561 }
1562
1563 return 0;
1564 }
1565
wsa_macro_hd2_control(struct snd_soc_component * component,u16 reg,int event)1566 static void wsa_macro_hd2_control(struct snd_soc_component *component,
1567 u16 reg, int event)
1568 {
1569 u16 hd2_scale_reg;
1570 u16 hd2_enable_reg;
1571
1572 if (reg == CDC_WSA_RX0_RX_PATH_CTL) {
1573 hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3;
1574 hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0;
1575 }
1576 if (reg == CDC_WSA_RX1_RX_PATH_CTL) {
1577 hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3;
1578 hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0;
1579 }
1580
1581 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
1582 snd_soc_component_update_bits(component, hd2_scale_reg,
1583 CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1584 0x10);
1585 snd_soc_component_update_bits(component, hd2_scale_reg,
1586 CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1587 0x1);
1588 snd_soc_component_update_bits(component, hd2_enable_reg,
1589 CDC_WSA_RX_PATH_HD2_EN_MASK,
1590 CDC_WSA_RX_PATH_HD2_ENABLE);
1591 }
1592
1593 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
1594 snd_soc_component_update_bits(component, hd2_enable_reg,
1595 CDC_WSA_RX_PATH_HD2_EN_MASK, 0);
1596 snd_soc_component_update_bits(component, hd2_scale_reg,
1597 CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1598 0);
1599 snd_soc_component_update_bits(component, hd2_scale_reg,
1600 CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1601 0);
1602 }
1603 }
1604
wsa_macro_config_compander(struct snd_soc_component * component,int comp,int event)1605 static int wsa_macro_config_compander(struct snd_soc_component *component,
1606 int comp, int event)
1607 {
1608 u16 comp_ctl0_reg, rx_path_cfg0_reg;
1609 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1610
1611 if (!wsa->comp_enabled[comp])
1612 return 0;
1613
1614 comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 +
1615 (comp * wsa->reg_layout->compander1_reg_offset);
1616 rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 +
1617 (comp * WSA_MACRO_RX_PATH_OFFSET);
1618
1619 if (SND_SOC_DAPM_EVENT_ON(event)) {
1620 /* Enable Compander Clock */
1621 snd_soc_component_update_bits(component, comp_ctl0_reg,
1622 CDC_WSA_COMPANDER_CLK_EN_MASK,
1623 CDC_WSA_COMPANDER_CLK_ENABLE);
1624 snd_soc_component_update_bits(component, comp_ctl0_reg,
1625 CDC_WSA_COMPANDER_SOFT_RST_MASK,
1626 CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1627 snd_soc_component_update_bits(component, comp_ctl0_reg,
1628 CDC_WSA_COMPANDER_SOFT_RST_MASK,
1629 0);
1630 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1631 CDC_WSA_RX_PATH_COMP_EN_MASK,
1632 CDC_WSA_RX_PATH_COMP_ENABLE);
1633 }
1634
1635 if (SND_SOC_DAPM_EVENT_OFF(event)) {
1636 snd_soc_component_update_bits(component, comp_ctl0_reg,
1637 CDC_WSA_COMPANDER_HALT_MASK,
1638 CDC_WSA_COMPANDER_HALT);
1639 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1640 CDC_WSA_RX_PATH_COMP_EN_MASK, 0);
1641 snd_soc_component_update_bits(component, comp_ctl0_reg,
1642 CDC_WSA_COMPANDER_SOFT_RST_MASK,
1643 CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1644 snd_soc_component_update_bits(component, comp_ctl0_reg,
1645 CDC_WSA_COMPANDER_SOFT_RST_MASK,
1646 0);
1647 snd_soc_component_update_bits(component, comp_ctl0_reg,
1648 CDC_WSA_COMPANDER_CLK_EN_MASK, 0);
1649 snd_soc_component_update_bits(component, comp_ctl0_reg,
1650 CDC_WSA_COMPANDER_HALT_MASK, 0);
1651 }
1652
1653 return 0;
1654 }
1655
wsa_macro_enable_softclip_clk(struct snd_soc_component * component,struct wsa_macro * wsa,int path,bool enable)1656 static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component,
1657 struct wsa_macro *wsa,
1658 int path,
1659 bool enable)
1660 {
1661 u16 softclip_clk_reg = wsa->reg_layout->softclip0_reg_base +
1662 (path * wsa->reg_layout->softclip1_reg_offset);
1663 u8 softclip_mux_mask = (1 << path);
1664 u8 softclip_mux_value = (1 << path);
1665
1666 if (enable) {
1667 if (wsa->softclip_clk_users[path] == 0) {
1668 snd_soc_component_update_bits(component,
1669 softclip_clk_reg,
1670 CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1671 CDC_WSA_SOFTCLIP_CLK_ENABLE);
1672 snd_soc_component_update_bits(component,
1673 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1674 softclip_mux_mask, softclip_mux_value);
1675 }
1676 wsa->softclip_clk_users[path]++;
1677 } else {
1678 wsa->softclip_clk_users[path]--;
1679 if (wsa->softclip_clk_users[path] == 0) {
1680 snd_soc_component_update_bits(component,
1681 softclip_clk_reg,
1682 CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1683 0);
1684 snd_soc_component_update_bits(component,
1685 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1686 softclip_mux_mask, 0x00);
1687 }
1688 }
1689 }
1690
wsa_macro_config_softclip(struct snd_soc_component * component,int path,int event)1691 static int wsa_macro_config_softclip(struct snd_soc_component *component,
1692 int path, int event)
1693 {
1694 u16 softclip_ctrl_reg;
1695 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1696 int softclip_path = 0;
1697
1698 if (path == WSA_MACRO_COMP1)
1699 softclip_path = WSA_MACRO_SOFTCLIP0;
1700 else if (path == WSA_MACRO_COMP2)
1701 softclip_path = WSA_MACRO_SOFTCLIP1;
1702
1703 if (!wsa->is_softclip_on[softclip_path])
1704 return 0;
1705
1706 softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL +
1707 (softclip_path * wsa->reg_layout->softclip1_reg_offset);
1708
1709 if (SND_SOC_DAPM_EVENT_ON(event)) {
1710 /* Enable Softclip clock and mux */
1711 wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1712 true);
1713 /* Enable Softclip control */
1714 snd_soc_component_update_bits(component, softclip_ctrl_reg,
1715 CDC_WSA_SOFTCLIP_EN_MASK,
1716 CDC_WSA_SOFTCLIP_ENABLE);
1717 }
1718
1719 if (SND_SOC_DAPM_EVENT_OFF(event)) {
1720 snd_soc_component_update_bits(component, softclip_ctrl_reg,
1721 CDC_WSA_SOFTCLIP_EN_MASK, 0);
1722 wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1723 false);
1724 }
1725
1726 return 0;
1727 }
1728
wsa_macro_interp_get_primary_reg(u16 reg,u16 * ind)1729 static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind)
1730 {
1731 u16 prim_int_reg = 0;
1732
1733 switch (reg) {
1734 case CDC_WSA_RX0_RX_PATH_CTL:
1735 case CDC_WSA_RX0_RX_PATH_MIX_CTL:
1736 prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL;
1737 *ind = 0;
1738 break;
1739 case CDC_WSA_RX1_RX_PATH_CTL:
1740 case CDC_WSA_RX1_RX_PATH_MIX_CTL:
1741 prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL;
1742 *ind = 1;
1743 break;
1744 }
1745
1746 return prim_int_reg;
1747 }
1748
wsa_macro_enable_prim_interpolator(struct snd_soc_component * component,u16 reg,int event)1749 static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component,
1750 u16 reg, int event)
1751 {
1752 u16 prim_int_reg;
1753 u16 ind = 0;
1754 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1755
1756 prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind);
1757
1758 switch (event) {
1759 case SND_SOC_DAPM_PRE_PMU:
1760 wsa->prim_int_users[ind]++;
1761 if (wsa->prim_int_users[ind] == 1) {
1762 snd_soc_component_update_bits(component,
1763 prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET,
1764 CDC_WSA_RX_DC_DCOEFF_MASK,
1765 0x3);
1766 snd_soc_component_update_bits(component, prim_int_reg,
1767 CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK,
1768 CDC_WSA_RX_PATH_PGA_MUTE_ENABLE);
1769 wsa_macro_hd2_control(component, prim_int_reg, event);
1770 snd_soc_component_update_bits(component,
1771 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1772 CDC_WSA_RX_DSMDEM_CLK_EN_MASK,
1773 CDC_WSA_RX_DSMDEM_CLK_ENABLE);
1774 }
1775 if ((reg != prim_int_reg) &&
1776 ((snd_soc_component_read(
1777 component, prim_int_reg)) & 0x10))
1778 snd_soc_component_update_bits(component, reg,
1779 0x10, 0x10);
1780 break;
1781 case SND_SOC_DAPM_POST_PMD:
1782 wsa->prim_int_users[ind]--;
1783 if (wsa->prim_int_users[ind] == 0) {
1784 snd_soc_component_update_bits(component,
1785 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1786 CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0);
1787 wsa_macro_hd2_control(component, prim_int_reg, event);
1788 }
1789 break;
1790 }
1791
1792 return 0;
1793 }
1794
wsa_macro_config_ear_spkr_gain(struct snd_soc_component * component,struct wsa_macro * wsa,int event,int gain_reg)1795 static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
1796 struct wsa_macro *wsa,
1797 int event, int gain_reg)
1798 {
1799 int comp_gain_offset, val;
1800
1801 switch (wsa->spkr_mode) {
1802 /* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */
1803 case WSA_MACRO_SPKR_MODE_1:
1804 comp_gain_offset = -12;
1805 break;
1806 /* Default case compander gain is 15 dB */
1807 default:
1808 comp_gain_offset = -15;
1809 break;
1810 }
1811
1812 switch (event) {
1813 case SND_SOC_DAPM_POST_PMU:
1814 /* Apply ear spkr gain only if compander is enabled */
1815 if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1816 (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1817 (wsa->ear_spkr_gain != 0)) {
1818 /* For example, val is -8(-12+5-1) for 4dB of gain */
1819 val = comp_gain_offset + wsa->ear_spkr_gain - 1;
1820 snd_soc_component_write(component, gain_reg, val);
1821 }
1822 break;
1823 case SND_SOC_DAPM_POST_PMD:
1824 /*
1825 * Reset RX0 volume to 0 dB if compander is enabled and
1826 * ear_spkr_gain is non-zero.
1827 */
1828 if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1829 (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1830 (wsa->ear_spkr_gain != 0)) {
1831 snd_soc_component_write(component, gain_reg, 0x0);
1832 }
1833 break;
1834 }
1835
1836 return 0;
1837 }
1838
wsa_macro_enable_interpolator(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1839 static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w,
1840 struct snd_kcontrol *kcontrol,
1841 int event)
1842 {
1843 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1844 u16 gain_reg;
1845 u16 reg;
1846 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1847
1848 if (w->shift == WSA_MACRO_COMP1) {
1849 reg = CDC_WSA_RX0_RX_PATH_CTL;
1850 gain_reg = CDC_WSA_RX0_RX_VOL_CTL;
1851 } else if (w->shift == WSA_MACRO_COMP2) {
1852 reg = CDC_WSA_RX1_RX_PATH_CTL;
1853 gain_reg = CDC_WSA_RX1_RX_VOL_CTL;
1854 }
1855
1856 switch (event) {
1857 case SND_SOC_DAPM_PRE_PMU:
1858 /* Reset if needed */
1859 wsa_macro_enable_prim_interpolator(component, reg, event);
1860 break;
1861 case SND_SOC_DAPM_POST_PMU:
1862 wsa_macro_config_compander(component, w->shift, event);
1863 wsa_macro_config_softclip(component, w->shift, event);
1864 /* apply gain after int clk is enabled */
1865 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1866 (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1867 wsa->comp_enabled[WSA_MACRO_COMP2])) {
1868 snd_soc_component_update_bits(component,
1869 CDC_WSA_RX0_RX_PATH_SEC1,
1870 CDC_WSA_RX_PGA_HALF_DB_MASK,
1871 CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1872 snd_soc_component_update_bits(component,
1873 CDC_WSA_RX0_RX_PATH_MIX_SEC0,
1874 CDC_WSA_RX_PGA_HALF_DB_MASK,
1875 CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1876 snd_soc_component_update_bits(component,
1877 CDC_WSA_RX1_RX_PATH_SEC1,
1878 CDC_WSA_RX_PGA_HALF_DB_MASK,
1879 CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1880 snd_soc_component_update_bits(component,
1881 CDC_WSA_RX1_RX_PATH_MIX_SEC0,
1882 CDC_WSA_RX_PGA_HALF_DB_MASK,
1883 CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1884 }
1885 wsa_macro_config_ear_spkr_gain(component, wsa,
1886 event, gain_reg);
1887 break;
1888 case SND_SOC_DAPM_POST_PMD:
1889 wsa_macro_config_compander(component, w->shift, event);
1890 wsa_macro_config_softclip(component, w->shift, event);
1891 wsa_macro_enable_prim_interpolator(component, reg, event);
1892 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1893 (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1894 wsa->comp_enabled[WSA_MACRO_COMP2])) {
1895 snd_soc_component_update_bits(component,
1896 CDC_WSA_RX0_RX_PATH_SEC1,
1897 CDC_WSA_RX_PGA_HALF_DB_MASK,
1898 CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1899 snd_soc_component_update_bits(component,
1900 CDC_WSA_RX0_RX_PATH_MIX_SEC0,
1901 CDC_WSA_RX_PGA_HALF_DB_MASK,
1902 CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1903 snd_soc_component_update_bits(component,
1904 CDC_WSA_RX1_RX_PATH_SEC1,
1905 CDC_WSA_RX_PGA_HALF_DB_MASK,
1906 CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1907 snd_soc_component_update_bits(component,
1908 CDC_WSA_RX1_RX_PATH_MIX_SEC0,
1909 CDC_WSA_RX_PGA_HALF_DB_MASK,
1910 CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1911 }
1912 wsa_macro_config_ear_spkr_gain(component, wsa,
1913 event, gain_reg);
1914 break;
1915 }
1916
1917 return 0;
1918 }
1919
wsa_macro_spk_boost_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1920 static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
1921 struct snd_kcontrol *kcontrol,
1922 int event)
1923 {
1924 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1925 u16 boost_path_ctl, boost_path_cfg1;
1926 u16 reg, reg_mix;
1927
1928 if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT0 CHAIN")) {
1929 boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL;
1930 boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1;
1931 reg = CDC_WSA_RX0_RX_PATH_CTL;
1932 reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL;
1933 } else if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT1 CHAIN")) {
1934 boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL;
1935 boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1;
1936 reg = CDC_WSA_RX1_RX_PATH_CTL;
1937 reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL;
1938 } else {
1939 dev_warn(component->dev, "Incorrect widget name in the driver\n");
1940 return -EINVAL;
1941 }
1942
1943 switch (event) {
1944 case SND_SOC_DAPM_PRE_PMU:
1945 snd_soc_component_update_bits(component, boost_path_cfg1,
1946 CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
1947 CDC_WSA_RX_PATH_SMART_BST_ENABLE);
1948 snd_soc_component_update_bits(component, boost_path_ctl,
1949 CDC_WSA_BOOST_PATH_CLK_EN_MASK,
1950 CDC_WSA_BOOST_PATH_CLK_ENABLE);
1951 if ((snd_soc_component_read(component, reg_mix)) & 0x10)
1952 snd_soc_component_update_bits(component, reg_mix,
1953 0x10, 0x00);
1954 break;
1955 case SND_SOC_DAPM_POST_PMU:
1956 snd_soc_component_update_bits(component, reg, 0x10, 0x00);
1957 break;
1958 case SND_SOC_DAPM_POST_PMD:
1959 snd_soc_component_update_bits(component, boost_path_ctl,
1960 CDC_WSA_BOOST_PATH_CLK_EN_MASK,
1961 CDC_WSA_BOOST_PATH_CLK_DISABLE);
1962 snd_soc_component_update_bits(component, boost_path_cfg1,
1963 CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
1964 CDC_WSA_RX_PATH_SMART_BST_DISABLE);
1965 break;
1966 }
1967
1968 return 0;
1969 }
1970
wsa_macro_enable_echo(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1971 static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w,
1972 struct snd_kcontrol *kcontrol,
1973 int event)
1974 {
1975 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1976 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1977 u16 val, ec_tx, ec_hq_reg;
1978
1979 val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
1980
1981 switch (w->shift) {
1982 case WSA_MACRO_EC0_MUX:
1983 val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK;
1984 ec_tx = val - 1;
1985 break;
1986 case WSA_MACRO_EC1_MUX:
1987 val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK;
1988 ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1;
1989 break;
1990 default:
1991 dev_err(component->dev, "%s: Invalid shift %u\n",
1992 __func__, w->shift);
1993 return -EINVAL;
1994 }
1995
1996 if (wsa->ec_hq[ec_tx]) {
1997 ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + 0x40 * ec_tx;
1998 snd_soc_component_update_bits(component, ec_hq_reg,
1999 CDC_WSA_EC_HQ_EC_CLK_EN_MASK,
2000 CDC_WSA_EC_HQ_EC_CLK_ENABLE);
2001 ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx;
2002 /* default set to 48k */
2003 snd_soc_component_update_bits(component, ec_hq_reg,
2004 CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK,
2005 CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K);
2006 }
2007
2008 return 0;
2009 }
2010
wsa_macro_get_ec_hq(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2011 static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol,
2012 struct snd_ctl_elem_value *ucontrol)
2013 {
2014
2015 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2016 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2017 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2018
2019 ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx];
2020
2021 return 0;
2022 }
2023
wsa_macro_set_ec_hq(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2024 static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol,
2025 struct snd_ctl_elem_value *ucontrol)
2026 {
2027 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2028 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2029 int value = ucontrol->value.integer.value[0];
2030 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2031
2032 wsa->ec_hq[ec_tx] = value;
2033
2034 return 0;
2035 }
2036
wsa_macro_get_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2037 static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol,
2038 struct snd_ctl_elem_value *ucontrol)
2039 {
2040
2041 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2042 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2043 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2044
2045 ucontrol->value.integer.value[0] = wsa->comp_enabled[comp];
2046 return 0;
2047 }
2048
wsa_macro_set_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2049 static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol,
2050 struct snd_ctl_elem_value *ucontrol)
2051 {
2052 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2053 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2054 int value = ucontrol->value.integer.value[0];
2055 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2056
2057 wsa->comp_enabled[comp] = value;
2058
2059 return 0;
2060 }
2061
wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2062 static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol,
2063 struct snd_ctl_elem_value *ucontrol)
2064 {
2065 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2066 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2067
2068 ucontrol->value.enumerated.item[0] = wsa->ear_spkr_gain;
2069
2070 return 0;
2071 }
2072
wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2073 static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol,
2074 struct snd_ctl_elem_value *ucontrol)
2075 {
2076 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2077 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2078
2079 wsa->ear_spkr_gain = ucontrol->value.enumerated.item[0];
2080
2081 return 0;
2082 }
2083
wsa_macro_rx_mux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2084 static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol,
2085 struct snd_ctl_elem_value *ucontrol)
2086 {
2087 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
2088 struct snd_soc_component *component =
2089 snd_soc_dapm_to_component(widget->dapm);
2090 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2091
2092 ucontrol->value.enumerated.item[0] =
2093 wsa->rx_port_value[widget->shift];
2094 return 0;
2095 }
2096
wsa_macro_rx_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2097 static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol,
2098 struct snd_ctl_elem_value *ucontrol)
2099 {
2100 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
2101 struct snd_soc_component *component =
2102 snd_soc_dapm_to_component(widget->dapm);
2103 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2104 struct snd_soc_dapm_update *update = NULL;
2105 u32 rx_port_value = ucontrol->value.enumerated.item[0];
2106 u32 bit_input;
2107 u32 aif_rst;
2108 unsigned int dai_id;
2109 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2110
2111 aif_rst = wsa->rx_port_value[widget->shift];
2112 if (!rx_port_value) {
2113 if (aif_rst == 0)
2114 return 0;
2115 if (aif_rst >= WSA_MACRO_RX_MAX) {
2116 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
2117 return 0;
2118 }
2119 }
2120 wsa->rx_port_value[widget->shift] = rx_port_value;
2121
2122 bit_input = widget->shift;
2123
2124 switch (rx_port_value) {
2125 case 0:
2126 /*
2127 * active_ch_cnt and active_ch_mask use DAI IDs (WSA_MACRO_MAX_DAIS).
2128 * active_ch_cnt == 0 was tested in if() above.
2129 */
2130 dai_id = aif_rst - 1;
2131 if (wsa->active_ch_cnt[dai_id]) {
2132 clear_bit(bit_input, &wsa->active_ch_mask[dai_id]);
2133 wsa->active_ch_cnt[dai_id]--;
2134 }
2135 break;
2136 case 1:
2137 case 2:
2138 /* active_ch_cnt and active_ch_mask use DAI IDs (WSA_MACRO_MAX_DAIS). */
2139 dai_id = rx_port_value - 1;
2140 set_bit(bit_input, &wsa->active_ch_mask[dai_id]);
2141 wsa->active_ch_cnt[dai_id]++;
2142 break;
2143 default:
2144 dev_err(component->dev,
2145 "%s: Invalid AIF_ID for WSA RX MUX %d\n",
2146 __func__, rx_port_value);
2147 return -EINVAL;
2148 }
2149
2150 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
2151 rx_port_value, e, update);
2152 return 0;
2153 }
2154
wsa_macro_soft_clip_enable_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2155 static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
2156 struct snd_ctl_elem_value *ucontrol)
2157 {
2158 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2159 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2160 int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift;
2161
2162 ucontrol->value.integer.value[0] = wsa->is_softclip_on[path];
2163
2164 return 0;
2165 }
2166
wsa_macro_soft_clip_enable_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2167 static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
2168 struct snd_ctl_elem_value *ucontrol)
2169 {
2170 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2171 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2172 int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2173
2174 wsa->is_softclip_on[path] = ucontrol->value.integer.value[0];
2175
2176 return 0;
2177 }
2178
2179 static const struct snd_kcontrol_new wsa_macro_snd_controls[] = {
2180 SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum,
2181 wsa_macro_ear_spkr_pa_gain_get,
2182 wsa_macro_ear_spkr_pa_gain_put),
2183 SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM,
2184 WSA_MACRO_SOFTCLIP0, 1, 0,
2185 wsa_macro_soft_clip_enable_get,
2186 wsa_macro_soft_clip_enable_put),
2187 SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM,
2188 WSA_MACRO_SOFTCLIP1, 1, 0,
2189 wsa_macro_soft_clip_enable_get,
2190 wsa_macro_soft_clip_enable_put),
2191
2192 SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL,
2193 -84, 40, digital_gain),
2194 SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL,
2195 -84, 40, digital_gain),
2196 SOC_SINGLE_S8_TLV("WSA_RX0_MIX Digital Volume", CDC_WSA_RX0_RX_VOL_MIX_CTL,
2197 -84, 40, digital_gain),
2198 SOC_SINGLE_S8_TLV("WSA_RX1_MIX Digital Volume", CDC_WSA_RX1_RX_VOL_MIX_CTL,
2199 -84, 40, digital_gain),
2200
2201 SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0),
2202 SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0),
2203 SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4,
2204 1, 0),
2205 SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4,
2206 1, 0),
2207 SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0,
2208 wsa_macro_get_compander, wsa_macro_set_compander),
2209 SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0,
2210 wsa_macro_get_compander, wsa_macro_set_compander),
2211 SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0,
2212 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
2213 SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0,
2214 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
2215 };
2216
2217 static const struct soc_enum rx_mux_enum =
2218 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text);
2219
2220 static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = {
2221 SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum,
2222 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2223 SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum,
2224 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2225 SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum,
2226 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2227 SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum,
2228 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2229 };
2230
wsa_macro_vi_feed_mixer_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2231 static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
2232 struct snd_ctl_elem_value *ucontrol)
2233 {
2234 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
2235 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2236 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2237 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2238 u32 spk_tx_id = mixer->shift;
2239 u32 dai_id = widget->shift;
2240
2241 if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id]))
2242 ucontrol->value.integer.value[0] = 1;
2243 else
2244 ucontrol->value.integer.value[0] = 0;
2245
2246 return 0;
2247 }
2248
wsa_macro_vi_feed_mixer_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2249 static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
2250 struct snd_ctl_elem_value *ucontrol)
2251 {
2252 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
2253 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2254 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2255 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2256 u32 enable = ucontrol->value.integer.value[0];
2257 u32 spk_tx_id = mixer->shift;
2258 u32 dai_id = widget->shift;
2259
2260 if (enable) {
2261 if (spk_tx_id == WSA_MACRO_TX0 &&
2262 !test_bit(WSA_MACRO_TX0,
2263 &wsa->active_ch_mask[dai_id])) {
2264 set_bit(WSA_MACRO_TX0,
2265 &wsa->active_ch_mask[dai_id]);
2266 wsa->active_ch_cnt[dai_id]++;
2267 }
2268 if (spk_tx_id == WSA_MACRO_TX1 &&
2269 !test_bit(WSA_MACRO_TX1,
2270 &wsa->active_ch_mask[dai_id])) {
2271 set_bit(WSA_MACRO_TX1,
2272 &wsa->active_ch_mask[dai_id]);
2273 wsa->active_ch_cnt[dai_id]++;
2274 }
2275 } else {
2276 if (spk_tx_id == WSA_MACRO_TX0 &&
2277 test_bit(WSA_MACRO_TX0,
2278 &wsa->active_ch_mask[dai_id])) {
2279 clear_bit(WSA_MACRO_TX0,
2280 &wsa->active_ch_mask[dai_id]);
2281 wsa->active_ch_cnt[dai_id]--;
2282 }
2283 if (spk_tx_id == WSA_MACRO_TX1 &&
2284 test_bit(WSA_MACRO_TX1,
2285 &wsa->active_ch_mask[dai_id])) {
2286 clear_bit(WSA_MACRO_TX1,
2287 &wsa->active_ch_mask[dai_id]);
2288 wsa->active_ch_cnt[dai_id]--;
2289 }
2290 }
2291 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
2292
2293 return 0;
2294 }
2295
2296 static const struct snd_kcontrol_new aif_vi_mixer[] = {
2297 SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0,
2298 wsa_macro_vi_feed_mixer_get,
2299 wsa_macro_vi_feed_mixer_put),
2300 SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0,
2301 wsa_macro_vi_feed_mixer_get,
2302 wsa_macro_vi_feed_mixer_put),
2303 };
2304
2305 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = {
2306 SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0,
2307 SND_SOC_NOPM, 0, 0),
2308 SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0,
2309 SND_SOC_NOPM, 0, 0),
2310
2311 SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0,
2312 SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0,
2313 wsa_macro_enable_vi_feedback,
2314 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2315 SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0,
2316 SND_SOC_NOPM, 0, 0),
2317
2318 SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI,
2319 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)),
2320 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM,
2321 WSA_MACRO_EC0_MUX, 0,
2322 &rx_mix_ec0_mux, wsa_macro_enable_echo,
2323 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2324 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM,
2325 WSA_MACRO_EC1_MUX, 0,
2326 &rx_mix_ec1_mux, wsa_macro_enable_echo,
2327 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2328
2329 SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0,
2330 &rx_mux[WSA_MACRO_RX0]),
2331 SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0,
2332 &rx_mux[WSA_MACRO_RX1]),
2333 SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0,
2334 &rx_mux[WSA_MACRO_RX_MIX0]),
2335 SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0,
2336 &rx_mux[WSA_MACRO_RX_MIX1]),
2337
2338 SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2339 SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2340 SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2341 SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2342
2343 SND_SOC_DAPM_MIXER("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2344 SND_SOC_DAPM_MIXER("WSA_RX INT1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2345
2346 SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2347 SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2348
2349 SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1,
2350 4, 0, &rx0_sidetone_mix_mux),
2351
2352 SND_SOC_DAPM_INPUT("WSA SRC0_INP"),
2353 SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"),
2354 SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"),
2355
2356 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM,
2357 WSA_MACRO_COMP1, 0, NULL, 0,
2358 wsa_macro_enable_interpolator,
2359 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2360 SND_SOC_DAPM_POST_PMD),
2361
2362 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM,
2363 WSA_MACRO_COMP2, 0, NULL, 0,
2364 wsa_macro_enable_interpolator,
2365 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2366 SND_SOC_DAPM_POST_PMD),
2367
2368 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0,
2369 NULL, 0, wsa_macro_spk_boost_event,
2370 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2371 SND_SOC_DAPM_POST_PMD),
2372
2373 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0,
2374 NULL, 0, wsa_macro_spk_boost_event,
2375 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2376 SND_SOC_DAPM_POST_PMD),
2377
2378 SND_SOC_DAPM_INPUT("VIINPUT_WSA"),
2379 SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"),
2380 SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"),
2381
2382 SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0),
2383 SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0),
2384 SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2385 SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2386 SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0,
2387 wsa_macro_mclk_event,
2388 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2389 };
2390
2391 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets_v2_1[] = {
2392 SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux_v2_1),
2393 SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux_v2_1),
2394 SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux_v2_1),
2395 SND_SOC_DAPM_MUX("WSA_RX0 MIX INP", SND_SOC_NOPM, 0, 0, &rx0_mix_mux_v2_1),
2396 SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux_v2_1),
2397 SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux_v2_1),
2398 SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux_v2_1),
2399 SND_SOC_DAPM_MUX("WSA_RX1 MIX INP", SND_SOC_NOPM, 0, 0, &rx1_mix_mux_v2_1),
2400 };
2401
2402 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets_v2_5[] = {
2403 SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux_v2_5),
2404 SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux_v2_5),
2405 SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux_v2_5),
2406 SND_SOC_DAPM_MUX("WSA_RX0 MIX INP", SND_SOC_NOPM, 0, 0, &rx0_mix_mux_v2_5),
2407 SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux_v2_5),
2408 SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux_v2_5),
2409 SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux_v2_5),
2410 SND_SOC_DAPM_MUX("WSA_RX1 MIX INP", SND_SOC_NOPM, 0, 0, &rx1_mix_mux_v2_5),
2411 };
2412
2413 static const struct snd_soc_dapm_route wsa_audio_map[] = {
2414 /* VI Feedback */
2415 {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"},
2416 {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"},
2417 {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"},
2418 {"WSA AIF_VI", NULL, "WSA_MCLK"},
2419
2420 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2421 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2422 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2423 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2424 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"},
2425 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"},
2426 {"WSA AIF_ECHO", NULL, "WSA_MCLK"},
2427
2428 {"WSA AIF1 PB", NULL, "WSA_MCLK"},
2429 {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"},
2430
2431 {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2432 {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2433 {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2434 {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2435
2436 {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2437 {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2438 {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2439 {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2440
2441 {"WSA RX0", NULL, "WSA RX0 MUX"},
2442 {"WSA RX1", NULL, "WSA RX1 MUX"},
2443 {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"},
2444 {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"},
2445
2446 {"WSA_RX INT0 MIX", NULL, "WSA_RX0_CLK"},
2447 {"WSA_RX INT1 MIX", NULL, "WSA_RX1_CLK"},
2448
2449 {"WSA_RX0 INP0", "RX0", "WSA RX0"},
2450 {"WSA_RX0 INP0", "RX1", "WSA RX1"},
2451 {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"},
2452 {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"},
2453 {"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"},
2454 {"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"},
2455 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"},
2456
2457 {"WSA_RX0 INP1", "RX0", "WSA RX0"},
2458 {"WSA_RX0 INP1", "RX1", "WSA RX1"},
2459 {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"},
2460 {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"},
2461 {"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"},
2462 {"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"},
2463 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"},
2464
2465 {"WSA_RX0 INP2", "RX0", "WSA RX0"},
2466 {"WSA_RX0 INP2", "RX1", "WSA RX1"},
2467 {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"},
2468 {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"},
2469 {"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"},
2470 {"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"},
2471 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"},
2472
2473 {"WSA_RX0 MIX INP", "RX0", "WSA RX0"},
2474 {"WSA_RX0 MIX INP", "RX1", "WSA RX1"},
2475 {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2476 {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2477 {"WSA_RX0 MIX INP", NULL, "WSA_RX0_CLK"},
2478 {"WSA_RX0 MIX INP", NULL, "WSA_RX_MIX0_CLK"},
2479 {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"},
2480
2481 {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"},
2482 {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"},
2483 {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"},
2484 {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"},
2485 {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"},
2486
2487 {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"},
2488 {"WSA_SPK1 OUT", NULL, "WSA_MCLK"},
2489
2490 {"WSA_RX1 INP0", "RX0", "WSA RX0"},
2491 {"WSA_RX1 INP0", "RX1", "WSA RX1"},
2492 {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"},
2493 {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"},
2494 {"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"},
2495 {"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"},
2496 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"},
2497
2498 {"WSA_RX1 INP1", "RX0", "WSA RX0"},
2499 {"WSA_RX1 INP1", "RX1", "WSA RX1"},
2500 {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"},
2501 {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"},
2502 {"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"},
2503 {"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"},
2504 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"},
2505
2506 {"WSA_RX1 INP2", "RX0", "WSA RX0"},
2507 {"WSA_RX1 INP2", "RX1", "WSA RX1"},
2508 {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"},
2509 {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"},
2510 {"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"},
2511 {"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"},
2512 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"},
2513
2514 {"WSA_RX1 MIX INP", "RX0", "WSA RX0"},
2515 {"WSA_RX1 MIX INP", "RX1", "WSA RX1"},
2516 {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2517 {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2518 {"WSA_RX1 MIX INP", NULL, "WSA_RX1_CLK"},
2519 {"WSA_RX1 MIX INP", NULL, "WSA_RX_MIX1_CLK"},
2520 {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"},
2521
2522 {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"},
2523 {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"},
2524
2525 {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"},
2526 {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"},
2527 {"WSA_SPK2 OUT", NULL, "WSA_MCLK"},
2528 };
2529
wsa_swrm_clock(struct wsa_macro * wsa,bool enable)2530 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
2531 {
2532 struct regmap *regmap = wsa->regmap;
2533 int ret;
2534
2535 if (enable) {
2536 ret = pm_runtime_resume_and_get(wsa->dev);
2537 if (ret < 0)
2538 return ret;
2539
2540 wsa_macro_mclk_enable(wsa, true);
2541
2542 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2543 CDC_WSA_SWR_CLK_EN_MASK,
2544 CDC_WSA_SWR_CLK_ENABLE);
2545
2546 } else {
2547 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2548 CDC_WSA_SWR_CLK_EN_MASK, 0);
2549 wsa_macro_mclk_enable(wsa, false);
2550
2551 ret = pm_runtime_put_autosuspend(wsa->dev);
2552 if (ret < 0)
2553 dev_warn(wsa->dev, "runtime PM put failed: %d\n", ret);
2554 }
2555
2556 return 0;
2557 }
2558
wsa_macro_component_probe(struct snd_soc_component * comp)2559 static int wsa_macro_component_probe(struct snd_soc_component *comp)
2560 {
2561 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(comp);
2562 struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);
2563 const struct snd_soc_dapm_widget *widgets;
2564 unsigned int num_widgets;
2565
2566 snd_soc_component_init_regmap(comp, wsa->regmap);
2567
2568 wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;
2569
2570 /* set SPKR rate to FS_2P4_3P072 */
2571 snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1,
2572 CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2573 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2574
2575 snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1,
2576 CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2577 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2578
2579 wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1);
2580
2581 switch (wsa->codec_version) {
2582 case LPASS_CODEC_VERSION_1_0:
2583 case LPASS_CODEC_VERSION_1_1:
2584 case LPASS_CODEC_VERSION_1_2:
2585 case LPASS_CODEC_VERSION_2_0:
2586 case LPASS_CODEC_VERSION_2_1:
2587 widgets = wsa_macro_dapm_widgets_v2_1;
2588 num_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets_v2_1);
2589 break;
2590 case LPASS_CODEC_VERSION_2_5:
2591 case LPASS_CODEC_VERSION_2_6:
2592 case LPASS_CODEC_VERSION_2_7:
2593 case LPASS_CODEC_VERSION_2_8:
2594 case LPASS_CODEC_VERSION_2_9:
2595 widgets = wsa_macro_dapm_widgets_v2_5;
2596 num_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets_v2_5);
2597 break;
2598 default:
2599 return -EINVAL;
2600 }
2601
2602 return snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
2603 }
2604
swclk_gate_enable(struct clk_hw * hw)2605 static int swclk_gate_enable(struct clk_hw *hw)
2606 {
2607 return wsa_swrm_clock(to_wsa_macro(hw), true);
2608 }
2609
swclk_gate_disable(struct clk_hw * hw)2610 static void swclk_gate_disable(struct clk_hw *hw)
2611 {
2612 wsa_swrm_clock(to_wsa_macro(hw), false);
2613 }
2614
swclk_gate_is_enabled(struct clk_hw * hw)2615 static int swclk_gate_is_enabled(struct clk_hw *hw)
2616 {
2617 struct wsa_macro *wsa = to_wsa_macro(hw);
2618 int ret, val;
2619
2620 regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val);
2621 ret = val & BIT(0);
2622
2623 return ret;
2624 }
2625
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2626 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2627 unsigned long parent_rate)
2628 {
2629 return parent_rate / 2;
2630 }
2631
2632 static const struct clk_ops swclk_gate_ops = {
2633 .prepare = swclk_gate_enable,
2634 .unprepare = swclk_gate_disable,
2635 .is_enabled = swclk_gate_is_enabled,
2636 .recalc_rate = swclk_recalc_rate,
2637 };
2638
wsa_macro_register_mclk_output(struct wsa_macro * wsa)2639 static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
2640 {
2641 struct device *dev = wsa->dev;
2642 const char *parent_clk_name;
2643 struct clk_hw *hw;
2644 struct clk_init_data init;
2645 int ret;
2646
2647 if (wsa->npl)
2648 parent_clk_name = __clk_get_name(wsa->npl);
2649 else
2650 parent_clk_name = __clk_get_name(wsa->mclk);
2651
2652 init.name = "mclk";
2653 of_property_read_string(dev_of_node(dev), "clock-output-names",
2654 &init.name);
2655 init.ops = &swclk_gate_ops;
2656 init.flags = 0;
2657 init.parent_names = &parent_clk_name;
2658 init.num_parents = 1;
2659 wsa->hw.init = &init;
2660 hw = &wsa->hw;
2661 ret = devm_clk_hw_register(wsa->dev, hw);
2662 if (ret)
2663 return ret;
2664
2665 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2666 }
2667
2668 static const struct snd_soc_component_driver wsa_macro_component_drv = {
2669 .name = "WSA MACRO",
2670 .probe = wsa_macro_component_probe,
2671 .controls = wsa_macro_snd_controls,
2672 .num_controls = ARRAY_SIZE(wsa_macro_snd_controls),
2673 .dapm_widgets = wsa_macro_dapm_widgets,
2674 .num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets),
2675 .dapm_routes = wsa_audio_map,
2676 .num_dapm_routes = ARRAY_SIZE(wsa_audio_map),
2677 };
2678
wsa_macro_probe(struct platform_device * pdev)2679 static int wsa_macro_probe(struct platform_device *pdev)
2680 {
2681 struct device *dev = &pdev->dev;
2682 struct wsa_macro *wsa;
2683 kernel_ulong_t flags;
2684 void __iomem *base;
2685 int ret, def_count;
2686
2687 flags = (kernel_ulong_t)device_get_match_data(dev);
2688
2689 wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL);
2690 if (!wsa)
2691 return -ENOMEM;
2692
2693 wsa->macro = devm_clk_get_optional(dev, "macro");
2694 if (IS_ERR(wsa->macro))
2695 return dev_err_probe(dev, PTR_ERR(wsa->macro), "unable to get macro clock\n");
2696
2697 wsa->dcodec = devm_clk_get_optional(dev, "dcodec");
2698 if (IS_ERR(wsa->dcodec))
2699 return dev_err_probe(dev, PTR_ERR(wsa->dcodec), "unable to get dcodec clock\n");
2700
2701 wsa->mclk = devm_clk_get(dev, "mclk");
2702 if (IS_ERR(wsa->mclk))
2703 return dev_err_probe(dev, PTR_ERR(wsa->mclk), "unable to get mclk clock\n");
2704
2705 if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
2706 wsa->npl = devm_clk_get(dev, "npl");
2707 if (IS_ERR(wsa->npl))
2708 return dev_err_probe(dev, PTR_ERR(wsa->npl), "unable to get npl clock\n");
2709 }
2710
2711 wsa->fsgen = devm_clk_get(dev, "fsgen");
2712 if (IS_ERR(wsa->fsgen))
2713 return dev_err_probe(dev, PTR_ERR(wsa->fsgen), "unable to get fsgen clock\n");
2714
2715 base = devm_platform_ioremap_resource(pdev, 0);
2716 if (IS_ERR(base))
2717 return PTR_ERR(base);
2718
2719 wsa->codec_version = lpass_macro_get_codec_version();
2720 struct reg_default *reg_defaults __free(kfree) = NULL;
2721
2722 switch (wsa->codec_version) {
2723 case LPASS_CODEC_VERSION_1_0:
2724 case LPASS_CODEC_VERSION_1_1:
2725 case LPASS_CODEC_VERSION_1_2:
2726 case LPASS_CODEC_VERSION_2_0:
2727 case LPASS_CODEC_VERSION_2_1:
2728 wsa->reg_layout = &wsa_codec_v2_1;
2729 def_count = ARRAY_SIZE(wsa_defaults) + ARRAY_SIZE(wsa_defaults_v2_1);
2730 reg_defaults = kmalloc_objs(*reg_defaults, def_count);
2731 if (!reg_defaults)
2732 return -ENOMEM;
2733 memcpy(®_defaults[0], wsa_defaults, sizeof(wsa_defaults));
2734 memcpy(®_defaults[ARRAY_SIZE(wsa_defaults)],
2735 wsa_defaults_v2_1, sizeof(wsa_defaults_v2_1));
2736 break;
2737
2738 case LPASS_CODEC_VERSION_2_5:
2739 case LPASS_CODEC_VERSION_2_6:
2740 case LPASS_CODEC_VERSION_2_7:
2741 case LPASS_CODEC_VERSION_2_8:
2742 case LPASS_CODEC_VERSION_2_9:
2743 wsa->reg_layout = &wsa_codec_v2_5;
2744 def_count = ARRAY_SIZE(wsa_defaults) + ARRAY_SIZE(wsa_defaults_v2_5);
2745 reg_defaults = kmalloc_objs(*reg_defaults, def_count);
2746 if (!reg_defaults)
2747 return -ENOMEM;
2748 memcpy(®_defaults[0], wsa_defaults, sizeof(wsa_defaults));
2749 memcpy(®_defaults[ARRAY_SIZE(wsa_defaults)],
2750 wsa_defaults_v2_5, sizeof(wsa_defaults_v2_5));
2751 break;
2752
2753 default:
2754 dev_err(dev, "Unsupported Codec version (%d)\n", wsa->codec_version);
2755 return -EINVAL;
2756 }
2757
2758 struct regmap_config *reg_config __free(kfree) = kmemdup(&wsa_regmap_config,
2759 sizeof(*reg_config),
2760 GFP_KERNEL);
2761 if (!reg_config)
2762 return -ENOMEM;
2763
2764 reg_config->reg_defaults = reg_defaults;
2765 reg_config->num_reg_defaults = def_count;
2766
2767 wsa->regmap = devm_regmap_init_mmio(dev, base, reg_config);
2768 if (IS_ERR(wsa->regmap))
2769 return PTR_ERR(wsa->regmap);
2770
2771 dev_set_drvdata(dev, wsa);
2772
2773 wsa->dev = dev;
2774
2775 /* set MCLK and NPL rates */
2776 ret = clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ);
2777 if (ret)
2778 return ret;
2779
2780 ret = clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ);
2781 if (ret)
2782 return ret;
2783
2784 ret = devm_pm_clk_create(dev);
2785 if (ret)
2786 return ret;
2787
2788 ret = of_pm_clk_add_clks(dev);
2789 if (ret < 0)
2790 return ret;
2791
2792 pm_runtime_set_autosuspend_delay(dev, 100);
2793 pm_runtime_use_autosuspend(dev);
2794 ret = devm_pm_runtime_enable(dev);
2795 if (ret)
2796 return ret;
2797
2798 ret = pm_runtime_resume_and_get(dev);
2799 if (ret < 0)
2800 return ret;
2801
2802 /* reset swr ip */
2803 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2804 CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE);
2805
2806 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2807 CDC_WSA_SWR_CLK_EN_MASK, CDC_WSA_SWR_CLK_ENABLE);
2808
2809 /* Bring out of reset */
2810 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2811 CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE);
2812
2813 ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
2814 wsa_macro_dai,
2815 ARRAY_SIZE(wsa_macro_dai));
2816 if (ret)
2817 goto err_rpm_put;
2818
2819 ret = wsa_macro_register_mclk_output(wsa);
2820 if (ret)
2821 goto err_rpm_put;
2822
2823 ret = pm_runtime_put_autosuspend(dev);
2824 if (ret < 0)
2825 dev_warn(dev, "runtime PM put failed after probe: %d\n", ret);
2826
2827 return 0;
2828 err_rpm_put:
2829 if (pm_runtime_put_sync_suspend(dev) < 0)
2830 dev_warn(dev, "runtime PM sync suspend failed in probe unwind\n");
2831 return ret;
2832 }
2833
wsa_macro_runtime_suspend(struct device * dev)2834 static int wsa_macro_runtime_suspend(struct device *dev)
2835 {
2836 struct wsa_macro *wsa = dev_get_drvdata(dev);
2837 int ret;
2838
2839 regcache_cache_only(wsa->regmap, true);
2840
2841 ret = pm_clk_suspend(dev);
2842 if (ret) {
2843 regcache_cache_only(wsa->regmap, false);
2844 return ret;
2845 }
2846
2847 regcache_mark_dirty(wsa->regmap);
2848
2849 return 0;
2850 }
2851
wsa_macro_runtime_resume(struct device * dev)2852 static int wsa_macro_runtime_resume(struct device *dev)
2853 {
2854 struct wsa_macro *wsa = dev_get_drvdata(dev);
2855 int ret, sret;
2856
2857 ret = pm_clk_resume(dev);
2858 if (ret) {
2859 regcache_cache_only(wsa->regmap, true);
2860 regcache_mark_dirty(wsa->regmap);
2861 return ret;
2862 }
2863 regcache_cache_only(wsa->regmap, false);
2864
2865 ret = regcache_sync(wsa->regmap);
2866 if (ret) {
2867 regcache_cache_only(wsa->regmap, true);
2868 regcache_mark_dirty(wsa->regmap);
2869 sret = pm_clk_suspend(dev);
2870 if (sret)
2871 dev_err(dev,
2872 "failed to suspend clocks after regcache sync failure: %d\n",
2873 sret);
2874 return ret;
2875 }
2876
2877 return 0;
2878 }
2879
2880 static const struct dev_pm_ops wsa_macro_pm_ops = {
2881 RUNTIME_PM_OPS(wsa_macro_runtime_suspend, wsa_macro_runtime_resume, NULL)
2882 };
2883
2884 static const struct of_device_id wsa_macro_dt_match[] = {
2885 {
2886 .compatible = "qcom,sc7280-lpass-wsa-macro",
2887 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2888 }, {
2889 .compatible = "qcom,sm8250-lpass-wsa-macro",
2890 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2891 }, {
2892 .compatible = "qcom,sm8450-lpass-wsa-macro",
2893 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2894 }, {
2895 .compatible = "qcom,sm8550-lpass-wsa-macro",
2896 }, {
2897 .compatible = "qcom,sc8280xp-lpass-wsa-macro",
2898 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2899 },
2900 {}
2901 };
2902 MODULE_DEVICE_TABLE(of, wsa_macro_dt_match);
2903
2904 static struct platform_driver wsa_macro_driver = {
2905 .driver = {
2906 .name = "wsa_macro",
2907 .of_match_table = wsa_macro_dt_match,
2908 .pm = pm_ptr(&wsa_macro_pm_ops),
2909 },
2910 .probe = wsa_macro_probe,
2911 };
2912
2913 module_platform_driver(wsa_macro_driver);
2914 MODULE_DESCRIPTION("WSA macro driver");
2915 MODULE_LICENSE("GPL");
2916