1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Renesas RZ/V2M I2C unit
4 *
5 * Copyright (C) 2016-2022 Renesas Electronics Corporation
6 */
7
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/i2c.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/math64.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23
24 /* Register offsets */
25 #define IICB0DAT 0x00 /* Data Register */
26 #define IICB0CTL0 0x08 /* Control Register 0 */
27 #define IICB0TRG 0x0C /* Trigger Register */
28 #define IICB0STR0 0x10 /* Status Register 0 */
29 #define IICB0CTL1 0x20 /* Control Register 1 */
30 #define IICB0WL 0x24 /* Low Level Width Setting Reg */
31 #define IICB0WH 0x28 /* How Level Width Setting Reg */
32
33 /* IICB0CTL0 */
34 #define IICB0IICE BIT(7) /* I2C Enable */
35 #define IICB0SLWT BIT(1) /* Interrupt Request Timing */
36 #define IICB0SLAC BIT(0) /* Acknowledge */
37
38 /* IICB0TRG */
39 #define IICB0WRET BIT(2) /* Quit Wait Trigger */
40 #define IICB0STT BIT(1) /* Create Start Condition Trigger */
41 #define IICB0SPT BIT(0) /* Create Stop Condition Trigger */
42
43 /* IICB0STR0 */
44 #define IICB0SSAC BIT(8) /* Ack Flag */
45 #define IICB0SSBS BIT(6) /* Bus Flag */
46 #define IICB0SSSP BIT(4) /* Stop Condition Flag */
47
48 /* IICB0CTL1 */
49 #define IICB0MDSC BIT(7) /* Bus Mode */
50 #define IICB0SLSE BIT(1) /* Start condition output */
51
52 struct rzv2m_i2c_priv {
53 void __iomem *base;
54 struct i2c_adapter adap;
55 struct clk *clk;
56 int bus_mode;
57 struct completion msg_tia_done;
58 u32 iicb0wl;
59 u32 iicb0wh;
60 };
61
62 enum bcr_index {
63 RZV2M_I2C_100K = 0,
64 RZV2M_I2C_400K,
65 };
66
67 struct bitrate_config {
68 unsigned int percent_low;
69 unsigned int min_hold_time_ns;
70 };
71
72 static const struct bitrate_config bitrate_configs[] = {
73 [RZV2M_I2C_100K] = { 47, 3450 },
74 [RZV2M_I2C_400K] = { 52, 900 },
75 };
76
bit_setl(void __iomem * addr,u32 val)77 static inline void bit_setl(void __iomem *addr, u32 val)
78 {
79 writel(readl(addr) | val, addr);
80 }
81
bit_clrl(void __iomem * addr,u32 val)82 static inline void bit_clrl(void __iomem *addr, u32 val)
83 {
84 writel(readl(addr) & ~val, addr);
85 }
86
rzv2m_i2c_tia_irq_handler(int this_irq,void * dev_id)87 static irqreturn_t rzv2m_i2c_tia_irq_handler(int this_irq, void *dev_id)
88 {
89 struct rzv2m_i2c_priv *priv = dev_id;
90
91 complete(&priv->msg_tia_done);
92
93 return IRQ_HANDLED;
94 }
95
96 /* Calculate IICB0WL and IICB0WH */
rzv2m_i2c_clock_calculate(struct device * dev,struct rzv2m_i2c_priv * priv)97 static int rzv2m_i2c_clock_calculate(struct device *dev,
98 struct rzv2m_i2c_priv *priv)
99 {
100 const struct bitrate_config *config;
101 unsigned int hold_time_ns;
102 unsigned int total_pclks;
103 unsigned int trf_pclks;
104 unsigned long pclk_hz;
105 struct i2c_timings t;
106 u32 trf_ns;
107
108 i2c_parse_fw_timings(dev, &t, true);
109
110 pclk_hz = clk_get_rate(priv->clk);
111 total_pclks = pclk_hz / t.bus_freq_hz;
112
113 trf_ns = t.scl_rise_ns + t.scl_fall_ns;
114 trf_pclks = mul_u64_u32_div(pclk_hz, trf_ns, NSEC_PER_SEC);
115
116 /* Config setting */
117 switch (t.bus_freq_hz) {
118 case I2C_MAX_FAST_MODE_FREQ:
119 priv->bus_mode = RZV2M_I2C_400K;
120 break;
121 case I2C_MAX_STANDARD_MODE_FREQ:
122 priv->bus_mode = RZV2M_I2C_100K;
123 break;
124 default:
125 dev_err(dev, "transfer speed is invalid\n");
126 return -EINVAL;
127 }
128 config = &bitrate_configs[priv->bus_mode];
129
130 /* IICB0WL = (percent_low / Transfer clock) x PCLK */
131 priv->iicb0wl = total_pclks * config->percent_low / 100;
132 if (priv->iicb0wl > (BIT(10) - 1))
133 return -EINVAL;
134
135 /* IICB0WH = ((percent_high / Transfer clock) x PCLK) - (tR + tF) */
136 priv->iicb0wh = total_pclks - priv->iicb0wl - trf_pclks;
137 if (priv->iicb0wh > (BIT(10) - 1))
138 return -EINVAL;
139
140 /*
141 * Data hold time must be less than 0.9us in fast mode and
142 * 3.45us in standard mode.
143 * Data hold time = IICB0WL[9:2] / PCLK
144 */
145 hold_time_ns = div64_ul((u64)(priv->iicb0wl >> 2) * NSEC_PER_SEC, pclk_hz);
146 if (hold_time_ns > config->min_hold_time_ns) {
147 dev_err(dev, "data hold time %dns is over %dns\n",
148 hold_time_ns, config->min_hold_time_ns);
149 return -EINVAL;
150 }
151
152 return 0;
153 }
154
rzv2m_i2c_init(struct rzv2m_i2c_priv * priv)155 static void rzv2m_i2c_init(struct rzv2m_i2c_priv *priv)
156 {
157 u32 i2c_ctl0;
158 u32 i2c_ctl1;
159
160 /* i2c disable */
161 writel(0, priv->base + IICB0CTL0);
162
163 /* IICB0CTL1 setting */
164 i2c_ctl1 = IICB0SLSE;
165 if (priv->bus_mode == RZV2M_I2C_400K)
166 i2c_ctl1 |= IICB0MDSC;
167 writel(i2c_ctl1, priv->base + IICB0CTL1);
168
169 /* IICB0WL IICB0WH setting */
170 writel(priv->iicb0wl, priv->base + IICB0WL);
171 writel(priv->iicb0wh, priv->base + IICB0WH);
172
173 /* i2c enable after setting */
174 i2c_ctl0 = IICB0SLWT | IICB0SLAC | IICB0IICE;
175 writel(i2c_ctl0, priv->base + IICB0CTL0);
176 }
177
rzv2m_i2c_write_with_ack(struct rzv2m_i2c_priv * priv,u32 data)178 static int rzv2m_i2c_write_with_ack(struct rzv2m_i2c_priv *priv, u32 data)
179 {
180 unsigned long time_left;
181
182 reinit_completion(&priv->msg_tia_done);
183
184 writel(data, priv->base + IICB0DAT);
185
186 time_left = wait_for_completion_timeout(&priv->msg_tia_done,
187 priv->adap.timeout);
188 if (!time_left)
189 return -ETIMEDOUT;
190
191 /* Confirm ACK */
192 if ((readl(priv->base + IICB0STR0) & IICB0SSAC) != IICB0SSAC)
193 return -ENXIO;
194
195 return 0;
196 }
197
rzv2m_i2c_read_with_ack(struct rzv2m_i2c_priv * priv,u8 * data,bool last)198 static int rzv2m_i2c_read_with_ack(struct rzv2m_i2c_priv *priv, u8 *data,
199 bool last)
200 {
201 unsigned long time_left;
202 u32 data_tmp;
203
204 reinit_completion(&priv->msg_tia_done);
205
206 /* Interrupt request timing : 8th clock */
207 bit_clrl(priv->base + IICB0CTL0, IICB0SLWT);
208
209 /* Exit the wait state */
210 writel(IICB0WRET, priv->base + IICB0TRG);
211
212 /* Wait for transaction */
213 time_left = wait_for_completion_timeout(&priv->msg_tia_done,
214 priv->adap.timeout);
215 if (!time_left)
216 return -ETIMEDOUT;
217
218 if (last) {
219 /* Disable ACK */
220 bit_clrl(priv->base + IICB0CTL0, IICB0SLAC);
221
222 /* Read data*/
223 data_tmp = readl(priv->base + IICB0DAT);
224
225 /* Interrupt request timing : 9th clock */
226 bit_setl(priv->base + IICB0CTL0, IICB0SLWT);
227
228 /* Exit the wait state */
229 writel(IICB0WRET, priv->base + IICB0TRG);
230
231 /* Wait for transaction */
232 time_left = wait_for_completion_timeout(&priv->msg_tia_done,
233 priv->adap.timeout);
234 if (!time_left)
235 return -ETIMEDOUT;
236
237 /* Enable ACK */
238 bit_setl(priv->base + IICB0CTL0, IICB0SLAC);
239 } else {
240 /* Read data */
241 data_tmp = readl(priv->base + IICB0DAT);
242 }
243
244 *data = data_tmp;
245
246 return 0;
247 }
248
rzv2m_i2c_send(struct rzv2m_i2c_priv * priv,struct i2c_msg * msg,unsigned int * count)249 static int rzv2m_i2c_send(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
250 unsigned int *count)
251 {
252 unsigned int i;
253 int ret;
254
255 for (i = 0; i < msg->len; i++) {
256 ret = rzv2m_i2c_write_with_ack(priv, msg->buf[i]);
257 if (ret < 0)
258 return ret;
259 }
260 *count = i;
261
262 return 0;
263 }
264
rzv2m_i2c_receive(struct rzv2m_i2c_priv * priv,struct i2c_msg * msg,unsigned int * count)265 static int rzv2m_i2c_receive(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
266 unsigned int *count)
267 {
268 unsigned int i;
269 int ret;
270
271 for (i = 0; i < msg->len; i++) {
272 ret = rzv2m_i2c_read_with_ack(priv, &msg->buf[i],
273 (msg->len - 1) == i);
274 if (ret < 0)
275 return ret;
276 }
277 *count = i;
278
279 return 0;
280 }
281
rzv2m_i2c_send_address(struct rzv2m_i2c_priv * priv,struct i2c_msg * msg)282 static int rzv2m_i2c_send_address(struct rzv2m_i2c_priv *priv,
283 struct i2c_msg *msg)
284 {
285 u32 addr;
286 int ret;
287
288 if (msg->flags & I2C_M_TEN) {
289 /* 10-bit address: Send 1st address(extend code) */
290 addr = i2c_10bit_addr_hi_from_msg(msg);
291 ret = rzv2m_i2c_write_with_ack(priv, addr);
292 if (ret)
293 return ret;
294
295 /* 10-bit address: Send 2nd address */
296 addr = i2c_10bit_addr_lo_from_msg(msg);
297 ret = rzv2m_i2c_write_with_ack(priv, addr);
298 } else {
299 /* 7-bit address */
300 addr = i2c_8bit_addr_from_msg(msg);
301 ret = rzv2m_i2c_write_with_ack(priv, addr);
302 }
303
304 return ret;
305 }
306
rzv2m_i2c_stop_condition(struct rzv2m_i2c_priv * priv)307 static int rzv2m_i2c_stop_condition(struct rzv2m_i2c_priv *priv)
308 {
309 u32 value;
310
311 /* Send stop condition */
312 writel(IICB0SPT, priv->base + IICB0TRG);
313 return readl_poll_timeout(priv->base + IICB0STR0,
314 value, value & IICB0SSSP,
315 100, jiffies_to_usecs(priv->adap.timeout));
316 }
317
rzv2m_i2c_xfer_msg(struct rzv2m_i2c_priv * priv,struct i2c_msg * msg,int stop)318 static int rzv2m_i2c_xfer_msg(struct rzv2m_i2c_priv *priv,
319 struct i2c_msg *msg, int stop)
320 {
321 unsigned int count = 0;
322 int ret, read = !!(msg->flags & I2C_M_RD);
323
324 /* Send start condition */
325 writel(IICB0STT, priv->base + IICB0TRG);
326
327 ret = rzv2m_i2c_send_address(priv, msg);
328 if (!ret) {
329 if (read)
330 ret = rzv2m_i2c_receive(priv, msg, &count);
331 else
332 ret = rzv2m_i2c_send(priv, msg, &count);
333
334 if (!ret && stop)
335 ret = rzv2m_i2c_stop_condition(priv);
336 }
337
338 if (ret == -ENXIO)
339 rzv2m_i2c_stop_condition(priv);
340 else if (ret < 0)
341 rzv2m_i2c_init(priv);
342 else
343 ret = count;
344
345 return ret;
346 }
347
rzv2m_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)348 static int rzv2m_i2c_xfer(struct i2c_adapter *adap,
349 struct i2c_msg *msgs, int num)
350 {
351 struct rzv2m_i2c_priv *priv = i2c_get_adapdata(adap);
352 struct device *dev = priv->adap.dev.parent;
353 unsigned int i;
354 int ret;
355
356 ret = pm_runtime_resume_and_get(dev);
357 if (ret < 0)
358 return ret;
359
360 if (readl(priv->base + IICB0STR0) & IICB0SSBS) {
361 ret = -EAGAIN;
362 goto out;
363 }
364
365 /* I2C main transfer */
366 for (i = 0; i < num; i++) {
367 ret = rzv2m_i2c_xfer_msg(priv, &msgs[i], i == (num - 1));
368 if (ret < 0)
369 goto out;
370 }
371 ret = num;
372
373 out:
374 pm_runtime_put_autosuspend(dev);
375
376 return ret;
377 }
378
rzv2m_i2c_func(struct i2c_adapter * adap)379 static u32 rzv2m_i2c_func(struct i2c_adapter *adap)
380 {
381 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
382 I2C_FUNC_10BIT_ADDR;
383 }
384
rzv2m_i2c_disable(struct device * dev,struct rzv2m_i2c_priv * priv)385 static int rzv2m_i2c_disable(struct device *dev, struct rzv2m_i2c_priv *priv)
386 {
387 int ret;
388
389 ret = pm_runtime_resume_and_get(dev);
390 if (ret < 0)
391 return ret;
392
393 bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
394 pm_runtime_put(dev);
395
396 return 0;
397 }
398
399 static const struct i2c_adapter_quirks rzv2m_i2c_quirks = {
400 .flags = I2C_AQ_NO_ZERO_LEN,
401 };
402
403 static const struct i2c_algorithm rzv2m_i2c_algo = {
404 .xfer = rzv2m_i2c_xfer,
405 .functionality = rzv2m_i2c_func,
406 };
407
rzv2m_i2c_probe(struct platform_device * pdev)408 static int rzv2m_i2c_probe(struct platform_device *pdev)
409 {
410 struct device *dev = &pdev->dev;
411 struct rzv2m_i2c_priv *priv;
412 struct reset_control *rstc;
413 struct i2c_adapter *adap;
414 struct resource *res;
415 int irq, ret;
416
417 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
418 if (!priv)
419 return -ENOMEM;
420
421 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
422 if (IS_ERR(priv->base))
423 return PTR_ERR(priv->base);
424
425 priv->clk = devm_clk_get(dev, NULL);
426 if (IS_ERR(priv->clk))
427 return dev_err_probe(dev, PTR_ERR(priv->clk), "Can't get clock\n");
428
429 rstc = devm_reset_control_get_shared(dev, NULL);
430 if (IS_ERR(rstc))
431 return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
432 /*
433 * The reset also affects other HW that is not under the control
434 * of Linux. Therefore, all we can do is deassert the reset.
435 */
436 reset_control_deassert(rstc);
437
438 irq = platform_get_irq(pdev, 0);
439 if (irq < 0)
440 return irq;
441
442 ret = devm_request_irq(dev, irq, rzv2m_i2c_tia_irq_handler, 0,
443 dev_name(dev), priv);
444 if (ret < 0)
445 return ret;
446
447 adap = &priv->adap;
448 adap->nr = pdev->id;
449 adap->algo = &rzv2m_i2c_algo;
450 adap->quirks = &rzv2m_i2c_quirks;
451 adap->dev.parent = dev;
452 adap->owner = THIS_MODULE;
453 device_set_node(&adap->dev, dev_fwnode(dev));
454 i2c_set_adapdata(adap, priv);
455 strscpy(adap->name, pdev->name, sizeof(adap->name));
456 init_completion(&priv->msg_tia_done);
457
458 ret = rzv2m_i2c_clock_calculate(dev, priv);
459 if (ret < 0)
460 return ret;
461
462 pm_runtime_enable(dev);
463
464 pm_runtime_get_sync(dev);
465 rzv2m_i2c_init(priv);
466 pm_runtime_put(dev);
467
468 platform_set_drvdata(pdev, priv);
469
470 ret = i2c_add_numbered_adapter(adap);
471 if (ret < 0) {
472 rzv2m_i2c_disable(dev, priv);
473 pm_runtime_disable(dev);
474 }
475
476 return ret;
477 }
478
rzv2m_i2c_remove(struct platform_device * pdev)479 static void rzv2m_i2c_remove(struct platform_device *pdev)
480 {
481 struct rzv2m_i2c_priv *priv = platform_get_drvdata(pdev);
482 struct device *dev = priv->adap.dev.parent;
483
484 i2c_del_adapter(&priv->adap);
485 rzv2m_i2c_disable(dev, priv);
486 pm_runtime_disable(dev);
487 }
488
rzv2m_i2c_suspend(struct device * dev)489 static int rzv2m_i2c_suspend(struct device *dev)
490 {
491 struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
492
493 return rzv2m_i2c_disable(dev, priv);
494 }
495
rzv2m_i2c_resume(struct device * dev)496 static int rzv2m_i2c_resume(struct device *dev)
497 {
498 struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
499 int ret;
500
501 ret = rzv2m_i2c_clock_calculate(dev, priv);
502 if (ret < 0)
503 return ret;
504
505 ret = pm_runtime_resume_and_get(dev);
506 if (ret < 0)
507 return ret;
508
509 rzv2m_i2c_init(priv);
510 pm_runtime_put(dev);
511
512 return 0;
513 }
514
515 static const struct of_device_id rzv2m_i2c_ids[] = {
516 { .compatible = "renesas,rzv2m-i2c" },
517 { }
518 };
519 MODULE_DEVICE_TABLE(of, rzv2m_i2c_ids);
520
521 static const struct dev_pm_ops rzv2m_i2c_pm_ops = {
522 SYSTEM_SLEEP_PM_OPS(rzv2m_i2c_suspend, rzv2m_i2c_resume)
523 };
524
525 static struct platform_driver rzv2m_i2c_driver = {
526 .driver = {
527 .name = "rzv2m-i2c",
528 .of_match_table = rzv2m_i2c_ids,
529 .pm = pm_sleep_ptr(&rzv2m_i2c_pm_ops),
530 },
531 .probe = rzv2m_i2c_probe,
532 .remove = rzv2m_i2c_remove,
533 };
534 module_platform_driver(rzv2m_i2c_driver);
535
536 MODULE_DESCRIPTION("RZ/V2M I2C bus driver");
537 MODULE_AUTHOR("Renesas Electronics Corporation");
538 MODULE_LICENSE("GPL");
539