1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 8 #include <drm/drm_print.h> 9 #include <drm/intel/intel_pcode_regs.h> 10 11 #include "intel_backlight_regs.h" 12 #include "intel_combo_phy.h" 13 #include "intel_combo_phy_regs.h" 14 #include "intel_crt.h" 15 #include "intel_de.h" 16 #include "intel_display_irq.h" 17 #include "intel_display_power_well.h" 18 #include "intel_display_regs.h" 19 #include "intel_display_rpm.h" 20 #include "intel_display_types.h" 21 #include "intel_display_wa.h" 22 #include "intel_dkl_phy.h" 23 #include "intel_dkl_phy_regs.h" 24 #include "intel_dmc.h" 25 #include "intel_dmc_wl.h" 26 #include "intel_dp_aux_regs.h" 27 #include "intel_dpio_phy.h" 28 #include "intel_dpll.h" 29 #include "intel_hotplug.h" 30 #include "intel_parent.h" 31 #include "intel_pps.h" 32 #include "intel_psr.h" 33 #include "intel_tc.h" 34 #include "intel_vga.h" 35 #include "skl_watermark.h" 36 #include "vlv_dpio_phy_regs.h" 37 #include "vlv_sideband.h" 38 39 /* 40 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 41 * 42 * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4 43 */ 44 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) 45 { 46 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; 47 48 return pw_idx - pw1_idx + SKL_PG1; 49 } 50 51 struct i915_power_well_regs { 52 intel_reg_t bios; 53 intel_reg_t driver; 54 intel_reg_t kvmr; 55 intel_reg_t debug; 56 }; 57 58 struct i915_power_well_ops { 59 const struct i915_power_well_regs *regs; 60 /* 61 * Synchronize the well's hw state to match the current sw state, for 62 * example enable/disable it based on the current refcount. Called 63 * during driver init and resume time, possibly after first calling 64 * the enable/disable handlers. 65 */ 66 void (*sync_hw)(struct intel_display *display, 67 struct i915_power_well *power_well); 68 /* 69 * Enable the well and resources that depend on it (for example 70 * interrupts located on the well). Called after the 0->1 refcount 71 * transition. 72 */ 73 void (*enable)(struct intel_display *display, 74 struct i915_power_well *power_well); 75 /* 76 * Disable the well and resources that depend on it. Called after 77 * the 1->0 refcount transition. 78 */ 79 void (*disable)(struct intel_display *display, 80 struct i915_power_well *power_well); 81 /* Returns the hw enabled state. */ 82 bool (*is_enabled)(struct intel_display *display, 83 struct i915_power_well *power_well); 84 }; 85 86 static const struct i915_power_well_instance * 87 i915_power_well_instance(const struct i915_power_well *power_well) 88 { 89 return &power_well->desc->instances->list[power_well->instance_idx]; 90 } 91 92 struct i915_power_well * 93 lookup_power_well(struct intel_display *display, 94 enum i915_power_well_id power_well_id) 95 { 96 struct i915_power_well *power_well; 97 98 for_each_power_well(display, power_well) 99 if (i915_power_well_instance(power_well)->id == power_well_id) 100 return power_well; 101 102 /* 103 * It's not feasible to add error checking code to the callers since 104 * this condition really shouldn't happen and it doesn't even make sense 105 * to abort things like display initialization sequences. Just return 106 * the first power well and hope the WARN gets reported so we can fix 107 * our driver. 108 */ 109 drm_WARN(display->drm, 1, 110 "Power well %d not defined for this platform\n", 111 power_well_id); 112 return &display->power.domains.power_wells[0]; 113 } 114 115 void intel_power_well_enable(struct intel_display *display, 116 struct i915_power_well *power_well) 117 { 118 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 119 power_well->desc->ops->enable(display, power_well); 120 power_well->hw_enabled = true; 121 } 122 123 void intel_power_well_disable(struct intel_display *display, 124 struct i915_power_well *power_well) 125 { 126 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 127 power_well->hw_enabled = false; 128 power_well->desc->ops->disable(display, power_well); 129 } 130 131 void intel_power_well_sync_hw(struct intel_display *display, 132 struct i915_power_well *power_well) 133 { 134 power_well->desc->ops->sync_hw(display, power_well); 135 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 136 } 137 138 void intel_power_well_get(struct intel_display *display, 139 struct i915_power_well *power_well) 140 { 141 if (!power_well->count++) 142 intel_power_well_enable(display, power_well); 143 } 144 145 void intel_power_well_put(struct intel_display *display, 146 struct i915_power_well *power_well) 147 { 148 drm_WARN(display->drm, !power_well->count, 149 "Use count on power well %s is already zero", 150 i915_power_well_instance(power_well)->name); 151 152 if (!--power_well->count) 153 intel_power_well_disable(display, power_well); 154 } 155 156 bool intel_power_well_is_enabled(struct intel_display *display, 157 struct i915_power_well *power_well) 158 { 159 return power_well->desc->ops->is_enabled(display, power_well); 160 } 161 162 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 163 { 164 return power_well->hw_enabled; 165 } 166 167 bool intel_display_power_well_is_enabled(struct intel_display *display, 168 enum i915_power_well_id power_well_id) 169 { 170 struct i915_power_well *power_well; 171 172 power_well = lookup_power_well(display, power_well_id); 173 174 return intel_power_well_is_enabled(display, power_well); 175 } 176 177 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 178 { 179 return power_well->desc->always_on; 180 } 181 182 const char *intel_power_well_name(struct i915_power_well *power_well) 183 { 184 return i915_power_well_instance(power_well)->name; 185 } 186 187 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 188 { 189 return &power_well->domains; 190 } 191 192 int intel_power_well_refcount(struct i915_power_well *power_well) 193 { 194 return power_well->count; 195 } 196 197 static u32 dss_pipe_gating_bits(u8 irq_pipe_mask) 198 { 199 u32 bits = 0; 200 201 if (irq_pipe_mask & BIT(PIPE_A)) 202 bits |= DSS_PIPE_A_GATING_DISABLED; 203 if (irq_pipe_mask & BIT(PIPE_B)) 204 bits |= DSS_PIPE_B_GATING_DISABLED; 205 if (irq_pipe_mask & BIT(PIPE_C)) 206 bits |= DSS_PIPE_C_GATING_DISABLED; 207 if (irq_pipe_mask & BIT(PIPE_D)) 208 bits |= DSS_PIPE_D_GATING_DISABLED; 209 210 return bits; 211 } 212 213 static void dss_pipe_gating_enable_disable(struct intel_display *display, 214 u8 irq_pipe_mask, 215 bool disable) 216 { 217 u32 bits = dss_pipe_gating_bits(irq_pipe_mask); 218 u32 clear, set; 219 220 if (!bits) 221 return; 222 223 /* 224 * Single intel_de_rmw() for both enable/disable: 225 * - disable == true, set bits (disable clock gating) 226 * - disable == false, clear bits (re-enable clock gating) 227 */ 228 set = disable ? bits : 0; 229 clear = disable ? 0 : bits; 230 231 intel_de_rmw(display, CLKGATE_DIS_DSSDSC, clear, set); 232 233 drm_dbg_kms(display->drm, 234 "DSS clock gating %sd for pipe_mask=0x%x (CLKGATE_DIS_DSSDSC=0x%08x)\n", 235 str_enable_disable(!disable), irq_pipe_mask, 236 intel_de_read(display, CLKGATE_DIS_DSSDSC)); 237 } 238 239 /* 240 * Starting with Haswell, we have a "Power Down Well" that can be turned off 241 * when not needed anymore. We have 4 registers that can request the power well 242 * to be enabled, and it will only be disabled if none of the registers is 243 * requesting it to be enabled. 244 */ 245 static void hsw_power_well_post_enable(struct intel_display *display, 246 u8 irq_pipe_mask) 247 { 248 if (irq_pipe_mask) { 249 gen8_irq_power_well_post_enable(display, irq_pipe_mask); 250 251 if (intel_display_wa(display, INTEL_DISPLAY_WA_22021048059)) 252 dss_pipe_gating_enable_disable(display, irq_pipe_mask, false); 253 } 254 } 255 256 static void hsw_power_well_pre_disable(struct intel_display *display, 257 u8 irq_pipe_mask) 258 { 259 if (irq_pipe_mask) { 260 if (intel_display_wa(display, INTEL_DISPLAY_WA_22021048059)) 261 dss_pipe_gating_enable_disable(display, irq_pipe_mask, true); 262 263 gen8_irq_power_well_pre_disable(display, irq_pipe_mask); 264 } 265 } 266 267 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 268 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 269 270 #define ICL_AUX_PW_TO_CH(pw_idx) \ 271 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 272 273 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 274 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 275 276 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 277 { 278 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 279 280 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 281 ICL_AUX_PW_TO_CH(pw_idx); 282 } 283 284 static struct intel_digital_port * 285 aux_ch_to_digital_port(struct intel_display *display, 286 enum aux_ch aux_ch) 287 { 288 struct intel_encoder *encoder; 289 290 for_each_intel_encoder(display->drm, encoder) { 291 struct intel_digital_port *dig_port; 292 293 /* We'll check the MST primary port */ 294 if (encoder->type == INTEL_OUTPUT_DP_MST) 295 continue; 296 297 dig_port = enc_to_dig_port(encoder); 298 299 if (dig_port && dig_port->aux_ch == aux_ch) 300 return dig_port; 301 } 302 303 return NULL; 304 } 305 306 static struct intel_encoder * 307 icl_aux_pw_to_encoder(struct intel_display *display, 308 const struct i915_power_well *power_well) 309 { 310 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 311 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 312 313 /* 314 * FIXME should we care about the (VBT defined) dig_port->aux_ch 315 * relationship or should this be purely defined by the hardware layout? 316 * Currently if the port doesn't appear in the VBT, or if it's declared 317 * as HDMI-only and routed to a combo PHY, the encoder either won't be 318 * present at all or it will not have an aux_ch assigned. 319 */ 320 return dig_port ? &dig_port->base : NULL; 321 } 322 323 static enum phy icl_aux_pw_to_phy(struct intel_display *display, 324 const struct i915_power_well *power_well) 325 { 326 struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 327 328 return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE; 329 } 330 331 static bool icl_aux_pw_is_tc_phy(struct intel_display *display, 332 const struct i915_power_well *power_well) 333 { 334 struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 335 336 return encoder && intel_encoder_is_tc(encoder); 337 } 338 339 static void hsw_wait_for_power_well_enable(struct intel_display *display, 340 struct i915_power_well *power_well, 341 bool timeout_expected) 342 { 343 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 344 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 345 int timeout = power_well->desc->enable_timeout ? : 1; 346 347 /* 348 * For some power wells we're not supposed to watch the status bit for 349 * an ack, but rather just wait a fixed amount of time and then 350 * proceed. This is only used on DG2. 351 */ 352 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 353 usleep_range(600, 1200); 354 return; 355 } 356 357 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 358 if (intel_de_wait_for_set_ms(display, regs->driver, 359 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 360 drm_dbg_kms(display->drm, "%s power well enable timeout\n", 361 intel_power_well_name(power_well)); 362 363 drm_WARN_ON(display->drm, !timeout_expected); 364 365 } 366 } 367 368 static u32 hsw_power_well_requesters(struct intel_display *display, 369 const struct i915_power_well_regs *regs, 370 int pw_idx) 371 { 372 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 373 u32 ret; 374 375 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 376 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 377 if (regs->kvmr.reg) 378 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 379 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 380 381 return ret; 382 } 383 384 static void hsw_wait_for_power_well_disable(struct intel_display *display, 385 struct i915_power_well *power_well) 386 { 387 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 388 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 389 u32 reqs; 390 int ret; 391 392 /* 393 * Bspec doesn't require waiting for PWs to get disabled, but still do 394 * this for paranoia. The known cases where a PW will be forced on: 395 * - a KVMR request on any power well via the KVMR request register 396 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 397 * DEBUG request registers 398 * Skip the wait in case any of the request bits are set and print a 399 * diagnostic message. 400 */ 401 reqs = hsw_power_well_requesters(display, regs, pw_idx); 402 403 ret = intel_de_wait_for_clear_ms(display, regs->driver, 404 HSW_PWR_WELL_CTL_STATE(pw_idx), 405 reqs ? 0 : 1); 406 if (!ret) 407 return; 408 409 /* Refresh requesters in case they popped up during the wait. */ 410 if (!reqs) 411 reqs = hsw_power_well_requesters(display, regs, pw_idx); 412 413 drm_dbg_kms(display->drm, 414 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 415 intel_power_well_name(power_well), 416 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 417 } 418 419 static void gen9_wait_for_power_well_fuses(struct intel_display *display, 420 enum skl_power_gate pg) 421 { 422 /* Timeout 5us for PG#0, for other PGs 1us */ 423 drm_WARN_ON(display->drm, 424 intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS, 425 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 426 } 427 428 static void hsw_power_well_enable(struct intel_display *display, 429 struct i915_power_well *power_well) 430 { 431 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 432 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 433 434 if (power_well->desc->has_fuses) { 435 enum skl_power_gate pg; 436 437 pg = pw_idx_to_pg(display, pw_idx); 438 439 /* Wa_16013190616:adlp */ 440 if (display->platform.alderlake_p && pg == SKL_PG1) 441 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 442 443 /* 444 * For PW1 we have to wait both for the PW0/PG0 fuse state 445 * before enabling the power well and PW1/PG1's own fuse 446 * state after the enabling. For all other power wells with 447 * fuses we only have to wait for that PW/PG's fuse state 448 * after the enabling. 449 */ 450 if (pg == SKL_PG1) 451 gen9_wait_for_power_well_fuses(display, SKL_PG0); 452 } 453 454 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 455 456 hsw_wait_for_power_well_enable(display, power_well, false); 457 458 if (power_well->desc->has_fuses) { 459 enum skl_power_gate pg; 460 461 pg = pw_idx_to_pg(display, pw_idx); 462 463 gen9_wait_for_power_well_fuses(display, pg); 464 } 465 466 hsw_power_well_post_enable(display, 467 power_well->desc->irq_pipe_mask); 468 } 469 470 static void hsw_power_well_disable(struct intel_display *display, 471 struct i915_power_well *power_well) 472 { 473 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 474 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 475 476 hsw_power_well_pre_disable(display, 477 power_well->desc->irq_pipe_mask); 478 479 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 480 hsw_wait_for_power_well_disable(display, power_well); 481 } 482 483 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 484 { 485 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 486 487 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 488 } 489 490 static void 491 icl_combo_phy_aux_power_well_enable(struct intel_display *display, 492 struct i915_power_well *power_well) 493 { 494 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 495 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 496 497 drm_WARN_ON(display->drm, !display->platform.icelake); 498 499 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 500 501 /* 502 * FIXME not sure if we should derive the PHY from the pw_idx, or 503 * from the VBT defined AUX_CH->DDI->PHY mapping. 504 */ 505 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 506 0, ICL_LANE_ENABLE_AUX); 507 508 hsw_wait_for_power_well_enable(display, power_well, false); 509 510 /* Display WA #1178: icl */ 511 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 512 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 513 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 514 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 515 } 516 517 static void 518 icl_combo_phy_aux_power_well_disable(struct intel_display *display, 519 struct i915_power_well *power_well) 520 { 521 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 522 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 523 524 drm_WARN_ON(display->drm, !display->platform.icelake); 525 526 /* 527 * FIXME not sure if we should derive the PHY from the pw_idx, or 528 * from the VBT defined AUX_CH->DDI->PHY mapping. 529 */ 530 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 531 ICL_LANE_ENABLE_AUX, 0); 532 533 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 534 535 hsw_wait_for_power_well_disable(display, power_well); 536 } 537 538 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 539 540 static void icl_tc_port_assert_ref_held(struct intel_display *display, 541 struct i915_power_well *power_well, 542 struct intel_digital_port *dig_port) 543 { 544 if (drm_WARN_ON(display->drm, !dig_port)) 545 return; 546 547 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 548 return; 549 550 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 551 } 552 553 #else 554 555 static void icl_tc_port_assert_ref_held(struct intel_display *display, 556 struct i915_power_well *power_well, 557 struct intel_digital_port *dig_port) 558 { 559 } 560 561 #endif 562 563 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 564 565 static void icl_tc_cold_exit(struct intel_display *display) 566 { 567 int ret, tries = 0; 568 569 while (1) { 570 ret = intel_parent_pcode_write(display, ICL_PCODE_EXIT_TCCOLD, 0); 571 if (ret != -EAGAIN || ++tries == 3) 572 break; 573 msleep(1); 574 } 575 576 /* Spec states that TC cold exit can take up to 1ms to complete */ 577 if (!ret) 578 msleep(1); 579 580 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 581 drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" : 582 "succeeded"); 583 } 584 585 static void 586 icl_tc_phy_aux_power_well_enable(struct intel_display *display, 587 struct i915_power_well *power_well) 588 { 589 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 590 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 591 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 592 bool is_tbt = power_well->desc->is_tc_tbt; 593 bool timeout_expected; 594 u32 val; 595 int ret; 596 597 icl_tc_port_assert_ref_held(display, power_well, dig_port); 598 599 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 600 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 601 602 intel_de_rmw(display, regs->driver, 603 0, 604 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 605 606 /* 607 * An AUX timeout is expected if the TBT DP tunnel is down, 608 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 609 * exit sequence. 610 */ 611 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 612 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 613 icl_tc_cold_exit(display); 614 615 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 616 617 if (DISPLAY_VER(display) >= 12 && !is_tbt) { 618 enum tc_port tc_port; 619 620 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 621 622 ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)), 623 val & DKL_CMN_UC_DW27_UC_HEALTH, 624 100, 1000, false); 625 if (ret) 626 drm_warn(display->drm, "Timeout waiting TC uC health\n"); 627 } 628 } 629 630 static void 631 icl_aux_power_well_enable(struct intel_display *display, 632 struct i915_power_well *power_well) 633 { 634 if (icl_aux_pw_is_tc_phy(display, power_well)) 635 return icl_tc_phy_aux_power_well_enable(display, power_well); 636 else if (display->platform.icelake) 637 return icl_combo_phy_aux_power_well_enable(display, 638 power_well); 639 else 640 return hsw_power_well_enable(display, power_well); 641 } 642 643 static void 644 icl_aux_power_well_disable(struct intel_display *display, 645 struct i915_power_well *power_well) 646 { 647 if (icl_aux_pw_is_tc_phy(display, power_well)) 648 return hsw_power_well_disable(display, power_well); 649 else if (display->platform.icelake) 650 return icl_combo_phy_aux_power_well_disable(display, 651 power_well); 652 else 653 return hsw_power_well_disable(display, power_well); 654 } 655 656 /* 657 * We should only use the power well if we explicitly asked the hardware to 658 * enable it, so check if it's enabled and also check if we've requested it to 659 * be enabled. 660 */ 661 static bool hsw_power_well_enabled(struct intel_display *display, 662 struct i915_power_well *power_well) 663 { 664 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 665 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 666 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 667 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 668 HSW_PWR_WELL_CTL_STATE(pw_idx); 669 u32 val; 670 671 val = intel_de_read(display, regs->driver); 672 673 /* 674 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 675 * and the MISC_IO PW will be not restored, so check instead for the 676 * BIOS's own request bits, which are forced-on for these power wells 677 * when exiting DC5/6. 678 */ 679 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 680 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 681 val |= intel_de_read(display, regs->bios); 682 683 return (val & mask) == mask; 684 } 685 686 static void assert_can_enable_dc9(struct intel_display *display) 687 { 688 drm_WARN_ONCE(display->drm, 689 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 690 "DC9 already programmed to be enabled.\n"); 691 drm_WARN_ONCE(display->drm, 692 intel_de_read(display, DC_STATE_EN) & 693 DC_STATE_EN_UPTO_DC5, 694 "DC5 still not disabled to enable DC9.\n"); 695 drm_WARN_ONCE(display->drm, 696 intel_de_read(display, HSW_PWR_WELL_CTL2) & 697 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 698 "Power well 2 on.\n"); 699 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 700 "Interrupts not disabled yet.\n"); 701 702 /* 703 * TODO: check for the following to verify the conditions to enter DC9 704 * state are satisfied: 705 * 1] Check relevant display engine registers to verify if mode set 706 * disable sequence was followed. 707 * 2] Check if display uninitialize sequence is initialized. 708 */ 709 } 710 711 static void assert_can_disable_dc9(struct intel_display *display) 712 { 713 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 714 "Interrupts not disabled yet.\n"); 715 drm_WARN_ONCE(display->drm, 716 intel_de_read(display, DC_STATE_EN) & 717 DC_STATE_EN_UPTO_DC5, 718 "DC5 still not disabled.\n"); 719 720 /* 721 * TODO: check for the following to verify DC9 state was indeed 722 * entered before programming to disable it: 723 * 1] Check relevant display engine registers to verify if mode 724 * set disable sequence was followed. 725 * 2] Check if display uninitialize sequence is initialized. 726 */ 727 } 728 729 static void gen9_write_dc_state(struct intel_display *display, 730 u32 state) 731 { 732 int rewrites = 0; 733 int rereads = 0; 734 u32 v; 735 736 intel_de_write(display, DC_STATE_EN, state); 737 738 /* It has been observed that disabling the dc6 state sometimes 739 * doesn't stick and dmc keeps returning old value. Make sure 740 * the write really sticks enough times and also force rewrite until 741 * we are confident that state is exactly what we want. 742 */ 743 do { 744 v = intel_de_read(display, DC_STATE_EN); 745 746 if (v != state) { 747 intel_de_write(display, DC_STATE_EN, state); 748 rewrites++; 749 rereads = 0; 750 } else if (rereads++ > 5) { 751 break; 752 } 753 754 } while (rewrites < 100); 755 756 if (v != state) 757 drm_err(display->drm, 758 "Writing dc state to 0x%x failed, now 0x%x\n", 759 state, v); 760 761 /* Most of the times we need one retry, avoid spam */ 762 if (rewrites > 1) 763 drm_dbg_kms(display->drm, 764 "Rewrote dc state to 0x%x %d times\n", 765 state, rewrites); 766 } 767 768 static u32 gen9_dc_mask(struct intel_display *display) 769 { 770 u32 mask; 771 772 mask = DC_STATE_EN_UPTO_DC5; 773 774 if (DISPLAY_VER(display) >= 12) 775 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 776 | DC_STATE_EN_DC9; 777 else if (DISPLAY_VER(display) == 11) 778 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 779 else if (display->platform.geminilake || display->platform.broxton) 780 mask |= DC_STATE_EN_DC9; 781 else 782 mask |= DC_STATE_EN_UPTO_DC6; 783 784 return mask; 785 } 786 787 void gen9_sanitize_dc_state(struct intel_display *display) 788 { 789 struct i915_power_domains *power_domains = &display->power.domains; 790 u32 val; 791 792 if (!HAS_DISPLAY(display)) 793 return; 794 795 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 796 797 drm_dbg_kms(display->drm, 798 "Resetting DC state tracking from %02x to %02x\n", 799 power_domains->dc_state, val); 800 power_domains->dc_state = val; 801 } 802 803 /** 804 * gen9_set_dc_state - set target display C power state 805 * @display: display instance 806 * @state: target DC power state 807 * - DC_STATE_DISABLE 808 * - DC_STATE_EN_UPTO_DC5 809 * - DC_STATE_EN_UPTO_DC6 810 * - DC_STATE_EN_DC9 811 * 812 * Signal to DMC firmware/HW the target DC power state passed in @state. 813 * DMC/HW can turn off individual display clocks and power rails when entering 814 * a deeper DC power state (higher in number) and turns these back when exiting 815 * that state to a shallower power state (lower in number). The HW will decide 816 * when to actually enter a given state on an on-demand basis, for instance 817 * depending on the active state of display pipes. The state of display 818 * registers backed by affected power rails are saved/restored as needed. 819 * 820 * Based on the above enabling a deeper DC power state is asynchronous wrt. 821 * enabling it. Disabling a deeper power state is synchronous: for instance 822 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 823 * back on and register state is restored. This is guaranteed by the MMIO write 824 * to DC_STATE_EN blocking until the state is restored. 825 */ 826 void gen9_set_dc_state(struct intel_display *display, u32 state) 827 { 828 struct i915_power_domains *power_domains = &display->power.domains; 829 bool dc6_was_enabled, enable_dc6; 830 u32 mask; 831 u32 val; 832 833 if (!HAS_DISPLAY(display)) 834 return; 835 836 if (drm_WARN_ON_ONCE(display->drm, 837 state & ~power_domains->allowed_dc_mask)) 838 state &= power_domains->allowed_dc_mask; 839 840 if (!power_domains->initializing) 841 intel_psr_notify_dc5_dc6(display); 842 843 val = intel_de_read(display, DC_STATE_EN); 844 mask = gen9_dc_mask(display); 845 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 846 val & mask, state); 847 848 /* Check if DMC is ignoring our DC state requests */ 849 if ((val & mask) != power_domains->dc_state) 850 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 851 power_domains->dc_state, val & mask); 852 853 enable_dc6 = state & DC_STATE_EN_UPTO_DC6; 854 dc6_was_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6; 855 if (!dc6_was_enabled && enable_dc6) 856 intel_dmc_update_dc6_allowed_count(display, true); 857 858 val &= ~mask; 859 val |= state; 860 861 gen9_write_dc_state(display, val); 862 863 if (!enable_dc6 && dc6_was_enabled) 864 intel_dmc_update_dc6_allowed_count(display, false); 865 866 power_domains->dc_state = val & mask; 867 } 868 869 static void tgl_enable_dc3co(struct intel_display *display) 870 { 871 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 872 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); 873 } 874 875 static void tgl_disable_dc3co(struct intel_display *display) 876 { 877 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); 878 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 879 gen9_set_dc_state(display, DC_STATE_DISABLE); 880 /* 881 * Delay of 200us DC3CO Exit time B.Spec 49196 882 */ 883 usleep_range(200, 210); 884 } 885 886 static void assert_can_enable_dc5(struct intel_display *display) 887 { 888 enum i915_power_well_id high_pg; 889 890 /* Power wells at this level and above must be disabled for DC5 entry */ 891 if (DISPLAY_VER(display) == 12) 892 high_pg = ICL_DISP_PW_3; 893 else 894 high_pg = SKL_DISP_PW_2; 895 896 drm_WARN_ONCE(display->drm, 897 intel_display_power_well_is_enabled(display, high_pg), 898 "Power wells above platform's DC5 limit still enabled.\n"); 899 900 drm_WARN_ONCE(display->drm, 901 (intel_de_read(display, DC_STATE_EN) & 902 DC_STATE_EN_UPTO_DC5), 903 "DC5 already programmed to be enabled.\n"); 904 905 assert_display_rpm_held(display); 906 907 assert_main_dmc_loaded(display); 908 } 909 910 void gen9_enable_dc5(struct intel_display *display) 911 { 912 assert_can_enable_dc5(display); 913 914 drm_dbg_kms(display->drm, "Enabling DC5\n"); 915 916 /* Wa Display #1183: skl,kbl,cfl */ 917 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 918 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 919 0, SKL_SELECT_ALTERNATE_DC_EXIT); 920 921 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 922 923 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 924 } 925 926 static void assert_can_enable_dc6(struct intel_display *display) 927 { 928 drm_WARN_ONCE(display->drm, 929 (intel_de_read(display, UTIL_PIN_CTL) & 930 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 931 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 932 "Utility pin enabled in PWM mode\n"); 933 drm_WARN_ONCE(display->drm, 934 (intel_de_read(display, DC_STATE_EN) & 935 DC_STATE_EN_UPTO_DC6), 936 "DC6 already programmed to be enabled.\n"); 937 938 assert_main_dmc_loaded(display); 939 } 940 941 void skl_enable_dc6(struct intel_display *display) 942 { 943 assert_can_enable_dc6(display); 944 945 drm_dbg_kms(display->drm, "Enabling DC6\n"); 946 947 /* Wa Display #1183: skl,kbl,cfl */ 948 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 949 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 950 0, SKL_SELECT_ALTERNATE_DC_EXIT); 951 952 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 953 954 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 955 } 956 957 void bxt_enable_dc9(struct intel_display *display) 958 { 959 assert_can_enable_dc9(display); 960 961 drm_dbg_kms(display->drm, "Enabling DC9\n"); 962 /* 963 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 964 * aren't always on, unlike with South Display Engine on PCH. 965 */ 966 if (display->platform.broxton || display->platform.geminilake) 967 bxt_pps_reset_all(display); 968 gen9_set_dc_state(display, DC_STATE_EN_DC9); 969 } 970 971 void bxt_disable_dc9(struct intel_display *display) 972 { 973 assert_can_disable_dc9(display); 974 975 drm_dbg_kms(display->drm, "Disabling DC9\n"); 976 977 gen9_set_dc_state(display, DC_STATE_DISABLE); 978 979 intel_pps_unlock_regs_wa(display); 980 } 981 982 static void hsw_power_well_sync_hw(struct intel_display *display, 983 struct i915_power_well *power_well) 984 { 985 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 986 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 987 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 988 u32 bios_req = intel_de_read(display, regs->bios); 989 990 /* Take over the request bit if set by BIOS. */ 991 if (bios_req & mask) { 992 u32 drv_req = intel_de_read(display, regs->driver); 993 994 if (!(drv_req & mask)) 995 intel_de_write(display, regs->driver, drv_req | mask); 996 intel_de_write(display, regs->bios, bios_req & ~mask); 997 } 998 } 999 1000 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 1001 struct i915_power_well *power_well) 1002 { 1003 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 1004 } 1005 1006 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 1007 struct i915_power_well *power_well) 1008 { 1009 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 1010 } 1011 1012 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 1013 struct i915_power_well *power_well) 1014 { 1015 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 1016 } 1017 1018 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 1019 { 1020 struct i915_power_well *power_well; 1021 1022 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 1023 if (intel_power_well_refcount(power_well) > 0) 1024 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 1025 1026 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1027 if (intel_power_well_refcount(power_well) > 0) 1028 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 1029 1030 if (display->platform.geminilake) { 1031 power_well = lookup_power_well(display, 1032 GLK_DISP_PW_DPIO_CMN_C); 1033 if (intel_power_well_refcount(power_well) > 0) 1034 bxt_dpio_phy_verify_state(display, 1035 i915_power_well_instance(power_well)->bxt.phy); 1036 } 1037 } 1038 1039 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 1040 struct i915_power_well *power_well) 1041 { 1042 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 1043 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 1044 } 1045 1046 static void gen9_assert_dbuf_enabled(struct intel_display *display) 1047 { 1048 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); 1049 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 1050 1051 drm_WARN(display->drm, 1052 hw_enabled_dbuf_slices != enabled_dbuf_slices, 1053 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 1054 hw_enabled_dbuf_slices, 1055 enabled_dbuf_slices); 1056 } 1057 1058 void gen9_disable_dc_states(struct intel_display *display) 1059 { 1060 struct i915_power_domains *power_domains = &display->power.domains; 1061 struct intel_cdclk_config cdclk_config = {}; 1062 u32 old_state = power_domains->dc_state; 1063 1064 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 1065 tgl_disable_dc3co(display); 1066 return; 1067 } 1068 1069 if (HAS_DISPLAY(display)) { 1070 intel_dmc_wl_get_noreg(display); 1071 gen9_set_dc_state(display, DC_STATE_DISABLE); 1072 intel_dmc_wl_put_noreg(display); 1073 } else { 1074 gen9_set_dc_state(display, DC_STATE_DISABLE); 1075 return; 1076 } 1077 1078 if (old_state == DC_STATE_EN_UPTO_DC5 || 1079 old_state == DC_STATE_EN_UPTO_DC6) 1080 intel_dmc_wl_disable(display); 1081 1082 intel_cdclk_get_cdclk(display, &cdclk_config); 1083 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1084 drm_WARN_ON(display->drm, 1085 intel_cdclk_clock_changed(&display->cdclk.hw, 1086 &cdclk_config)); 1087 1088 gen9_assert_dbuf_enabled(display); 1089 1090 if (display->platform.geminilake || display->platform.broxton) 1091 bxt_verify_dpio_phy_power_wells(display); 1092 1093 if (DISPLAY_VER(display) >= 11) 1094 /* 1095 * DMC retains HW context only for port A, the other combo 1096 * PHY's HW context for port B is lost after DC transitions, 1097 * so we need to restore it manually. 1098 */ 1099 intel_combo_phy_init(display); 1100 } 1101 1102 static void gen9_dc_off_power_well_enable(struct intel_display *display, 1103 struct i915_power_well *power_well) 1104 { 1105 gen9_disable_dc_states(display); 1106 } 1107 1108 static void gen9_dc_off_power_well_disable(struct intel_display *display, 1109 struct i915_power_well *power_well) 1110 { 1111 struct i915_power_domains *power_domains = &display->power.domains; 1112 1113 if (!intel_dmc_has_payload(display)) 1114 return; 1115 1116 switch (power_domains->target_dc_state) { 1117 case DC_STATE_EN_DC3CO: 1118 tgl_enable_dc3co(display); 1119 break; 1120 case DC_STATE_EN_UPTO_DC6: 1121 skl_enable_dc6(display); 1122 break; 1123 case DC_STATE_EN_UPTO_DC5: 1124 gen9_enable_dc5(display); 1125 break; 1126 } 1127 } 1128 1129 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1130 struct i915_power_well *power_well) 1131 { 1132 } 1133 1134 static void i9xx_always_on_power_well_noop(struct intel_display *display, 1135 struct i915_power_well *power_well) 1136 { 1137 } 1138 1139 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1140 struct i915_power_well *power_well) 1141 { 1142 return true; 1143 } 1144 1145 static void i830_pipes_power_well_enable(struct intel_display *display, 1146 struct i915_power_well *power_well) 1147 { 1148 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1149 i830_enable_pipe(display, PIPE_A); 1150 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1151 i830_enable_pipe(display, PIPE_B); 1152 } 1153 1154 static void i830_pipes_power_well_disable(struct intel_display *display, 1155 struct i915_power_well *power_well) 1156 { 1157 i830_disable_pipe(display, PIPE_B); 1158 i830_disable_pipe(display, PIPE_A); 1159 } 1160 1161 static bool i830_pipes_power_well_enabled(struct intel_display *display, 1162 struct i915_power_well *power_well) 1163 { 1164 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1165 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1166 } 1167 1168 static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1169 struct i915_power_well *power_well) 1170 { 1171 if (intel_power_well_refcount(power_well) > 0) 1172 i830_pipes_power_well_enable(display, power_well); 1173 else 1174 i830_pipes_power_well_disable(display, power_well); 1175 } 1176 1177 static void vlv_set_power_well(struct intel_display *display, 1178 struct i915_power_well *power_well, bool enable) 1179 { 1180 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1181 u32 mask; 1182 u32 state; 1183 u32 ctrl; 1184 u32 val; 1185 int ret; 1186 1187 mask = PUNIT_PWRGT_MASK(pw_idx); 1188 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1189 PUNIT_PWRGT_PWR_GATE(pw_idx); 1190 1191 vlv_punit_get(display); 1192 1193 val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS); 1194 if ((val & mask) == state) 1195 goto out; 1196 1197 ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL); 1198 ctrl &= ~mask; 1199 ctrl |= state; 1200 vlv_punit_write(display, PUNIT_REG_PWRGT_CTRL, ctrl); 1201 1202 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS), 1203 (val & mask) == state, 1204 500, 100 * 1000, false); 1205 if (ret) 1206 drm_err(display->drm, 1207 "timeout setting power well state %08x (%08x)\n", 1208 state, 1209 vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL)); 1210 1211 out: 1212 vlv_punit_put(display); 1213 } 1214 1215 static void vlv_power_well_enable(struct intel_display *display, 1216 struct i915_power_well *power_well) 1217 { 1218 vlv_set_power_well(display, power_well, true); 1219 } 1220 1221 static void vlv_power_well_disable(struct intel_display *display, 1222 struct i915_power_well *power_well) 1223 { 1224 vlv_set_power_well(display, power_well, false); 1225 } 1226 1227 static bool vlv_power_well_enabled(struct intel_display *display, 1228 struct i915_power_well *power_well) 1229 { 1230 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1231 bool enabled = false; 1232 u32 mask; 1233 u32 state; 1234 u32 ctrl; 1235 1236 mask = PUNIT_PWRGT_MASK(pw_idx); 1237 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1238 1239 vlv_punit_get(display); 1240 1241 state = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS) & mask; 1242 /* 1243 * We only ever set the power-on and power-gate states, anything 1244 * else is unexpected. 1245 */ 1246 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1247 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1248 if (state == ctrl) 1249 enabled = true; 1250 1251 /* 1252 * A transient state at this point would mean some unexpected party 1253 * is poking at the power controls too. 1254 */ 1255 ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL) & mask; 1256 drm_WARN_ON(display->drm, ctrl != state); 1257 1258 vlv_punit_put(display); 1259 1260 return enabled; 1261 } 1262 1263 static void vlv_init_display_clock_gating(struct intel_display *display) 1264 { 1265 /* 1266 * On driver load, a pipe may be active and driving a DSI display. 1267 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1268 * (and never recovering) in this case. intel_dsi_post_disable() will 1269 * clear it when we turn off the display. 1270 */ 1271 intel_de_rmw(display, VLV_DSPCLK_GATE_D, 1272 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1273 1274 /* 1275 * Disable trickle feed and enable pnd deadline calculation 1276 */ 1277 intel_de_write(display, MI_ARB_VLV, 1278 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE_VLV); 1279 intel_de_write(display, CBR1_VLV, 0); 1280 1281 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1282 intel_de_write(display, RAWCLK_FREQ_VLV, 1283 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1284 1000)); 1285 } 1286 1287 static void vlv_display_power_well_init(struct intel_display *display) 1288 { 1289 struct intel_encoder *encoder; 1290 enum pipe pipe; 1291 1292 /* 1293 * Enable the CRI clock source so we can get at the 1294 * display and the reference clock for VGA 1295 * hotplug / manual detection. Supposedly DSI also 1296 * needs the ref clock up and running. 1297 * 1298 * CHV DPLL B/C have some issues if VGA mode is enabled. 1299 */ 1300 for_each_pipe(display, pipe) { 1301 u32 val = intel_de_read(display, DPLL(display, pipe)); 1302 1303 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1304 if (pipe != PIPE_A) 1305 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1306 1307 intel_de_write(display, DPLL(display, pipe), val); 1308 } 1309 1310 vlv_init_display_clock_gating(display); 1311 1312 valleyview_enable_display_irqs(display); 1313 1314 /* 1315 * During driver initialization/resume we can avoid restoring the 1316 * part of the HW/SW state that will be inited anyway explicitly. 1317 */ 1318 if (display->power.domains.initializing) 1319 return; 1320 1321 intel_hpd_init(display); 1322 intel_hpd_poll_disable(display); 1323 1324 /* Re-enable the ADPA, if we have one */ 1325 for_each_intel_encoder(display->drm, encoder) { 1326 if (encoder->type == INTEL_OUTPUT_ANALOG) 1327 intel_crt_reset(&encoder->base); 1328 } 1329 1330 intel_vga_disable(display); 1331 1332 intel_pps_unlock_regs_wa(display); 1333 } 1334 1335 static void vlv_display_power_well_deinit(struct intel_display *display) 1336 { 1337 valleyview_disable_display_irqs(display); 1338 1339 /* make sure we're done processing display irqs */ 1340 intel_parent_irq_synchronize(display); 1341 1342 vlv_pps_reset_all(display); 1343 1344 /* Prevent us from re-enabling polling on accident in late suspend */ 1345 if (!display->drm->dev->power.is_suspended) 1346 intel_hpd_poll_enable(display); 1347 } 1348 1349 static void vlv_display_power_well_enable(struct intel_display *display, 1350 struct i915_power_well *power_well) 1351 { 1352 vlv_set_power_well(display, power_well, true); 1353 1354 vlv_display_power_well_init(display); 1355 } 1356 1357 static void vlv_display_power_well_disable(struct intel_display *display, 1358 struct i915_power_well *power_well) 1359 { 1360 vlv_display_power_well_deinit(display); 1361 1362 vlv_set_power_well(display, power_well, false); 1363 } 1364 1365 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1366 struct i915_power_well *power_well) 1367 { 1368 /* since ref/cri clock was enabled */ 1369 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1370 1371 vlv_set_power_well(display, power_well, true); 1372 1373 /* 1374 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1375 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1376 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1377 * b. The other bits such as sfr settings / modesel may all 1378 * be set to 0. 1379 * 1380 * This should only be done on init and resume from S3 with 1381 * both PLLs disabled, or we risk losing DPIO and PLL 1382 * synchronization. 1383 */ 1384 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1385 } 1386 1387 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1388 struct i915_power_well *power_well) 1389 { 1390 enum pipe pipe; 1391 1392 for_each_pipe(display, pipe) 1393 assert_pll_disabled(display, pipe); 1394 1395 /* Assert common reset */ 1396 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1397 1398 vlv_set_power_well(display, power_well, false); 1399 } 1400 1401 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1402 1403 static void assert_chv_phy_status(struct intel_display *display) 1404 { 1405 struct i915_power_well *cmn_bc = 1406 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1407 struct i915_power_well *cmn_d = 1408 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1409 u32 phy_control = display->power.chv_phy_control; 1410 u32 phy_status = 0; 1411 u32 phy_status_mask = 0xffffffff; 1412 u32 val; 1413 1414 /* 1415 * The BIOS can leave the PHY is some weird state 1416 * where it doesn't fully power down some parts. 1417 * Disable the asserts until the PHY has been fully 1418 * reset (ie. the power well has been disabled at 1419 * least once). 1420 */ 1421 if (!display->power.chv_phy_assert[DPIO_PHY0]) 1422 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1423 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1424 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1425 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1426 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1427 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1428 1429 if (!display->power.chv_phy_assert[DPIO_PHY1]) 1430 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1431 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1432 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1433 1434 if (intel_power_well_is_enabled(display, cmn_bc)) { 1435 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1436 1437 /* this assumes override is only used to enable lanes */ 1438 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1439 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1440 1441 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1442 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1443 1444 /* CL1 is on whenever anything is on in either channel */ 1445 if (BITS_SET(phy_control, 1446 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1447 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1448 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1449 1450 /* 1451 * The DPLLB check accounts for the pipe B + port A usage 1452 * with CL2 powered up but all the lanes in the second channel 1453 * powered down. 1454 */ 1455 if (BITS_SET(phy_control, 1456 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1457 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1458 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1459 1460 if (BITS_SET(phy_control, 1461 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1462 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1463 if (BITS_SET(phy_control, 1464 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1465 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1466 1467 if (BITS_SET(phy_control, 1468 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1469 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1470 if (BITS_SET(phy_control, 1471 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1472 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1473 } 1474 1475 if (intel_power_well_is_enabled(display, cmn_d)) { 1476 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1477 1478 /* this assumes override is only used to enable lanes */ 1479 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1480 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1481 1482 if (BITS_SET(phy_control, 1483 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1484 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1485 1486 if (BITS_SET(phy_control, 1487 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1488 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1489 if (BITS_SET(phy_control, 1490 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1491 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1492 } 1493 1494 phy_status &= phy_status_mask; 1495 1496 /* 1497 * The PHY may be busy with some initial calibration and whatnot, 1498 * so the power state can take a while to actually change. 1499 */ 1500 if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS, 1501 phy_status_mask, phy_status, 10, &val)) 1502 drm_err(display->drm, 1503 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1504 val & phy_status_mask, phy_status, display->power.chv_phy_control); 1505 } 1506 1507 #undef BITS_SET 1508 1509 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1510 struct i915_power_well *power_well) 1511 { 1512 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1513 enum dpio_phy phy; 1514 u32 tmp; 1515 1516 drm_WARN_ON_ONCE(display->drm, 1517 id != VLV_DISP_PW_DPIO_CMN_BC && 1518 id != CHV_DISP_PW_DPIO_CMN_D); 1519 1520 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1521 phy = DPIO_PHY0; 1522 else 1523 phy = DPIO_PHY1; 1524 1525 /* since ref/cri clock was enabled */ 1526 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1527 vlv_set_power_well(display, power_well, true); 1528 1529 /* Poll for phypwrgood signal */ 1530 if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS, 1531 PHY_POWERGOOD(phy), 1)) 1532 drm_err(display->drm, "Display PHY %d is not power up\n", 1533 phy); 1534 1535 vlv_dpio_get(display); 1536 1537 /* Enable dynamic power down */ 1538 tmp = vlv_dpio_read(display, phy, CHV_CMN_DW28); 1539 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1540 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1541 vlv_dpio_write(display, phy, CHV_CMN_DW28, tmp); 1542 1543 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1544 tmp = vlv_dpio_read(display, phy, CHV_CMN_DW6_CH1); 1545 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1546 vlv_dpio_write(display, phy, CHV_CMN_DW6_CH1, tmp); 1547 } else { 1548 /* 1549 * Force the non-existing CL2 off. BXT does this 1550 * too, so maybe it saves some power even though 1551 * CL2 doesn't exist? 1552 */ 1553 tmp = vlv_dpio_read(display, phy, CHV_CMN_DW30); 1554 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1555 vlv_dpio_write(display, phy, CHV_CMN_DW30, tmp); 1556 } 1557 1558 vlv_dpio_put(display); 1559 1560 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1561 intel_de_write(display, DISPLAY_PHY_CONTROL, 1562 display->power.chv_phy_control); 1563 1564 drm_dbg_kms(display->drm, 1565 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1566 phy, display->power.chv_phy_control); 1567 1568 assert_chv_phy_status(display); 1569 } 1570 1571 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1572 struct i915_power_well *power_well) 1573 { 1574 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1575 enum dpio_phy phy; 1576 1577 drm_WARN_ON_ONCE(display->drm, 1578 id != VLV_DISP_PW_DPIO_CMN_BC && 1579 id != CHV_DISP_PW_DPIO_CMN_D); 1580 1581 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1582 phy = DPIO_PHY0; 1583 assert_pll_disabled(display, PIPE_A); 1584 assert_pll_disabled(display, PIPE_B); 1585 } else { 1586 phy = DPIO_PHY1; 1587 assert_pll_disabled(display, PIPE_C); 1588 } 1589 1590 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1591 intel_de_write(display, DISPLAY_PHY_CONTROL, 1592 display->power.chv_phy_control); 1593 1594 vlv_set_power_well(display, power_well, false); 1595 1596 drm_dbg_kms(display->drm, 1597 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1598 phy, display->power.chv_phy_control); 1599 1600 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1601 display->power.chv_phy_assert[phy] = true; 1602 1603 assert_chv_phy_status(display); 1604 } 1605 1606 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1607 enum dpio_channel ch, bool override, unsigned int mask) 1608 { 1609 u32 reg, val, expected, actual; 1610 1611 /* 1612 * The BIOS can leave the PHY is some weird state 1613 * where it doesn't fully power down some parts. 1614 * Disable the asserts until the PHY has been fully 1615 * reset (ie. the power well has been disabled at 1616 * least once). 1617 */ 1618 if (!display->power.chv_phy_assert[phy]) 1619 return; 1620 1621 if (ch == DPIO_CH0) 1622 reg = CHV_CMN_DW0_CH0; 1623 else 1624 reg = CHV_CMN_DW6_CH1; 1625 1626 vlv_dpio_get(display); 1627 val = vlv_dpio_read(display, phy, reg); 1628 vlv_dpio_put(display); 1629 1630 /* 1631 * This assumes !override is only used when the port is disabled. 1632 * All lanes should power down even without the override when 1633 * the port is disabled. 1634 */ 1635 if (!override || mask == 0xf) { 1636 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1637 /* 1638 * If CH1 common lane is not active anymore 1639 * (eg. for pipe B DPLL) the entire channel will 1640 * shut down, which causes the common lane registers 1641 * to read as 0. That means we can't actually check 1642 * the lane power down status bits, but as the entire 1643 * register reads as 0 it's a good indication that the 1644 * channel is indeed entirely powered down. 1645 */ 1646 if (ch == DPIO_CH1 && val == 0) 1647 expected = 0; 1648 } else if (mask != 0x0) { 1649 expected = DPIO_ANYDL_POWERDOWN; 1650 } else { 1651 expected = 0; 1652 } 1653 1654 if (ch == DPIO_CH0) 1655 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1656 DPIO_ALLDL_POWERDOWN_CH0, val); 1657 else 1658 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1659 DPIO_ALLDL_POWERDOWN_CH1, val); 1660 1661 drm_WARN(display->drm, actual != expected, 1662 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1663 !!(actual & DPIO_ALLDL_POWERDOWN), 1664 !!(actual & DPIO_ANYDL_POWERDOWN), 1665 !!(expected & DPIO_ALLDL_POWERDOWN), 1666 !!(expected & DPIO_ANYDL_POWERDOWN), 1667 reg, val); 1668 } 1669 1670 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1671 enum dpio_channel ch, bool override) 1672 { 1673 struct i915_power_domains *power_domains = &display->power.domains; 1674 bool was_override; 1675 1676 mutex_lock(&power_domains->lock); 1677 1678 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1679 1680 if (override == was_override) 1681 goto out; 1682 1683 if (override) 1684 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1685 else 1686 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1687 1688 intel_de_write(display, DISPLAY_PHY_CONTROL, 1689 display->power.chv_phy_control); 1690 1691 drm_dbg_kms(display->drm, 1692 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1693 phy, ch, display->power.chv_phy_control); 1694 1695 assert_chv_phy_status(display); 1696 1697 out: 1698 mutex_unlock(&power_domains->lock); 1699 1700 return was_override; 1701 } 1702 1703 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1704 bool override, unsigned int mask) 1705 { 1706 struct intel_display *display = to_intel_display(encoder); 1707 struct i915_power_domains *power_domains = &display->power.domains; 1708 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1709 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1710 1711 mutex_lock(&power_domains->lock); 1712 1713 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1714 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1715 1716 if (override) 1717 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1718 else 1719 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1720 1721 intel_de_write(display, DISPLAY_PHY_CONTROL, 1722 display->power.chv_phy_control); 1723 1724 drm_dbg_kms(display->drm, 1725 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1726 phy, ch, mask, display->power.chv_phy_control); 1727 1728 assert_chv_phy_status(display); 1729 1730 assert_chv_phy_powergate(display, phy, ch, override, mask); 1731 1732 mutex_unlock(&power_domains->lock); 1733 } 1734 1735 static bool chv_pipe_power_well_enabled(struct intel_display *display, 1736 struct i915_power_well *power_well) 1737 { 1738 enum pipe pipe = PIPE_A; 1739 bool enabled; 1740 u32 state, ctrl; 1741 1742 vlv_punit_get(display); 1743 1744 state = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1745 /* 1746 * We only ever set the power-on and power-gate states, anything 1747 * else is unexpected. 1748 */ 1749 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1750 state != DP_SSS_PWR_GATE(pipe)); 1751 enabled = state == DP_SSS_PWR_ON(pipe); 1752 1753 /* 1754 * A transient state at this point would mean some unexpected party 1755 * is poking at the power controls too. 1756 */ 1757 ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1758 drm_WARN_ON(display->drm, ctrl << 16 != state); 1759 1760 vlv_punit_put(display); 1761 1762 return enabled; 1763 } 1764 1765 static void chv_set_pipe_power_well(struct intel_display *display, 1766 struct i915_power_well *power_well, 1767 bool enable) 1768 { 1769 enum pipe pipe = PIPE_A; 1770 u32 state; 1771 u32 ctrl; 1772 int ret; 1773 1774 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1775 1776 vlv_punit_get(display); 1777 1778 ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 1779 if ((ctrl & DP_SSS_MASK(pipe)) == state) 1780 goto out; 1781 1782 ctrl &= ~DP_SSC_MASK(pipe); 1783 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1784 vlv_punit_write(display, PUNIT_REG_DSPSSPM, ctrl); 1785 1786 ret = poll_timeout_us(ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 1787 (ctrl & DP_SSS_MASK(pipe)) == state, 1788 500, 100 * 1000, false); 1789 if (ret) 1790 drm_err(display->drm, 1791 "timeout setting power well state %08x (%08x)\n", 1792 state, 1793 vlv_punit_read(display, PUNIT_REG_DSPSSPM)); 1794 1795 #undef COND 1796 1797 out: 1798 vlv_punit_put(display); 1799 } 1800 1801 static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1802 struct i915_power_well *power_well) 1803 { 1804 intel_de_write(display, DISPLAY_PHY_CONTROL, 1805 display->power.chv_phy_control); 1806 } 1807 1808 static void chv_pipe_power_well_enable(struct intel_display *display, 1809 struct i915_power_well *power_well) 1810 { 1811 chv_set_pipe_power_well(display, power_well, true); 1812 1813 vlv_display_power_well_init(display); 1814 } 1815 1816 static void chv_pipe_power_well_disable(struct intel_display *display, 1817 struct i915_power_well *power_well) 1818 { 1819 vlv_display_power_well_deinit(display); 1820 1821 chv_set_pipe_power_well(display, power_well, false); 1822 } 1823 1824 static void 1825 tgl_tc_cold_request(struct intel_display *display, bool block) 1826 { 1827 u8 tries = 0; 1828 int ret; 1829 1830 while (1) { 1831 u32 low_val; 1832 u32 high_val = 0; 1833 1834 if (block) 1835 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1836 else 1837 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1838 1839 /* 1840 * Spec states that we should timeout the request after 200us 1841 * but the function below will timeout after 500us 1842 */ 1843 ret = intel_parent_pcode_read(display, TGL_PCODE_TCCOLD, &low_val, &high_val); 1844 if (ret == 0) { 1845 if (block && 1846 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1847 ret = -EIO; 1848 else 1849 break; 1850 } 1851 1852 if (++tries == 3) 1853 break; 1854 1855 msleep(1); 1856 } 1857 1858 if (ret) 1859 drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un"); 1860 else 1861 drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n", 1862 block ? "" : "un"); 1863 } 1864 1865 static void 1866 tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1867 struct i915_power_well *power_well) 1868 { 1869 tgl_tc_cold_request(display, true); 1870 } 1871 1872 static void 1873 tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1874 struct i915_power_well *power_well) 1875 { 1876 tgl_tc_cold_request(display, false); 1877 } 1878 1879 static void 1880 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1881 struct i915_power_well *power_well) 1882 { 1883 if (intel_power_well_refcount(power_well) > 0) 1884 tgl_tc_cold_off_power_well_enable(display, power_well); 1885 else 1886 tgl_tc_cold_off_power_well_disable(display, power_well); 1887 } 1888 1889 static bool 1890 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1891 struct i915_power_well *power_well) 1892 { 1893 /* 1894 * Not the correctly implementation but there is no way to just read it 1895 * from PCODE, so returning count to avoid state mismatch errors 1896 */ 1897 return intel_power_well_refcount(power_well); 1898 } 1899 1900 static void xelpdp_aux_power_well_enable(struct intel_display *display, 1901 struct i915_power_well *power_well) 1902 { 1903 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1904 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1905 1906 if (icl_aux_pw_is_tc_phy(display, power_well)) 1907 icl_tc_port_assert_ref_held(display, power_well, 1908 aux_ch_to_digital_port(display, aux_ch)); 1909 1910 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1911 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1912 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1913 1914 if (HAS_LT_PHY(display)) { 1915 if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1916 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2)) 1917 drm_warn(display->drm, 1918 "Timeout waiting for PHY %c AUX channel power to be up\n", 1919 phy_name(phy)); 1920 } else { 1921 /* 1922 * The power status flag cannot be used to determine whether aux 1923 * power wells have finished powering up. Instead we're 1924 * expected to just wait a fixed 600us after raising the request 1925 * bit. 1926 */ 1927 usleep_range(600, 1200); 1928 } 1929 } 1930 1931 static void xelpdp_aux_power_well_disable(struct intel_display *display, 1932 struct i915_power_well *power_well) 1933 { 1934 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1935 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1936 1937 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1938 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1939 0); 1940 1941 if (HAS_LT_PHY(display)) { 1942 if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1943 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) 1944 drm_warn(display->drm, 1945 "Timeout waiting for PHY %c AUX channel to powerdown\n", 1946 phy_name(phy)); 1947 } else { 1948 usleep_range(10, 30); 1949 } 1950 } 1951 1952 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1953 struct i915_power_well *power_well) 1954 { 1955 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1956 1957 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1958 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1959 } 1960 1961 static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1962 struct i915_power_well *power_well) 1963 { 1964 intel_de_write(display, XE2LPD_PICA_PW_CTL, 1965 XE2LPD_PICA_CTL_POWER_REQUEST); 1966 1967 if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL, 1968 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1969 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1970 1971 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1972 } 1973 } 1974 1975 static void xe2lpd_pica_power_well_disable(struct intel_display *display, 1976 struct i915_power_well *power_well) 1977 { 1978 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 1979 1980 if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL, 1981 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1982 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 1983 1984 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 1985 } 1986 } 1987 1988 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 1989 struct i915_power_well *power_well) 1990 { 1991 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 1992 XE2LPD_PICA_CTL_POWER_STATUS; 1993 } 1994 1995 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1996 .sync_hw = i9xx_power_well_sync_hw_noop, 1997 .enable = i9xx_always_on_power_well_noop, 1998 .disable = i9xx_always_on_power_well_noop, 1999 .is_enabled = i9xx_always_on_power_well_enabled, 2000 }; 2001 2002 const struct i915_power_well_ops chv_pipe_power_well_ops = { 2003 .sync_hw = chv_pipe_power_well_sync_hw, 2004 .enable = chv_pipe_power_well_enable, 2005 .disable = chv_pipe_power_well_disable, 2006 .is_enabled = chv_pipe_power_well_enabled, 2007 }; 2008 2009 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 2010 .sync_hw = i9xx_power_well_sync_hw_noop, 2011 .enable = chv_dpio_cmn_power_well_enable, 2012 .disable = chv_dpio_cmn_power_well_disable, 2013 .is_enabled = vlv_power_well_enabled, 2014 }; 2015 2016 const struct i915_power_well_ops i830_pipes_power_well_ops = { 2017 .sync_hw = i830_pipes_power_well_sync_hw, 2018 .enable = i830_pipes_power_well_enable, 2019 .disable = i830_pipes_power_well_disable, 2020 .is_enabled = i830_pipes_power_well_enabled, 2021 }; 2022 2023 static const struct i915_power_well_regs hsw_power_well_regs = { 2024 .bios = HSW_PWR_WELL_CTL1, 2025 .driver = HSW_PWR_WELL_CTL2, 2026 .kvmr = HSW_PWR_WELL_CTL3, 2027 .debug = HSW_PWR_WELL_CTL4, 2028 }; 2029 2030 const struct i915_power_well_ops hsw_power_well_ops = { 2031 .regs = &hsw_power_well_regs, 2032 .sync_hw = hsw_power_well_sync_hw, 2033 .enable = hsw_power_well_enable, 2034 .disable = hsw_power_well_disable, 2035 .is_enabled = hsw_power_well_enabled, 2036 }; 2037 2038 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 2039 .sync_hw = i9xx_power_well_sync_hw_noop, 2040 .enable = gen9_dc_off_power_well_enable, 2041 .disable = gen9_dc_off_power_well_disable, 2042 .is_enabled = gen9_dc_off_power_well_enabled, 2043 }; 2044 2045 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 2046 .sync_hw = i9xx_power_well_sync_hw_noop, 2047 .enable = bxt_dpio_cmn_power_well_enable, 2048 .disable = bxt_dpio_cmn_power_well_disable, 2049 .is_enabled = bxt_dpio_cmn_power_well_enabled, 2050 }; 2051 2052 const struct i915_power_well_ops vlv_display_power_well_ops = { 2053 .sync_hw = i9xx_power_well_sync_hw_noop, 2054 .enable = vlv_display_power_well_enable, 2055 .disable = vlv_display_power_well_disable, 2056 .is_enabled = vlv_power_well_enabled, 2057 }; 2058 2059 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2060 .sync_hw = i9xx_power_well_sync_hw_noop, 2061 .enable = vlv_dpio_cmn_power_well_enable, 2062 .disable = vlv_dpio_cmn_power_well_disable, 2063 .is_enabled = vlv_power_well_enabled, 2064 }; 2065 2066 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2067 .sync_hw = i9xx_power_well_sync_hw_noop, 2068 .enable = vlv_power_well_enable, 2069 .disable = vlv_power_well_disable, 2070 .is_enabled = vlv_power_well_enabled, 2071 }; 2072 2073 static const struct i915_power_well_regs icl_aux_power_well_regs = { 2074 .bios = ICL_PWR_WELL_CTL_AUX1, 2075 .driver = ICL_PWR_WELL_CTL_AUX2, 2076 .debug = ICL_PWR_WELL_CTL_AUX4, 2077 }; 2078 2079 const struct i915_power_well_ops icl_aux_power_well_ops = { 2080 .regs = &icl_aux_power_well_regs, 2081 .sync_hw = hsw_power_well_sync_hw, 2082 .enable = icl_aux_power_well_enable, 2083 .disable = icl_aux_power_well_disable, 2084 .is_enabled = hsw_power_well_enabled, 2085 }; 2086 2087 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2088 .bios = ICL_PWR_WELL_CTL_DDI1, 2089 .driver = ICL_PWR_WELL_CTL_DDI2, 2090 .debug = ICL_PWR_WELL_CTL_DDI4, 2091 }; 2092 2093 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2094 .regs = &icl_ddi_power_well_regs, 2095 .sync_hw = hsw_power_well_sync_hw, 2096 .enable = hsw_power_well_enable, 2097 .disable = hsw_power_well_disable, 2098 .is_enabled = hsw_power_well_enabled, 2099 }; 2100 2101 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2102 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2103 .enable = tgl_tc_cold_off_power_well_enable, 2104 .disable = tgl_tc_cold_off_power_well_disable, 2105 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2106 }; 2107 2108 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2109 .sync_hw = i9xx_power_well_sync_hw_noop, 2110 .enable = xelpdp_aux_power_well_enable, 2111 .disable = xelpdp_aux_power_well_disable, 2112 .is_enabled = xelpdp_aux_power_well_enabled, 2113 }; 2114 2115 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2116 .sync_hw = i9xx_power_well_sync_hw_noop, 2117 .enable = xe2lpd_pica_power_well_enable, 2118 .disable = xe2lpd_pica_power_well_disable, 2119 .is_enabled = xe2lpd_pica_power_well_enabled, 2120 }; 2121