1 // SPDX-License-Identifier: GPL-2.0
2 // TLV320ADCX140 Sound driver
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4
5 #include <linux/module.h>
6 #include <linux/moduleparam.h>
7 #include <linux/init.h>
8 #include <linux/delay.h>
9 #include <linux/pm.h>
10 #include <linux/i2c.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/acpi.h>
14 #include <linux/of.h>
15 #include <linux/slab.h>
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
20 #include <sound/initval.h>
21 #include <sound/tlv.h>
22
23 #include "tlv320adcx140.h"
24
25 struct adcx140_priv {
26 struct regulator *supply_areg;
27 struct gpio_desc *gpio_reset;
28 struct regmap *regmap;
29 struct device *dev;
30
31 bool micbias_vg;
32 bool phase_calib_on;
33
34 unsigned int dai_fmt;
35 unsigned int slot_width;
36 };
37
38 static const char * const gpo_config_names[] = {
39 "ti,gpo-config-1",
40 "ti,gpo-config-2",
41 "ti,gpo-config-3",
42 "ti,gpo-config-4",
43 };
44
45 static const struct reg_default adcx140_reg_defaults[] = {
46 { ADCX140_PAGE_SELECT, 0x00 },
47 { ADCX140_SW_RESET, 0x00 },
48 { ADCX140_SLEEP_CFG, 0x00 },
49 { ADCX140_SHDN_CFG, 0x05 },
50 { ADCX140_ASI_CFG0, 0x30 },
51 { ADCX140_ASI_CFG1, 0x00 },
52 { ADCX140_ASI_CFG2, 0x00 },
53 { ADCX140_ASI_CH1, 0x00 },
54 { ADCX140_ASI_CH2, 0x01 },
55 { ADCX140_ASI_CH3, 0x02 },
56 { ADCX140_ASI_CH4, 0x03 },
57 { ADCX140_ASI_CH5, 0x04 },
58 { ADCX140_ASI_CH6, 0x05 },
59 { ADCX140_ASI_CH7, 0x06 },
60 { ADCX140_ASI_CH8, 0x07 },
61 { ADCX140_MST_CFG0, 0x02 },
62 { ADCX140_MST_CFG1, 0x48 },
63 { ADCX140_ASI_STS, 0xff },
64 { ADCX140_CLK_SRC, 0x10 },
65 { ADCX140_PDMCLK_CFG, 0x40 },
66 { ADCX140_PDM_CFG, 0x00 },
67 { ADCX140_GPIO_CFG0, 0x22 },
68 { ADCX140_GPO_CFG0, 0x00 },
69 { ADCX140_GPO_CFG1, 0x00 },
70 { ADCX140_GPO_CFG2, 0x00 },
71 { ADCX140_GPO_CFG3, 0x00 },
72 { ADCX140_GPO_VAL, 0x00 },
73 { ADCX140_GPIO_MON, 0x00 },
74 { ADCX140_GPI_CFG0, 0x00 },
75 { ADCX140_GPI_CFG1, 0x00 },
76 { ADCX140_GPI_MON, 0x00 },
77 { ADCX140_INT_CFG, 0x00 },
78 { ADCX140_INT_MASK0, 0xff },
79 { ADCX140_INT_LTCH0, 0x00 },
80 { ADCX140_BIAS_CFG, 0x00 },
81 { ADCX140_CH1_CFG0, 0x00 },
82 { ADCX140_CH1_CFG1, 0x00 },
83 { ADCX140_CH1_CFG2, 0xc9 },
84 { ADCX140_CH1_CFG3, 0x80 },
85 { ADCX140_CH1_CFG4, 0x00 },
86 { ADCX140_CH2_CFG0, 0x00 },
87 { ADCX140_CH2_CFG1, 0x00 },
88 { ADCX140_CH2_CFG2, 0xc9 },
89 { ADCX140_CH2_CFG3, 0x80 },
90 { ADCX140_CH2_CFG4, 0x00 },
91 { ADCX140_CH3_CFG0, 0x00 },
92 { ADCX140_CH3_CFG1, 0x00 },
93 { ADCX140_CH3_CFG2, 0xc9 },
94 { ADCX140_CH3_CFG3, 0x80 },
95 { ADCX140_CH3_CFG4, 0x00 },
96 { ADCX140_CH4_CFG0, 0x00 },
97 { ADCX140_CH4_CFG1, 0x00 },
98 { ADCX140_CH4_CFG2, 0xc9 },
99 { ADCX140_CH4_CFG3, 0x80 },
100 { ADCX140_CH4_CFG4, 0x00 },
101 { ADCX140_CH5_CFG2, 0xc9 },
102 { ADCX140_CH5_CFG3, 0x80 },
103 { ADCX140_CH5_CFG4, 0x00 },
104 { ADCX140_CH6_CFG2, 0xc9 },
105 { ADCX140_CH6_CFG3, 0x80 },
106 { ADCX140_CH6_CFG4, 0x00 },
107 { ADCX140_CH7_CFG2, 0xc9 },
108 { ADCX140_CH7_CFG3, 0x80 },
109 { ADCX140_CH7_CFG4, 0x00 },
110 { ADCX140_CH8_CFG2, 0xc9 },
111 { ADCX140_CH8_CFG3, 0x80 },
112 { ADCX140_CH8_CFG4, 0x00 },
113 { ADCX140_DSP_CFG0, 0x01 },
114 { ADCX140_DSP_CFG1, 0x40 },
115 { ADCX140_DRE_CFG0, 0x7b },
116 { ADCX140_AGC_CFG0, 0xe7 },
117 { ADCX140_IN_CH_EN, 0xf0 },
118 { ADCX140_ASI_OUT_CH_EN, 0x00 },
119 { ADCX140_PWR_CFG, 0x00 },
120 { ADCX140_DEV_STS0, 0x00 },
121 { ADCX140_DEV_STS1, 0x80 },
122 };
123
124 static const struct regmap_range_cfg adcx140_ranges[] = {
125 {
126 .range_min = 0,
127 .range_max = 12 * 128,
128 .selector_reg = ADCX140_PAGE_SELECT,
129 .selector_mask = 0xff,
130 .selector_shift = 0,
131 .window_start = 0,
132 .window_len = 128,
133 },
134 };
135
adcx140_volatile(struct device * dev,unsigned int reg)136 static bool adcx140_volatile(struct device *dev, unsigned int reg)
137 {
138 switch (reg) {
139 case ADCX140_SW_RESET:
140 case ADCX140_DEV_STS0:
141 case ADCX140_DEV_STS1:
142 case ADCX140_ASI_STS:
143 return true;
144 default:
145 return false;
146 }
147 }
148
149 static const struct regmap_config adcx140_i2c_regmap = {
150 .reg_bits = 8,
151 .val_bits = 8,
152 .reg_defaults = adcx140_reg_defaults,
153 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
154 .cache_type = REGCACHE_FLAT,
155 .ranges = adcx140_ranges,
156 .num_ranges = ARRAY_SIZE(adcx140_ranges),
157 .max_register = 12 * 128,
158 .volatile_reg = adcx140_volatile,
159 };
160
161 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
162 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
163
164 /* ADC gain. From 0 to 42 dB in 1 dB steps */
165 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
166
167 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
168 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
169 /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
170 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
171
172 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
173 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
174 /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
175 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
176
177 static const char * const decimation_filter_text[] = {
178 "Linear Phase", "Low Latency", "Ultra-low Latency"
179 };
180
181 static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
182 decimation_filter_text);
183
184 static const struct snd_kcontrol_new decimation_filter_controls[] = {
185 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
186 };
187
188 static const char * const pdmclk_text[] = {
189 "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
190 };
191
192 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
193 pdmclk_text);
194
195 static const struct snd_kcontrol_new pdmclk_div_controls[] = {
196 SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
197 };
198
199 static const char * const resistor_text[] = {
200 "2.5 kOhm", "10 kOhm", "20 kOhm"
201 };
202
203 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
204 resistor_text);
205 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
206 resistor_text);
207 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
208 resistor_text);
209 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
210 resistor_text);
211
212 static const struct snd_kcontrol_new in1_resistor_controls[] = {
213 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
214 };
215 static const struct snd_kcontrol_new in2_resistor_controls[] = {
216 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
217 };
218 static const struct snd_kcontrol_new in3_resistor_controls[] = {
219 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
220 };
221 static const struct snd_kcontrol_new in4_resistor_controls[] = {
222 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
223 };
224
225 /* Analog/Digital Selection */
226 static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
227 static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
228
229 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
230 ADCX140_CH1_CFG0, 5,
231 adcx140_mic_sel_text);
232
233 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
234 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
235
236 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
237 ADCX140_CH1_CFG0, 7,
238 adcx140_analog_sel_text);
239
240 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
241 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
242
243 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
244 ADCX140_CH1_CFG0, 5,
245 adcx140_mic_sel_text);
246
247 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
248 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
249
250 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
251 ADCX140_CH2_CFG0, 5,
252 adcx140_mic_sel_text);
253
254 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
255 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
256
257 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
258 ADCX140_CH2_CFG0, 7,
259 adcx140_analog_sel_text);
260
261 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
262 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
263
264 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
265 ADCX140_CH2_CFG0, 5,
266 adcx140_mic_sel_text);
267
268 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
269 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
270
271 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
272 ADCX140_CH3_CFG0, 5,
273 adcx140_mic_sel_text);
274
275 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
276 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
277
278 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
279 ADCX140_CH3_CFG0, 7,
280 adcx140_analog_sel_text);
281
282 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
283 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
284
285 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
286 ADCX140_CH3_CFG0, 5,
287 adcx140_mic_sel_text);
288
289 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
290 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
291
292 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
293 ADCX140_CH4_CFG0, 5,
294 adcx140_mic_sel_text);
295
296 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
297 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
298
299 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
300 ADCX140_CH4_CFG0, 7,
301 adcx140_analog_sel_text);
302
303 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
304 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
305
306 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
307 ADCX140_CH4_CFG0, 5,
308 adcx140_mic_sel_text);
309
310 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
311 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
312
313 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
314 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
315 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
316 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
317 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
318 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
319 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
320 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
321 static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
322 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
323 static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
324 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
325 static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
326 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
327 static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
328 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
329
330 static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
331 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
332 static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
333 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
334 static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
335 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
336 static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
337 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
338
339 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
340 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 1);
341
342 /* Output Mixer */
343 static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
344 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
345 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
346 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
347 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
348 };
349
350 static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
351 /* Analog Differential Inputs */
352 SND_SOC_DAPM_INPUT("MIC1P"),
353 SND_SOC_DAPM_INPUT("MIC1M"),
354 SND_SOC_DAPM_INPUT("MIC2P"),
355 SND_SOC_DAPM_INPUT("MIC2M"),
356 SND_SOC_DAPM_INPUT("MIC3P"),
357 SND_SOC_DAPM_INPUT("MIC3M"),
358 SND_SOC_DAPM_INPUT("MIC4P"),
359 SND_SOC_DAPM_INPUT("MIC4M"),
360
361 SND_SOC_DAPM_OUTPUT("CH1_OUT"),
362 SND_SOC_DAPM_OUTPUT("CH2_OUT"),
363 SND_SOC_DAPM_OUTPUT("CH3_OUT"),
364 SND_SOC_DAPM_OUTPUT("CH4_OUT"),
365 SND_SOC_DAPM_OUTPUT("CH5_OUT"),
366 SND_SOC_DAPM_OUTPUT("CH6_OUT"),
367 SND_SOC_DAPM_OUTPUT("CH7_OUT"),
368 SND_SOC_DAPM_OUTPUT("CH8_OUT"),
369
370 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
371 &adcx140_output_mixer_controls[0],
372 ARRAY_SIZE(adcx140_output_mixer_controls)),
373
374 /* Input Selection to MIC_PGA */
375 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
376 &adcx140_dapm_mic1p_control),
377 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
378 &adcx140_dapm_mic2p_control),
379 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
380 &adcx140_dapm_mic3p_control),
381 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
382 &adcx140_dapm_mic4p_control),
383
384 /* Input Selection to MIC_PGA */
385 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
386 &adcx140_dapm_mic1_analog_control),
387 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
388 &adcx140_dapm_mic2_analog_control),
389 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
390 &adcx140_dapm_mic3_analog_control),
391 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
392 &adcx140_dapm_mic4_analog_control),
393
394 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
395 &adcx140_dapm_mic1m_control),
396 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
397 &adcx140_dapm_mic2m_control),
398 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
399 &adcx140_dapm_mic3m_control),
400 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
401 &adcx140_dapm_mic4m_control),
402
403 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
404 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
405 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
406 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
407
408 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
409 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
410 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
411 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
412
413 SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
414 SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
415 SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
416 SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
417 SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
418 SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
419 SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
420 SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
421
422
423 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
424 &adcx140_dapm_ch1_en_switch),
425 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
426 &adcx140_dapm_ch2_en_switch),
427 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
428 &adcx140_dapm_ch3_en_switch),
429 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
430 &adcx140_dapm_ch4_en_switch),
431
432 SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
433 &adcx140_dapm_ch5_en_switch),
434 SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
435 &adcx140_dapm_ch6_en_switch),
436 SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
437 &adcx140_dapm_ch7_en_switch),
438 SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
439 &adcx140_dapm_ch8_en_switch),
440
441 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
442 &adcx140_dapm_dre_en_switch),
443
444 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
445 &adcx140_dapm_ch1_dre_en_switch),
446 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
447 &adcx140_dapm_ch2_dre_en_switch),
448 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
449 &adcx140_dapm_ch3_dre_en_switch),
450 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
451 &adcx140_dapm_ch4_dre_en_switch),
452
453 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
454 in1_resistor_controls),
455 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
456 in2_resistor_controls),
457 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
458 in3_resistor_controls),
459 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
460 in4_resistor_controls),
461
462 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
463 pdmclk_div_controls),
464
465 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
466 decimation_filter_controls),
467 };
468
469 static const struct snd_soc_dapm_route adcx140_audio_map[] = {
470 /* Outputs */
471 {"CH1_OUT", NULL, "Output Mixer"},
472 {"CH2_OUT", NULL, "Output Mixer"},
473 {"CH3_OUT", NULL, "Output Mixer"},
474 {"CH4_OUT", NULL, "Output Mixer"},
475
476 {"CH1_ASI_EN", "Switch", "CH1_ADC"},
477 {"CH2_ASI_EN", "Switch", "CH2_ADC"},
478 {"CH3_ASI_EN", "Switch", "CH3_ADC"},
479 {"CH4_ASI_EN", "Switch", "CH4_ADC"},
480
481 {"CH1_ASI_EN", "Switch", "CH1_DIG"},
482 {"CH2_ASI_EN", "Switch", "CH2_DIG"},
483 {"CH3_ASI_EN", "Switch", "CH3_DIG"},
484 {"CH4_ASI_EN", "Switch", "CH4_DIG"},
485 {"CH5_ASI_EN", "Switch", "CH5_DIG"},
486 {"CH6_ASI_EN", "Switch", "CH6_DIG"},
487 {"CH7_ASI_EN", "Switch", "CH7_DIG"},
488 {"CH8_ASI_EN", "Switch", "CH8_DIG"},
489
490 {"CH5_ASI_EN", "Switch", "CH5_OUT"},
491 {"CH6_ASI_EN", "Switch", "CH6_OUT"},
492 {"CH7_ASI_EN", "Switch", "CH7_OUT"},
493 {"CH8_ASI_EN", "Switch", "CH8_OUT"},
494
495 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
496 {"Decimation Filter", "Low Latency", "DRE_ENABLE"},
497 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
498
499 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
500 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
501 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
502 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
503
504 {"CH1_DRE_EN", "Switch", "CH1_ADC"},
505 {"CH2_DRE_EN", "Switch", "CH2_ADC"},
506 {"CH3_DRE_EN", "Switch", "CH3_ADC"},
507 {"CH4_DRE_EN", "Switch", "CH4_ADC"},
508
509 /* Mic input */
510 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
511 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
512 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
513 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
514
515 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
516 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
517 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
518 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
519 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
520 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
521 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
522 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
523
524 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
525 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
526 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
527
528 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
529 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
530 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
531
532 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
533 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
534 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
535
536 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
537 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
538 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
539
540 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
541 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
542 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
543
544 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
545 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
546 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
547
548 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
549 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
550 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
551
552 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
553 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
554 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
555
556 {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
557 {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
558 {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
559 {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
560
561 {"MIC1P Input Mux", NULL, "CH1_DIG"},
562 {"MIC1M Input Mux", NULL, "CH2_DIG"},
563 {"MIC2P Input Mux", NULL, "CH3_DIG"},
564 {"MIC2M Input Mux", NULL, "CH4_DIG"},
565 {"MIC3P Input Mux", NULL, "CH5_DIG"},
566 {"MIC3M Input Mux", NULL, "CH6_DIG"},
567 {"MIC4P Input Mux", NULL, "CH7_DIG"},
568 {"MIC4M Input Mux", NULL, "CH8_DIG"},
569
570 {"MIC1 Analog Mux", "Line In", "MIC1P"},
571 {"MIC2 Analog Mux", "Line In", "MIC2P"},
572 {"MIC3 Analog Mux", "Line In", "MIC3P"},
573 {"MIC4 Analog Mux", "Line In", "MIC4P"},
574
575 {"MIC1P Input Mux", "Analog", "MIC1P"},
576 {"MIC1M Input Mux", "Analog", "MIC1M"},
577 {"MIC2P Input Mux", "Analog", "MIC2P"},
578 {"MIC2M Input Mux", "Analog", "MIC2M"},
579 {"MIC3P Input Mux", "Analog", "MIC3P"},
580 {"MIC3M Input Mux", "Analog", "MIC3M"},
581 {"MIC4P Input Mux", "Analog", "MIC4P"},
582 {"MIC4M Input Mux", "Analog", "MIC4M"},
583
584 {"MIC1P Input Mux", "Digital", "MIC1P"},
585 {"MIC1M Input Mux", "Digital", "MIC1M"},
586 {"MIC2P Input Mux", "Digital", "MIC2P"},
587 {"MIC2M Input Mux", "Digital", "MIC2M"},
588 {"MIC3P Input Mux", "Digital", "MIC3P"},
589 {"MIC3M Input Mux", "Digital", "MIC3M"},
590 {"MIC4P Input Mux", "Digital", "MIC4P"},
591 {"MIC4M Input Mux", "Digital", "MIC4M"},
592 };
593
594 #define ADCX140_PHASE_CALIB_SWITCH(xname) {\
595 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
596 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
597 .info = adcx140_phase_calib_info, \
598 .get = adcx140_phase_calib_get, \
599 .put = adcx140_phase_calib_put}
600
adcx140_phase_calib_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)601 static int adcx140_phase_calib_info(struct snd_kcontrol *kcontrol,
602 struct snd_ctl_elem_info *uinfo)
603 {
604 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
605 uinfo->count = 1;
606 uinfo->value.integer.min = 0;
607 uinfo->value.integer.max = 1;
608 return 0;
609 }
610
adcx140_phase_calib_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * value)611 static int adcx140_phase_calib_get(struct snd_kcontrol *kcontrol,
612 struct snd_ctl_elem_value *value)
613 {
614 struct snd_soc_component *codec = snd_kcontrol_chip(kcontrol);
615 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
616
617 value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0;
618
619
620 return 0;
621 }
622
adcx140_phase_calib_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * value)623 static int adcx140_phase_calib_put(struct snd_kcontrol *kcontrol,
624 struct snd_ctl_elem_value *value)
625 {
626 struct snd_soc_component *codec = snd_kcontrol_chip(kcontrol);
627 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
628
629 bool v = value->value.integer.value[0] ? true : false;
630
631 if (adcx140->phase_calib_on != v) {
632 adcx140->phase_calib_on = v;
633 return 1;
634 }
635 return 0;
636 }
637
638 static const struct snd_kcontrol_new adcx140_snd_controls[] = {
639 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
640 adc_tlv),
641 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
642 adc_tlv),
643 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
644 adc_tlv),
645 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
646 adc_tlv),
647
648 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
649 dre_thresh_tlv),
650 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
651 dre_gain_tlv),
652
653 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
654 agc_thresh_tlv),
655 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
656 agc_gain_tlv),
657
658 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
659 0, 0xff, 0, dig_vol_tlv),
660 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
661 0, 0xff, 0, dig_vol_tlv),
662 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
663 0, 0xff, 0, dig_vol_tlv),
664 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
665 0, 0xff, 0, dig_vol_tlv),
666 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
667 0, 0xff, 0, dig_vol_tlv),
668 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
669 0, 0xff, 0, dig_vol_tlv),
670 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
671 0, 0xff, 0, dig_vol_tlv),
672 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
673 0, 0xff, 0, dig_vol_tlv),
674 ADCX140_PHASE_CALIB_SWITCH("Phase Calibration Switch"),
675 };
676
adcx140_reset(struct adcx140_priv * adcx140)677 static int adcx140_reset(struct adcx140_priv *adcx140)
678 {
679 int ret = 0;
680
681 if (adcx140->gpio_reset) {
682 gpiod_direction_output(adcx140->gpio_reset, 0);
683 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
684 usleep_range(30000, 100000);
685 gpiod_direction_output(adcx140->gpio_reset, 1);
686 } else {
687 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
688 ADCX140_RESET);
689 }
690
691 /* 8.4.2: wait >= 10 ms after entering sleep mode. */
692 usleep_range(10000, 100000);
693
694 return ret;
695 }
696
adcx140_pwr_ctrl(struct adcx140_priv * adcx140,bool power_state)697 static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
698 {
699 int pwr_ctrl = 0;
700 int ret = 0;
701
702 if (power_state)
703 pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
704
705 if (adcx140->micbias_vg && power_state)
706 pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
707
708 if (pwr_ctrl) {
709 ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB,
710 adcx140->phase_calib_on ? 0x00 : 0x40);
711 if (ret)
712 dev_err(adcx140->dev, "%s: register write error %d\n",
713 __func__, ret);
714 }
715
716 regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
717 ADCX140_PWR_CTRL_MSK, pwr_ctrl);
718 }
719
adcx140_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)720 static int adcx140_hw_params(struct snd_pcm_substream *substream,
721 struct snd_pcm_hw_params *params,
722 struct snd_soc_dai *dai)
723 {
724 struct snd_soc_component *component = dai->component;
725 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
726 u8 data = 0;
727
728 switch (params_physical_width(params)) {
729 case 16:
730 data = ADCX140_16_BIT_WORD;
731 break;
732 case 20:
733 data = ADCX140_20_BIT_WORD;
734 break;
735 case 24:
736 data = ADCX140_24_BIT_WORD;
737 break;
738 case 32:
739 data = ADCX140_32_BIT_WORD;
740 break;
741 default:
742 dev_err(component->dev, "%s: Unsupported width %d\n",
743 __func__, params_physical_width(params));
744 return -EINVAL;
745 }
746
747 adcx140_pwr_ctrl(adcx140, false);
748
749 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
750 ADCX140_WORD_LEN_MSK, data);
751
752 adcx140_pwr_ctrl(adcx140, true);
753
754 return 0;
755 }
756
adcx140_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)757 static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
758 unsigned int fmt)
759 {
760 struct snd_soc_component *component = codec_dai->component;
761 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
762 u8 iface_reg1 = 0;
763 u8 iface_reg2 = 0;
764 int offset = 0;
765 bool inverted_bclk = false;
766
767 /* set master/slave audio interface */
768 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
769 case SND_SOC_DAIFMT_CBP_CFP:
770 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
771 break;
772 case SND_SOC_DAIFMT_CBC_CFC:
773 break;
774 default:
775 dev_err(component->dev, "Invalid DAI clock provider\n");
776 return -EINVAL;
777 }
778
779 /* interface format */
780 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
781 case SND_SOC_DAIFMT_I2S:
782 iface_reg1 |= ADCX140_I2S_MODE_BIT;
783 break;
784 case SND_SOC_DAIFMT_LEFT_J:
785 iface_reg1 |= ADCX140_LEFT_JUST_BIT;
786 break;
787 case SND_SOC_DAIFMT_DSP_A:
788 offset = 1;
789 inverted_bclk = true;
790 break;
791 case SND_SOC_DAIFMT_DSP_B:
792 inverted_bclk = true;
793 break;
794 default:
795 dev_err(component->dev, "Invalid DAI interface format\n");
796 return -EINVAL;
797 }
798
799 /* signal polarity */
800 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
801 case SND_SOC_DAIFMT_IB_NF:
802 case SND_SOC_DAIFMT_IB_IF:
803 inverted_bclk = !inverted_bclk;
804 break;
805 case SND_SOC_DAIFMT_NB_IF:
806 iface_reg1 |= ADCX140_FSYNCINV_BIT;
807 break;
808 case SND_SOC_DAIFMT_NB_NF:
809 break;
810 default:
811 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
812 return -EINVAL;
813 }
814
815 if (inverted_bclk)
816 iface_reg1 |= ADCX140_BCLKINV_BIT;
817
818 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
819
820 adcx140_pwr_ctrl(adcx140, false);
821
822 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
823 ADCX140_FSYNCINV_BIT |
824 ADCX140_BCLKINV_BIT |
825 ADCX140_ASI_FORMAT_MSK,
826 iface_reg1);
827 snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
828 ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
829
830 /* Configure data offset */
831 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
832 ADCX140_TX_OFFSET_MASK, offset);
833
834 adcx140_pwr_ctrl(adcx140, true);
835
836 return 0;
837 }
838
adcx140_set_dai_tdm_slot(struct snd_soc_dai * codec_dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)839 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
840 unsigned int tx_mask, unsigned int rx_mask,
841 int slots, int slot_width)
842 {
843 struct snd_soc_component *component = codec_dai->component;
844 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
845
846 /*
847 * The chip itself supports arbitrary masks, but the driver currently
848 * only supports adjacent slots beginning at the first slot.
849 */
850 if (tx_mask != GENMASK(__fls(tx_mask), 0)) {
851 dev_err(component->dev, "Only lower adjacent slots are supported\n");
852 return -EINVAL;
853 }
854
855 switch (slot_width) {
856 case 16:
857 case 20:
858 case 24:
859 case 32:
860 break;
861 default:
862 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
863 return -EINVAL;
864 }
865
866 adcx140->slot_width = slot_width;
867
868 return 0;
869 }
870
871 static const struct snd_soc_dai_ops adcx140_dai_ops = {
872 .hw_params = adcx140_hw_params,
873 .set_fmt = adcx140_set_dai_fmt,
874 .set_tdm_slot = adcx140_set_dai_tdm_slot,
875 };
876
adcx140_configure_gpo(struct adcx140_priv * adcx140)877 static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
878 {
879 u32 gpo_outputs[ADCX140_NUM_GPOS];
880 u32 gpo_output_val = 0;
881 int ret;
882 int i;
883
884 for (i = 0; i < ADCX140_NUM_GPOS; i++) {
885 ret = device_property_read_u32_array(adcx140->dev,
886 gpo_config_names[i],
887 gpo_outputs,
888 ADCX140_NUM_GPO_CFGS);
889 if (ret)
890 continue;
891
892 if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
893 dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
894 return -EINVAL;
895 }
896
897 if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
898 dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
899 return -EINVAL;
900 }
901
902 gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
903 gpo_outputs[1];
904 ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
905 gpo_output_val);
906 if (ret)
907 return ret;
908 }
909
910 return 0;
911
912 }
913
adcx140_configure_gpio(struct adcx140_priv * adcx140)914 static int adcx140_configure_gpio(struct adcx140_priv *adcx140)
915 {
916 int gpio_count = 0;
917 u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS];
918 u32 gpio_output_val = 0;
919 int ret;
920
921 gpio_count = device_property_count_u32(adcx140->dev,
922 "ti,gpio-config");
923 if (gpio_count <= 0)
924 return 0;
925
926 if (gpio_count != ADCX140_NUM_GPIO_CFGS)
927 return -EINVAL;
928
929 ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
930 gpio_outputs, gpio_count);
931 if (ret)
932 return ret;
933
934 if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {
935 dev_err(adcx140->dev, "GPIO config out of range\n");
936 return -EINVAL;
937 }
938
939 if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {
940 dev_err(adcx140->dev, "GPIO drive out of range\n");
941 return -EINVAL;
942 }
943
944 gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT
945 | gpio_outputs[1];
946
947 return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
948 }
949
adcx140_codec_probe(struct snd_soc_component * component)950 static int adcx140_codec_probe(struct snd_soc_component *component)
951 {
952 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
953 int sleep_cfg_val = ADCX140_WAKE_DEV;
954 u32 bias_source;
955 u32 vref_source;
956 u8 bias_cfg;
957 int pdm_count;
958 u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
959 u32 pdm_edge_val = 0;
960 int gpi_count;
961 u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
962 u32 gpi_input_val = 0;
963 int i;
964 int ret;
965 bool tx_high_z;
966
967 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
968 &bias_source);
969 if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
970 bias_source = ADCX140_MIC_BIAS_VAL_VREF;
971 adcx140->micbias_vg = false;
972 } else {
973 adcx140->micbias_vg = true;
974 }
975
976 ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
977 &vref_source);
978 if (ret)
979 vref_source = ADCX140_MIC_BIAS_VREF_275V;
980
981 if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
982 dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
983 return -EINVAL;
984 }
985
986 bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
987
988 ret = adcx140_reset(adcx140);
989 if (ret)
990 goto out;
991
992 if (adcx140->supply_areg == NULL)
993 sleep_cfg_val |= ADCX140_AREG_INTERNAL;
994
995 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
996 if (ret) {
997 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
998 goto out;
999 }
1000
1001 /* 8.4.3: Wait >= 1ms after entering active mode. */
1002 usleep_range(1000, 100000);
1003
1004 pdm_count = device_property_count_u32(adcx140->dev,
1005 "ti,pdm-edge-select");
1006 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
1007 ret = device_property_read_u32_array(adcx140->dev,
1008 "ti,pdm-edge-select",
1009 pdm_edges, pdm_count);
1010 if (ret)
1011 return ret;
1012
1013 for (i = 0; i < pdm_count; i++)
1014 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
1015
1016 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
1017 pdm_edge_val);
1018 if (ret)
1019 return ret;
1020 }
1021
1022 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
1023 if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
1024 ret = device_property_read_u32_array(adcx140->dev,
1025 "ti,gpi-config",
1026 gpi_inputs, gpi_count);
1027 if (ret)
1028 return ret;
1029
1030 gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
1031 gpi_inputs[ADCX140_GPI2_INDEX];
1032
1033 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
1034 gpi_input_val);
1035 if (ret)
1036 return ret;
1037
1038 gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
1039 gpi_inputs[ADCX140_GPI4_INDEX];
1040
1041 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
1042 gpi_input_val);
1043 if (ret)
1044 return ret;
1045 }
1046
1047 ret = adcx140_configure_gpio(adcx140);
1048 if (ret)
1049 return ret;
1050
1051 ret = adcx140_configure_gpo(adcx140);
1052 if (ret)
1053 goto out;
1054
1055 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
1056 ADCX140_MIC_BIAS_VAL_MSK |
1057 ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
1058 if (ret)
1059 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
1060
1061 tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
1062 if (tx_high_z) {
1063 ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
1064 ADCX140_TX_FILL, ADCX140_TX_FILL);
1065 if (ret) {
1066 dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
1067 goto out;
1068 }
1069 }
1070
1071 adcx140_pwr_ctrl(adcx140, true);
1072 out:
1073 return ret;
1074 }
1075
adcx140_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1076 static int adcx140_set_bias_level(struct snd_soc_component *component,
1077 enum snd_soc_bias_level level)
1078 {
1079 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
1080
1081 switch (level) {
1082 case SND_SOC_BIAS_ON:
1083 case SND_SOC_BIAS_PREPARE:
1084 case SND_SOC_BIAS_STANDBY:
1085 adcx140_pwr_ctrl(adcx140, true);
1086 break;
1087 case SND_SOC_BIAS_OFF:
1088 adcx140_pwr_ctrl(adcx140, false);
1089 break;
1090 }
1091
1092 return 0;
1093 }
1094
1095 static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
1096 .probe = adcx140_codec_probe,
1097 .set_bias_level = adcx140_set_bias_level,
1098 .controls = adcx140_snd_controls,
1099 .num_controls = ARRAY_SIZE(adcx140_snd_controls),
1100 .dapm_widgets = adcx140_dapm_widgets,
1101 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets),
1102 .dapm_routes = adcx140_audio_map,
1103 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map),
1104 .suspend_bias_off = 1,
1105 .idle_bias_on = 0,
1106 .use_pmdown_time = 1,
1107 .endianness = 1,
1108 };
1109
1110 static struct snd_soc_dai_driver adcx140_dai_driver[] = {
1111 {
1112 .name = "tlv320adcx140-codec",
1113 .capture = {
1114 .stream_name = "Capture",
1115 .channels_min = 2,
1116 .channels_max = ADCX140_MAX_CHANNELS,
1117 .rates = ADCX140_RATES,
1118 .formats = ADCX140_FORMATS,
1119 },
1120 .ops = &adcx140_dai_ops,
1121 .symmetric_rate = 1,
1122 }
1123 };
1124
1125 #ifdef CONFIG_OF
1126 static const struct of_device_id tlv320adcx140_of_match[] = {
1127 { .compatible = "ti,tlv320adc3140" },
1128 { .compatible = "ti,tlv320adc5140" },
1129 { .compatible = "ti,tlv320adc6140" },
1130 {},
1131 };
1132 MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
1133 #endif
1134
adcx140_disable_regulator(void * arg)1135 static void adcx140_disable_regulator(void *arg)
1136 {
1137 struct adcx140_priv *adcx140 = arg;
1138
1139 regulator_disable(adcx140->supply_areg);
1140 }
1141
adcx140_i2c_probe(struct i2c_client * i2c)1142 static int adcx140_i2c_probe(struct i2c_client *i2c)
1143 {
1144 struct adcx140_priv *adcx140;
1145 int ret;
1146
1147 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
1148 if (!adcx140)
1149 return -ENOMEM;
1150
1151 adcx140->phase_calib_on = false;
1152 adcx140->dev = &i2c->dev;
1153
1154 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
1155 "reset", GPIOD_OUT_LOW);
1156 if (IS_ERR(adcx140->gpio_reset))
1157 return dev_err_probe(&i2c->dev, PTR_ERR(adcx140->gpio_reset),
1158 "Failed to get Reset GPIO\n");
1159 if (!adcx140->gpio_reset)
1160 dev_info(&i2c->dev, "Reset GPIO not defined\n");
1161
1162 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
1163 "areg");
1164 if (IS_ERR(adcx140->supply_areg)) {
1165 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
1166 return -EPROBE_DEFER;
1167
1168 adcx140->supply_areg = NULL;
1169 } else {
1170 ret = regulator_enable(adcx140->supply_areg);
1171 if (ret) {
1172 dev_err(adcx140->dev, "Failed to enable areg\n");
1173 return ret;
1174 }
1175
1176 ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);
1177 if (ret)
1178 return ret;
1179 }
1180
1181 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
1182 if (IS_ERR(adcx140->regmap)) {
1183 ret = PTR_ERR(adcx140->regmap);
1184 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1185 ret);
1186 return ret;
1187 }
1188
1189 i2c_set_clientdata(i2c, adcx140);
1190
1191 return devm_snd_soc_register_component(&i2c->dev,
1192 &soc_codec_driver_adcx140,
1193 adcx140_dai_driver, 1);
1194 }
1195
1196 static const struct i2c_device_id adcx140_i2c_id[] = {
1197 { "tlv320adc3140", 0 },
1198 { "tlv320adc5140", 1 },
1199 { "tlv320adc6140", 2 },
1200 {}
1201 };
1202 MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
1203
1204 static struct i2c_driver adcx140_i2c_driver = {
1205 .driver = {
1206 .name = "tlv320adcx140-codec",
1207 .of_match_table = of_match_ptr(tlv320adcx140_of_match),
1208 },
1209 .probe = adcx140_i2c_probe,
1210 .id_table = adcx140_i2c_id,
1211 };
1212 module_i2c_driver(adcx140_i2c_driver);
1213
1214 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1215 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
1216 MODULE_LICENSE("GPL v2");
1217