1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de 5 */ 6 7 #include <linux/cleanup.h> 8 #include <linux/delay.h> 9 #include <linux/slab.h> 10 #include <linux/init.h> 11 #include <linux/module.h> 12 #include <linux/mtd/mtd.h> 13 #include <linux/mtd/rawnand.h> 14 #include <linux/mtd/partitions.h> 15 #include <linux/interrupt.h> 16 #include <linux/device.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/err.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/completion.h> 23 #include <linux/of.h> 24 #include <linux/bitfield.h> 25 26 #define DRIVER_NAME "mxc_nand" 27 28 /* Addresses for NFC registers */ 29 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) 30 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) 31 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) 32 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) 33 #define NFC_V1_V2_CONFIG (host->regs + 0x0a) 34 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) 35 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) 36 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10) 37 #define NFC_V1_V2_WRPROT (host->regs + 0x12) 38 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) 39 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) 40 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) 41 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) 42 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) 43 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) 44 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) 45 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) 46 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) 47 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) 48 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) 49 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) 50 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) 51 52 #define NFC_V1_V2_ECC_STATUS_RESULT_ERM GENMASK(3, 2) 53 54 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) 55 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) 56 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) 57 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) 58 #define NFC_V1_V2_CONFIG1_BIG (1 << 5) 59 #define NFC_V1_V2_CONFIG1_RST (1 << 6) 60 #define NFC_V1_V2_CONFIG1_CE (1 << 7) 61 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) 62 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) 63 #define NFC_V2_CONFIG1_FP_INT (1 << 11) 64 65 #define NFC_V1_V2_CONFIG2_INT (1 << 15) 66 67 /* 68 * Operation modes for the NFC. Valid for v1, v2 and v3 69 * type controllers. 70 */ 71 #define NFC_CMD (1 << 0) 72 #define NFC_ADDR (1 << 1) 73 #define NFC_INPUT (1 << 2) 74 #define NFC_OUTPUT (1 << 3) 75 #define NFC_ID (1 << 4) 76 #define NFC_STATUS (1 << 5) 77 78 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) 79 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) 80 81 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) 82 #define NFC_V3_CONFIG1_SP_EN (1 << 0) 83 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) 84 85 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) 86 87 #define NFC_V3_LAUNCH (host->regs_axi + 0x40) 88 89 #define NFC_V3_WRPROT (host->regs_ip + 0x0) 90 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) 91 #define NFC_V3_WRPROT_LOCK (1 << 1) 92 #define NFC_V3_WRPROT_UNLOCK (1 << 2) 93 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) 94 95 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) 96 97 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) 98 #define NFC_V3_CONFIG2_PS_512 (0 << 0) 99 #define NFC_V3_CONFIG2_PS_2048 (1 << 0) 100 #define NFC_V3_CONFIG2_PS_4096 (2 << 0) 101 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) 102 #define NFC_V3_CONFIG2_ECC_EN (1 << 3) 103 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) 104 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) 105 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) 106 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) 107 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) 108 #define NFC_V3_CONFIG2_INT_MSK (1 << 15) 109 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) 110 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) 111 112 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) 113 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) 114 #define NFC_V3_CONFIG3_FW8 (1 << 3) 115 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) 116 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) 117 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) 118 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) 119 120 #define NFC_V3_IPC (host->regs_ip + 0x2C) 121 #define NFC_V3_IPC_CREQ (1 << 0) 122 #define NFC_V3_IPC_INT (1 << 31) 123 124 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) 125 126 struct mxc_nand_host; 127 128 struct mxc_nand_devtype_data { 129 void (*preset)(struct mtd_info *); 130 int (*read_page)(struct nand_chip *chip); 131 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); 132 void (*send_addr)(struct mxc_nand_host *, uint16_t, int); 133 void (*send_page)(struct mtd_info *, unsigned int); 134 void (*send_read_id)(struct mxc_nand_host *); 135 uint16_t (*get_dev_status)(struct mxc_nand_host *); 136 int (*check_int)(struct mxc_nand_host *); 137 void (*irq_control)(struct mxc_nand_host *, int); 138 u32 (*get_ecc_status)(struct nand_chip *); 139 const struct mtd_ooblayout_ops *ooblayout; 140 void (*select_chip)(struct nand_chip *chip, int cs); 141 int (*setup_interface)(struct nand_chip *chip, int csline, 142 const struct nand_interface_config *conf); 143 void (*enable_hwecc)(struct nand_chip *chip, bool enable); 144 145 /* 146 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked 147 * (CONFIG1:INT_MSK is set). To handle this the driver uses 148 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK 149 */ 150 int irqpending_quirk; 151 int needs_ip; 152 153 size_t regs_offset; 154 size_t spare0_offset; 155 size_t axi_offset; 156 157 int spare_len; 158 int eccbytes; 159 int eccsize; 160 int ppb_shift; 161 }; 162 163 struct mxc_nand_host { 164 struct nand_chip nand; 165 struct device *dev; 166 167 void __iomem *spare0; 168 void __iomem *main_area0; 169 170 void __iomem *base; 171 void __iomem *regs; 172 void __iomem *regs_axi; 173 void __iomem *regs_ip; 174 int status_request; 175 struct clk *clk; 176 int clk_act; 177 int irq; 178 int eccsize; 179 int used_oobsize; 180 int active_cs; 181 unsigned int ecc_stats_v1; 182 183 struct completion op_completion; 184 185 void *data_buf; 186 187 const struct mxc_nand_devtype_data *devtype_data; 188 }; 189 190 static const char * const part_probes[] = { 191 "cmdlinepart", "RedBoot", "ofpart", NULL }; 192 193 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) 194 { 195 int i; 196 u32 *t = trg; 197 const __iomem u32 *s = src; 198 199 for (i = 0; i < (size >> 2); i++) 200 *t++ = __raw_readl(s++); 201 } 202 203 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size) 204 { 205 int i; 206 u16 *t = trg; 207 const __iomem u16 *s = src; 208 209 /* We assume that src (IO) is always 32bit aligned */ 210 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) { 211 memcpy32_fromio(trg, src, size); 212 return; 213 } 214 215 for (i = 0; i < (size >> 1); i++) 216 *t++ = __raw_readw(s++); 217 } 218 219 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size) 220 { 221 /* __iowrite32_copy use 32bit size values so divide by 4 */ 222 __iowrite32_copy(trg, src, size / 4); 223 } 224 225 static void memcpy16_toio(void __iomem *trg, const void *src, int size) 226 { 227 int i; 228 __iomem u16 *t = trg; 229 const u16 *s = src; 230 231 /* We assume that trg (IO) is always 32bit aligned */ 232 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) { 233 memcpy32_toio(trg, src, size); 234 return; 235 } 236 237 for (i = 0; i < (size >> 1); i++) 238 __raw_writew(*s++, t++); 239 } 240 241 /* 242 * The controller splits a page into data chunks of 512 bytes + partial oob. 243 * There are writesize / 512 such chunks, the size of the partial oob parts is 244 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then 245 * contains additionally the byte lost by rounding (if any). 246 * This function handles the needed shuffling between host->data_buf (which 247 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes 248 * spare) and the NFC buffer. 249 */ 250 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf) 251 { 252 struct nand_chip *this = mtd_to_nand(mtd); 253 struct mxc_nand_host *host = nand_get_controller_data(this); 254 u16 i, oob_chunk_size; 255 u16 num_chunks = mtd->writesize / 512; 256 257 u8 *d = buf; 258 u8 __iomem *s = host->spare0; 259 u16 sparebuf_size = host->devtype_data->spare_len; 260 261 /* size of oob chunk for all but possibly the last one */ 262 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1; 263 264 if (bfrom) { 265 for (i = 0; i < num_chunks - 1; i++) 266 memcpy16_fromio(d + i * oob_chunk_size, 267 s + i * sparebuf_size, 268 oob_chunk_size); 269 270 /* the last chunk */ 271 memcpy16_fromio(d + i * oob_chunk_size, 272 s + i * sparebuf_size, 273 host->used_oobsize - i * oob_chunk_size); 274 } else { 275 for (i = 0; i < num_chunks - 1; i++) 276 memcpy16_toio(&s[i * sparebuf_size], 277 &d[i * oob_chunk_size], 278 oob_chunk_size); 279 280 /* the last chunk */ 281 memcpy16_toio(&s[i * sparebuf_size], 282 &d[i * oob_chunk_size], 283 host->used_oobsize - i * oob_chunk_size); 284 } 285 } 286 287 static int check_int_v3(struct mxc_nand_host *host) 288 { 289 uint32_t tmp; 290 291 tmp = readl(NFC_V3_IPC); 292 if (!(tmp & NFC_V3_IPC_INT)) 293 return 0; 294 295 tmp &= ~NFC_V3_IPC_INT; 296 writel(tmp, NFC_V3_IPC); 297 298 return 1; 299 } 300 301 static int check_int_v1_v2(struct mxc_nand_host *host) 302 { 303 uint32_t tmp; 304 305 tmp = readw(NFC_V1_V2_CONFIG2); 306 if (!(tmp & NFC_V1_V2_CONFIG2_INT)) 307 return 0; 308 309 if (!host->devtype_data->irqpending_quirk) 310 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); 311 312 return 1; 313 } 314 315 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) 316 { 317 uint16_t tmp; 318 319 tmp = readw(NFC_V1_V2_CONFIG1); 320 321 if (activate) 322 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; 323 else 324 tmp |= NFC_V1_V2_CONFIG1_INT_MSK; 325 326 writew(tmp, NFC_V1_V2_CONFIG1); 327 } 328 329 static void irq_control_v3(struct mxc_nand_host *host, int activate) 330 { 331 uint32_t tmp; 332 333 tmp = readl(NFC_V3_CONFIG2); 334 335 if (activate) 336 tmp &= ~NFC_V3_CONFIG2_INT_MSK; 337 else 338 tmp |= NFC_V3_CONFIG2_INT_MSK; 339 340 writel(tmp, NFC_V3_CONFIG2); 341 } 342 343 static void irq_control(struct mxc_nand_host *host, int activate) 344 { 345 if (host->devtype_data->irqpending_quirk) { 346 if (activate) 347 enable_irq(host->irq); 348 else 349 disable_irq_nosync(host->irq); 350 } else { 351 host->devtype_data->irq_control(host, activate); 352 } 353 } 354 355 static u32 get_ecc_status_v1(struct nand_chip *chip) 356 { 357 struct mtd_info *mtd = nand_to_mtd(chip); 358 struct mxc_nand_host *host = nand_get_controller_data(chip); 359 unsigned int ecc_stats, max_bitflips = 0; 360 int no_subpages, i; 361 362 no_subpages = mtd->writesize >> 9; 363 364 ecc_stats = host->ecc_stats_v1; 365 366 for (i = 0; i < no_subpages; i++) { 367 switch (ecc_stats & 0x3) { 368 case 0: 369 default: 370 break; 371 case 1: 372 mtd->ecc_stats.corrected++; 373 max_bitflips = 1; 374 break; 375 case 2: 376 mtd->ecc_stats.failed++; 377 break; 378 } 379 380 ecc_stats >>= 2; 381 } 382 383 return max_bitflips; 384 } 385 386 static u32 get_ecc_status_v2_v3(struct nand_chip *chip, unsigned int ecc_stat) 387 { 388 struct mtd_info *mtd = nand_to_mtd(chip); 389 struct mxc_nand_host *host = nand_get_controller_data(chip); 390 u8 ecc_bit_mask, err_limit; 391 unsigned int max_bitflips = 0; 392 int no_subpages, err; 393 394 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; 395 err_limit = (host->eccsize == 4) ? 0x4 : 0x8; 396 397 no_subpages = mtd->writesize >> 9; 398 399 do { 400 err = ecc_stat & ecc_bit_mask; 401 if (err > err_limit) { 402 mtd->ecc_stats.failed++; 403 } else { 404 mtd->ecc_stats.corrected += err; 405 max_bitflips = max_t(unsigned int, max_bitflips, err); 406 } 407 408 ecc_stat >>= 4; 409 } while (--no_subpages); 410 411 return max_bitflips; 412 } 413 414 static u32 get_ecc_status_v2(struct nand_chip *chip) 415 { 416 struct mxc_nand_host *host = nand_get_controller_data(chip); 417 418 u32 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT); 419 420 return get_ecc_status_v2_v3(chip, ecc_stat); 421 } 422 423 static u32 get_ecc_status_v3(struct nand_chip *chip) 424 { 425 struct mxc_nand_host *host = nand_get_controller_data(chip); 426 427 u32 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT); 428 429 return get_ecc_status_v2_v3(chip, ecc_stat); 430 } 431 432 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) 433 { 434 struct mxc_nand_host *host = dev_id; 435 436 if (!host->devtype_data->check_int(host)) 437 return IRQ_NONE; 438 439 irq_control(host, 0); 440 441 complete(&host->op_completion); 442 443 return IRQ_HANDLED; 444 } 445 446 /* This function polls the NANDFC to wait for the basic operation to 447 * complete by checking the INT bit of config2 register. 448 */ 449 static int wait_op_done(struct mxc_nand_host *host, int useirq) 450 { 451 int ret = 0; 452 453 /* 454 * If operation is already complete, don't bother to setup an irq or a 455 * loop. 456 */ 457 if (host->devtype_data->check_int(host)) 458 return 0; 459 460 if (useirq) { 461 unsigned long time_left; 462 463 reinit_completion(&host->op_completion); 464 465 irq_control(host, 1); 466 467 time_left = wait_for_completion_timeout(&host->op_completion, HZ); 468 if (!time_left && !host->devtype_data->check_int(host)) { 469 dev_dbg(host->dev, "timeout waiting for irq\n"); 470 ret = -ETIMEDOUT; 471 } 472 } else { 473 int max_retries = 8000; 474 int done; 475 476 do { 477 udelay(1); 478 479 done = host->devtype_data->check_int(host); 480 if (done) 481 break; 482 483 } while (--max_retries); 484 485 if (!done) { 486 dev_dbg(host->dev, "timeout polling for completion\n"); 487 ret = -ETIMEDOUT; 488 } 489 } 490 491 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq); 492 493 return ret; 494 } 495 496 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) 497 { 498 /* fill command */ 499 writel(cmd, NFC_V3_FLASH_CMD); 500 501 /* send out command */ 502 writel(NFC_CMD, NFC_V3_LAUNCH); 503 504 /* Wait for operation to complete */ 505 wait_op_done(host, useirq); 506 } 507 508 /* This function issues the specified command to the NAND device and 509 * waits for completion. */ 510 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) 511 { 512 dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq); 513 514 writew(cmd, NFC_V1_V2_FLASH_CMD); 515 writew(NFC_CMD, NFC_V1_V2_CONFIG2); 516 517 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { 518 int max_retries = 100; 519 /* Reset completion is indicated by NFC_CONFIG2 */ 520 /* being set to 0 */ 521 while (max_retries-- > 0) { 522 if (readw(NFC_V1_V2_CONFIG2) == 0) { 523 break; 524 } 525 udelay(1); 526 } 527 if (max_retries < 0) 528 dev_dbg(host->dev, "%s: RESET failed\n", __func__); 529 } else { 530 /* Wait for operation to complete */ 531 wait_op_done(host, useirq); 532 } 533 } 534 535 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) 536 { 537 /* fill address */ 538 writel(addr, NFC_V3_FLASH_ADDR0); 539 540 /* send out address */ 541 writel(NFC_ADDR, NFC_V3_LAUNCH); 542 543 wait_op_done(host, 0); 544 } 545 546 /* This function sends an address (or partial address) to the 547 * NAND device. The address is used to select the source/destination for 548 * a NAND command. */ 549 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) 550 { 551 dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast); 552 553 writew(addr, NFC_V1_V2_FLASH_ADDR); 554 writew(NFC_ADDR, NFC_V1_V2_CONFIG2); 555 556 /* Wait for operation to complete */ 557 wait_op_done(host, islast); 558 } 559 560 static void send_page_v3(struct mtd_info *mtd, unsigned int ops) 561 { 562 struct nand_chip *nand_chip = mtd_to_nand(mtd); 563 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 564 uint32_t tmp; 565 566 tmp = readl(NFC_V3_CONFIG1); 567 tmp &= ~(7 << 4); 568 writel(tmp, NFC_V3_CONFIG1); 569 570 /* transfer data from NFC ram to nand */ 571 writel(ops, NFC_V3_LAUNCH); 572 573 wait_op_done(host, false); 574 } 575 576 static void send_page_v2(struct mtd_info *mtd, unsigned int ops) 577 { 578 struct nand_chip *nand_chip = mtd_to_nand(mtd); 579 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 580 581 /* NANDFC buffer 0 is used for page read/write */ 582 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 583 584 writew(ops, NFC_V1_V2_CONFIG2); 585 586 /* Wait for operation to complete */ 587 wait_op_done(host, true); 588 } 589 590 static void send_page_v1(struct mtd_info *mtd, unsigned int ops) 591 { 592 struct nand_chip *nand_chip = mtd_to_nand(mtd); 593 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 594 int bufs, i; 595 596 if (mtd->writesize > 512) 597 bufs = 4; 598 else 599 bufs = 1; 600 601 for (i = 0; i < bufs; i++) { 602 603 /* NANDFC buffer 0 is used for page read/write */ 604 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); 605 606 writew(ops, NFC_V1_V2_CONFIG2); 607 608 /* Wait for operation to complete */ 609 wait_op_done(host, true); 610 } 611 } 612 613 static void send_read_id_v3(struct mxc_nand_host *host) 614 { 615 /* Read ID into main buffer */ 616 writel(NFC_ID, NFC_V3_LAUNCH); 617 618 wait_op_done(host, true); 619 620 memcpy32_fromio(host->data_buf, host->main_area0, 16); 621 } 622 623 /* Request the NANDFC to perform a read of the NAND device ID. */ 624 static void send_read_id_v1_v2(struct mxc_nand_host *host) 625 { 626 /* NANDFC buffer 0 is used for device ID output */ 627 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 628 629 writew(NFC_ID, NFC_V1_V2_CONFIG2); 630 631 /* Wait for operation to complete */ 632 wait_op_done(host, true); 633 634 memcpy32_fromio(host->data_buf, host->main_area0, 16); 635 } 636 637 static uint16_t get_dev_status_v3(struct mxc_nand_host *host) 638 { 639 writew(NFC_STATUS, NFC_V3_LAUNCH); 640 wait_op_done(host, true); 641 642 return readl(NFC_V3_CONFIG1) >> 16; 643 } 644 645 /* This function requests the NANDFC to perform a read of the 646 * NAND device status and returns the current status. */ 647 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) 648 { 649 void __iomem *main_buf = host->main_area0; 650 uint32_t store; 651 uint16_t ret; 652 653 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 654 655 /* 656 * The device status is stored in main_area0. To 657 * prevent corruption of the buffer save the value 658 * and restore it afterwards. 659 */ 660 store = readl(main_buf); 661 662 writew(NFC_STATUS, NFC_V1_V2_CONFIG2); 663 wait_op_done(host, true); 664 665 ret = readw(main_buf); 666 667 writel(store, main_buf); 668 669 return ret; 670 } 671 672 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable) 673 { 674 struct mxc_nand_host *host = nand_get_controller_data(chip); 675 uint16_t config1; 676 677 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 678 return; 679 680 config1 = readw(NFC_V1_V2_CONFIG1); 681 682 if (enable) 683 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 684 else 685 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN; 686 687 writew(config1, NFC_V1_V2_CONFIG1); 688 } 689 690 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable) 691 { 692 struct mxc_nand_host *host = nand_get_controller_data(chip); 693 uint32_t config2; 694 695 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 696 return; 697 698 config2 = readl(NFC_V3_CONFIG2); 699 700 if (enable) 701 config2 |= NFC_V3_CONFIG2_ECC_EN; 702 else 703 config2 &= ~NFC_V3_CONFIG2_ECC_EN; 704 705 writel(config2, NFC_V3_CONFIG2); 706 } 707 708 static int mxc_nand_read_page_v1(struct nand_chip *chip) 709 { 710 struct mtd_info *mtd = nand_to_mtd(chip); 711 struct mxc_nand_host *host = nand_get_controller_data(chip); 712 int no_subpages; 713 int i; 714 unsigned int ecc_stats = 0; 715 716 if (mtd->writesize) 717 no_subpages = mtd->writesize >> 9; 718 else 719 /* READ PARAMETER PAGE is called when mtd->writesize is not yet set */ 720 no_subpages = 1; 721 722 for (i = 0; i < no_subpages; i++) { 723 /* NANDFC buffer 0 is used for page read/write */ 724 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); 725 726 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2); 727 728 /* Wait for operation to complete */ 729 wait_op_done(host, true); 730 731 ecc_stats |= FIELD_GET(NFC_V1_V2_ECC_STATUS_RESULT_ERM, 732 readw(NFC_V1_V2_ECC_STATUS_RESULT)) << i * 2; 733 } 734 735 host->ecc_stats_v1 = ecc_stats; 736 737 return 0; 738 } 739 740 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip) 741 { 742 struct mtd_info *mtd = nand_to_mtd(chip); 743 struct mxc_nand_host *host = nand_get_controller_data(chip); 744 745 host->devtype_data->send_page(mtd, NFC_OUTPUT); 746 747 return 0; 748 } 749 750 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf, 751 int oob_required, int page) 752 { 753 struct mtd_info *mtd = nand_to_mtd(chip); 754 struct mxc_nand_host *host = nand_get_controller_data(chip); 755 int ret; 756 757 host->devtype_data->enable_hwecc(chip, true); 758 759 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); 760 761 host->devtype_data->enable_hwecc(chip, false); 762 763 if (ret) 764 return ret; 765 766 if (oob_required) 767 copy_spare(mtd, true, chip->oob_poi); 768 769 return host->devtype_data->get_ecc_status(chip); 770 } 771 772 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, 773 int oob_required, int page) 774 { 775 struct mtd_info *mtd = nand_to_mtd(chip); 776 int ret; 777 778 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); 779 if (ret) 780 return ret; 781 782 if (oob_required) 783 copy_spare(mtd, true, chip->oob_poi); 784 785 return 0; 786 } 787 788 static int mxc_nand_read_oob(struct nand_chip *chip, int page) 789 { 790 struct mtd_info *mtd = nand_to_mtd(chip); 791 struct mxc_nand_host *host = nand_get_controller_data(chip); 792 int ret; 793 794 ret = nand_read_page_op(chip, page, 0, host->data_buf, mtd->writesize); 795 if (ret) 796 return ret; 797 798 copy_spare(mtd, true, chip->oob_poi); 799 800 return 0; 801 } 802 803 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf, 804 int oob_required, int page) 805 { 806 struct mtd_info *mtd = nand_to_mtd(chip); 807 struct mxc_nand_host *host = nand_get_controller_data(chip); 808 int ret; 809 810 copy_spare(mtd, false, chip->oob_poi); 811 812 host->devtype_data->enable_hwecc(chip, true); 813 814 ret = nand_prog_page_op(chip, page, 0, buf, mtd->writesize); 815 816 host->devtype_data->enable_hwecc(chip, false); 817 818 return ret; 819 } 820 821 static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 822 int oob_required, int page) 823 { 824 struct mtd_info *mtd = nand_to_mtd(chip); 825 826 copy_spare(mtd, false, chip->oob_poi); 827 828 return nand_prog_page_op(chip, page, 0, buf, mtd->writesize); 829 } 830 831 static int mxc_nand_write_oob(struct nand_chip *chip, int page) 832 { 833 struct mtd_info *mtd = nand_to_mtd(chip); 834 struct mxc_nand_host *host = nand_get_controller_data(chip); 835 836 memset(host->data_buf, 0xff, mtd->writesize); 837 copy_spare(mtd, false, chip->oob_poi); 838 839 return nand_prog_page_op(chip, page, 0, host->data_buf, mtd->writesize); 840 } 841 842 /* This function is used by upper layer for select and 843 * deselect of the NAND chip */ 844 static void mxc_nand_select_chip_v1_v3(struct nand_chip *nand_chip, int chip) 845 { 846 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 847 848 if (chip == -1) { 849 /* Disable the NFC clock */ 850 if (host->clk_act) { 851 clk_disable_unprepare(host->clk); 852 host->clk_act = 0; 853 } 854 return; 855 } 856 857 if (!host->clk_act) { 858 /* Enable the NFC clock */ 859 clk_prepare_enable(host->clk); 860 host->clk_act = 1; 861 } 862 } 863 864 static void mxc_nand_select_chip_v2(struct nand_chip *nand_chip, int chip) 865 { 866 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 867 868 if (chip == -1) { 869 /* Disable the NFC clock */ 870 if (host->clk_act) { 871 clk_disable_unprepare(host->clk); 872 host->clk_act = 0; 873 } 874 return; 875 } 876 877 if (!host->clk_act) { 878 /* Enable the NFC clock */ 879 clk_prepare_enable(host->clk); 880 host->clk_act = 1; 881 } 882 883 host->active_cs = chip; 884 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 885 } 886 887 #define MXC_V1_ECCBYTES 5 888 889 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section, 890 struct mtd_oob_region *oobregion) 891 { 892 struct nand_chip *nand_chip = mtd_to_nand(mtd); 893 894 if (section >= nand_chip->ecc.steps) 895 return -ERANGE; 896 897 oobregion->offset = (section * 16) + 6; 898 oobregion->length = MXC_V1_ECCBYTES; 899 900 return 0; 901 } 902 903 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section, 904 struct mtd_oob_region *oobregion) 905 { 906 struct nand_chip *nand_chip = mtd_to_nand(mtd); 907 908 if (section > nand_chip->ecc.steps) 909 return -ERANGE; 910 911 if (!section) { 912 if (mtd->writesize <= 512) { 913 oobregion->offset = 0; 914 oobregion->length = 5; 915 } else { 916 oobregion->offset = 2; 917 oobregion->length = 4; 918 } 919 } else { 920 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6; 921 if (section < nand_chip->ecc.steps) 922 oobregion->length = (section * 16) + 6 - 923 oobregion->offset; 924 else 925 oobregion->length = mtd->oobsize - oobregion->offset; 926 } 927 928 return 0; 929 } 930 931 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = { 932 .ecc = mxc_v1_ooblayout_ecc, 933 .free = mxc_v1_ooblayout_free, 934 }; 935 936 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section, 937 struct mtd_oob_region *oobregion) 938 { 939 struct nand_chip *nand_chip = mtd_to_nand(mtd); 940 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; 941 942 if (section >= nand_chip->ecc.steps) 943 return -ERANGE; 944 945 oobregion->offset = (section * stepsize) + 7; 946 oobregion->length = nand_chip->ecc.bytes; 947 948 return 0; 949 } 950 951 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section, 952 struct mtd_oob_region *oobregion) 953 { 954 struct nand_chip *nand_chip = mtd_to_nand(mtd); 955 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; 956 957 if (section >= nand_chip->ecc.steps) 958 return -ERANGE; 959 960 if (!section) { 961 if (mtd->writesize <= 512) { 962 oobregion->offset = 0; 963 oobregion->length = 5; 964 } else { 965 oobregion->offset = 2; 966 oobregion->length = 4; 967 } 968 } else { 969 oobregion->offset = section * stepsize; 970 oobregion->length = 7; 971 } 972 973 return 0; 974 } 975 976 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = { 977 .ecc = mxc_v2_ooblayout_ecc, 978 .free = mxc_v2_ooblayout_free, 979 }; 980 981 /* 982 * v2 and v3 type controllers can do 4bit or 8bit ecc depending 983 * on how much oob the nand chip has. For 8bit ecc we need at least 984 * 26 bytes of oob data per 512 byte block. 985 */ 986 static int get_eccsize(struct mtd_info *mtd) 987 { 988 int oobbytes_per_512 = 0; 989 990 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; 991 992 if (oobbytes_per_512 < 26) 993 return 4; 994 else 995 return 8; 996 } 997 998 static void preset_v1(struct mtd_info *mtd) 999 { 1000 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1001 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1002 uint16_t config1 = 0; 1003 1004 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST && 1005 mtd->writesize) 1006 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1007 1008 if (!host->devtype_data->irqpending_quirk) 1009 config1 |= NFC_V1_V2_CONFIG1_INT_MSK; 1010 1011 host->eccsize = 1; 1012 1013 writew(config1, NFC_V1_V2_CONFIG1); 1014 /* preset operation */ 1015 1016 /* Unlock the internal RAM Buffer */ 1017 writew(0x2, NFC_V1_V2_CONFIG); 1018 1019 /* Blocks to be unlocked */ 1020 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); 1021 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); 1022 1023 /* Unlock Block Command for given address range */ 1024 writew(0x4, NFC_V1_V2_WRPROT); 1025 } 1026 1027 static int mxc_nand_v2_setup_interface(struct nand_chip *chip, int csline, 1028 const struct nand_interface_config *conf) 1029 { 1030 struct mxc_nand_host *host = nand_get_controller_data(chip); 1031 int tRC_min_ns, tRC_ps, ret; 1032 unsigned long rate, rate_round; 1033 const struct nand_sdr_timings *timings; 1034 u16 config1; 1035 1036 timings = nand_get_sdr_timings(conf); 1037 if (IS_ERR(timings)) 1038 return -ENOTSUPP; 1039 1040 config1 = readw(NFC_V1_V2_CONFIG1); 1041 1042 tRC_min_ns = timings->tRC_min / 1000; 1043 rate = 1000000000 / tRC_min_ns; 1044 1045 /* 1046 * For tRC < 30ns we have to use EDO mode. In this case the controller 1047 * does one access per clock cycle. Otherwise the controller does one 1048 * access in two clock cycles, thus we have to double the rate to the 1049 * controller. 1050 */ 1051 if (tRC_min_ns < 30) { 1052 rate_round = clk_round_rate(host->clk, rate); 1053 config1 |= NFC_V2_CONFIG1_ONE_CYCLE; 1054 tRC_ps = 1000000000 / (rate_round / 1000); 1055 } else { 1056 rate *= 2; 1057 rate_round = clk_round_rate(host->clk, rate); 1058 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE; 1059 tRC_ps = 1000000000 / (rate_round / 1000 / 2); 1060 } 1061 1062 /* 1063 * The timing values compared against are from the i.MX25 Automotive 1064 * datasheet, Table 50. NFC Timing Parameters 1065 */ 1066 if (timings->tCLS_min > tRC_ps - 1000 || 1067 timings->tCLH_min > tRC_ps - 2000 || 1068 timings->tCS_min > tRC_ps - 1000 || 1069 timings->tCH_min > tRC_ps - 2000 || 1070 timings->tWP_min > tRC_ps - 1500 || 1071 timings->tALS_min > tRC_ps || 1072 timings->tALH_min > tRC_ps - 3000 || 1073 timings->tDS_min > tRC_ps || 1074 timings->tDH_min > tRC_ps - 5000 || 1075 timings->tWC_min > 2 * tRC_ps || 1076 timings->tWH_min > tRC_ps - 2500 || 1077 timings->tRR_min > 6 * tRC_ps || 1078 timings->tRP_min > 3 * tRC_ps / 2 || 1079 timings->tRC_min > 2 * tRC_ps || 1080 timings->tREH_min > (tRC_ps / 2) - 2500) { 1081 dev_dbg(host->dev, "Timing out of bounds\n"); 1082 return -EINVAL; 1083 } 1084 1085 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1086 return 0; 1087 1088 ret = clk_set_rate(host->clk, rate); 1089 if (ret) 1090 return ret; 1091 1092 writew(config1, NFC_V1_V2_CONFIG1); 1093 1094 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round, 1095 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" : 1096 "normal"); 1097 1098 return 0; 1099 } 1100 1101 static void preset_v2(struct mtd_info *mtd) 1102 { 1103 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1104 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1105 uint16_t config1 = 0; 1106 1107 config1 |= NFC_V2_CONFIG1_FP_INT; 1108 1109 if (!host->devtype_data->irqpending_quirk) 1110 config1 |= NFC_V1_V2_CONFIG1_INT_MSK; 1111 1112 if (mtd->writesize) { 1113 uint16_t pages_per_block = mtd->erasesize / mtd->writesize; 1114 1115 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1116 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1117 1118 host->eccsize = get_eccsize(mtd); 1119 if (host->eccsize == 4) 1120 config1 |= NFC_V2_CONFIG1_ECC_MODE_4; 1121 1122 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); 1123 } else { 1124 host->eccsize = 1; 1125 } 1126 1127 writew(config1, NFC_V1_V2_CONFIG1); 1128 /* preset operation */ 1129 1130 /* spare area size in 16-bit half-words */ 1131 writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA); 1132 1133 /* Unlock the internal RAM Buffer */ 1134 writew(0x2, NFC_V1_V2_CONFIG); 1135 1136 /* Blocks to be unlocked */ 1137 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); 1138 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); 1139 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); 1140 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); 1141 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); 1142 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); 1143 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); 1144 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); 1145 1146 /* Unlock Block Command for given address range */ 1147 writew(0x4, NFC_V1_V2_WRPROT); 1148 } 1149 1150 static void preset_v3(struct mtd_info *mtd) 1151 { 1152 struct nand_chip *chip = mtd_to_nand(mtd); 1153 struct mxc_nand_host *host = nand_get_controller_data(chip); 1154 uint32_t config2, config3; 1155 int i, addr_phases; 1156 1157 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); 1158 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); 1159 1160 /* Unlock the internal RAM Buffer */ 1161 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, 1162 NFC_V3_WRPROT); 1163 1164 /* Blocks to be unlocked */ 1165 for (i = 0; i < NAND_MAX_CHIPS; i++) 1166 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); 1167 1168 writel(0, NFC_V3_IPC); 1169 1170 config2 = NFC_V3_CONFIG2_ONE_CYCLE | 1171 NFC_V3_CONFIG2_2CMD_PHASES | 1172 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | 1173 NFC_V3_CONFIG2_ST_CMD(0x70) | 1174 NFC_V3_CONFIG2_INT_MSK | 1175 NFC_V3_CONFIG2_NUM_ADDR_PHASE0; 1176 1177 addr_phases = fls(chip->pagemask) >> 3; 1178 1179 if (mtd->writesize == 2048) { 1180 config2 |= NFC_V3_CONFIG2_PS_2048; 1181 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); 1182 } else if (mtd->writesize == 4096) { 1183 config2 |= NFC_V3_CONFIG2_PS_4096; 1184 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); 1185 } else { 1186 config2 |= NFC_V3_CONFIG2_PS_512; 1187 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); 1188 } 1189 1190 if (mtd->writesize) { 1191 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1192 config2 |= NFC_V3_CONFIG2_ECC_EN; 1193 1194 config2 |= NFC_V3_CONFIG2_PPB( 1195 ffs(mtd->erasesize / mtd->writesize) - 6, 1196 host->devtype_data->ppb_shift); 1197 host->eccsize = get_eccsize(mtd); 1198 if (host->eccsize == 8) 1199 config2 |= NFC_V3_CONFIG2_ECC_MODE_8; 1200 } 1201 1202 writel(config2, NFC_V3_CONFIG2); 1203 1204 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | 1205 NFC_V3_CONFIG3_NO_SDMA | 1206 NFC_V3_CONFIG3_RBB_MODE | 1207 NFC_V3_CONFIG3_SBB(6) | /* Reset default */ 1208 NFC_V3_CONFIG3_ADD_OP(0); 1209 1210 if (!(chip->options & NAND_BUSWIDTH_16)) 1211 config3 |= NFC_V3_CONFIG3_FW8; 1212 1213 writel(config3, NFC_V3_CONFIG3); 1214 1215 writel(0, NFC_V3_DELAY_LINE); 1216 } 1217 1218 /* 1219 * The generic flash bbt descriptors overlap with our ecc 1220 * hardware, so define some i.MX specific ones. 1221 */ 1222 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; 1223 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; 1224 1225 static struct nand_bbt_descr bbt_main_descr = { 1226 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 1227 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1228 .offs = 0, 1229 .len = 4, 1230 .veroffs = 4, 1231 .maxblocks = 4, 1232 .pattern = bbt_pattern, 1233 }; 1234 1235 static struct nand_bbt_descr bbt_mirror_descr = { 1236 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 1237 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1238 .offs = 0, 1239 .len = 4, 1240 .veroffs = 4, 1241 .maxblocks = 4, 1242 .pattern = mirror_pattern, 1243 }; 1244 1245 /* v1 + irqpending_quirk: i.MX21 */ 1246 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { 1247 .preset = preset_v1, 1248 .read_page = mxc_nand_read_page_v1, 1249 .send_cmd = send_cmd_v1_v2, 1250 .send_addr = send_addr_v1_v2, 1251 .send_page = send_page_v1, 1252 .send_read_id = send_read_id_v1_v2, 1253 .get_dev_status = get_dev_status_v1_v2, 1254 .check_int = check_int_v1_v2, 1255 .irq_control = irq_control_v1_v2, 1256 .get_ecc_status = get_ecc_status_v1, 1257 .ooblayout = &mxc_v1_ooblayout_ops, 1258 .select_chip = mxc_nand_select_chip_v1_v3, 1259 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1260 .irqpending_quirk = 1, 1261 .needs_ip = 0, 1262 .regs_offset = 0xe00, 1263 .spare0_offset = 0x800, 1264 .spare_len = 16, 1265 .eccbytes = 3, 1266 .eccsize = 1, 1267 }; 1268 1269 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ 1270 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { 1271 .preset = preset_v1, 1272 .read_page = mxc_nand_read_page_v1, 1273 .send_cmd = send_cmd_v1_v2, 1274 .send_addr = send_addr_v1_v2, 1275 .send_page = send_page_v1, 1276 .send_read_id = send_read_id_v1_v2, 1277 .get_dev_status = get_dev_status_v1_v2, 1278 .check_int = check_int_v1_v2, 1279 .irq_control = irq_control_v1_v2, 1280 .get_ecc_status = get_ecc_status_v1, 1281 .ooblayout = &mxc_v1_ooblayout_ops, 1282 .select_chip = mxc_nand_select_chip_v1_v3, 1283 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1284 .irqpending_quirk = 0, 1285 .needs_ip = 0, 1286 .regs_offset = 0xe00, 1287 .spare0_offset = 0x800, 1288 .axi_offset = 0, 1289 .spare_len = 16, 1290 .eccbytes = 3, 1291 .eccsize = 1, 1292 }; 1293 1294 /* v21: i.MX25, i.MX35 */ 1295 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { 1296 .preset = preset_v2, 1297 .read_page = mxc_nand_read_page_v2_v3, 1298 .send_cmd = send_cmd_v1_v2, 1299 .send_addr = send_addr_v1_v2, 1300 .send_page = send_page_v2, 1301 .send_read_id = send_read_id_v1_v2, 1302 .get_dev_status = get_dev_status_v1_v2, 1303 .check_int = check_int_v1_v2, 1304 .irq_control = irq_control_v1_v2, 1305 .get_ecc_status = get_ecc_status_v2, 1306 .ooblayout = &mxc_v2_ooblayout_ops, 1307 .select_chip = mxc_nand_select_chip_v2, 1308 .setup_interface = mxc_nand_v2_setup_interface, 1309 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1310 .irqpending_quirk = 0, 1311 .needs_ip = 0, 1312 .regs_offset = 0x1e00, 1313 .spare0_offset = 0x1000, 1314 .axi_offset = 0, 1315 .spare_len = 64, 1316 .eccbytes = 9, 1317 .eccsize = 0, 1318 }; 1319 1320 /* v3.2a: i.MX51 */ 1321 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { 1322 .preset = preset_v3, 1323 .read_page = mxc_nand_read_page_v2_v3, 1324 .send_cmd = send_cmd_v3, 1325 .send_addr = send_addr_v3, 1326 .send_page = send_page_v3, 1327 .send_read_id = send_read_id_v3, 1328 .get_dev_status = get_dev_status_v3, 1329 .check_int = check_int_v3, 1330 .irq_control = irq_control_v3, 1331 .get_ecc_status = get_ecc_status_v3, 1332 .ooblayout = &mxc_v2_ooblayout_ops, 1333 .select_chip = mxc_nand_select_chip_v1_v3, 1334 .enable_hwecc = mxc_nand_enable_hwecc_v3, 1335 .irqpending_quirk = 0, 1336 .needs_ip = 1, 1337 .regs_offset = 0, 1338 .spare0_offset = 0x1000, 1339 .axi_offset = 0x1e00, 1340 .spare_len = 64, 1341 .eccbytes = 0, 1342 .eccsize = 0, 1343 .ppb_shift = 7, 1344 }; 1345 1346 /* v3.2b: i.MX53 */ 1347 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { 1348 .preset = preset_v3, 1349 .read_page = mxc_nand_read_page_v2_v3, 1350 .send_cmd = send_cmd_v3, 1351 .send_addr = send_addr_v3, 1352 .send_page = send_page_v3, 1353 .send_read_id = send_read_id_v3, 1354 .get_dev_status = get_dev_status_v3, 1355 .check_int = check_int_v3, 1356 .irq_control = irq_control_v3, 1357 .get_ecc_status = get_ecc_status_v3, 1358 .ooblayout = &mxc_v2_ooblayout_ops, 1359 .select_chip = mxc_nand_select_chip_v1_v3, 1360 .enable_hwecc = mxc_nand_enable_hwecc_v3, 1361 .irqpending_quirk = 0, 1362 .needs_ip = 1, 1363 .regs_offset = 0, 1364 .spare0_offset = 0x1000, 1365 .axi_offset = 0x1e00, 1366 .spare_len = 64, 1367 .eccbytes = 0, 1368 .eccsize = 0, 1369 .ppb_shift = 8, 1370 }; 1371 1372 static inline int is_imx21_nfc(struct mxc_nand_host *host) 1373 { 1374 return host->devtype_data == &imx21_nand_devtype_data; 1375 } 1376 1377 static inline int is_imx27_nfc(struct mxc_nand_host *host) 1378 { 1379 return host->devtype_data == &imx27_nand_devtype_data; 1380 } 1381 1382 static inline int is_imx25_nfc(struct mxc_nand_host *host) 1383 { 1384 return host->devtype_data == &imx25_nand_devtype_data; 1385 } 1386 1387 static const struct of_device_id mxcnd_dt_ids[] = { 1388 { .compatible = "fsl,imx21-nand", .data = &imx21_nand_devtype_data, }, 1389 { .compatible = "fsl,imx27-nand", .data = &imx27_nand_devtype_data, }, 1390 { .compatible = "fsl,imx25-nand", .data = &imx25_nand_devtype_data, }, 1391 { .compatible = "fsl,imx51-nand", .data = &imx51_nand_devtype_data, }, 1392 { .compatible = "fsl,imx53-nand", .data = &imx53_nand_devtype_data, }, 1393 { /* sentinel */ } 1394 }; 1395 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids); 1396 1397 static int mxcnd_attach_chip(struct nand_chip *chip) 1398 { 1399 struct mtd_info *mtd = nand_to_mtd(chip); 1400 struct mxc_nand_host *host = nand_get_controller_data(chip); 1401 struct device *dev = mtd->dev.parent; 1402 1403 chip->ecc.bytes = host->devtype_data->eccbytes; 1404 host->eccsize = host->devtype_data->eccsize; 1405 chip->ecc.size = 512; 1406 1407 switch (chip->ecc.engine_type) { 1408 case NAND_ECC_ENGINE_TYPE_ON_HOST: 1409 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout); 1410 chip->ecc.read_page = mxc_nand_read_page; 1411 chip->ecc.read_page_raw = mxc_nand_read_page_raw; 1412 chip->ecc.read_oob = mxc_nand_read_oob; 1413 chip->ecc.write_page = mxc_nand_write_page_ecc; 1414 chip->ecc.write_page_raw = mxc_nand_write_page_raw; 1415 chip->ecc.write_oob = mxc_nand_write_oob; 1416 break; 1417 1418 case NAND_ECC_ENGINE_TYPE_SOFT: 1419 chip->ecc.write_page_raw = nand_monolithic_write_page_raw; 1420 chip->ecc.read_page_raw = nand_monolithic_read_page_raw; 1421 break; 1422 1423 default: 1424 return -EINVAL; 1425 } 1426 1427 if (chip->bbt_options & NAND_BBT_USE_FLASH) { 1428 chip->bbt_td = &bbt_main_descr; 1429 chip->bbt_md = &bbt_mirror_descr; 1430 } 1431 1432 /* Allocate the right size buffer now */ 1433 devm_kfree(dev, (void *)host->data_buf); 1434 host->data_buf = devm_kzalloc(dev, mtd->writesize + mtd->oobsize, 1435 GFP_KERNEL); 1436 if (!host->data_buf) 1437 return -ENOMEM; 1438 1439 /* Call preset again, with correct writesize chip time */ 1440 host->devtype_data->preset(mtd); 1441 1442 if (!chip->ecc.bytes) { 1443 if (host->eccsize == 8) 1444 chip->ecc.bytes = 18; 1445 else if (host->eccsize == 4) 1446 chip->ecc.bytes = 9; 1447 } 1448 1449 /* 1450 * Experimentation shows that i.MX NFC can only handle up to 218 oob 1451 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare() 1452 * into copying invalid data to/from the spare IO buffer, as this 1453 * might cause ECC data corruption when doing sub-page write to a 1454 * partially written page. 1455 */ 1456 host->used_oobsize = min(mtd->oobsize, 218U); 1457 1458 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 1459 if (is_imx21_nfc(host) || is_imx27_nfc(host)) 1460 chip->ecc.strength = 1; 1461 else 1462 chip->ecc.strength = (host->eccsize == 4) ? 4 : 8; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static int mxcnd_setup_interface(struct nand_chip *chip, int chipnr, 1469 const struct nand_interface_config *conf) 1470 { 1471 struct mxc_nand_host *host = nand_get_controller_data(chip); 1472 1473 return host->devtype_data->setup_interface(chip, chipnr, conf); 1474 } 1475 1476 static void memff16_toio(void *buf, int n) 1477 { 1478 __iomem u16 *t = buf; 1479 int i; 1480 1481 for (i = 0; i < (n >> 1); i++) 1482 __raw_writew(0xffff, t++); 1483 } 1484 1485 static void copy_page_to_sram(struct mtd_info *mtd, const void *buf, int buf_len) 1486 { 1487 struct nand_chip *this = mtd_to_nand(mtd); 1488 struct mxc_nand_host *host = nand_get_controller_data(this); 1489 unsigned int no_subpages = mtd->writesize / 512; 1490 int oob_per_subpage, i; 1491 1492 oob_per_subpage = (mtd->oobsize / no_subpages) & ~1; 1493 1494 /* 1495 * During a page write the i.MX NAND controller will read 512b from 1496 * main_area0 SRAM, then oob_per_subpage bytes from spare0 SRAM, then 1497 * 512b from main_area1 SRAM and so on until the full page is written. 1498 * For software ECC we want to have a 1:1 mapping between the raw page 1499 * data on the NAND chip and the view of the NAND core. This is 1500 * necessary to make the NAND_CMD_RNDOUT read the data it expects. 1501 * To accomplish this we have to write the data in the order the controller 1502 * reads it. This is reversed in copy_page_from_sram() below. 1503 * 1504 * buf_len can either be the full page including the OOB or user data only. 1505 * When it's user data only make sure that we fill up the rest of the 1506 * SRAM with 0xff. 1507 */ 1508 for (i = 0; i < no_subpages; i++) { 1509 int now = min(buf_len, 512); 1510 1511 if (now) 1512 memcpy16_toio(host->main_area0 + i * 512, buf, now); 1513 1514 if (now < 512) 1515 memff16_toio(host->main_area0 + i * 512 + now, 512 - now); 1516 1517 buf += 512; 1518 buf_len -= now; 1519 1520 now = min(buf_len, oob_per_subpage); 1521 if (now) 1522 memcpy16_toio(host->spare0 + i * host->devtype_data->spare_len, 1523 buf, now); 1524 1525 if (now < oob_per_subpage) 1526 memff16_toio(host->spare0 + i * host->devtype_data->spare_len + now, 1527 oob_per_subpage - now); 1528 1529 buf += oob_per_subpage; 1530 buf_len -= now; 1531 } 1532 } 1533 1534 static void copy_page_from_sram(struct mtd_info *mtd) 1535 { 1536 struct nand_chip *this = mtd_to_nand(mtd); 1537 struct mxc_nand_host *host = nand_get_controller_data(this); 1538 void *buf = host->data_buf; 1539 unsigned int no_subpages = mtd->writesize / 512; 1540 int oob_per_subpage, i; 1541 1542 /* mtd->writesize is not set during ident scanning */ 1543 if (!no_subpages) 1544 no_subpages = 1; 1545 1546 oob_per_subpage = (mtd->oobsize / no_subpages) & ~1; 1547 1548 for (i = 0; i < no_subpages; i++) { 1549 memcpy16_fromio(buf, host->main_area0 + i * 512, 512); 1550 buf += 512; 1551 1552 memcpy16_fromio(buf, host->spare0 + i * host->devtype_data->spare_len, 1553 oob_per_subpage); 1554 buf += oob_per_subpage; 1555 } 1556 } 1557 1558 static int mxcnd_do_exec_op(struct nand_chip *chip, 1559 const struct nand_subop *op) 1560 { 1561 struct mxc_nand_host *host = nand_get_controller_data(chip); 1562 struct mtd_info *mtd = nand_to_mtd(chip); 1563 int i, j, buf_len; 1564 void *buf_read = NULL; 1565 const void *buf_write = NULL; 1566 const struct nand_op_instr *instr; 1567 bool readid = false; 1568 bool statusreq = false; 1569 1570 for (i = 0; i < op->ninstrs; i++) { 1571 instr = &op->instrs[i]; 1572 1573 switch (instr->type) { 1574 case NAND_OP_WAITRDY_INSTR: 1575 /* NFC handles R/B internally, nothing to do here */ 1576 break; 1577 case NAND_OP_CMD_INSTR: 1578 host->devtype_data->send_cmd(host, instr->ctx.cmd.opcode, true); 1579 1580 if (instr->ctx.cmd.opcode == NAND_CMD_READID) 1581 readid = true; 1582 if (instr->ctx.cmd.opcode == NAND_CMD_STATUS) 1583 statusreq = true; 1584 1585 break; 1586 case NAND_OP_ADDR_INSTR: 1587 for (j = 0; j < instr->ctx.addr.naddrs; j++) { 1588 bool islast = j == instr->ctx.addr.naddrs - 1; 1589 host->devtype_data->send_addr(host, instr->ctx.addr.addrs[j], islast); 1590 } 1591 break; 1592 case NAND_OP_DATA_OUT_INSTR: 1593 buf_write = instr->ctx.data.buf.out; 1594 buf_len = instr->ctx.data.len; 1595 1596 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1597 memcpy32_toio(host->main_area0, buf_write, buf_len); 1598 else 1599 copy_page_to_sram(mtd, buf_write, buf_len); 1600 1601 host->devtype_data->send_page(mtd, NFC_INPUT); 1602 1603 break; 1604 case NAND_OP_DATA_IN_INSTR: 1605 1606 buf_read = instr->ctx.data.buf.in; 1607 buf_len = instr->ctx.data.len; 1608 1609 if (readid) { 1610 host->devtype_data->send_read_id(host); 1611 readid = false; 1612 1613 memcpy32_fromio(host->data_buf, host->main_area0, buf_len * 2); 1614 1615 if (chip->options & NAND_BUSWIDTH_16) { 1616 u8 *bufr = buf_read; 1617 u16 *bufw = host->data_buf; 1618 for (j = 0; j < buf_len; j++) 1619 bufr[j] = bufw[j]; 1620 } else { 1621 memcpy(buf_read, host->data_buf, buf_len); 1622 } 1623 break; 1624 } 1625 1626 if (statusreq) { 1627 *(u8*)buf_read = host->devtype_data->get_dev_status(host); 1628 statusreq = false; 1629 break; 1630 } 1631 1632 host->devtype_data->read_page(chip); 1633 1634 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 1635 if (IS_ALIGNED(buf_len, 4)) { 1636 memcpy32_fromio(buf_read, host->main_area0, buf_len); 1637 } else { 1638 memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize); 1639 memcpy(buf_read, host->data_buf, buf_len); 1640 } 1641 } else { 1642 copy_page_from_sram(mtd); 1643 memcpy(buf_read, host->data_buf, buf_len); 1644 } 1645 1646 break; 1647 } 1648 } 1649 1650 return 0; 1651 } 1652 1653 #define MAX_DATA_SIZE (4096 + 512) 1654 1655 static const struct nand_op_parser mxcnd_op_parser = NAND_OP_PARSER( 1656 NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op, 1657 NAND_OP_PARSER_PAT_CMD_ELEM(false), 1658 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7), 1659 NAND_OP_PARSER_PAT_CMD_ELEM(true), 1660 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 1661 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, MAX_DATA_SIZE)), 1662 NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op, 1663 NAND_OP_PARSER_PAT_CMD_ELEM(false), 1664 NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7), 1665 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE), 1666 NAND_OP_PARSER_PAT_CMD_ELEM(false), 1667 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 1668 NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op, 1669 NAND_OP_PARSER_PAT_CMD_ELEM(false), 1670 NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7), 1671 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE), 1672 NAND_OP_PARSER_PAT_CMD_ELEM(true), 1673 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 1674 ); 1675 1676 static int mxcnd_exec_op(struct nand_chip *chip, 1677 const struct nand_operation *op, bool check_only) 1678 { 1679 return nand_op_parser_exec_op(chip, &mxcnd_op_parser, 1680 op, check_only); 1681 } 1682 1683 static const struct nand_controller_ops mxcnd_controller_ops = { 1684 .attach_chip = mxcnd_attach_chip, 1685 .setup_interface = mxcnd_setup_interface, 1686 .exec_op = mxcnd_exec_op, 1687 }; 1688 1689 static int mxcnd_probe(struct platform_device *pdev) 1690 { 1691 struct nand_chip *this; 1692 struct mtd_info *mtd; 1693 struct mxc_nand_host *host; 1694 int err = 0; 1695 1696 /* Allocate memory for MTD device structure and private data */ 1697 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host), 1698 GFP_KERNEL); 1699 if (!host) 1700 return -ENOMEM; 1701 1702 /* allocate a temporary buffer for the nand_scan_ident() */ 1703 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL); 1704 if (!host->data_buf) 1705 return -ENOMEM; 1706 1707 host->dev = &pdev->dev; 1708 /* structures must be linked */ 1709 this = &host->nand; 1710 mtd = nand_to_mtd(this); 1711 mtd->dev.parent = &pdev->dev; 1712 mtd->name = DRIVER_NAME; 1713 1714 /* 50 us command delay time */ 1715 this->legacy.chip_delay = 5; 1716 1717 nand_set_controller_data(this, host); 1718 1719 struct device_node *np __free(device_node) = 1720 of_get_next_child_with_prefix(pdev->dev.of_node, NULL, "nand"); 1721 1722 if (np) 1723 nand_set_flash_node(this, np); 1724 else 1725 nand_set_flash_node(this, pdev->dev.of_node); 1726 1727 host->clk = devm_clk_get(&pdev->dev, NULL); 1728 if (IS_ERR(host->clk)) 1729 return PTR_ERR(host->clk); 1730 1731 host->devtype_data = device_get_match_data(&pdev->dev); 1732 1733 if (!host->devtype_data->setup_interface) 1734 this->options |= NAND_KEEP_TIMINGS; 1735 1736 if (host->devtype_data->needs_ip) { 1737 host->regs_ip = devm_platform_ioremap_resource(pdev, 0); 1738 if (IS_ERR(host->regs_ip)) 1739 return PTR_ERR(host->regs_ip); 1740 1741 host->base = devm_platform_ioremap_resource(pdev, 1); 1742 } else { 1743 host->base = devm_platform_ioremap_resource(pdev, 0); 1744 } 1745 1746 if (IS_ERR(host->base)) 1747 return PTR_ERR(host->base); 1748 1749 host->main_area0 = host->base; 1750 1751 if (host->devtype_data->regs_offset) 1752 host->regs = host->base + host->devtype_data->regs_offset; 1753 host->spare0 = host->base + host->devtype_data->spare0_offset; 1754 if (host->devtype_data->axi_offset) 1755 host->regs_axi = host->base + host->devtype_data->axi_offset; 1756 1757 this->legacy.select_chip = host->devtype_data->select_chip; 1758 1759 init_completion(&host->op_completion); 1760 1761 host->irq = platform_get_irq(pdev, 0); 1762 if (host->irq < 0) 1763 return host->irq; 1764 1765 /* 1766 * Use host->devtype_data->irq_control() here instead of irq_control() 1767 * because we must not disable_irq_nosync without having requested the 1768 * irq. 1769 */ 1770 host->devtype_data->irq_control(host, 0); 1771 1772 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, 1773 0, DRIVER_NAME, host); 1774 if (err) 1775 return err; 1776 1777 err = clk_prepare_enable(host->clk); 1778 if (err) 1779 return err; 1780 host->clk_act = 1; 1781 1782 /* 1783 * Now that we "own" the interrupt make sure the interrupt mask bit is 1784 * cleared on i.MX21. Otherwise we can't read the interrupt status bit 1785 * on this machine. 1786 */ 1787 if (host->devtype_data->irqpending_quirk) { 1788 disable_irq_nosync(host->irq); 1789 host->devtype_data->irq_control(host, 1); 1790 } 1791 1792 /* Scan the NAND device */ 1793 this->legacy.dummy_controller.ops = &mxcnd_controller_ops; 1794 err = nand_scan(this, is_imx25_nfc(host) ? 4 : 1); 1795 if (err) 1796 goto escan; 1797 1798 /* Register the partitions */ 1799 err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0); 1800 if (err) 1801 goto cleanup_nand; 1802 1803 platform_set_drvdata(pdev, host); 1804 1805 return 0; 1806 1807 cleanup_nand: 1808 nand_cleanup(this); 1809 escan: 1810 if (host->clk_act) 1811 clk_disable_unprepare(host->clk); 1812 1813 return err; 1814 } 1815 1816 static void mxcnd_remove(struct platform_device *pdev) 1817 { 1818 struct mxc_nand_host *host = platform_get_drvdata(pdev); 1819 struct nand_chip *chip = &host->nand; 1820 int ret; 1821 1822 ret = mtd_device_unregister(nand_to_mtd(chip)); 1823 WARN_ON(ret); 1824 nand_cleanup(chip); 1825 if (host->clk_act) 1826 clk_disable_unprepare(host->clk); 1827 } 1828 1829 static struct platform_driver mxcnd_driver = { 1830 .driver = { 1831 .name = DRIVER_NAME, 1832 .of_match_table = mxcnd_dt_ids, 1833 }, 1834 .probe = mxcnd_probe, 1835 .remove = mxcnd_remove, 1836 }; 1837 module_platform_driver(mxcnd_driver); 1838 1839 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1840 MODULE_DESCRIPTION("MXC NAND MTD driver"); 1841 MODULE_LICENSE("GPL"); 1842