1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * isst_tpmi.c: SST TPMI interface core
4 *
5 * Copyright (c) 2023, Intel Corporation.
6 * All Rights Reserved.
7 *
8 * This information will be useful to understand flows:
9 * In the current generation of platforms, TPMI is supported via OOB
10 * PCI device. This PCI device has one instance per CPU package.
11 * There is a unique TPMI ID for SST. Each TPMI ID also has multiple
12 * entries, representing per power domain information.
13 *
14 * There is one dev file for complete SST information and control same as the
15 * prior generation of hardware. User spaces don't need to know how the
16 * information is presented by the hardware. The TPMI core module implements
17 * the hardware mapping.
18 */
19
20 #define dev_fmt(fmt) "tpmi_sst: " fmt
21
22 #include <linux/auxiliary_bus.h>
23 #include <linux/delay.h>
24 #include <linux/intel_tpmi.h>
25 #include <linux/intel_vsec.h>
26 #include <linux/fs.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/minmax.h>
30 #include <linux/module.h>
31 #include <asm/msr.h>
32 #include <uapi/linux/isst_if.h>
33
34 #include "isst_tpmi_core.h"
35 #include "isst_if_common.h"
36
37 /* Supported SST hardware version by this driver */
38 #define ISST_MAJOR_VERSION 0
39 #define ISST_MINOR_VERSION 2
40
41 /*
42 * Used to indicate if value read from MMIO needs to get multiplied
43 * to get to a standard unit or not.
44 */
45 #define SST_MUL_FACTOR_NONE 1
46
47 /* Define 100 as a scaling factor frequency ratio to frequency conversion */
48 #define SST_MUL_FACTOR_FREQ 100
49
50 /* All SST regs are 64 bit size */
51 #define SST_REG_SIZE 8
52
53 /**
54 * struct sst_header - SST main header
55 * @interface_version: Version number for this interface
56 * @cap_mask: Bitmask of the supported sub features. 1=the sub feature is enabled.
57 * 0=disabled.
58 * Bit[8]= SST_CP enable (1), disable (0)
59 * bit[9]= SST_PP enable (1), disable (0)
60 * other bits are reserved for future use
61 * @cp_offset: Qword (8 bytes) offset to the SST_CP register bank
62 * @pp_offset: Qword (8 bytes) offset to the SST_PP register bank
63 * @reserved: Reserved for future use
64 *
65 * This register allows SW to discover SST capability and the offsets to SST-CP
66 * and SST-PP register banks.
67 */
68 struct sst_header {
69 u8 interface_version;
70 u8 cap_mask;
71 u8 cp_offset;
72 u8 pp_offset;
73 u32 reserved;
74 } __packed;
75
76 /**
77 * struct cp_header - SST-CP (core-power) header
78 * @feature_id: 0=SST-CP, 1=SST-PP, 2=SST-BF, 3=SST-TF
79 * @feature_rev: Interface Version number for this SST feature
80 * @ratio_unit: Frequency ratio unit. 00: 100MHz. All others are reserved
81 * @reserved: Reserved for future use
82 *
83 * This structure is used store SST-CP header. This is packed to the same
84 * format as defined in the specifications.
85 */
86 struct cp_header {
87 u64 feature_id :4;
88 u64 feature_rev :8;
89 u64 ratio_unit :2;
90 u64 reserved :50;
91 } __packed;
92
93 /**
94 * struct pp_header - SST-PP (Perf profile) header
95 * @feature_id: 0=SST-CP, 1=SST-PP, 2=SST-BF, 3=SST-TF
96 * @feature_rev: Interface Version number for this SST feature
97 * @level_en_mask: SST-PP level enable/disable fuse mask
98 * @allowed_level_mask: Allowed level mask used for dynamic config level switching
99 * @reserved0: Reserved for future use
100 * @ratio_unit: Frequency ratio unit. 00: 100MHz. All others are reserved
101 * @block_size: Size of PP block in Qword unit (8 bytes)
102 * @dynamic_switch: If set (1), dynamic switching of SST PP is supported
103 * @memory_ratio_unit: Memory Controller frequency ratio unit. 00: 100MHz, others reserved
104 * @reserved1: Reserved for future use
105 *
106 * This structure is used store SST-PP header. This is packed to the same
107 * format as defined in the specifications.
108 */
109 struct pp_header {
110 u64 feature_id :4;
111 u64 feature_rev :8;
112 u64 level_en_mask :8;
113 u64 allowed_level_mask :8;
114 u64 reserved0 :4;
115 u64 ratio_unit :2;
116 u64 block_size :8;
117 u64 dynamic_switch :1;
118 u64 memory_ratio_unit :2;
119 u64 reserved1 :19;
120 } __packed;
121
122 /**
123 * struct feature_offset - Offsets to SST-PP features
124 * @pp_offset: Qword offset within PP level for the SST_PP register bank
125 * @bf_offset: Qword offset within PP level for the SST_BF register bank
126 * @tf_offset: Qword offset within PP level for the SST_TF register bank
127 * @reserved: Reserved for future use
128 *
129 * This structure is used store offsets for SST features in the register bank.
130 * This is packed to the same format as defined in the specifications.
131 */
132 struct feature_offset {
133 u64 pp_offset :8;
134 u64 bf_offset :8;
135 u64 tf_offset :8;
136 u64 reserved :40;
137 } __packed;
138
139 /**
140 * struct levels_offset - Offsets to each SST PP level
141 * @sst_pp_level0_offset: Qword offset to the register block of PP level 0
142 * @sst_pp_level1_offset: Qword offset to the register block of PP level 1
143 * @sst_pp_level2_offset: Qword offset to the register block of PP level 2
144 * @sst_pp_level3_offset: Qword offset to the register block of PP level 3
145 * @sst_pp_level4_offset: Qword offset to the register block of PP level 4
146 * @reserved: Reserved for future use
147 *
148 * This structure is used store offsets of SST PP levels in the register bank.
149 * This is packed to the same format as defined in the specifications.
150 */
151 struct levels_offset {
152 u64 sst_pp_level0_offset :8;
153 u64 sst_pp_level1_offset :8;
154 u64 sst_pp_level2_offset :8;
155 u64 sst_pp_level3_offset :8;
156 u64 sst_pp_level4_offset :8;
157 u64 reserved :24;
158 } __packed;
159
160 /**
161 * struct pp_control_offset - Offsets for SST PP controls
162 * @perf_level: A SST-PP level that SW intends to switch to
163 * @perf_level_lock: SST-PP level select lock. 0 - unlocked. 1 - locked till next reset
164 * @resvd0: Reserved for future use
165 * @current_state: Bit mask to control the enable(1)/disable(0) state of each feature
166 * of the current PP level, bit 0 = BF, bit 1 = TF, bit 2-7 = reserved
167 * @reserved: Reserved for future use
168 *
169 * This structure is used store offsets of SST PP controls in the register bank.
170 * This is packed to the same format as defined in the specifications.
171 */
172 struct pp_control_offset {
173 u64 perf_level :3;
174 u64 perf_level_lock :1;
175 u64 resvd0 :4;
176 u64 current_state :8;
177 u64 reserved :48;
178 } __packed;
179
180 /**
181 * struct pp_status_offset - Offsets for SST PP status fields
182 * @sst_pp_level: Returns the current SST-PP level
183 * @sst_pp_lock: Returns the lock bit setting of perf_level_lock in pp_control_offset
184 * @error_type: Returns last error of SST-PP level change request. 0: no error,
185 * 1: level change not allowed, others: reserved
186 * @feature_state: Bit mask to indicate the enable(1)/disable(0) state of each feature of the
187 * current PP level. bit 0 = BF, bit 1 = TF, bit 2-7 reserved
188 * @reserved0: Reserved for future use
189 * @feature_error_type: Returns last error of the specific feature. Three error_type bits per
190 * feature. i.e. ERROR_TYPE[2:0] for BF, ERROR_TYPE[5:3] for TF, etc.
191 * 0x0: no error, 0x1: The specific feature is not supported by the hardware.
192 * 0x2-0x6: Reserved. 0x7: feature state change is not allowed.
193 * @reserved1: Reserved for future use
194 *
195 * This structure is used store offsets of SST PP status in the register bank.
196 * This is packed to the same format as defined in the specifications.
197 */
198 struct pp_status_offset {
199 u64 sst_pp_level :3;
200 u64 sst_pp_lock :1;
201 u64 error_type :4;
202 u64 feature_state :8;
203 u64 reserved0 :16;
204 u64 feature_error_type : 24;
205 u64 reserved1 :8;
206 } __packed;
207
208 /**
209 * struct perf_level - Used to store perf level and mmio offset
210 * @mmio_offset: mmio offset for a perf level
211 * @level: perf level for this offset
212 *
213 * This structure is used store final mmio offset of each perf level from the
214 * SST base mmio offset.
215 */
216 struct perf_level {
217 int mmio_offset;
218 int level;
219 };
220
221 /**
222 * struct tpmi_per_power_domain_info - Store per power_domain SST info
223 * @package_id: Package id for this power_domain
224 * @power_domain_id: Power domain id, Each entry from the SST-TPMI instance is a power_domain.
225 * @max_level: Max possible PP level possible for this power_domain
226 * @ratio_unit: Ratio unit for converting to MHz
227 * @avx_levels: Number of AVX levels
228 * @pp_block_size: Block size from PP header
229 * @sst_header: Store SST header for this power_domain
230 * @cp_header: Store SST-CP header for this power_domain
231 * @pp_header: Store SST-PP header for this power_domain
232 * @perf_levels: Pointer to each perf level to map level to mmio offset
233 * @feature_offsets: Store feature offsets for each PP-level
234 * @control_offset: Store the control offset for each PP-level
235 * @status_offset: Store the status offset for each PP-level
236 * @sst_base: Mapped SST base IO memory
237 * @auxdev: Auxiliary device instance enumerated this instance
238 * @saved_sst_cp_control: Save SST-CP control configuration to store restore for suspend/resume
239 * @saved_clos_configs: Save SST-CP CLOS configuration to store restore for suspend/resume
240 * @saved_clos_assocs: Save SST-CP CLOS association to store restore for suspend/resume
241 * @saved_pp_control: Save SST-PP control information to store restore for suspend/resume
242 * @write_blocked: Write operation is blocked, so can't change SST state
243 *
244 * This structure is used store complete SST information for a power_domain. This information
245 * is used to read/write request for any SST IOCTL. Each physical CPU package can have multiple
246 * power_domains. Each power domain describes its own SST information and has its own controls.
247 */
248 struct tpmi_per_power_domain_info {
249 int package_id;
250 int power_domain_id;
251 int max_level;
252 int ratio_unit;
253 int avx_levels;
254 int pp_block_size;
255 struct sst_header sst_header;
256 struct cp_header cp_header;
257 struct pp_header pp_header;
258 struct perf_level *perf_levels;
259 struct feature_offset feature_offsets;
260 struct pp_control_offset control_offset;
261 struct pp_status_offset status_offset;
262 void __iomem *sst_base;
263 struct auxiliary_device *auxdev;
264 u64 saved_sst_cp_control;
265 u64 saved_clos_configs[4];
266 u64 saved_clos_assocs[4];
267 u64 saved_pp_control;
268 bool write_blocked;
269 };
270
271 /* Supported maximum partitions */
272 #define SST_MAX_PARTITIONS 2
273
274 /**
275 * struct tpmi_sst_struct - Store sst info for a package
276 * @package_id: Package id for this aux device instance
277 * @number_of_power_domains: Number of power_domains pointed by power_domain_info pointer
278 * @power_domain_info: Pointer to power domains information
279 * @cdie_mask: Mask of compute dies present in a partition from hardware.
280 * This mask is not present in the version 1 information header.
281 * @io_dies: Number of IO dies in a partition. This will be 0 for TPMI
282 * version 1 information header.
283 * @partition_mask: Mask of all partitions.
284 * @partition_mask_current: Current partition mask as some may have been unbound.
285 *
286 * This structure is used store full SST information for a package.
287 * Each package has one or multiple OOB PCI devices. Each package can contain multiple
288 * power domains.
289 */
290 struct tpmi_sst_struct {
291 int package_id;
292 struct tpmi_per_power_domain_info *power_domain_info[SST_MAX_PARTITIONS];
293 u16 cdie_mask[SST_MAX_PARTITIONS];
294 u8 number_of_power_domains[SST_MAX_PARTITIONS];
295 u8 io_dies[SST_MAX_PARTITIONS];
296 u8 partition_mask;
297 u8 partition_mask_current;
298 };
299
300 /**
301 * struct tpmi_sst_common_struct - Store all SST instances
302 * @max_index: Maximum instances currently present
303 * @sst_inst: Pointer to per package instance
304 *
305 * Stores every SST Package instance.
306 */
307 struct tpmi_sst_common_struct {
308 int max_index;
309 struct tpmi_sst_struct **sst_inst;
310 };
311
312 /*
313 * Each IOCTL request is processed under this lock. Also used to protect
314 * registration functions and common data structures.
315 */
316 static DEFINE_MUTEX(isst_tpmi_dev_lock);
317
318 /* Usage count to track, number of TPMI SST instances registered to this core. */
319 static int isst_core_usage_count;
320
321 /* Stores complete SST information for every package and power_domain */
322 static struct tpmi_sst_common_struct isst_common;
323
324 #define SST_MAX_AVX_LEVELS 3
325
326 #define SST_PP_OFFSET_0 8
327 #define SST_PP_OFFSET_1 16
328 #define SST_PP_OFFSET_SIZE 8
329
sst_add_perf_profiles(struct auxiliary_device * auxdev,struct tpmi_per_power_domain_info * pd_info,int levels)330 static int sst_add_perf_profiles(struct auxiliary_device *auxdev,
331 struct tpmi_per_power_domain_info *pd_info,
332 int levels)
333 {
334 struct device *dev = &auxdev->dev;
335 u64 perf_level_offsets;
336 int i;
337
338 pd_info->perf_levels = devm_kcalloc(dev, levels, sizeof(struct perf_level), GFP_KERNEL);
339 if (!pd_info->perf_levels)
340 return 0;
341
342 pd_info->ratio_unit = pd_info->pp_header.ratio_unit;
343 pd_info->avx_levels = SST_MAX_AVX_LEVELS;
344 pd_info->pp_block_size = pd_info->pp_header.block_size;
345
346 /* Read PP Offset 0: Get feature offset with PP level */
347 *((u64 *)&pd_info->feature_offsets) = readq(pd_info->sst_base +
348 pd_info->sst_header.pp_offset +
349 SST_PP_OFFSET_0);
350
351 perf_level_offsets = readq(pd_info->sst_base + pd_info->sst_header.pp_offset +
352 SST_PP_OFFSET_1);
353
354 for (i = 0; i < levels; ++i) {
355 u64 offset;
356
357 offset = perf_level_offsets & (0xffULL << (i * SST_PP_OFFSET_SIZE));
358 offset >>= (i * 8);
359 offset &= 0xff;
360 offset *= 8; /* Convert to byte from QWORD offset */
361 pd_info->perf_levels[i].mmio_offset = pd_info->sst_header.pp_offset + offset;
362 }
363
364 return 0;
365 }
366
sst_main(struct auxiliary_device * auxdev,struct tpmi_per_power_domain_info * pd_info)367 static int sst_main(struct auxiliary_device *auxdev, struct tpmi_per_power_domain_info *pd_info)
368 {
369 struct device *dev = &auxdev->dev;
370 int i, mask, levels;
371
372 *((u64 *)&pd_info->sst_header) = readq(pd_info->sst_base);
373 pd_info->sst_header.cp_offset *= 8;
374 pd_info->sst_header.pp_offset *= 8;
375
376 if (pd_info->sst_header.interface_version == TPMI_VERSION_INVALID)
377 return -ENODEV;
378
379 if (TPMI_MAJOR_VERSION(pd_info->sst_header.interface_version) != ISST_MAJOR_VERSION) {
380 dev_err(dev, "SST: Unsupported major version:%lx\n",
381 TPMI_MAJOR_VERSION(pd_info->sst_header.interface_version));
382 return -ENODEV;
383 }
384
385 if (TPMI_MINOR_VERSION(pd_info->sst_header.interface_version) > ISST_MINOR_VERSION)
386 dev_info(dev, "SST: Ignore: Unsupported minor version:%lx\n",
387 TPMI_MINOR_VERSION(pd_info->sst_header.interface_version));
388
389 /* Read SST CP Header */
390 *((u64 *)&pd_info->cp_header) = readq(pd_info->sst_base + pd_info->sst_header.cp_offset);
391
392 /* Read PP header */
393 *((u64 *)&pd_info->pp_header) = readq(pd_info->sst_base + pd_info->sst_header.pp_offset);
394
395 mask = 0x01;
396 levels = 0;
397 for (i = 0; i < 8; ++i) {
398 if (pd_info->pp_header.level_en_mask & mask)
399 levels = i;
400 mask <<= 1;
401 }
402 pd_info->max_level = levels;
403 sst_add_perf_profiles(auxdev, pd_info, levels + 1);
404
405 return 0;
406 }
407
isst_instance_count(struct tpmi_sst_struct * sst_inst)408 static u8 isst_instance_count(struct tpmi_sst_struct *sst_inst)
409 {
410 u8 i, max_part, count = 0;
411
412 /* Partition mask starts from bit 0 and contains 1s only */
413 max_part = hweight8(sst_inst->partition_mask);
414 for (i = 0; i < max_part; i++)
415 count += sst_inst->number_of_power_domains[i];
416
417 return count;
418 }
419
420 /**
421 * map_cdies() - Map user domain ID to compute domain ID
422 * @sst_inst: TPMI Instance
423 * @id: User domain ID
424 * @partition: Resolved partition
425 *
426 * Helper function to map_partition_power_domain_id() to resolve compute
427 * domain ID and partition. Use hardware provided cdie_mask for a partition
428 * as is to resolve a compute domain ID.
429 *
430 * Return: %-EINVAL on error, otherwise mapped domain ID >= 0.
431 */
map_cdies(struct tpmi_sst_struct * sst_inst,u8 id,u8 * partition)432 static int map_cdies(struct tpmi_sst_struct *sst_inst, u8 id, u8 *partition)
433 {
434 u8 i, max_part;
435
436 max_part = hweight8(sst_inst->partition_mask);
437 for (i = 0; i < max_part; i++) {
438 if (!(sst_inst->cdie_mask[i] & BIT(id)))
439 continue;
440
441 *partition = i;
442 return id - ffs(sst_inst->cdie_mask[i]) + 1;
443 }
444
445 return -EINVAL;
446 }
447
448 /**
449 * map_partition_power_domain_id() - Map user domain ID to partition domain ID
450 * @sst_inst: TPMI Instance
451 * @id: User domain ID
452 * @partition: Resolved partition
453 *
454 * In a partitioned system a CPU package has two separate MMIO ranges (Under
455 * two PCI devices). But the CPU package compute die/power domain IDs are
456 * unique in a package. User space can get compute die/power domain ID from
457 * CPUID and MSR 0x54 for a CPU. So, those IDs need to be preserved even if
458 * they are present in two different partitions with its own order.
459 *
460 * For example for command ISST_IF_COUNT_TPMI_INSTANCES, the valid_mask
461 * is 111111b for a 4 compute and 2 IO dies system. This is presented as
462 * provided by the hardware in a non-partitioned system with the following
463 * order:
464 * I1-I0-C3-C2-C1-C0
465 * Here: "C": for compute and "I" for IO die.
466 * Compute dies are always present first in TPMI instances, as they have
467 * to map to the real power domain/die ID of a system. In a non-partitioned
468 * system there is no way to identify compute and IO die boundaries from
469 * this driver without reading each CPU's mapping.
470 *
471 * The same order needs to be preserved, even if those compute dies are
472 * distributed among multiple partitions. For example:
473 * Partition 1 can contain: I1-C1-C0
474 * Partition 2 can contain: I2-C3-C2
475 *
476 * This will require a conversion of user space IDs to the actual index into
477 * array of stored power domains for each partition. For the above example
478 * this function will return partition and index as follows:
479 *
480 * ============= ========= ===== ========
481 * User space ID Partition Index Die type
482 * ============= ========= ===== ========
483 * 0 0 0 Compute
484 * 1 0 1 Compute
485 * 2 1 0 Compute
486 * 3 1 1 Compute
487 * 4 0 2 IO
488 * 5 1 2 IO
489 * ============= ========= ===== ========
490 *
491 * Return: %-EINVAL on error, otherwise mapped domain ID >= 0.
492 */
map_partition_power_domain_id(struct tpmi_sst_struct * sst_inst,u8 id,u8 * partition)493 static int map_partition_power_domain_id(struct tpmi_sst_struct *sst_inst, u8 id, u8 *partition)
494 {
495 u8 i, io_start_id, max_part;
496
497 *partition = 0;
498
499 /* If any PCI device for partition is unbound, treat this as failure */
500 if (sst_inst->partition_mask != sst_inst->partition_mask_current)
501 return -EINVAL;
502
503 max_part = hweight8(sst_inst->partition_mask);
504
505 /* IO Index begin here */
506 io_start_id = fls(sst_inst->cdie_mask[max_part - 1]);
507
508 if (id < io_start_id)
509 return map_cdies(sst_inst, id, partition);
510
511 for (i = 0; i < max_part; i++) {
512 u8 io_id;
513
514 io_id = id - io_start_id;
515 if (io_id < sst_inst->io_dies[i]) {
516 u8 cdie_range;
517
518 cdie_range = fls(sst_inst->cdie_mask[i]) - ffs(sst_inst->cdie_mask[i]) + 1;
519 *partition = i;
520 return cdie_range + io_id;
521 }
522 io_start_id += sst_inst->io_dies[i];
523 }
524
525 return -EINVAL;
526 }
527
528 /*
529 * Map a package and power_domain id to SST information structure unique for a power_domain.
530 * The caller should call under isst_tpmi_dev_lock.
531 */
get_instance(int pkg_id,int power_domain_id)532 static struct tpmi_per_power_domain_info *get_instance(int pkg_id, int power_domain_id)
533 {
534 struct tpmi_per_power_domain_info *power_domain_info;
535 struct tpmi_sst_struct *sst_inst;
536 u8 part;
537
538 if (!in_range(pkg_id, 0, topology_max_packages()) || pkg_id > isst_common.max_index)
539 return NULL;
540
541 sst_inst = isst_common.sst_inst[pkg_id];
542 if (!sst_inst)
543 return NULL;
544
545 power_domain_id = map_partition_power_domain_id(sst_inst, power_domain_id, &part);
546 if (power_domain_id < 0)
547 return NULL;
548
549 power_domain_info = &sst_inst->power_domain_info[part][power_domain_id];
550
551 if (power_domain_info && !power_domain_info->sst_base)
552 return NULL;
553
554 return power_domain_info;
555 }
556
disable_dynamic_sst_features(void)557 static bool disable_dynamic_sst_features(void)
558 {
559 u64 value;
560
561 rdmsrq(MSR_PM_ENABLE, value);
562 return !(value & 0x1);
563 }
564
565 #define _read_cp_info(name_str, name, offset, start, width, mult_factor)\
566 {\
567 u64 val, mask;\
568 \
569 val = readq(power_domain_info->sst_base + power_domain_info->sst_header.cp_offset +\
570 (offset));\
571 mask = GENMASK_ULL((start + width - 1), start);\
572 val &= mask; \
573 val >>= start;\
574 name = (val * mult_factor);\
575 }
576
577 #define _write_cp_info(name_str, name, offset, start, width, div_factor)\
578 {\
579 u64 val, mask;\
580 \
581 val = readq(power_domain_info->sst_base +\
582 power_domain_info->sst_header.cp_offset + (offset));\
583 mask = GENMASK_ULL((start + width - 1), start);\
584 val &= ~mask;\
585 val |= (name / div_factor) << start;\
586 writeq(val, power_domain_info->sst_base + power_domain_info->sst_header.cp_offset +\
587 (offset));\
588 }
589
590 #define SST_CP_CONTROL_OFFSET 8
591 #define SST_CP_STATUS_OFFSET 16
592
593 #define SST_CP_ENABLE_START 0
594 #define SST_CP_ENABLE_WIDTH 1
595
596 #define SST_CP_PRIORITY_TYPE_START 1
597 #define SST_CP_PRIORITY_TYPE_WIDTH 1
598
isst_if_core_power_state(void __user * argp)599 static long isst_if_core_power_state(void __user *argp)
600 {
601 struct tpmi_per_power_domain_info *power_domain_info;
602 struct isst_core_power core_power;
603
604 if (copy_from_user(&core_power, argp, sizeof(core_power)))
605 return -EFAULT;
606
607 if (core_power.get_set && disable_dynamic_sst_features())
608 return -EFAULT;
609
610 power_domain_info = get_instance(core_power.socket_id, core_power.power_domain_id);
611 if (!power_domain_info)
612 return -EINVAL;
613
614 if (core_power.get_set) {
615 _write_cp_info("cp_enable", core_power.enable, SST_CP_CONTROL_OFFSET,
616 SST_CP_ENABLE_START, SST_CP_ENABLE_WIDTH, SST_MUL_FACTOR_NONE)
617 _write_cp_info("cp_prio_type", core_power.priority_type, SST_CP_CONTROL_OFFSET,
618 SST_CP_PRIORITY_TYPE_START, SST_CP_PRIORITY_TYPE_WIDTH,
619 SST_MUL_FACTOR_NONE)
620 } else {
621 /* get */
622 _read_cp_info("cp_enable", core_power.enable, SST_CP_STATUS_OFFSET,
623 SST_CP_ENABLE_START, SST_CP_ENABLE_WIDTH, SST_MUL_FACTOR_NONE)
624 _read_cp_info("cp_prio_type", core_power.priority_type, SST_CP_STATUS_OFFSET,
625 SST_CP_PRIORITY_TYPE_START, SST_CP_PRIORITY_TYPE_WIDTH,
626 SST_MUL_FACTOR_NONE)
627 core_power.supported = !!(power_domain_info->sst_header.cap_mask & BIT(0));
628 if (copy_to_user(argp, &core_power, sizeof(core_power)))
629 return -EFAULT;
630 }
631
632 return 0;
633 }
634
635 #define SST_CLOS_CONFIG_0_OFFSET 24
636
637 #define SST_CLOS_CONFIG_PRIO_START 4
638 #define SST_CLOS_CONFIG_PRIO_WIDTH 4
639
640 #define SST_CLOS_CONFIG_MIN_START 8
641 #define SST_CLOS_CONFIG_MIN_WIDTH 8
642
643 #define SST_CLOS_CONFIG_MAX_START 16
644 #define SST_CLOS_CONFIG_MAX_WIDTH 8
645
isst_if_clos_param(void __user * argp)646 static long isst_if_clos_param(void __user *argp)
647 {
648 struct tpmi_per_power_domain_info *power_domain_info;
649 struct isst_clos_param clos_param;
650
651 if (copy_from_user(&clos_param, argp, sizeof(clos_param)))
652 return -EFAULT;
653
654 power_domain_info = get_instance(clos_param.socket_id, clos_param.power_domain_id);
655 if (!power_domain_info)
656 return -EINVAL;
657
658 if (clos_param.get_set) {
659 if (power_domain_info->write_blocked)
660 return -EPERM;
661
662 _write_cp_info("clos.min_freq", clos_param.min_freq_mhz,
663 (SST_CLOS_CONFIG_0_OFFSET + clos_param.clos * SST_REG_SIZE),
664 SST_CLOS_CONFIG_MIN_START, SST_CLOS_CONFIG_MIN_WIDTH,
665 SST_MUL_FACTOR_FREQ);
666 _write_cp_info("clos.max_freq", clos_param.max_freq_mhz,
667 (SST_CLOS_CONFIG_0_OFFSET + clos_param.clos * SST_REG_SIZE),
668 SST_CLOS_CONFIG_MAX_START, SST_CLOS_CONFIG_MAX_WIDTH,
669 SST_MUL_FACTOR_FREQ);
670 _write_cp_info("clos.prio", clos_param.prop_prio,
671 (SST_CLOS_CONFIG_0_OFFSET + clos_param.clos * SST_REG_SIZE),
672 SST_CLOS_CONFIG_PRIO_START, SST_CLOS_CONFIG_PRIO_WIDTH,
673 SST_MUL_FACTOR_NONE);
674 } else {
675 /* get */
676 _read_cp_info("clos.min_freq", clos_param.min_freq_mhz,
677 (SST_CLOS_CONFIG_0_OFFSET + clos_param.clos * SST_REG_SIZE),
678 SST_CLOS_CONFIG_MIN_START, SST_CLOS_CONFIG_MIN_WIDTH,
679 SST_MUL_FACTOR_FREQ)
680 _read_cp_info("clos.max_freq", clos_param.max_freq_mhz,
681 (SST_CLOS_CONFIG_0_OFFSET + clos_param.clos * SST_REG_SIZE),
682 SST_CLOS_CONFIG_MAX_START, SST_CLOS_CONFIG_MAX_WIDTH,
683 SST_MUL_FACTOR_FREQ)
684 _read_cp_info("clos.prio", clos_param.prop_prio,
685 (SST_CLOS_CONFIG_0_OFFSET + clos_param.clos * SST_REG_SIZE),
686 SST_CLOS_CONFIG_PRIO_START, SST_CLOS_CONFIG_PRIO_WIDTH,
687 SST_MUL_FACTOR_NONE)
688
689 if (copy_to_user(argp, &clos_param, sizeof(clos_param)))
690 return -EFAULT;
691 }
692
693 return 0;
694 }
695
696 #define SST_CLOS_ASSOC_0_OFFSET 56
697 #define SST_CLOS_ASSOC_CPUS_PER_REG 16
698 #define SST_CLOS_ASSOC_BITS_PER_CPU 4
699
isst_if_clos_assoc(void __user * argp)700 static long isst_if_clos_assoc(void __user *argp)
701 {
702 struct isst_if_clos_assoc_cmds assoc_cmds;
703 unsigned char __user *ptr;
704 int i;
705
706 /* Each multi command has u16 command count as the first field */
707 if (copy_from_user(&assoc_cmds, argp, sizeof(assoc_cmds)))
708 return -EFAULT;
709
710 if (!assoc_cmds.cmd_count || assoc_cmds.cmd_count > ISST_IF_CMD_LIMIT)
711 return -EINVAL;
712
713 ptr = argp + offsetof(struct isst_if_clos_assoc_cmds, assoc_info);
714 for (i = 0; i < assoc_cmds.cmd_count; ++i) {
715 struct tpmi_per_power_domain_info *power_domain_info;
716 struct isst_if_clos_assoc clos_assoc;
717 int punit_id, punit_cpu_no, pkg_id;
718 struct tpmi_sst_struct *sst_inst;
719 int offset, shift, cpu;
720 u64 val, mask, clos;
721 u8 part;
722
723 if (copy_from_user(&clos_assoc, ptr, sizeof(clos_assoc)))
724 return -EFAULT;
725
726 if (clos_assoc.socket_id > topology_max_packages())
727 return -EINVAL;
728
729 cpu = clos_assoc.logical_cpu;
730 clos = clos_assoc.clos;
731
732 if (assoc_cmds.punit_cpu_map)
733 punit_cpu_no = cpu;
734 else
735 return -EOPNOTSUPP;
736
737 if (punit_cpu_no < 0)
738 return -EINVAL;
739
740 punit_id = clos_assoc.power_domain_id;
741 pkg_id = clos_assoc.socket_id;
742
743 sst_inst = isst_common.sst_inst[pkg_id];
744
745 punit_id = map_partition_power_domain_id(sst_inst, punit_id, &part);
746 if (punit_id < 0)
747 return -EINVAL;
748
749 power_domain_info = &sst_inst->power_domain_info[part][punit_id];
750
751 if (assoc_cmds.get_set && power_domain_info->write_blocked)
752 return -EPERM;
753
754 offset = SST_CLOS_ASSOC_0_OFFSET +
755 (punit_cpu_no / SST_CLOS_ASSOC_CPUS_PER_REG) * SST_REG_SIZE;
756 shift = punit_cpu_no % SST_CLOS_ASSOC_CPUS_PER_REG;
757 shift *= SST_CLOS_ASSOC_BITS_PER_CPU;
758
759 val = readq(power_domain_info->sst_base +
760 power_domain_info->sst_header.cp_offset + offset);
761 if (assoc_cmds.get_set) {
762 mask = GENMASK_ULL((shift + SST_CLOS_ASSOC_BITS_PER_CPU - 1), shift);
763 val &= ~mask;
764 val |= (clos << shift);
765 writeq(val, power_domain_info->sst_base +
766 power_domain_info->sst_header.cp_offset + offset);
767 } else {
768 val >>= shift;
769 clos_assoc.clos = val & GENMASK(SST_CLOS_ASSOC_BITS_PER_CPU - 1, 0);
770 if (copy_to_user(ptr, &clos_assoc, sizeof(clos_assoc)))
771 return -EFAULT;
772 }
773
774 ptr += sizeof(clos_assoc);
775 }
776
777 return 0;
778 }
779
780 #define _read_pp_info(name_str, name, offset, start, width, mult_factor)\
781 {\
782 u64 val, _mask;\
783 \
784 val = readq(power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\
785 (offset));\
786 _mask = GENMASK_ULL((start + width - 1), start);\
787 val &= _mask;\
788 val >>= start;\
789 name = (val * mult_factor);\
790 }
791
792 #define _write_pp_info(name_str, name, offset, start, width, div_factor)\
793 {\
794 u64 val, _mask;\
795 \
796 val = readq(power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\
797 (offset));\
798 _mask = GENMASK((start + width - 1), start);\
799 val &= ~_mask;\
800 val |= (name / div_factor) << start;\
801 writeq(val, power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\
802 (offset));\
803 }
804
805 #define _read_bf_level_info(name_str, name, level, offset, start, width, mult_factor)\
806 {\
807 u64 val, _mask;\
808 \
809 val = readq(power_domain_info->sst_base +\
810 power_domain_info->perf_levels[level].mmio_offset +\
811 (power_domain_info->feature_offsets.bf_offset * 8) + (offset));\
812 _mask = GENMASK_ULL((start + width - 1), start);\
813 val &= _mask; \
814 val >>= start;\
815 name = (val * mult_factor);\
816 }
817
818 #define _read_tf_level_info(name_str, name, level, offset, start, width, mult_factor)\
819 {\
820 u64 val, _mask;\
821 \
822 val = readq(power_domain_info->sst_base +\
823 power_domain_info->perf_levels[level].mmio_offset +\
824 (power_domain_info->feature_offsets.tf_offset * 8) + (offset));\
825 _mask = GENMASK_ULL((start + width - 1), start);\
826 val &= _mask; \
827 val >>= start;\
828 name = (val * mult_factor);\
829 }
830
831 #define SST_PP_STATUS_OFFSET 32
832
833 #define SST_PP_LEVEL_START 0
834 #define SST_PP_LEVEL_WIDTH 3
835
836 #define SST_PP_LOCK_START 3
837 #define SST_PP_LOCK_WIDTH 1
838
839 #define SST_PP_FEATURE_STATE_START 8
840 #define SST_PP_FEATURE_STATE_WIDTH 8
841
842 #define SST_BF_FEATURE_SUPPORTED_START 12
843 #define SST_BF_FEATURE_SUPPORTED_WIDTH 1
844
845 #define SST_TF_FEATURE_SUPPORTED_START 12
846 #define SST_TF_FEATURE_SUPPORTED_WIDTH 1
847
isst_if_get_perf_level(void __user * argp)848 static int isst_if_get_perf_level(void __user *argp)
849 {
850 struct isst_perf_level_info perf_level;
851 struct tpmi_per_power_domain_info *power_domain_info;
852 unsigned long level_mask;
853 u8 level, support;
854
855 if (copy_from_user(&perf_level, argp, sizeof(perf_level)))
856 return -EFAULT;
857
858 power_domain_info = get_instance(perf_level.socket_id, perf_level.power_domain_id);
859 if (!power_domain_info)
860 return -EINVAL;
861
862 perf_level.max_level = power_domain_info->max_level;
863 perf_level.level_mask = power_domain_info->pp_header.level_en_mask;
864 perf_level.feature_rev = power_domain_info->pp_header.feature_rev;
865 _read_pp_info("current_level", perf_level.current_level, SST_PP_STATUS_OFFSET,
866 SST_PP_LEVEL_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE)
867 _read_pp_info("locked", perf_level.locked, SST_PP_STATUS_OFFSET,
868 SST_PP_LOCK_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE)
869 _read_pp_info("feature_state", perf_level.feature_state, SST_PP_STATUS_OFFSET,
870 SST_PP_FEATURE_STATE_START, SST_PP_FEATURE_STATE_WIDTH, SST_MUL_FACTOR_NONE)
871 perf_level.enabled = !!(power_domain_info->sst_header.cap_mask & BIT(1));
872
873 level_mask = perf_level.level_mask;
874 perf_level.sst_bf_support = 0;
875 for_each_set_bit(level, &level_mask, BITS_PER_BYTE) {
876 /*
877 * Read BF support for a level. Read output is updated
878 * to "support" variable by the below macro.
879 */
880 _read_bf_level_info("bf_support", support, level, 0, SST_BF_FEATURE_SUPPORTED_START,
881 SST_BF_FEATURE_SUPPORTED_WIDTH, SST_MUL_FACTOR_NONE);
882
883 /* If supported set the bit for the level */
884 if (support)
885 perf_level.sst_bf_support |= BIT(level);
886 }
887
888 perf_level.sst_tf_support = 0;
889 for_each_set_bit(level, &level_mask, BITS_PER_BYTE) {
890 /*
891 * Read TF support for a level. Read output is updated
892 * to "support" variable by the below macro.
893 */
894 _read_tf_level_info("tf_support", support, level, 0, SST_TF_FEATURE_SUPPORTED_START,
895 SST_TF_FEATURE_SUPPORTED_WIDTH, SST_MUL_FACTOR_NONE);
896
897 /* If supported set the bit for the level */
898 if (support)
899 perf_level.sst_tf_support |= BIT(level);
900 }
901
902 if (copy_to_user(argp, &perf_level, sizeof(perf_level)))
903 return -EFAULT;
904
905 return 0;
906 }
907
908 #define SST_PP_CONTROL_OFFSET 24
909 #define SST_PP_LEVEL_CHANGE_TIME_MS 5
910 #define SST_PP_LEVEL_CHANGE_RETRY_COUNT 3
911
isst_if_set_perf_level(void __user * argp)912 static int isst_if_set_perf_level(void __user *argp)
913 {
914 struct isst_perf_level_control perf_level;
915 struct tpmi_per_power_domain_info *power_domain_info;
916 int level, retry = 0;
917
918 if (disable_dynamic_sst_features())
919 return -EFAULT;
920
921 if (copy_from_user(&perf_level, argp, sizeof(perf_level)))
922 return -EFAULT;
923
924 power_domain_info = get_instance(perf_level.socket_id, perf_level.power_domain_id);
925 if (!power_domain_info)
926 return -EINVAL;
927
928 if (power_domain_info->write_blocked)
929 return -EPERM;
930
931 if (!(power_domain_info->pp_header.allowed_level_mask & BIT(perf_level.level)))
932 return -EINVAL;
933
934 _read_pp_info("current_level", level, SST_PP_STATUS_OFFSET,
935 SST_PP_LEVEL_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE)
936
937 /* If the requested new level is same as the current level, reject */
938 if (perf_level.level == level)
939 return -EINVAL;
940
941 _write_pp_info("perf_level", perf_level.level, SST_PP_CONTROL_OFFSET,
942 SST_PP_LEVEL_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE)
943
944 /* It is possible that firmware is busy (although unlikely), so retry */
945 do {
946 /* Give time to FW to process */
947 msleep(SST_PP_LEVEL_CHANGE_TIME_MS);
948
949 _read_pp_info("current_level", level, SST_PP_STATUS_OFFSET,
950 SST_PP_LEVEL_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE)
951
952 /* Check if the new level is active */
953 if (perf_level.level == level)
954 break;
955
956 } while (retry++ < SST_PP_LEVEL_CHANGE_RETRY_COUNT);
957
958 /* If the level change didn't happen, return fault */
959 if (perf_level.level != level)
960 return -EFAULT;
961
962 /* Reset the feature state on level change */
963 _write_pp_info("perf_feature", 0, SST_PP_CONTROL_OFFSET,
964 SST_PP_FEATURE_STATE_START, SST_PP_FEATURE_STATE_WIDTH,
965 SST_MUL_FACTOR_NONE)
966
967 /* Give time to FW to process */
968 msleep(SST_PP_LEVEL_CHANGE_TIME_MS);
969
970 return 0;
971 }
972
isst_if_set_perf_feature(void __user * argp)973 static int isst_if_set_perf_feature(void __user *argp)
974 {
975 struct isst_perf_feature_control perf_feature;
976 struct tpmi_per_power_domain_info *power_domain_info;
977
978 if (disable_dynamic_sst_features())
979 return -EFAULT;
980
981 if (copy_from_user(&perf_feature, argp, sizeof(perf_feature)))
982 return -EFAULT;
983
984 power_domain_info = get_instance(perf_feature.socket_id, perf_feature.power_domain_id);
985 if (!power_domain_info)
986 return -EINVAL;
987
988 if (power_domain_info->write_blocked)
989 return -EPERM;
990
991 _write_pp_info("perf_feature", perf_feature.feature, SST_PP_CONTROL_OFFSET,
992 SST_PP_FEATURE_STATE_START, SST_PP_FEATURE_STATE_WIDTH,
993 SST_MUL_FACTOR_NONE)
994
995 return 0;
996 }
997
998 #define _read_pp_level_info(name_str, name, level, offset, start, width, mult_factor)\
999 {\
1000 u64 val, _mask;\
1001 \
1002 val = readq(power_domain_info->sst_base +\
1003 power_domain_info->perf_levels[level].mmio_offset +\
1004 (power_domain_info->feature_offsets.pp_offset * 8) + (offset));\
1005 _mask = GENMASK_ULL((start + width - 1), start);\
1006 val &= _mask; \
1007 val >>= start;\
1008 name = (val * mult_factor);\
1009 }
1010
1011 #define SST_PP_INFO_0_OFFSET 0
1012 #define SST_PP_INFO_1_OFFSET 8
1013 #define SST_PP_INFO_2_OFFSET 16
1014 #define SST_PP_INFO_3_OFFSET 24
1015
1016 /* SST_PP_INFO_4_OFFSET to SST_PP_INFO_9_OFFSET are trl levels */
1017 #define SST_PP_INFO_4_OFFSET 32
1018
1019 #define SST_PP_INFO_10_OFFSET 80
1020 #define SST_PP_INFO_11_OFFSET 88
1021 #define SST_PP_INFO_12_OFFSET 96
1022
1023 #define SST_PP_P1_SSE_START 0
1024 #define SST_PP_P1_SSE_WIDTH 8
1025
1026 #define SST_PP_P1_AVX2_START 8
1027 #define SST_PP_P1_AVX2_WIDTH 8
1028
1029 #define SST_PP_P1_AVX512_START 16
1030 #define SST_PP_P1_AVX512_WIDTH 8
1031
1032 #define SST_PP_P1_AMX_START 24
1033 #define SST_PP_P1_AMX_WIDTH 8
1034
1035 #define SST_PP_TDP_START 32
1036 #define SST_PP_TDP_WIDTH 15
1037
1038 #define SST_PP_T_PROCHOT_START 47
1039 #define SST_PP_T_PROCHOT_WIDTH 8
1040
1041 #define SST_PP_MAX_MEMORY_FREQ_START 55
1042 #define SST_PP_MAX_MEMORY_FREQ_WIDTH 7
1043
1044 #define SST_PP_COOLING_TYPE_START 62
1045 #define SST_PP_COOLING_TYPE_WIDTH 2
1046
1047 #define SST_PP_TRL_0_RATIO_0_START 0
1048 #define SST_PP_TRL_0_RATIO_0_WIDTH 8
1049
1050 #define SST_PP_TRL_CORES_BUCKET_0_START 0
1051 #define SST_PP_TRL_CORES_BUCKET_0_WIDTH 8
1052
1053 #define SST_PP_CORE_RATIO_P0_START 0
1054 #define SST_PP_CORE_RATIO_P0_WIDTH 8
1055
1056 #define SST_PP_CORE_RATIO_P1_START 8
1057 #define SST_PP_CORE_RATIO_P1_WIDTH 8
1058
1059 #define SST_PP_CORE_RATIO_PN_START 16
1060 #define SST_PP_CORE_RATIO_PN_WIDTH 8
1061
1062 #define SST_PP_CORE_RATIO_PM_START 24
1063 #define SST_PP_CORE_RATIO_PM_WIDTH 8
1064
1065 #define SST_PP_CORE_RATIO_P0_FABRIC_START 32
1066 #define SST_PP_CORE_RATIO_P0_FABRIC_WIDTH 8
1067
1068 #define SST_PP_CORE_RATIO_P1_FABRIC_START 40
1069 #define SST_PP_CORE_RATIO_P1_FABRIC_WIDTH 8
1070
1071 #define SST_PP_CORE_RATIO_PM_FABRIC_START 48
1072 #define SST_PP_CORE_RATIO_PM_FABRIC_WIDTH 8
1073
1074 #define SST_PP_CORE_RATIO_P0_FABRIC_1_START 0
1075 #define SST_PP_CORE_RATIO_P0_FABRIC_1_WIDTH 8
1076
1077 #define SST_PP_CORE_RATIO_P1_FABRIC_1_START 8
1078 #define SST_PP_CORE_RATIO_P1_FABRIC_1_WIDTH 8
1079
1080 #define SST_PP_CORE_RATIO_PM_FABRIC_1_START 16
1081 #define SST_PP_CORE_RATIO_PM_FABRIC_1_WIDTH 8
1082
isst_if_get_perf_level_info(void __user * argp)1083 static int isst_if_get_perf_level_info(void __user *argp)
1084 {
1085 struct isst_perf_level_data_info perf_level;
1086 struct tpmi_per_power_domain_info *power_domain_info;
1087 int i, j;
1088
1089 if (copy_from_user(&perf_level, argp, sizeof(perf_level)))
1090 return -EFAULT;
1091
1092 power_domain_info = get_instance(perf_level.socket_id, perf_level.power_domain_id);
1093 if (!power_domain_info)
1094 return -EINVAL;
1095
1096 if (perf_level.level > power_domain_info->max_level)
1097 return -EINVAL;
1098
1099 if (!(power_domain_info->pp_header.level_en_mask & BIT(perf_level.level)))
1100 return -EINVAL;
1101
1102 _read_pp_level_info("tdp_ratio", perf_level.tdp_ratio, perf_level.level,
1103 SST_PP_INFO_0_OFFSET, SST_PP_P1_SSE_START, SST_PP_P1_SSE_WIDTH,
1104 SST_MUL_FACTOR_NONE)
1105 _read_pp_level_info("base_freq_mhz", perf_level.base_freq_mhz, perf_level.level,
1106 SST_PP_INFO_0_OFFSET, SST_PP_P1_SSE_START, SST_PP_P1_SSE_WIDTH,
1107 SST_MUL_FACTOR_FREQ)
1108 _read_pp_level_info("base_freq_avx2_mhz", perf_level.base_freq_avx2_mhz, perf_level.level,
1109 SST_PP_INFO_0_OFFSET, SST_PP_P1_AVX2_START, SST_PP_P1_AVX2_WIDTH,
1110 SST_MUL_FACTOR_FREQ)
1111 _read_pp_level_info("base_freq_avx512_mhz", perf_level.base_freq_avx512_mhz,
1112 perf_level.level, SST_PP_INFO_0_OFFSET, SST_PP_P1_AVX512_START,
1113 SST_PP_P1_AVX512_WIDTH, SST_MUL_FACTOR_FREQ)
1114 _read_pp_level_info("base_freq_amx_mhz", perf_level.base_freq_amx_mhz, perf_level.level,
1115 SST_PP_INFO_0_OFFSET, SST_PP_P1_AMX_START, SST_PP_P1_AMX_WIDTH,
1116 SST_MUL_FACTOR_FREQ)
1117
1118 _read_pp_level_info("thermal_design_power_w", perf_level.thermal_design_power_w,
1119 perf_level.level, SST_PP_INFO_1_OFFSET, SST_PP_TDP_START,
1120 SST_PP_TDP_WIDTH, SST_MUL_FACTOR_NONE)
1121 perf_level.thermal_design_power_w /= 8; /* units are in 1/8th watt */
1122 _read_pp_level_info("tjunction_max_c", perf_level.tjunction_max_c, perf_level.level,
1123 SST_PP_INFO_1_OFFSET, SST_PP_T_PROCHOT_START, SST_PP_T_PROCHOT_WIDTH,
1124 SST_MUL_FACTOR_NONE)
1125 _read_pp_level_info("max_memory_freq_mhz", perf_level.max_memory_freq_mhz,
1126 perf_level.level, SST_PP_INFO_1_OFFSET, SST_PP_MAX_MEMORY_FREQ_START,
1127 SST_PP_MAX_MEMORY_FREQ_WIDTH, SST_MUL_FACTOR_FREQ)
1128 _read_pp_level_info("cooling_type", perf_level.cooling_type, perf_level.level,
1129 SST_PP_INFO_1_OFFSET, SST_PP_COOLING_TYPE_START,
1130 SST_PP_COOLING_TYPE_WIDTH, SST_MUL_FACTOR_NONE)
1131
1132 for (i = 0; i < TRL_MAX_LEVELS; ++i) {
1133 for (j = 0; j < TRL_MAX_BUCKETS; ++j)
1134 _read_pp_level_info("trl*_bucket*_freq_mhz",
1135 perf_level.trl_freq_mhz[i][j], perf_level.level,
1136 SST_PP_INFO_4_OFFSET + (i * SST_PP_TRL_0_RATIO_0_WIDTH),
1137 j * SST_PP_TRL_0_RATIO_0_WIDTH,
1138 SST_PP_TRL_0_RATIO_0_WIDTH,
1139 SST_MUL_FACTOR_FREQ);
1140 }
1141
1142 for (i = 0; i < TRL_MAX_BUCKETS; ++i)
1143 _read_pp_level_info("bucket*_core_count", perf_level.bucket_core_counts[i],
1144 perf_level.level, SST_PP_INFO_10_OFFSET,
1145 SST_PP_TRL_CORES_BUCKET_0_WIDTH * i,
1146 SST_PP_TRL_CORES_BUCKET_0_WIDTH, SST_MUL_FACTOR_NONE)
1147
1148 perf_level.max_buckets = TRL_MAX_BUCKETS;
1149 perf_level.max_trl_levels = TRL_MAX_LEVELS;
1150
1151 _read_pp_level_info("p0_freq_mhz", perf_level.p0_freq_mhz, perf_level.level,
1152 SST_PP_INFO_11_OFFSET, SST_PP_CORE_RATIO_P0_START,
1153 SST_PP_CORE_RATIO_P0_WIDTH, SST_MUL_FACTOR_FREQ)
1154 _read_pp_level_info("p1_freq_mhz", perf_level.p1_freq_mhz, perf_level.level,
1155 SST_PP_INFO_11_OFFSET, SST_PP_CORE_RATIO_P1_START,
1156 SST_PP_CORE_RATIO_P1_WIDTH, SST_MUL_FACTOR_FREQ)
1157 _read_pp_level_info("pn_freq_mhz", perf_level.pn_freq_mhz, perf_level.level,
1158 SST_PP_INFO_11_OFFSET, SST_PP_CORE_RATIO_PN_START,
1159 SST_PP_CORE_RATIO_PN_WIDTH, SST_MUL_FACTOR_FREQ)
1160 _read_pp_level_info("pm_freq_mhz", perf_level.pm_freq_mhz, perf_level.level,
1161 SST_PP_INFO_11_OFFSET, SST_PP_CORE_RATIO_PM_START,
1162 SST_PP_CORE_RATIO_PM_WIDTH, SST_MUL_FACTOR_FREQ)
1163 _read_pp_level_info("p0_fabric_freq_mhz", perf_level.p0_fabric_freq_mhz,
1164 perf_level.level, SST_PP_INFO_11_OFFSET,
1165 SST_PP_CORE_RATIO_P0_FABRIC_START,
1166 SST_PP_CORE_RATIO_P0_FABRIC_WIDTH, SST_MUL_FACTOR_FREQ)
1167 _read_pp_level_info("p1_fabric_freq_mhz", perf_level.p1_fabric_freq_mhz,
1168 perf_level.level, SST_PP_INFO_11_OFFSET,
1169 SST_PP_CORE_RATIO_P1_FABRIC_START,
1170 SST_PP_CORE_RATIO_P1_FABRIC_WIDTH, SST_MUL_FACTOR_FREQ)
1171 _read_pp_level_info("pm_fabric_freq_mhz", perf_level.pm_fabric_freq_mhz,
1172 perf_level.level, SST_PP_INFO_11_OFFSET,
1173 SST_PP_CORE_RATIO_PM_FABRIC_START,
1174 SST_PP_CORE_RATIO_PM_FABRIC_WIDTH, SST_MUL_FACTOR_FREQ)
1175
1176 if (copy_to_user(argp, &perf_level, sizeof(perf_level)))
1177 return -EFAULT;
1178
1179 return 0;
1180 }
1181
isst_if_get_perf_level_fabric_info(void __user * argp)1182 static int isst_if_get_perf_level_fabric_info(void __user *argp)
1183 {
1184 struct isst_perf_level_fabric_info perf_level_fabric;
1185 struct tpmi_per_power_domain_info *power_domain_info;
1186 int start = SST_PP_CORE_RATIO_P0_FABRIC_START;
1187 int width = SST_PP_CORE_RATIO_P0_FABRIC_WIDTH;
1188 int offset = SST_PP_INFO_11_OFFSET;
1189 int i;
1190
1191 if (copy_from_user(&perf_level_fabric, argp, sizeof(perf_level_fabric)))
1192 return -EFAULT;
1193
1194 power_domain_info = get_instance(perf_level_fabric.socket_id,
1195 perf_level_fabric.power_domain_id);
1196 if (!power_domain_info)
1197 return -EINVAL;
1198
1199 if (perf_level_fabric.level > power_domain_info->max_level)
1200 return -EINVAL;
1201
1202 if (power_domain_info->pp_header.feature_rev < 2)
1203 return -EINVAL;
1204
1205 if (!(power_domain_info->pp_header.level_en_mask & BIT(perf_level_fabric.level)))
1206 return -EINVAL;
1207
1208 /* For revision 2, maximum number of fabrics is 2 */
1209 perf_level_fabric.max_fabrics = 2;
1210
1211 for (i = 0; i < perf_level_fabric.max_fabrics; i++) {
1212 _read_pp_level_info("p0_fabric_freq_mhz", perf_level_fabric.p0_fabric_freq_mhz[i],
1213 perf_level_fabric.level, offset, start, width,
1214 SST_MUL_FACTOR_FREQ)
1215 start += width;
1216
1217 _read_pp_level_info("p1_fabric_freq_mhz", perf_level_fabric.p1_fabric_freq_mhz[i],
1218 perf_level_fabric.level, offset, start, width,
1219 SST_MUL_FACTOR_FREQ)
1220 start += width;
1221
1222 _read_pp_level_info("pm_fabric_freq_mhz", perf_level_fabric.pm_fabric_freq_mhz[i],
1223 perf_level_fabric.level, offset, start, width,
1224 SST_MUL_FACTOR_FREQ)
1225 offset = SST_PP_INFO_12_OFFSET;
1226 start = SST_PP_CORE_RATIO_P0_FABRIC_1_START;
1227 }
1228
1229 if (copy_to_user(argp, &perf_level_fabric, sizeof(perf_level_fabric)))
1230 return -EFAULT;
1231
1232 return 0;
1233 }
1234
1235 #define SST_PP_FUSED_CORE_COUNT_START 0
1236 #define SST_PP_FUSED_CORE_COUNT_WIDTH 8
1237
1238 #define SST_PP_RSLVD_CORE_COUNT_START 8
1239 #define SST_PP_RSLVD_CORE_COUNT_WIDTH 8
1240
1241 #define SST_PP_RSLVD_CORE_MASK_START 0
1242 #define SST_PP_RSLVD_CORE_MASK_WIDTH 64
1243
isst_if_get_perf_level_mask(void __user * argp)1244 static int isst_if_get_perf_level_mask(void __user *argp)
1245 {
1246 static struct isst_perf_level_cpu_mask cpumask;
1247 struct tpmi_per_power_domain_info *power_domain_info;
1248 u64 mask;
1249
1250 if (copy_from_user(&cpumask, argp, sizeof(cpumask)))
1251 return -EFAULT;
1252
1253 power_domain_info = get_instance(cpumask.socket_id, cpumask.power_domain_id);
1254 if (!power_domain_info)
1255 return -EINVAL;
1256
1257 _read_pp_level_info("mask", mask, cpumask.level, SST_PP_INFO_2_OFFSET,
1258 SST_PP_RSLVD_CORE_MASK_START, SST_PP_RSLVD_CORE_MASK_WIDTH,
1259 SST_MUL_FACTOR_NONE)
1260
1261 cpumask.mask = mask;
1262
1263 if (!cpumask.punit_cpu_map)
1264 return -EOPNOTSUPP;
1265
1266 if (copy_to_user(argp, &cpumask, sizeof(cpumask)))
1267 return -EFAULT;
1268
1269 return 0;
1270 }
1271
1272 #define SST_BF_INFO_0_OFFSET 0
1273 #define SST_BF_INFO_1_OFFSET 8
1274
1275 #define SST_BF_P1_HIGH_START 13
1276 #define SST_BF_P1_HIGH_WIDTH 8
1277
1278 #define SST_BF_P1_LOW_START 21
1279 #define SST_BF_P1_LOW_WIDTH 8
1280
1281 #define SST_BF_T_PROHOT_START 38
1282 #define SST_BF_T_PROHOT_WIDTH 8
1283
1284 #define SST_BF_TDP_START 46
1285 #define SST_BF_TDP_WIDTH 15
1286
isst_if_get_base_freq_info(void __user * argp)1287 static int isst_if_get_base_freq_info(void __user *argp)
1288 {
1289 static struct isst_base_freq_info base_freq;
1290 struct tpmi_per_power_domain_info *power_domain_info;
1291
1292 if (copy_from_user(&base_freq, argp, sizeof(base_freq)))
1293 return -EFAULT;
1294
1295 power_domain_info = get_instance(base_freq.socket_id, base_freq.power_domain_id);
1296 if (!power_domain_info)
1297 return -EINVAL;
1298
1299 if (base_freq.level > power_domain_info->max_level)
1300 return -EINVAL;
1301
1302 _read_bf_level_info("p1_high", base_freq.high_base_freq_mhz, base_freq.level,
1303 SST_BF_INFO_0_OFFSET, SST_BF_P1_HIGH_START, SST_BF_P1_HIGH_WIDTH,
1304 SST_MUL_FACTOR_FREQ)
1305 _read_bf_level_info("p1_low", base_freq.low_base_freq_mhz, base_freq.level,
1306 SST_BF_INFO_0_OFFSET, SST_BF_P1_LOW_START, SST_BF_P1_LOW_WIDTH,
1307 SST_MUL_FACTOR_FREQ)
1308 _read_bf_level_info("BF-TJ", base_freq.tjunction_max_c, base_freq.level,
1309 SST_BF_INFO_0_OFFSET, SST_BF_T_PROHOT_START, SST_BF_T_PROHOT_WIDTH,
1310 SST_MUL_FACTOR_NONE)
1311 _read_bf_level_info("BF-tdp", base_freq.thermal_design_power_w, base_freq.level,
1312 SST_BF_INFO_0_OFFSET, SST_BF_TDP_START, SST_BF_TDP_WIDTH,
1313 SST_MUL_FACTOR_NONE)
1314 base_freq.thermal_design_power_w /= 8; /*unit = 1/8th watt*/
1315
1316 if (copy_to_user(argp, &base_freq, sizeof(base_freq)))
1317 return -EFAULT;
1318
1319 return 0;
1320 }
1321
1322 #define P1_HI_CORE_MASK_START 0
1323 #define P1_HI_CORE_MASK_WIDTH 64
1324
isst_if_get_base_freq_mask(void __user * argp)1325 static int isst_if_get_base_freq_mask(void __user *argp)
1326 {
1327 static struct isst_perf_level_cpu_mask cpumask;
1328 struct tpmi_per_power_domain_info *power_domain_info;
1329 u64 mask;
1330
1331 if (copy_from_user(&cpumask, argp, sizeof(cpumask)))
1332 return -EFAULT;
1333
1334 power_domain_info = get_instance(cpumask.socket_id, cpumask.power_domain_id);
1335 if (!power_domain_info)
1336 return -EINVAL;
1337
1338 _read_bf_level_info("BF-cpumask", mask, cpumask.level, SST_BF_INFO_1_OFFSET,
1339 P1_HI_CORE_MASK_START, P1_HI_CORE_MASK_WIDTH,
1340 SST_MUL_FACTOR_NONE)
1341
1342 cpumask.mask = mask;
1343
1344 if (!cpumask.punit_cpu_map)
1345 return -EOPNOTSUPP;
1346
1347 if (copy_to_user(argp, &cpumask, sizeof(cpumask)))
1348 return -EFAULT;
1349
1350 return 0;
1351 }
1352
isst_if_get_tpmi_instance_count(void __user * argp)1353 static int isst_if_get_tpmi_instance_count(void __user *argp)
1354 {
1355 struct isst_tpmi_instance_count tpmi_inst;
1356 struct tpmi_sst_struct *sst_inst;
1357 int i;
1358
1359 if (copy_from_user(&tpmi_inst, argp, sizeof(tpmi_inst)))
1360 return -EFAULT;
1361
1362 if (tpmi_inst.socket_id >= topology_max_packages())
1363 return -EINVAL;
1364
1365 sst_inst = isst_common.sst_inst[tpmi_inst.socket_id];
1366
1367 tpmi_inst.count = isst_instance_count(sst_inst);
1368
1369 tpmi_inst.valid_mask = 0;
1370 for (i = 0; i < tpmi_inst.count; i++) {
1371 struct tpmi_per_power_domain_info *pd_info;
1372 u8 part;
1373 int pd;
1374
1375 pd = map_partition_power_domain_id(sst_inst, i, &part);
1376 if (pd < 0)
1377 continue;
1378
1379 pd_info = &sst_inst->power_domain_info[part][pd];
1380 if (pd_info->sst_base)
1381 tpmi_inst.valid_mask |= BIT(i);
1382 }
1383
1384 if (!tpmi_inst.valid_mask)
1385 tpmi_inst.count = 0;
1386
1387 if (copy_to_user(argp, &tpmi_inst, sizeof(tpmi_inst)))
1388 return -EFAULT;
1389
1390 return 0;
1391 }
1392
1393 #define SST_TF_INFO_0_OFFSET 0
1394 #define SST_TF_INFO_1_OFFSET 8
1395 #define SST_TF_INFO_2_OFFSET 16
1396 #define SST_TF_INFO_8_OFFSET 64
1397 #define SST_TF_INFO_8_BUCKETS 3
1398
1399 #define SST_TF_MAX_LP_CLIP_RATIOS TRL_MAX_LEVELS
1400
1401 #define SST_TF_FEATURE_REV_START 4
1402 #define SST_TF_FEATURE_REV_WIDTH 8
1403
1404 #define SST_TF_LP_CLIP_RATIO_0_START 16
1405 #define SST_TF_LP_CLIP_RATIO_0_WIDTH 8
1406
1407 #define SST_TF_RATIO_0_START 0
1408 #define SST_TF_RATIO_0_WIDTH 8
1409
1410 #define SST_TF_NUM_CORE_0_START 0
1411 #define SST_TF_NUM_CORE_0_WIDTH 8
1412
1413 #define SST_TF_NUM_MOD_0_START 0
1414 #define SST_TF_NUM_MOD_0_WIDTH 16
1415
isst_if_get_turbo_freq_info(void __user * argp)1416 static int isst_if_get_turbo_freq_info(void __user *argp)
1417 {
1418 static struct isst_turbo_freq_info turbo_freq;
1419 struct tpmi_per_power_domain_info *power_domain_info;
1420 u8 feature_rev;
1421 int i, j;
1422
1423 if (copy_from_user(&turbo_freq, argp, sizeof(turbo_freq)))
1424 return -EFAULT;
1425
1426 power_domain_info = get_instance(turbo_freq.socket_id, turbo_freq.power_domain_id);
1427 if (!power_domain_info)
1428 return -EINVAL;
1429
1430 if (turbo_freq.level > power_domain_info->max_level)
1431 return -EINVAL;
1432
1433 turbo_freq.max_buckets = TRL_MAX_BUCKETS;
1434 turbo_freq.max_trl_levels = TRL_MAX_LEVELS;
1435 turbo_freq.max_clip_freqs = SST_TF_MAX_LP_CLIP_RATIOS;
1436
1437 _read_tf_level_info("feature_rev", feature_rev, turbo_freq.level,
1438 SST_TF_INFO_0_OFFSET, SST_TF_FEATURE_REV_START,
1439 SST_TF_FEATURE_REV_WIDTH, SST_MUL_FACTOR_NONE);
1440
1441 for (i = 0; i < turbo_freq.max_clip_freqs; ++i)
1442 _read_tf_level_info("lp_clip*", turbo_freq.lp_clip_freq_mhz[i],
1443 turbo_freq.level, SST_TF_INFO_0_OFFSET,
1444 SST_TF_LP_CLIP_RATIO_0_START +
1445 (i * SST_TF_LP_CLIP_RATIO_0_WIDTH),
1446 SST_TF_LP_CLIP_RATIO_0_WIDTH, SST_MUL_FACTOR_FREQ)
1447
1448 for (i = 0; i < TRL_MAX_LEVELS; ++i) {
1449 for (j = 0; j < TRL_MAX_BUCKETS; ++j)
1450 _read_tf_level_info("cydn*_bucket_*_trl",
1451 turbo_freq.trl_freq_mhz[i][j], turbo_freq.level,
1452 SST_TF_INFO_2_OFFSET + (i * SST_TF_RATIO_0_WIDTH),
1453 j * SST_TF_RATIO_0_WIDTH, SST_TF_RATIO_0_WIDTH,
1454 SST_MUL_FACTOR_FREQ)
1455 }
1456
1457 if (feature_rev >= 2) {
1458 bool has_tf_info_8 = false;
1459
1460 for (i = 0; i < SST_TF_INFO_8_BUCKETS; ++i) {
1461 _read_tf_level_info("bucket_*_mod_count", turbo_freq.bucket_core_counts[i],
1462 turbo_freq.level, SST_TF_INFO_8_OFFSET,
1463 SST_TF_NUM_MOD_0_WIDTH * i, SST_TF_NUM_MOD_0_WIDTH,
1464 SST_MUL_FACTOR_NONE)
1465
1466 if (turbo_freq.bucket_core_counts[i])
1467 has_tf_info_8 = true;
1468 }
1469
1470 if (has_tf_info_8)
1471 goto done_core_count;
1472 }
1473
1474 for (i = 0; i < TRL_MAX_BUCKETS; ++i)
1475 _read_tf_level_info("bucket_*_core_count", turbo_freq.bucket_core_counts[i],
1476 turbo_freq.level, SST_TF_INFO_1_OFFSET,
1477 SST_TF_NUM_CORE_0_WIDTH * i, SST_TF_NUM_CORE_0_WIDTH,
1478 SST_MUL_FACTOR_NONE)
1479
1480
1481 done_core_count:
1482
1483 if (copy_to_user(argp, &turbo_freq, sizeof(turbo_freq)))
1484 return -EFAULT;
1485
1486 return 0;
1487 }
1488
isst_if_def_ioctl(struct file * file,unsigned int cmd,unsigned long arg)1489 static long isst_if_def_ioctl(struct file *file, unsigned int cmd,
1490 unsigned long arg)
1491 {
1492 void __user *argp = (void __user *)arg;
1493 long ret = -ENOTTY;
1494
1495 mutex_lock(&isst_tpmi_dev_lock);
1496 switch (cmd) {
1497 case ISST_IF_COUNT_TPMI_INSTANCES:
1498 ret = isst_if_get_tpmi_instance_count(argp);
1499 break;
1500 case ISST_IF_CORE_POWER_STATE:
1501 ret = isst_if_core_power_state(argp);
1502 break;
1503 case ISST_IF_CLOS_PARAM:
1504 ret = isst_if_clos_param(argp);
1505 break;
1506 case ISST_IF_CLOS_ASSOC:
1507 ret = isst_if_clos_assoc(argp);
1508 break;
1509 case ISST_IF_PERF_LEVELS:
1510 ret = isst_if_get_perf_level(argp);
1511 break;
1512 case ISST_IF_PERF_SET_LEVEL:
1513 ret = isst_if_set_perf_level(argp);
1514 break;
1515 case ISST_IF_PERF_SET_FEATURE:
1516 ret = isst_if_set_perf_feature(argp);
1517 break;
1518 case ISST_IF_GET_PERF_LEVEL_INFO:
1519 ret = isst_if_get_perf_level_info(argp);
1520 break;
1521 case ISST_IF_GET_PERF_LEVEL_FABRIC_INFO:
1522 ret = isst_if_get_perf_level_fabric_info(argp);
1523 break;
1524 case ISST_IF_GET_PERF_LEVEL_CPU_MASK:
1525 ret = isst_if_get_perf_level_mask(argp);
1526 break;
1527 case ISST_IF_GET_BASE_FREQ_INFO:
1528 ret = isst_if_get_base_freq_info(argp);
1529 break;
1530 case ISST_IF_GET_BASE_FREQ_CPU_MASK:
1531 ret = isst_if_get_base_freq_mask(argp);
1532 break;
1533 case ISST_IF_GET_TURBO_FREQ_INFO:
1534 ret = isst_if_get_turbo_freq_info(argp);
1535 break;
1536 default:
1537 break;
1538 }
1539 mutex_unlock(&isst_tpmi_dev_lock);
1540
1541 return ret;
1542 }
1543
1544 #define TPMI_SST_AUTO_SUSPEND_DELAY_MS 2000
1545
tpmi_sst_dev_add(struct auxiliary_device * auxdev)1546 int tpmi_sst_dev_add(struct auxiliary_device *auxdev)
1547 {
1548 struct tpmi_per_power_domain_info *pd_info;
1549 bool read_blocked = 0, write_blocked = 0;
1550 struct oobmsm_plat_info *plat_info;
1551 struct device *dev = &auxdev->dev;
1552 struct tpmi_sst_struct *tpmi_sst;
1553 u8 i, num_resources, io_die_cnt;
1554 int ret, pkg = 0, inst = 0;
1555 bool first_enum = false;
1556 u16 cdie_mask;
1557 u8 partition;
1558
1559 ret = tpmi_get_feature_status(auxdev, TPMI_ID_SST, &read_blocked, &write_blocked);
1560 if (ret)
1561 dev_info(dev, "Can't read feature status: ignoring read/write blocked status\n");
1562
1563 if (read_blocked) {
1564 dev_info(dev, "Firmware has blocked reads, exiting\n");
1565 return -ENODEV;
1566 }
1567
1568 plat_info = tpmi_get_platform_data(auxdev);
1569 if (!plat_info) {
1570 dev_err(dev, "No platform info\n");
1571 return -EINVAL;
1572 }
1573
1574 pkg = plat_info->package_id;
1575 if (pkg >= topology_max_packages()) {
1576 dev_err(dev, "Invalid package id :%x\n", pkg);
1577 return -EINVAL;
1578 }
1579
1580 partition = plat_info->partition;
1581 if (partition >= SST_MAX_PARTITIONS) {
1582 dev_err(&auxdev->dev, "Invalid partition :%x\n", partition);
1583 return -EINVAL;
1584 }
1585
1586 num_resources = tpmi_get_resource_count(auxdev);
1587
1588 if (!num_resources)
1589 return -EINVAL;
1590
1591 mutex_lock(&isst_tpmi_dev_lock);
1592
1593 if (isst_common.sst_inst[pkg]) {
1594 tpmi_sst = isst_common.sst_inst[pkg];
1595 } else {
1596 /*
1597 * tpmi_sst instance is for a package. So needs to be
1598 * allocated only once for both partitions. We can't use
1599 * devm_* allocation here as each partition is a
1600 * different device, which can be unbound.
1601 */
1602 tpmi_sst = kzalloc(sizeof(*tpmi_sst), GFP_KERNEL);
1603 if (!tpmi_sst) {
1604 ret = -ENOMEM;
1605 goto unlock_exit;
1606 }
1607 first_enum = true;
1608 }
1609
1610 ret = 0;
1611
1612 pd_info = devm_kcalloc(dev, num_resources, sizeof(*pd_info), GFP_KERNEL);
1613 if (!pd_info) {
1614 ret = -ENOMEM;
1615 goto unlock_free;
1616 }
1617
1618 /* Get the IO die count, if cdie_mask is present */
1619 if (plat_info->cdie_mask) {
1620 u8 cdie_range;
1621
1622 cdie_mask = plat_info->cdie_mask;
1623 cdie_range = fls(cdie_mask) - ffs(cdie_mask) + 1;
1624 io_die_cnt = num_resources - cdie_range;
1625 } else {
1626 /*
1627 * This is a synthetic mask, careful when assuming that
1628 * they are compute dies only.
1629 */
1630 cdie_mask = (1 << num_resources) - 1;
1631 io_die_cnt = 0;
1632 }
1633
1634 for (i = 0; i < num_resources; ++i) {
1635 struct resource *res;
1636
1637 res = tpmi_get_resource_at_index(auxdev, i);
1638 if (!res) {
1639 pd_info[i].sst_base = NULL;
1640 continue;
1641 }
1642
1643 pd_info[i].package_id = pkg;
1644 pd_info[i].power_domain_id = i;
1645 pd_info[i].auxdev = auxdev;
1646 pd_info[i].write_blocked = write_blocked;
1647 pd_info[i].sst_base = devm_ioremap_resource(dev, res);
1648 if (IS_ERR(pd_info[i].sst_base)) {
1649 ret = PTR_ERR(pd_info[i].sst_base);
1650 goto unlock_free;
1651 }
1652
1653 if (sst_main(auxdev, &pd_info[i])) {
1654 /*
1655 * This entry is not valid, hardware can partially
1656 * populate dies. In this case MMIO will have 0xFFs.
1657 * Also possible some pre-production hardware has
1658 * invalid data. But don't fail and continue to use
1659 * other dies with valid data.
1660 */
1661 devm_iounmap(dev, pd_info[i].sst_base);
1662 pd_info[i].sst_base = NULL;
1663 continue;
1664 }
1665
1666 ++inst;
1667 }
1668
1669 if (!inst) {
1670 ret = -ENODEV;
1671 goto unlock_free;
1672 }
1673
1674 tpmi_sst->package_id = pkg;
1675
1676 tpmi_sst->power_domain_info[partition] = pd_info;
1677 tpmi_sst->number_of_power_domains[partition] = num_resources;
1678 tpmi_sst->cdie_mask[partition] = cdie_mask;
1679 tpmi_sst->io_dies[partition] = io_die_cnt;
1680 tpmi_sst->partition_mask |= BIT(partition);
1681 tpmi_sst->partition_mask_current |= BIT(partition);
1682
1683 auxiliary_set_drvdata(auxdev, tpmi_sst);
1684
1685 if (isst_common.max_index < pkg)
1686 isst_common.max_index = pkg;
1687 isst_common.sst_inst[pkg] = tpmi_sst;
1688
1689 unlock_free:
1690 if (ret && first_enum)
1691 kfree(tpmi_sst);
1692 unlock_exit:
1693 mutex_unlock(&isst_tpmi_dev_lock);
1694
1695 return ret;
1696 }
1697 EXPORT_SYMBOL_NS_GPL(tpmi_sst_dev_add, "INTEL_TPMI_SST");
1698
tpmi_sst_dev_remove(struct auxiliary_device * auxdev)1699 void tpmi_sst_dev_remove(struct auxiliary_device *auxdev)
1700 {
1701 struct tpmi_sst_struct *tpmi_sst = auxiliary_get_drvdata(auxdev);
1702 struct oobmsm_plat_info *plat_info;
1703
1704 plat_info = tpmi_get_platform_data(auxdev);
1705 if (!plat_info)
1706 return;
1707
1708 mutex_lock(&isst_tpmi_dev_lock);
1709 tpmi_sst->power_domain_info[plat_info->partition] = NULL;
1710 tpmi_sst->partition_mask_current &= ~BIT(plat_info->partition);
1711 /* Free the package instance when the all partitions are removed */
1712 if (!tpmi_sst->partition_mask_current) {
1713 isst_common.sst_inst[tpmi_sst->package_id] = NULL;
1714 kfree(tpmi_sst);
1715 }
1716 mutex_unlock(&isst_tpmi_dev_lock);
1717 }
1718 EXPORT_SYMBOL_NS_GPL(tpmi_sst_dev_remove, "INTEL_TPMI_SST");
1719
tpmi_sst_dev_suspend(struct auxiliary_device * auxdev)1720 void tpmi_sst_dev_suspend(struct auxiliary_device *auxdev)
1721 {
1722 struct tpmi_sst_struct *tpmi_sst = auxiliary_get_drvdata(auxdev);
1723 struct tpmi_per_power_domain_info *power_domain_info;
1724 struct oobmsm_plat_info *plat_info;
1725 void __iomem *cp_base;
1726
1727 plat_info = tpmi_get_platform_data(auxdev);
1728 if (!plat_info)
1729 return;
1730
1731 power_domain_info = tpmi_sst->power_domain_info[plat_info->partition];
1732
1733 cp_base = power_domain_info->sst_base + power_domain_info->sst_header.cp_offset;
1734 power_domain_info->saved_sst_cp_control = readq(cp_base + SST_CP_CONTROL_OFFSET);
1735
1736 memcpy_fromio(power_domain_info->saved_clos_configs, cp_base + SST_CLOS_CONFIG_0_OFFSET,
1737 sizeof(power_domain_info->saved_clos_configs));
1738
1739 memcpy_fromio(power_domain_info->saved_clos_assocs, cp_base + SST_CLOS_ASSOC_0_OFFSET,
1740 sizeof(power_domain_info->saved_clos_assocs));
1741
1742 power_domain_info->saved_pp_control = readq(power_domain_info->sst_base +
1743 power_domain_info->sst_header.pp_offset +
1744 SST_PP_CONTROL_OFFSET);
1745 }
1746 EXPORT_SYMBOL_NS_GPL(tpmi_sst_dev_suspend, "INTEL_TPMI_SST");
1747
tpmi_sst_dev_resume(struct auxiliary_device * auxdev)1748 void tpmi_sst_dev_resume(struct auxiliary_device *auxdev)
1749 {
1750 struct tpmi_sst_struct *tpmi_sst = auxiliary_get_drvdata(auxdev);
1751 struct tpmi_per_power_domain_info *power_domain_info;
1752 struct oobmsm_plat_info *plat_info;
1753 void __iomem *cp_base;
1754
1755 plat_info = tpmi_get_platform_data(auxdev);
1756 if (!plat_info)
1757 return;
1758
1759 power_domain_info = tpmi_sst->power_domain_info[plat_info->partition];
1760
1761 cp_base = power_domain_info->sst_base + power_domain_info->sst_header.cp_offset;
1762 writeq(power_domain_info->saved_sst_cp_control, cp_base + SST_CP_CONTROL_OFFSET);
1763
1764 memcpy_toio(cp_base + SST_CLOS_CONFIG_0_OFFSET, power_domain_info->saved_clos_configs,
1765 sizeof(power_domain_info->saved_clos_configs));
1766
1767 memcpy_toio(cp_base + SST_CLOS_ASSOC_0_OFFSET, power_domain_info->saved_clos_assocs,
1768 sizeof(power_domain_info->saved_clos_assocs));
1769
1770 writeq(power_domain_info->saved_pp_control, power_domain_info->sst_base +
1771 power_domain_info->sst_header.pp_offset + SST_PP_CONTROL_OFFSET);
1772 }
1773 EXPORT_SYMBOL_NS_GPL(tpmi_sst_dev_resume, "INTEL_TPMI_SST");
1774
1775 #define ISST_TPMI_API_VERSION 0x03
1776
tpmi_sst_init(void)1777 int tpmi_sst_init(void)
1778 {
1779 struct isst_if_cmd_cb cb;
1780 int ret = 0;
1781
1782 mutex_lock(&isst_tpmi_dev_lock);
1783
1784 if (isst_core_usage_count) {
1785 ++isst_core_usage_count;
1786 goto init_done;
1787 }
1788
1789 isst_common.sst_inst = kcalloc(topology_max_packages(),
1790 sizeof(*isst_common.sst_inst),
1791 GFP_KERNEL);
1792 if (!isst_common.sst_inst) {
1793 ret = -ENOMEM;
1794 goto init_done;
1795 }
1796
1797 memset(&cb, 0, sizeof(cb));
1798 cb.cmd_size = sizeof(struct isst_if_io_reg);
1799 cb.offset = offsetof(struct isst_if_io_regs, io_reg);
1800 cb.cmd_callback = NULL;
1801 cb.api_version = ISST_TPMI_API_VERSION;
1802 cb.def_ioctl = isst_if_def_ioctl;
1803 cb.owner = THIS_MODULE;
1804 ret = isst_if_cdev_register(ISST_IF_DEV_TPMI, &cb);
1805 if (ret)
1806 kfree(isst_common.sst_inst);
1807 else
1808 ++isst_core_usage_count;
1809 init_done:
1810 mutex_unlock(&isst_tpmi_dev_lock);
1811 return ret;
1812 }
1813 EXPORT_SYMBOL_NS_GPL(tpmi_sst_init, "INTEL_TPMI_SST");
1814
tpmi_sst_exit(void)1815 void tpmi_sst_exit(void)
1816 {
1817 mutex_lock(&isst_tpmi_dev_lock);
1818 if (isst_core_usage_count)
1819 --isst_core_usage_count;
1820
1821 if (!isst_core_usage_count) {
1822 isst_if_cdev_unregister(ISST_IF_DEV_TPMI);
1823 kfree(isst_common.sst_inst);
1824 }
1825 mutex_unlock(&isst_tpmi_dev_lock);
1826 }
1827 EXPORT_SYMBOL_NS_GPL(tpmi_sst_exit, "INTEL_TPMI_SST");
1828
1829 MODULE_IMPORT_NS("INTEL_TPMI");
1830 MODULE_IMPORT_NS("INTEL_TPMI_POWER_DOMAIN");
1831
1832 MODULE_DESCRIPTION("ISST TPMI interface module");
1833 MODULE_LICENSE("GPL");
1834