1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 *
4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 *
6 * Authors:
7 * Md Sadre Alam <quic_mdalam@quicinc.com>
8 * Sricharan R <quic_srichara@quicinc.com>
9 * Varadarajan Narayanan <quic_varada@quicinc.com>
10 */
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dma/qcom_adm.h>
17 #include <linux/dma/qcom_bam_dma.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/mtd/nand-qpic-common.h>
23 #include <linux/mtd/spinand.h>
24 #include <linux/bitfield.h>
25
26 #define NAND_FLASH_SPI_CFG 0xc0
27 #define NAND_NUM_ADDR_CYCLES 0xc4
28 #define NAND_BUSY_CHECK_WAIT_CNT 0xc8
29 #define NAND_FLASH_FEATURES 0xf64
30
31 /* QSPI NAND config reg bits */
32 #define LOAD_CLK_CNTR_INIT_EN BIT(28)
33 #define CLK_CNTR_INIT_VAL_VEC 0x924
34 #define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
35 #define FEA_STATUS_DEV_ADDR 0xc0
36 #define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
37 #define SPI_CFG BIT(0)
38 #define SPI_NUM_ADDR 0xDA4DB
39 #define SPI_WAIT_CNT 0x10
40 #define QPIC_QSPI_NUM_CS 1
41 #define SPI_TRANSFER_MODE_x1 BIT(29)
42 #define SPI_TRANSFER_MODE_x4 (3 << 29)
43 #define SPI_WP BIT(28)
44 #define SPI_HOLD BIT(27)
45 #define QPIC_SET_FEATURE BIT(31)
46
47 #define SPINAND_RESET 0xff
48 #define SPINAND_READID 0x9f
49 #define SPINAND_FEATURE_ADDR 0xb0
50 #define SPINAND_GET_FEATURE 0x0f
51 #define SPINAND_SET_FEATURE 0x1f
52 #define SPINAND_READ_CACHE 0x0b
53 #define SPINAND_READ 0x13
54 #define SPINAND_READ_QUAD 0xeb
55 #define SPINAND_READ_MACRONIX 0x6b
56 #define SPINAND_ERASE 0xd8
57 #define SPINAND_WRITE_EN 0x06
58 #define SPINAND_PROGRAM_EXECUTE 0x10
59 #define SPINAND_PROGRAM_LOAD 0x84
60 #define SPINAND_PROGRAM_LOAD_QUAD 0x34
61
62 #define QUAD_WIDTH 0x4
63 #define ACC_FEATURE 0xe
64 #define BAD_BLOCK_MARKER_SIZE 0x2
65 #define OOB_BUF_SIZE 128
66 #define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
67
68 struct snandc_read_status {
69 __le32 snandc_flash;
70 __le32 snandc_buffer;
71 __le32 snandc_erased_cw;
72 };
73
74 /*
75 * ECC state struct
76 * @corrected: ECC corrected
77 * @bitflips: Max bit flip
78 * @failed: ECC failed
79 */
80 struct qcom_ecc_stats {
81 u32 corrected;
82 u32 bitflips;
83 u32 failed;
84 };
85
86 struct qpic_ecc {
87 int ecc_bytes_hw;
88 int spare_bytes;
89 int bbm_size;
90 int ecc_mode;
91 int bytes;
92 int steps;
93 int step_size;
94 int strength;
95 int cw_size;
96 int cw_data;
97 u32 cfg0;
98 u32 cfg1;
99 u32 cfg0_raw;
100 u32 cfg1_raw;
101 u32 ecc_buf_cfg;
102 u32 ecc_bch_cfg;
103 bool bch_enabled;
104 };
105
106 struct qpic_spi_nand {
107 struct qcom_nand_controller *snandc;
108 struct spi_controller *ctlr;
109 struct mtd_info *mtd;
110 struct clk *iomacro_clk;
111 struct qpic_ecc *ecc;
112 struct qcom_ecc_stats ecc_stats;
113 struct nand_ecc_engine ecc_eng;
114 u8 *data_buf;
115 u8 *oob_buf;
116 __le32 addr1;
117 __le32 addr2;
118 __le32 cmd;
119 u32 num_cw;
120 bool oob_rw;
121 bool page_rw;
122 bool raw_rw;
123 bool quad_mode;
124 };
125
qcom_spi_set_read_loc_first(struct qcom_nand_controller * snandc,int reg,int cw_offset,int read_size,int is_last_read_loc)126 static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
127 int reg, int cw_offset, int read_size,
128 int is_last_read_loc)
129 {
130 __le32 locreg_val;
131 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
132 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
133 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
134
135 locreg_val = cpu_to_le32(val);
136
137 if (reg == NAND_READ_LOCATION_0)
138 snandc->regs->read_location0 = locreg_val;
139 else if (reg == NAND_READ_LOCATION_1)
140 snandc->regs->read_location1 = locreg_val;
141 else if (reg == NAND_READ_LOCATION_2)
142 snandc->regs->read_location2 = locreg_val;
143 else if (reg == NAND_READ_LOCATION_3)
144 snandc->regs->read_location3 = locreg_val;
145 }
146
qcom_spi_set_read_loc_last(struct qcom_nand_controller * snandc,int reg,int cw_offset,int read_size,int is_last_read_loc)147 static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
148 int reg, int cw_offset, int read_size,
149 int is_last_read_loc)
150 {
151 __le32 locreg_val;
152 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
153 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
154 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
155
156 locreg_val = cpu_to_le32(val);
157
158 if (reg == NAND_READ_LOCATION_LAST_CW_0)
159 snandc->regs->read_location_last0 = locreg_val;
160 else if (reg == NAND_READ_LOCATION_LAST_CW_1)
161 snandc->regs->read_location_last1 = locreg_val;
162 else if (reg == NAND_READ_LOCATION_LAST_CW_2)
163 snandc->regs->read_location_last2 = locreg_val;
164 else if (reg == NAND_READ_LOCATION_LAST_CW_3)
165 snandc->regs->read_location_last3 = locreg_val;
166 }
167
nand_to_qcom_snand(struct nand_device * nand)168 static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
169 {
170 struct nand_ecc_engine *eng = nand->ecc.engine;
171 struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
172
173 return qspi->snandc;
174 }
175
qcom_spi_init(struct qcom_nand_controller * snandc)176 static int qcom_spi_init(struct qcom_nand_controller *snandc)
177 {
178 u32 snand_cfg_val = 0x0;
179 int ret;
180
181 snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
182 FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
183 FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
184 FIELD_PREP(SPI_CFG, 0);
185
186 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
187 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
188 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
189
190 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
191
192 snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
193 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
194
195 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
196
197 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
198 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
199 NAND_BAM_NEXT_SGL);
200
201 ret = qcom_submit_descs(snandc);
202 if (ret) {
203 dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
204 return ret;
205 }
206
207 return ret;
208 }
209
qcom_spi_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)210 static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
211 struct mtd_oob_region *oobregion)
212 {
213 struct nand_device *nand = mtd_to_nanddev(mtd);
214 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
215 struct qpic_ecc *qecc = snandc->qspi->ecc;
216
217 switch (section) {
218 case 0:
219 oobregion->offset = 0;
220 oobregion->length = qecc->bytes * (qecc->steps - 1) +
221 qecc->bbm_size;
222 return 0;
223 case 1:
224 oobregion->offset = qecc->bytes * (qecc->steps - 1) +
225 qecc->bbm_size +
226 qecc->steps * 4;
227 oobregion->length = mtd->oobsize - oobregion->offset;
228 return 0;
229 }
230
231 return -ERANGE;
232 }
233
qcom_spi_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)234 static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
235 struct mtd_oob_region *oobregion)
236 {
237 struct nand_device *nand = mtd_to_nanddev(mtd);
238 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
239 struct qpic_ecc *qecc = snandc->qspi->ecc;
240
241 if (section)
242 return -ERANGE;
243
244 oobregion->length = qecc->steps * 4;
245 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
246
247 return 0;
248 }
249
250 static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
251 .ecc = qcom_spi_ooblayout_ecc,
252 .free = qcom_spi_ooblayout_free,
253 };
254
qcom_spi_ecc_init_ctx_pipelined(struct nand_device * nand)255 static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
256 {
257 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
258 struct nand_ecc_props *reqs = &nand->ecc.requirements;
259 struct nand_ecc_props *user = &nand->ecc.user_conf;
260 struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
261 struct mtd_info *mtd = nanddev_to_mtd(nand);
262 int cwperpage, bad_block_byte, ret;
263 struct qpic_ecc *ecc_cfg;
264
265 cwperpage = mtd->writesize / NANDC_STEP_SIZE;
266 snandc->qspi->num_cw = cwperpage;
267
268 ecc_cfg = kzalloc_obj(*ecc_cfg);
269 if (!ecc_cfg)
270 return -ENOMEM;
271
272 if (user->step_size && user->strength) {
273 ecc_cfg->step_size = user->step_size;
274 ecc_cfg->strength = user->strength;
275 } else if (reqs->step_size && reqs->strength) {
276 ecc_cfg->step_size = reqs->step_size;
277 ecc_cfg->strength = reqs->strength;
278 } else {
279 /* use defaults */
280 ecc_cfg->step_size = NANDC_STEP_SIZE;
281 ecc_cfg->strength = 4;
282 }
283
284 /*
285 * Override ECC strength based on OOB size to avoid weak ECC warning.
286 * If OOB size is more than 128 bytes, use 8-bit ECC for better
287 * error correction capability, which is required by chips with
288 * larger OOB areas like Macronix SPI NAND with 256 bytes OOB.
289 */
290 if (mtd->oobsize >= 128 && ecc_cfg->strength < 8) {
291 dev_info(snandc->dev,
292 "Upgrading ECC strength from %d to 8 bits (OOB size: %d bytes)\n",
293 ecc_cfg->strength, mtd->oobsize);
294 ecc_cfg->strength = 8;
295 }
296
297 if (ecc_cfg->step_size != NANDC_STEP_SIZE) {
298 dev_err(snandc->dev,
299 "only %u bytes ECC step size is supported\n",
300 NANDC_STEP_SIZE);
301 ret = -EOPNOTSUPP;
302 goto err_free_ecc_cfg;
303 }
304
305 switch (ecc_cfg->strength) {
306 case 4:
307 ecc_cfg->ecc_mode = ECC_MODE_4BIT;
308 ecc_cfg->ecc_bytes_hw = 7;
309 ecc_cfg->spare_bytes = 4;
310 break;
311
312 case 8:
313 ecc_cfg->ecc_mode = ECC_MODE_8BIT;
314 ecc_cfg->ecc_bytes_hw = 13;
315 ecc_cfg->spare_bytes = 2;
316 break;
317
318 default:
319 dev_err(snandc->dev,
320 "only 4 or 8 bits ECC strength is supported\n");
321 ret = -EOPNOTSUPP;
322 goto err_free_ecc_cfg;
323 }
324
325 snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize,
326 GFP_KERNEL);
327 if (!snandc->qspi->oob_buf) {
328 ret = -ENOMEM;
329 goto err_free_ecc_cfg;
330 }
331
332 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
333
334 nand->ecc.ctx.priv = ecc_cfg;
335 snandc->qspi->mtd = mtd;
336
337 ecc_cfg->bbm_size = 1;
338 ecc_cfg->bch_enabled = true;
339 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
340
341 ecc_cfg->steps = cwperpage;
342 ecc_cfg->cw_data = 516;
343 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
344 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
345
346 mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
347
348 /*
349 * Free the temporary BAM transaction allocated initially by
350 * qcom_nandc_alloc(), and allocate a new one based on the
351 * updated max_cwperpage value.
352 */
353 qcom_free_bam_transaction(snandc);
354
355 snandc->max_cwperpage = cwperpage;
356
357 snandc->bam_txn = qcom_alloc_bam_transaction(snandc);
358 if (!snandc->bam_txn) {
359 dev_err(snandc->dev, "failed to allocate BAM transaction\n");
360 ret = -ENOMEM;
361 goto err_free_ecc_cfg;
362 }
363
364 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
365 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
366 FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
367 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
368 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
369 FIELD_PREP(STATUS_BFR_READ, 0) |
370 FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
371 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
372
373 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
374 FIELD_PREP(CS_ACTIVE_BSY, 0) |
375 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
376 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
377 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
378 FIELD_PREP(WIDE_FLASH, 0) |
379 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
380
381 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
382 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
383 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
384 FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
385
386 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
387 FIELD_PREP(CS_ACTIVE_BSY, 0) |
388 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
389 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
390 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
391 FIELD_PREP(WIDE_FLASH, 0) |
392 FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
393
394 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
395 FIELD_PREP(ECC_SW_RESET, 0) |
396 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
397 FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
398 FIELD_PREP(ECC_MODE_MASK, ecc_cfg->ecc_mode) |
399 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
400
401 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
402
403 conf->step_size = ecc_cfg->step_size;
404 conf->strength = ecc_cfg->strength;
405
406 snandc->regs->clrflashstatus = cpu_to_le32(FS_READY_BSY_N);
407 snandc->regs->clrreadstatus = cpu_to_le32(0xc0);
408 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
409 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
410
411 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
412 ecc_cfg->strength, ecc_cfg->step_size);
413
414 return 0;
415
416 err_free_ecc_cfg:
417 kfree(snandc->qspi->oob_buf);
418 snandc->qspi->oob_buf = NULL;
419 kfree(ecc_cfg);
420 return ret;
421 }
422
qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device * nand)423 static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
424 {
425 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
426 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
427
428 kfree(snandc->qspi->oob_buf);
429 snandc->qspi->oob_buf = NULL;
430 kfree(ecc_cfg);
431 }
432
qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device * nand,struct nand_page_io_req * req)433 static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
434 struct nand_page_io_req *req)
435 {
436 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
437 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
438
439 snandc->qspi->ecc = ecc_cfg;
440 snandc->qspi->raw_rw = false;
441 snandc->qspi->oob_rw = false;
442 snandc->qspi->page_rw = false;
443
444 if (req->datalen)
445 snandc->qspi->page_rw = true;
446
447 if (req->ooblen)
448 snandc->qspi->oob_rw = true;
449
450 if (req->mode == MTD_OPS_RAW)
451 snandc->qspi->raw_rw = true;
452
453 return 0;
454 }
455
qcom_spi_ecc_finish_io_req_pipelined(struct nand_device * nand,struct nand_page_io_req * req)456 static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
457 struct nand_page_io_req *req)
458 {
459 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
460 struct mtd_info *mtd = nanddev_to_mtd(nand);
461
462 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
463 return 0;
464
465 if (snandc->qspi->ecc_stats.failed)
466 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
467 else
468 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
469
470 if (snandc->qspi->ecc_stats.failed)
471 return -EBADMSG;
472 else
473 return snandc->qspi->ecc_stats.bitflips;
474 }
475
476 static const struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
477 .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
478 .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
479 .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
480 .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
481 };
482
483 /* helper to configure location register values */
qcom_spi_set_read_loc(struct qcom_nand_controller * snandc,int cw,int reg,int cw_offset,int read_size,int is_last_read_loc)484 static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
485 int cw_offset, int read_size, int is_last_read_loc)
486 {
487 int reg_base = NAND_READ_LOCATION_0;
488 int num_cw = snandc->qspi->num_cw;
489
490 if (cw == (num_cw - 1))
491 reg_base = NAND_READ_LOCATION_LAST_CW_0;
492
493 reg_base += reg * 4;
494
495 if (cw == (num_cw - 1))
496 return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
497 read_size, is_last_read_loc);
498 else
499 return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
500 read_size, is_last_read_loc);
501 }
502
503 static void
qcom_spi_config_cw_read(struct qcom_nand_controller * snandc,bool use_ecc,int cw)504 qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
505 {
506 __le32 *reg = &snandc->regs->read_location0;
507 int num_cw = snandc->qspi->num_cw;
508
509 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
510 if (cw == (num_cw - 1)) {
511 reg = &snandc->regs->read_location_last0;
512 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
513 NAND_BAM_NEXT_SGL);
514 }
515
516 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
517 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
518
519 if (use_ecc) {
520 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
521 qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
522 NAND_BAM_NEXT_SGL);
523 } else {
524 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1,
525 NAND_BAM_NEXT_SGL);
526 }
527 }
528
qcom_spi_block_erase(struct qcom_nand_controller * snandc)529 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
530 {
531 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
532 int ret;
533
534 snandc->buf_count = 0;
535 snandc->buf_start = 0;
536 qcom_clear_read_regs(snandc);
537 qcom_clear_bam_transaction(snandc);
538
539 snandc->regs->cmd = snandc->qspi->cmd;
540 snandc->regs->addr0 = snandc->qspi->addr1;
541 snandc->regs->addr1 = snandc->qspi->addr2;
542 snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
543 FIELD_PREP(CW_PER_PAGE_MASK, 0));
544 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
545 snandc->regs->exec = cpu_to_le32(1);
546
547 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
548 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
549 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
550
551 ret = qcom_submit_descs(snandc);
552 if (ret) {
553 dev_err(snandc->dev, "failure to erase block\n");
554 return ret;
555 }
556
557 return 0;
558 }
559
qcom_spi_config_single_cw_page_read(struct qcom_nand_controller * snandc,bool use_ecc,int cw)560 static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
561 bool use_ecc, int cw)
562 {
563 __le32 *reg = &snandc->regs->read_location0;
564 int num_cw = snandc->qspi->num_cw;
565
566 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
567 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
568 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
569 NAND_ERASED_CW_DETECT_CFG, 1, 0);
570 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
571 NAND_ERASED_CW_DETECT_CFG, 1,
572 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
573
574 if (cw == (num_cw - 1)) {
575 reg = &snandc->regs->read_location_last0;
576 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
577 }
578 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
579 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
580
581 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
582 }
583
qcom_spi_check_raw_flash_errors(struct qcom_nand_controller * snandc,int cw_cnt)584 static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
585 {
586 int i;
587
588 qcom_nandc_dev_to_mem(snandc, true);
589
590 for (i = 0; i < cw_cnt; i++) {
591 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
592
593 if (flash & (FS_OP_ERR | FS_MPU_ERR))
594 return -EIO;
595 }
596
597 return 0;
598 }
599
qcom_spi_read_last_cw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)600 static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
601 const struct spi_mem_op *op)
602 {
603 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
604 struct mtd_info *mtd = snandc->qspi->mtd;
605 int size, ret = 0;
606 int col, bbpos;
607 u32 cfg0, cfg1, ecc_bch_cfg;
608 u32 num_cw = snandc->qspi->num_cw;
609
610 qcom_clear_bam_transaction(snandc);
611 qcom_clear_read_regs(snandc);
612
613 size = ecc_cfg->cw_size;
614 col = ecc_cfg->cw_size * (num_cw - 1);
615
616 memset(snandc->data_buffer, 0xff, size);
617 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
618 snandc->regs->addr1 = snandc->qspi->addr2;
619
620 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
621 FIELD_PREP(CW_PER_PAGE_MASK, 0);
622 cfg1 = ecc_cfg->cfg1_raw;
623 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
624
625 snandc->regs->cmd = snandc->qspi->cmd;
626 snandc->regs->cfg0 = cpu_to_le32(cfg0);
627 snandc->regs->cfg1 = cpu_to_le32(cfg1);
628 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
629 snandc->regs->exec = cpu_to_le32(1);
630
631 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
632
633 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
634
635 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
636
637 ret = qcom_submit_descs(snandc);
638 if (ret) {
639 dev_err(snandc->dev, "failed to read last cw\n");
640 return ret;
641 }
642
643 ret = qcom_spi_check_raw_flash_errors(snandc, 1);
644 if (ret)
645 return ret;
646
647 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
648
649 /*
650 * TODO: The SPINAND code expects two bad block marker bytes
651 * at the beginning of the OOB area, but the OOB layout used by
652 * the driver has only one. Duplicate that for now in order to
653 * avoid certain blocks to be marked as bad.
654 *
655 * This can be removed once single-byte bad block marker support
656 * gets implemented in the SPINAND code.
657 */
658 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
659
660 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
661
662 return ret;
663 }
664
qcom_spi_check_error(struct qcom_nand_controller * snandc)665 static int qcom_spi_check_error(struct qcom_nand_controller *snandc)
666 {
667 struct snandc_read_status *buf;
668 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
669 int i, num_cw = snandc->qspi->num_cw;
670 bool flash_op_err = false, erased;
671 unsigned int max_bitflips = 0;
672 unsigned int uncorrectable_cws = 0;
673
674 snandc->qspi->ecc_stats.failed = 0;
675 snandc->qspi->ecc_stats.corrected = 0;
676
677 qcom_nandc_dev_to_mem(snandc, true);
678 buf = (struct snandc_read_status *)snandc->reg_read_buf;
679
680 for (i = 0; i < num_cw; i++, buf++) {
681 u32 flash, buffer, erased_cw;
682
683 flash = le32_to_cpu(buf->snandc_flash);
684 buffer = le32_to_cpu(buf->snandc_buffer);
685 erased_cw = le32_to_cpu(buf->snandc_erased_cw);
686
687 if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
688 if (ecc_cfg->bch_enabled)
689 erased = (erased_cw & ERASED_CW) == ERASED_CW;
690 else
691 erased = false;
692
693 if (!erased)
694 uncorrectable_cws |= BIT(i);
695
696 } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
697 flash_op_err = true;
698 } else {
699 unsigned int stat;
700
701 stat = buffer & BS_CORRECTABLE_ERR_MSK;
702
703 /*
704 * The exact number of the corrected bits is
705 * unknown because the hardware only reports the
706 * number of the corrected bytes.
707 *
708 * Since we have no better solution at the moment,
709 * report that value as the number of bit errors
710 * despite that it is inaccurate in most cases.
711 */
712 if (stat && stat != ecc_cfg->strength)
713 dev_warn_once(snandc->dev,
714 "Warning: due to hw limitation, the reported number of the corrected bits may be inaccurate\n");
715
716 snandc->qspi->ecc_stats.corrected += stat;
717 max_bitflips = max(max_bitflips, stat);
718 }
719 }
720
721 if (flash_op_err)
722 return -EIO;
723
724 if (!uncorrectable_cws)
725 snandc->qspi->ecc_stats.bitflips = max_bitflips;
726 else
727 snandc->qspi->ecc_stats.failed++;
728
729 return 0;
730 }
731
qcom_spi_read_cw_raw(struct qcom_nand_controller * snandc,u8 * data_buf,u8 * oob_buf,int cw)732 static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
733 u8 *oob_buf, int cw)
734 {
735 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
736 struct mtd_info *mtd = snandc->qspi->mtd;
737 int data_size1, data_size2, oob_size1, oob_size2;
738 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
739 int raw_cw = cw;
740 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
741 int col;
742
743 snandc->buf_count = 0;
744 snandc->buf_start = 0;
745 qcom_clear_read_regs(snandc);
746 qcom_clear_bam_transaction(snandc);
747 raw_cw = num_cw - 1;
748
749 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
750 FIELD_PREP(CW_PER_PAGE_MASK, 0);
751 cfg1 = ecc_cfg->cfg1_raw;
752 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
753
754 col = ecc_cfg->cw_size * cw;
755
756 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
757 snandc->regs->addr1 = snandc->qspi->addr2;
758 snandc->regs->cmd = snandc->qspi->cmd;
759 snandc->regs->cfg0 = cpu_to_le32(cfg0);
760 snandc->regs->cfg1 = cpu_to_le32(cfg1);
761 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
762 snandc->regs->exec = cpu_to_le32(1);
763
764 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
765
766 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
767 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
768 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
769
770 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
771 NAND_ERASED_CW_DETECT_CFG, 1, 0);
772 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
773 NAND_ERASED_CW_DETECT_CFG, 1,
774 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
775
776 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
777 oob_size1 = ecc_cfg->bbm_size;
778
779 if (cw == (num_cw - 1)) {
780 data_size2 = NANDC_STEP_SIZE - data_size1 -
781 ((num_cw - 1) * 4);
782 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
783 ecc_cfg->spare_bytes;
784 } else {
785 data_size2 = ecc_cfg->cw_data - data_size1;
786 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
787 }
788
789 qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
790 read_loc += data_size1;
791
792 qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
793 read_loc += oob_size1;
794
795 qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
796 read_loc += data_size2;
797
798 qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
799
800 qcom_spi_config_cw_read(snandc, false, raw_cw);
801
802 qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
803 reg_off += data_size1;
804
805 qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
806 reg_off += oob_size1;
807
808 qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
809 reg_off += data_size2;
810
811 qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
812
813 ret = qcom_submit_descs(snandc);
814 if (ret) {
815 dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
816 return ret;
817 }
818
819 return qcom_spi_check_raw_flash_errors(snandc, 1);
820 }
821
qcom_spi_read_page_raw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)822 static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
823 const struct spi_mem_op *op)
824 {
825 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
826 u8 *data_buf = NULL, *oob_buf = NULL;
827 int ret, cw;
828 u32 num_cw = snandc->qspi->num_cw;
829
830 if (snandc->qspi->page_rw)
831 data_buf = op->data.buf.in;
832
833 oob_buf = snandc->qspi->oob_buf;
834 memset(oob_buf, 0xff, OOB_BUF_SIZE);
835
836 for (cw = 0; cw < num_cw; cw++) {
837 ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
838 if (ret)
839 return ret;
840
841 if (data_buf)
842 data_buf += ecc_cfg->cw_data;
843 if (oob_buf)
844 oob_buf += ecc_cfg->bytes;
845 }
846
847 return 0;
848 }
849
qcom_spi_read_page_ecc(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)850 static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
851 const struct spi_mem_op *op)
852 {
853 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
854 u8 *data_buf = NULL, *oob_buf = NULL;
855 int ret, i;
856 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
857
858 data_buf = op->data.buf.in;
859 oob_buf = snandc->qspi->oob_buf;
860
861 snandc->buf_count = 0;
862 snandc->buf_start = 0;
863 qcom_clear_read_regs(snandc);
864
865 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
866 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
867 cfg1 = ecc_cfg->cfg1;
868 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
869
870 snandc->regs->addr0 = snandc->qspi->addr1;
871 snandc->regs->addr1 = snandc->qspi->addr2;
872 snandc->regs->cmd = snandc->qspi->cmd;
873 snandc->regs->cfg0 = cpu_to_le32(cfg0);
874 snandc->regs->cfg1 = cpu_to_le32(cfg1);
875 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
876 snandc->regs->exec = cpu_to_le32(1);
877
878 qcom_clear_bam_transaction(snandc);
879
880 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
881 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
882 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
883 NAND_ERASED_CW_DETECT_CFG, 1, 0);
884 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
885 NAND_ERASED_CW_DETECT_CFG, 1,
886 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
887
888 for (i = 0; i < num_cw; i++) {
889 int data_size, oob_size;
890
891 if (i == (num_cw - 1)) {
892 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
893 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
894 ecc_cfg->spare_bytes;
895 } else {
896 data_size = ecc_cfg->cw_data;
897 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
898 }
899
900 if (data_buf && oob_buf) {
901 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
902 qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
903 } else if (data_buf) {
904 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
905 } else {
906 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
907 }
908
909 qcom_spi_config_cw_read(snandc, true, i);
910
911 if (data_buf)
912 qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
913 data_size, 0);
914 if (oob_buf) {
915 int j;
916
917 for (j = 0; j < ecc_cfg->bbm_size; j++)
918 *oob_buf++ = 0xff;
919
920 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
921 oob_buf, oob_size, 0);
922 }
923
924 if (data_buf)
925 data_buf += data_size;
926 if (oob_buf)
927 oob_buf += oob_size;
928 }
929
930 ret = qcom_submit_descs(snandc);
931 if (ret) {
932 dev_err(snandc->dev, "failure to read page\n");
933 return ret;
934 }
935
936 return qcom_spi_check_error(snandc);
937 }
938
qcom_spi_read_page_oob(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)939 static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
940 const struct spi_mem_op *op)
941 {
942 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
943 u8 *oob_buf = NULL;
944 int ret, i;
945 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
946
947 oob_buf = op->data.buf.in;
948
949 snandc->buf_count = 0;
950 snandc->buf_start = 0;
951 qcom_clear_read_regs(snandc);
952 qcom_clear_bam_transaction(snandc);
953
954 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
955 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
956 cfg1 = ecc_cfg->cfg1;
957 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
958
959 snandc->regs->addr0 = snandc->qspi->addr1;
960 snandc->regs->addr1 = snandc->qspi->addr2;
961 snandc->regs->cmd = snandc->qspi->cmd;
962 snandc->regs->cfg0 = cpu_to_le32(cfg0);
963 snandc->regs->cfg1 = cpu_to_le32(cfg1);
964 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
965 snandc->regs->exec = cpu_to_le32(1);
966
967 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
968 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
969 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
970 NAND_ERASED_CW_DETECT_CFG, 1, 0);
971 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
972 NAND_ERASED_CW_DETECT_CFG, 1,
973 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
974
975 for (i = 0; i < num_cw; i++) {
976 int data_size, oob_size;
977
978 if (i == (num_cw - 1)) {
979 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
980 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
981 ecc_cfg->spare_bytes;
982 } else {
983 data_size = ecc_cfg->cw_data;
984 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
985 }
986
987 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
988
989 qcom_spi_config_cw_read(snandc, true, i);
990
991 if (oob_buf) {
992 int j;
993
994 for (j = 0; j < ecc_cfg->bbm_size; j++)
995 *oob_buf++ = 0xff;
996
997 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
998 oob_buf, oob_size, 0);
999 }
1000
1001 if (oob_buf)
1002 oob_buf += oob_size;
1003 }
1004
1005 ret = qcom_submit_descs(snandc);
1006 if (ret) {
1007 dev_err(snandc->dev, "failure to read oob\n");
1008 return ret;
1009 }
1010
1011 return qcom_spi_check_error(snandc);
1012 }
1013
qcom_spi_cmd_mapping(struct qcom_nand_controller * snandc,const struct spi_mem_op * op,u32 * cmd)1014 static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc,
1015 const struct spi_mem_op *op, u32 *cmd)
1016 {
1017 u32 opcode = op->cmd.opcode;
1018 u32 transfer_mode = SPI_TRANSFER_MODE_x1;
1019
1020 if (snandc->qspi->quad_mode && op->data.buswidth == QUAD_WIDTH)
1021 transfer_mode = SPI_TRANSFER_MODE_x4;
1022
1023 switch (opcode) {
1024 case SPINAND_RESET:
1025 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1026 break;
1027 case SPINAND_READID:
1028 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1029 break;
1030 case SPINAND_GET_FEATURE:
1031 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1032 break;
1033 case SPINAND_SET_FEATURE:
1034 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1035 QPIC_SET_FEATURE);
1036 break;
1037 case SPINAND_READ:
1038 case SPINAND_READ_QUAD:
1039 case SPINAND_READ_CACHE:
1040 case SPINAND_READ_MACRONIX:
1041 if (snandc->qspi->raw_rw) {
1042 *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
1043 SPI_WP | SPI_HOLD | OP_PAGE_READ);
1044 } else {
1045 *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
1046 SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1047 }
1048
1049 break;
1050 case SPINAND_ERASE:
1051 *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1052 SPI_HOLD | SPI_TRANSFER_MODE_x1;
1053 break;
1054 case SPINAND_WRITE_EN:
1055 *cmd = SPINAND_WRITE_EN;
1056 break;
1057 case SPINAND_PROGRAM_EXECUTE:
1058 *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
1059 SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1060 break;
1061 case SPINAND_PROGRAM_LOAD:
1062 *cmd = SPINAND_PROGRAM_LOAD;
1063 break;
1064 case SPINAND_PROGRAM_LOAD_QUAD:
1065 *cmd = SPINAND_PROGRAM_LOAD_QUAD;
1066 break;
1067 default:
1068 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1069 return -EOPNOTSUPP;
1070 }
1071
1072 return 0;
1073 }
1074
qcom_spi_read_page(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1075 static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
1076 const struct spi_mem_op *op)
1077 {
1078 int ret;
1079 u32 cmd;
1080
1081 /* Update the cached command for the cache-read opcode and bus width. */
1082 ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
1083 if (ret < 0)
1084 return ret;
1085
1086 snandc->qspi->cmd = cpu_to_le32(cmd);
1087
1088 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1089 return qcom_spi_read_page_raw(snandc, op);
1090
1091 if (snandc->qspi->page_rw)
1092 return qcom_spi_read_page_ecc(snandc, op);
1093
1094 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
1095 return qcom_spi_read_last_cw(snandc, op);
1096
1097 if (snandc->qspi->oob_rw)
1098 return qcom_spi_read_page_oob(snandc, op);
1099
1100 return 0;
1101 }
1102
qcom_spi_config_page_write(struct qcom_nand_controller * snandc)1103 static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
1104 {
1105 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1106 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1107 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
1108 1, NAND_BAM_NEXT_SGL);
1109 }
1110
qcom_spi_config_cw_write(struct qcom_nand_controller * snandc)1111 static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1112 {
1113 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1114 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1115 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1116
1117 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1118 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1119 NAND_BAM_NEXT_SGL);
1120 }
1121
qcom_spi_program_raw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1122 static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1123 const struct spi_mem_op *op)
1124 {
1125 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1126 struct mtd_info *mtd = snandc->qspi->mtd;
1127 u8 *data_buf = NULL, *oob_buf = NULL;
1128 int i, ret;
1129 int num_cw = snandc->qspi->num_cw;
1130 u32 cfg0, cfg1, ecc_bch_cfg;
1131
1132 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
1133 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1134 cfg1 = ecc_cfg->cfg1_raw;
1135 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1136
1137 data_buf = snandc->qspi->data_buf;
1138
1139 oob_buf = snandc->qspi->oob_buf;
1140 memset(oob_buf, 0xff, OOB_BUF_SIZE);
1141
1142 snandc->buf_count = 0;
1143 snandc->buf_start = 0;
1144 qcom_clear_read_regs(snandc);
1145 qcom_clear_bam_transaction(snandc);
1146
1147 snandc->regs->addr0 = snandc->qspi->addr1;
1148 snandc->regs->addr1 = snandc->qspi->addr2;
1149 snandc->regs->cmd = snandc->qspi->cmd;
1150 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1151 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1152 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1153 snandc->regs->exec = cpu_to_le32(1);
1154
1155 qcom_spi_config_page_write(snandc);
1156
1157 for (i = 0; i < num_cw; i++) {
1158 int data_size1, data_size2, oob_size1, oob_size2;
1159 int reg_off = FLASH_BUF_ACC;
1160
1161 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1162 oob_size1 = ecc_cfg->bbm_size;
1163
1164 if (i == (num_cw - 1)) {
1165 data_size2 = NANDC_STEP_SIZE - data_size1 -
1166 ((num_cw - 1) << 2);
1167 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1168 ecc_cfg->spare_bytes;
1169 } else {
1170 data_size2 = ecc_cfg->cw_data - data_size1;
1171 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1172 }
1173
1174 qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1175 NAND_BAM_NO_EOT);
1176 reg_off += data_size1;
1177 data_buf += data_size1;
1178
1179 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1180 NAND_BAM_NO_EOT);
1181 oob_buf += oob_size1;
1182 reg_off += oob_size1;
1183
1184 qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1185 NAND_BAM_NO_EOT);
1186 reg_off += data_size2;
1187 data_buf += data_size2;
1188
1189 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1190 oob_buf += oob_size2;
1191
1192 qcom_spi_config_cw_write(snandc);
1193 }
1194
1195 ret = qcom_submit_descs(snandc);
1196 if (ret) {
1197 dev_err(snandc->dev, "failure to write raw page\n");
1198 return ret;
1199 }
1200
1201 return 0;
1202 }
1203
qcom_spi_program_ecc(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1204 static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1205 const struct spi_mem_op *op)
1206 {
1207 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1208 u8 *data_buf = NULL, *oob_buf = NULL;
1209 int i, ret;
1210 int num_cw = snandc->qspi->num_cw;
1211 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1212
1213 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1214 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1215 cfg1 = ecc_cfg->cfg1;
1216 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1217 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1218
1219 if (snandc->qspi->data_buf)
1220 data_buf = snandc->qspi->data_buf;
1221
1222 oob_buf = snandc->qspi->oob_buf;
1223
1224 snandc->buf_count = 0;
1225 snandc->buf_start = 0;
1226 qcom_clear_read_regs(snandc);
1227 qcom_clear_bam_transaction(snandc);
1228
1229 snandc->regs->addr0 = snandc->qspi->addr1;
1230 snandc->regs->addr1 = snandc->qspi->addr2;
1231 snandc->regs->cmd = snandc->qspi->cmd;
1232 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1233 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1234 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1235 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1236 snandc->regs->exec = cpu_to_le32(1);
1237
1238 qcom_spi_config_page_write(snandc);
1239
1240 for (i = 0; i < num_cw; i++) {
1241 int data_size, oob_size;
1242
1243 if (i == (num_cw - 1)) {
1244 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1245 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1246 ecc_cfg->spare_bytes;
1247 } else {
1248 data_size = ecc_cfg->cw_data;
1249 oob_size = ecc_cfg->bytes;
1250 }
1251
1252 if (data_buf)
1253 qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1254 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1255
1256 if (i == (num_cw - 1)) {
1257 if (oob_buf) {
1258 oob_buf += ecc_cfg->bbm_size;
1259 qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1260 oob_buf, oob_size, 0);
1261 }
1262 }
1263
1264 qcom_spi_config_cw_write(snandc);
1265
1266 if (data_buf)
1267 data_buf += data_size;
1268 if (oob_buf)
1269 oob_buf += oob_size;
1270 }
1271
1272 ret = qcom_submit_descs(snandc);
1273 if (ret) {
1274 dev_err(snandc->dev, "failure to write page\n");
1275 return ret;
1276 }
1277
1278 return 0;
1279 }
1280
qcom_spi_program_oob(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1281 static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1282 const struct spi_mem_op *op)
1283 {
1284 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1285 u8 *oob_buf = NULL;
1286 int ret, col, data_size, oob_size;
1287 int num_cw = snandc->qspi->num_cw;
1288 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1289
1290 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1291 FIELD_PREP(CW_PER_PAGE_MASK, 0);
1292 cfg1 = ecc_cfg->cfg1;
1293 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1294 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1295
1296 col = ecc_cfg->cw_size * (num_cw - 1);
1297
1298 oob_buf = snandc->qspi->data_buf;
1299
1300 snandc->buf_count = 0;
1301 snandc->buf_start = 0;
1302 qcom_clear_read_regs(snandc);
1303 qcom_clear_bam_transaction(snandc);
1304 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1305 snandc->regs->addr1 = snandc->qspi->addr2;
1306 snandc->regs->cmd = snandc->qspi->cmd;
1307 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1308 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1309 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1310 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1311 snandc->regs->exec = cpu_to_le32(1);
1312
1313 /* calculate the data and oob size for the last codeword/step */
1314 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1315 oob_size = snandc->qspi->mtd->oobavail;
1316
1317 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1318 /* override new oob content to last codeword */
1319 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1320 oob_buf, 0, snandc->qspi->mtd->oobavail);
1321 qcom_spi_config_page_write(snandc);
1322 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1323 qcom_spi_config_cw_write(snandc);
1324
1325 ret = qcom_submit_descs(snandc);
1326 if (ret) {
1327 dev_err(snandc->dev, "failure to write oob\n");
1328 return ret;
1329 }
1330
1331 return 0;
1332 }
1333
qcom_spi_program_execute(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1334 static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1335 const struct spi_mem_op *op)
1336 {
1337 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1338 return qcom_spi_program_raw(snandc, op);
1339
1340 if (snandc->qspi->page_rw)
1341 return qcom_spi_program_ecc(snandc, op);
1342
1343 if (snandc->qspi->oob_rw)
1344 return qcom_spi_program_oob(snandc, op);
1345
1346 return 0;
1347 }
1348
qcom_spi_write_page(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1349 static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1350 const struct spi_mem_op *op)
1351 {
1352 int ret;
1353 u32 cmd;
1354
1355 ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
1356 if (ret < 0)
1357 return ret;
1358
1359 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD ||
1360 op->cmd.opcode == SPINAND_PROGRAM_LOAD_QUAD)
1361 snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1362
1363 return 0;
1364 }
1365
qcom_spi_send_cmdaddr(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1366 static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1367 const struct spi_mem_op *op)
1368 {
1369 u32 cmd;
1370 int ret, opcode;
1371
1372 ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
1373 if (ret < 0)
1374 return ret;
1375
1376 opcode = op->cmd.opcode;
1377
1378 switch (opcode) {
1379 case SPINAND_WRITE_EN:
1380 return 0;
1381 case SPINAND_PROGRAM_EXECUTE:
1382 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1383 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1384 snandc->qspi->cmd = cpu_to_le32(cmd);
1385 return qcom_spi_program_execute(snandc, op);
1386 case SPINAND_READ:
1387 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1388 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1389 snandc->qspi->cmd = cpu_to_le32(cmd);
1390 return 0;
1391 case SPINAND_ERASE:
1392 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1393 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xffff);
1394 snandc->qspi->cmd = cpu_to_le32(cmd);
1395 return qcom_spi_block_erase(snandc);
1396 default:
1397 break;
1398 }
1399
1400 snandc->buf_count = 0;
1401 snandc->buf_start = 0;
1402 qcom_clear_read_regs(snandc);
1403 qcom_clear_bam_transaction(snandc);
1404
1405 snandc->regs->cmd = cpu_to_le32(cmd);
1406 snandc->regs->exec = cpu_to_le32(1);
1407 snandc->regs->addr0 = cpu_to_le32(op->addr.val);
1408 snandc->regs->addr1 = cpu_to_le32(0);
1409
1410 /*
1411 * The feature value has to reach NAND_FLASH_FEATURES before the
1412 * command is executed, otherwise the controller programs the chip
1413 * with whatever the register happened to hold from a previous
1414 * operation.
1415 */
1416 if (opcode == SPINAND_SET_FEATURE) {
1417 u32 ftr = 0;
1418
1419 memcpy(&ftr, op->data.buf.out,
1420 min_t(size_t, op->data.nbytes, sizeof(ftr)));
1421 snandc->regs->flash_feature = cpu_to_le32(ftr);
1422 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1423 NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1424 }
1425
1426 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1427 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1428
1429 ret = qcom_submit_descs(snandc);
1430 if (ret)
1431 dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1432
1433 return ret;
1434 }
1435
qcom_spi_io_op(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1436 static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1437 {
1438 int ret, val, opcode;
1439 bool copy = false, copy_ftr = false;
1440
1441 ret = qcom_spi_send_cmdaddr(snandc, op);
1442 if (ret)
1443 return ret;
1444
1445 snandc->buf_count = 0;
1446 snandc->buf_start = 0;
1447 qcom_clear_read_regs(snandc);
1448 qcom_clear_bam_transaction(snandc);
1449 opcode = op->cmd.opcode;
1450
1451 switch (opcode) {
1452 case SPINAND_READID:
1453 snandc->buf_count = 4;
1454 qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1455 copy = true;
1456 break;
1457 case SPINAND_GET_FEATURE:
1458 snandc->buf_count = 4;
1459 qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1460 copy_ftr = true;
1461 break;
1462 case SPINAND_SET_FEATURE:
1463 /* fully handled by qcom_spi_send_cmdaddr() */
1464 return 0;
1465 case SPINAND_PROGRAM_EXECUTE:
1466 case SPINAND_WRITE_EN:
1467 case SPINAND_RESET:
1468 case SPINAND_ERASE:
1469 case SPINAND_READ:
1470 return 0;
1471 default:
1472 return -EOPNOTSUPP;
1473 }
1474
1475 ret = qcom_submit_descs(snandc);
1476 if (ret) {
1477 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1478 return ret;
1479 }
1480
1481 if (copy) {
1482 qcom_nandc_dev_to_mem(snandc, true);
1483 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1484 }
1485
1486 if (copy_ftr) {
1487 qcom_nandc_dev_to_mem(snandc, true);
1488 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1489 val >>= 8;
1490 memcpy(op->data.buf.in, &val, snandc->buf_count);
1491
1492 /*
1493 * Track QUAD mode state from configuration register.
1494 * When core layer reads register 0xB0 (CFG), check if
1495 * QUAD enable bit (bit 0) is set and update our state
1496 * accordingly for future READ/WRITE operations.
1497 */
1498 if (op->addr.val == SPINAND_FEATURE_ADDR) {
1499 bool quad_enabled = !!((u8)val & BIT(0));
1500
1501 if (snandc->qspi->quad_mode != quad_enabled) {
1502 snandc->qspi->quad_mode = quad_enabled;
1503 dev_info(snandc->dev, "SPI NAND QUAD mode: %s\n",
1504 quad_enabled ? "enabled" : "disabled");
1505 }
1506 }
1507 }
1508
1509 return 0;
1510 }
1511
qcom_spi_is_page_op(const struct spi_mem_op * op)1512 static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1513 {
1514 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1515 return false;
1516
1517 if (op->data.dir == SPI_MEM_DATA_IN) {
1518 if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1519 return true;
1520
1521 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1522 return true;
1523
1524 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1525 if (op->data.buswidth == 4)
1526 return true;
1527 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1528 return true;
1529 }
1530
1531 return false;
1532 }
1533
qcom_spi_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)1534 static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1535 {
1536 if (!spi_mem_default_supports_op(mem, op))
1537 return false;
1538
1539 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1540 return false;
1541
1542 if (qcom_spi_is_page_op(op))
1543 return true;
1544
1545 return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1546 (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1547 (!op->data.nbytes || op->data.buswidth == 1 ||
1548 op->data.buswidth == 4));
1549 }
1550
qcom_spi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)1551 static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1552 {
1553 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1554
1555 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1556 op->addr.val, op->addr.buswidth, op->addr.nbytes,
1557 op->data.buswidth, op->data.nbytes);
1558
1559 if (qcom_spi_is_page_op(op)) {
1560 if (op->data.dir == SPI_MEM_DATA_IN)
1561 return qcom_spi_read_page(snandc, op);
1562 if (op->data.dir == SPI_MEM_DATA_OUT)
1563 return qcom_spi_write_page(snandc, op);
1564 } else {
1565 return qcom_spi_io_op(snandc, op);
1566 }
1567
1568 return 0;
1569 }
1570
1571 static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1572 .supports_op = qcom_spi_supports_op,
1573 .exec_op = qcom_spi_exec_op,
1574 };
1575
1576 static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1577 .ecc = true,
1578 };
1579
qcom_spi_probe(struct platform_device * pdev)1580 static int qcom_spi_probe(struct platform_device *pdev)
1581 {
1582 struct device *dev = &pdev->dev;
1583 struct spi_controller *ctlr;
1584 struct qcom_nand_controller *snandc;
1585 struct qpic_spi_nand *qspi;
1586 struct qpic_ecc *ecc;
1587 struct resource *res;
1588 const void *dev_data;
1589 int ret;
1590
1591 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1592 if (!ecc)
1593 return -ENOMEM;
1594
1595 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1596 if (!qspi)
1597 return -ENOMEM;
1598
1599 /* Initialize QUAD mode state */
1600 qspi->quad_mode = false;
1601
1602 ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1603 if (!ctlr)
1604 return -ENOMEM;
1605
1606 platform_set_drvdata(pdev, ctlr);
1607
1608 snandc = spi_controller_get_devdata(ctlr);
1609 qspi->snandc = snandc;
1610
1611 snandc->dev = dev;
1612 snandc->qspi = qspi;
1613 snandc->qspi->ctlr = ctlr;
1614 snandc->qspi->ecc = ecc;
1615
1616 dev_data = of_device_get_match_data(dev);
1617 if (!dev_data) {
1618 dev_err(&pdev->dev, "failed to get device data\n");
1619 return -ENODEV;
1620 }
1621
1622 snandc->props = dev_data;
1623
1624 snandc->core_clk = devm_clk_get_enabled(dev, "core");
1625 if (IS_ERR(snandc->core_clk))
1626 return PTR_ERR(snandc->core_clk);
1627
1628 snandc->aon_clk = devm_clk_get_enabled(dev, "aon");
1629 if (IS_ERR(snandc->aon_clk))
1630 return PTR_ERR(snandc->aon_clk);
1631
1632 snandc->qspi->iomacro_clk = devm_clk_get_enabled(dev, "iom");
1633 if (IS_ERR(snandc->qspi->iomacro_clk))
1634 return PTR_ERR(snandc->qspi->iomacro_clk);
1635
1636 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1637 if (IS_ERR(snandc->base))
1638 return PTR_ERR(snandc->base);
1639
1640 snandc->base_phys = res->start;
1641 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1642 DMA_BIDIRECTIONAL, 0);
1643 if (dma_mapping_error(dev, snandc->base_dma))
1644 return -ENXIO;
1645
1646 ret = qcom_nandc_alloc(snandc);
1647 if (ret)
1648 goto err_snand_alloc;
1649
1650 ret = qcom_spi_init(snandc);
1651 if (ret)
1652 goto err_spi_init;
1653
1654 /* setup ECC engine */
1655 snandc->qspi->ecc_eng.dev = &pdev->dev;
1656 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1657 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1658 snandc->qspi->ecc_eng.priv = snandc;
1659
1660 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1661 if (ret) {
1662 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1663 goto err_spi_init;
1664 }
1665
1666 ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1667 ctlr->mem_ops = &qcom_spi_mem_ops;
1668 ctlr->mem_caps = &qcom_spi_mem_caps;
1669 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1670 SPI_TX_QUAD | SPI_RX_QUAD;
1671
1672 ret = spi_register_controller(ctlr);
1673 if (ret) {
1674 dev_err(&pdev->dev, "spi_register_controller failed.\n");
1675 goto err_register_controller;
1676 }
1677
1678 return 0;
1679
1680 err_register_controller:
1681 nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
1682 err_spi_init:
1683 qcom_nandc_unalloc(snandc);
1684 err_snand_alloc:
1685 dma_unmap_resource(dev, res->start, resource_size(res),
1686 DMA_BIDIRECTIONAL, 0);
1687 return ret;
1688 }
1689
qcom_spi_remove(struct platform_device * pdev)1690 static void qcom_spi_remove(struct platform_device *pdev)
1691 {
1692 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1693 struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1694 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1695
1696 spi_unregister_controller(ctlr);
1697 nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
1698 qcom_nandc_unalloc(snandc);
1699 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1700 DMA_BIDIRECTIONAL, 0);
1701 }
1702
1703 static const struct qcom_nandc_props ipq9574_snandc_props = {
1704 .dev_cmd_reg_start = 0x7000,
1705 .bam_offset = 0x30000,
1706 .supports_bam = true,
1707 };
1708
1709 static const struct of_device_id qcom_snandc_of_match[] = {
1710 {
1711 .compatible = "qcom,ipq9574-snand",
1712 .data = &ipq9574_snandc_props,
1713 },
1714 {}
1715 };
1716 MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1717
1718 static struct platform_driver qcom_spi_driver = {
1719 .driver = {
1720 .name = "qcom_snand",
1721 .of_match_table = qcom_snandc_of_match,
1722 },
1723 .probe = qcom_spi_probe,
1724 .remove = qcom_spi_remove,
1725 };
1726 module_platform_driver(qcom_spi_driver);
1727
1728 MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1729 MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1730 MODULE_LICENSE("GPL");
1731