1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RZ/G2L MIPI DSI Encoder Driver
4 *
5 * Copyright (C) 2022 Renesas Electronics Corporation
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk/renesas.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/math.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_graph.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/units.h>
24
25 #include <drm/drm_atomic.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_mipi_dsi.h>
29 #include <drm/drm_of.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_probe_helper.h>
32 #include <video/mipi_display.h>
33
34 #include "rzg2l_mipi_dsi_regs.h"
35
36 MODULE_IMPORT_NS("RZV2H_CPG");
37
38 #define RZG2L_DCS_BUF_SIZE 128 /* Maximum DCS buffer size in external memory. */
39
40 #define RZ_MIPI_DSI_FEATURE_16BPP BIT(0)
41
42 struct rzg2l_mipi_dsi;
43
44 struct rzg2l_mipi_dsi_hw_info {
45 int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);
46 void (*dphy_startup_late_init)(struct rzg2l_mipi_dsi *dsi);
47 void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
48 int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
49 u64 *hsfreq_millihz);
50 unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi,
51 unsigned long mode_freq);
52 struct {
53 const struct rzv2h_pll_limits **limits;
54 const u8 *table;
55 const u8 table_size;
56 } cpg_plldsi;
57 u32 phy_reg_offset;
58 u32 link_reg_offset;
59 unsigned long min_dclk;
60 unsigned long max_dclk;
61 u8 features;
62 };
63
64 struct rzv2h_dsi_mode_calc {
65 unsigned long mode_freq_khz;
66 struct rzv2h_pll_pars dsi_parameters;
67 };
68
69 struct rzg2l_mipi_dsi {
70 struct device *dev;
71 void __iomem *mmio;
72
73 const struct rzg2l_mipi_dsi_hw_info *info;
74
75 struct reset_control *rstc;
76 struct reset_control *arstc;
77 struct reset_control *prstc;
78
79 struct mipi_dsi_host host;
80 struct drm_bridge bridge;
81 struct drm_bridge *next_bridge;
82
83 struct clk *vclk;
84 struct clk *lpclk;
85
86 enum mipi_dsi_pixel_format format;
87 unsigned int num_data_lanes;
88 unsigned int lanes;
89 unsigned long mode_flags;
90
91 struct rzv2h_dsi_mode_calc mode_calc;
92
93 /* DCS buffer pointers when using external memory. */
94 dma_addr_t dcs_buf_phys;
95 u8 *dcs_buf_virt;
96 };
97
98 static const struct rzv2h_pll_limits rzv2h_plldsi_div_limits = {
99 .fout = { .min = 80 * MEGA, .max = 1500 * MEGA },
100 .fvco = { .min = 1050 * MEGA, .max = 2100 * MEGA },
101 .m = { .min = 64, .max = 1023 },
102 .p = { .min = 1, .max = 4 },
103 .s = { .min = 0, .max = 5 },
104 .k = { .min = -32768, .max = 32767 },
105 };
106
107 static inline struct rzg2l_mipi_dsi *
bridge_to_rzg2l_mipi_dsi(struct drm_bridge * bridge)108 bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge)
109 {
110 return container_of(bridge, struct rzg2l_mipi_dsi, bridge);
111 }
112
113 static inline struct rzg2l_mipi_dsi *
host_to_rzg2l_mipi_dsi(struct mipi_dsi_host * host)114 host_to_rzg2l_mipi_dsi(struct mipi_dsi_host *host)
115 {
116 return container_of(host, struct rzg2l_mipi_dsi, host);
117 }
118
119 struct rzg2l_mipi_dsi_timings {
120 unsigned long hsfreq_max;
121 u32 t_init;
122 u32 tclk_prepare;
123 u32 ths_prepare;
124 u32 tclk_zero;
125 u32 tclk_pre;
126 u32 tclk_post;
127 u32 tclk_trail;
128 u32 ths_zero;
129 u32 ths_trail;
130 u32 ths_exit;
131 u32 tlpx;
132 };
133
134 static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = {
135 {
136 .hsfreq_max = 80000000,
137 .t_init = 79801,
138 .tclk_prepare = 8,
139 .ths_prepare = 13,
140 .tclk_zero = 33,
141 .tclk_pre = 24,
142 .tclk_post = 94,
143 .tclk_trail = 10,
144 .ths_zero = 23,
145 .ths_trail = 17,
146 .ths_exit = 13,
147 .tlpx = 6,
148 },
149 {
150 .hsfreq_max = 125000000,
151 .t_init = 79801,
152 .tclk_prepare = 8,
153 .ths_prepare = 12,
154 .tclk_zero = 33,
155 .tclk_pre = 15,
156 .tclk_post = 94,
157 .tclk_trail = 10,
158 .ths_zero = 23,
159 .ths_trail = 17,
160 .ths_exit = 13,
161 .tlpx = 6,
162 },
163 {
164 .hsfreq_max = 250000000,
165 .t_init = 79801,
166 .tclk_prepare = 8,
167 .ths_prepare = 12,
168 .tclk_zero = 33,
169 .tclk_pre = 13,
170 .tclk_post = 94,
171 .tclk_trail = 10,
172 .ths_zero = 23,
173 .ths_trail = 16,
174 .ths_exit = 13,
175 .tlpx = 6,
176 },
177 {
178 .hsfreq_max = 360000000,
179 .t_init = 79801,
180 .tclk_prepare = 8,
181 .ths_prepare = 10,
182 .tclk_zero = 33,
183 .tclk_pre = 4,
184 .tclk_post = 35,
185 .tclk_trail = 7,
186 .ths_zero = 16,
187 .ths_trail = 9,
188 .ths_exit = 13,
189 .tlpx = 6,
190 },
191 {
192 .hsfreq_max = 720000000,
193 .t_init = 79801,
194 .tclk_prepare = 8,
195 .ths_prepare = 9,
196 .tclk_zero = 33,
197 .tclk_pre = 4,
198 .tclk_post = 35,
199 .tclk_trail = 7,
200 .ths_zero = 16,
201 .ths_trail = 9,
202 .ths_exit = 13,
203 .tlpx = 6,
204 },
205 {
206 .hsfreq_max = 1500000000,
207 .t_init = 79801,
208 .tclk_prepare = 8,
209 .ths_prepare = 9,
210 .tclk_zero = 33,
211 .tclk_pre = 4,
212 .tclk_post = 35,
213 .tclk_trail = 7,
214 .ths_zero = 16,
215 .ths_trail = 9,
216 .ths_exit = 13,
217 .tlpx = 6,
218 },
219 };
220
221 /**
222 * struct rzv2h_mipi_dsi_timings - Timing parameter table structure
223 *
224 * @hsfreq: Pointer to frequency threshold array
225 * @len: Number of entries in the hsfreq array
226 * @base_value: Base register value offset for this timing parameter
227 *
228 * Each timing parameter (TCLK*, THS*, etc.) has its own table with
229 * frequency thresholds and corresponding base register values.
230 */
231 struct rzv2h_mipi_dsi_timings {
232 const u8 *hsfreq;
233 u8 len;
234 u8 base_value;
235 };
236
237 /*
238 * enum rzv2h_dsi_timing_idx - MIPI DSI timing parameter indices
239 *
240 * These enums correspond to different MIPI DSI PHY timing parameters.
241 */
242 enum rzv2h_dsi_timing_idx {
243 TCLKPRPRCTL,
244 TCLKZEROCTL,
245 TCLKPOSTCTL,
246 TCLKTRAILCTL,
247 THSPRPRCTL,
248 THSZEROCTL,
249 THSTRAILCTL,
250 TLPXCTL,
251 THSEXITCTL,
252 };
253
254 /*
255 * RZ/V2H(P) Frequency threshold lookup tables for D-PHY timing parameters
256 *
257 * - Each array contains frequency thresholds (in units of 10 Mbps),
258 * taken directly from the table 9.5-4 hardware manual.
259 * - These thresholds define the frequency ranges for which timing
260 * register values must be programmed.
261 * - The actual register value is calculated in
262 * rzv2h_dphy_find_timings_val():
263 *
264 * register_value = timings->base_value + table_index
265 *
266 * Example (TCLKPRPRCTL, from HW manual):
267 * 0-150 Mbps -> index 0 -> register_value = base + 0 = 0 + 0 = 0
268 * 151-260 Mbps -> index 1 -> register_value = base + 1 = 0 + 1 = 1
269 * 261-370 Mbps -> index 2 -> register_value = base + 2 = 0 + 2 = 2
270 *
271 * Each of the following arrays corresponds to a specific timing
272 * parameter (TCLKPRPRCTL, TCLKZEROCTL, TCLKPOSTCTL, etc.).
273 */
274 static const u8 tclkprprctl[] = {
275 15, 26, 37, 47, 58, 69, 79, 90, 101, 111, 122, 133, 143, 150,
276 };
277
278 static const u8 tclkzeroctl[] = {
279 9, 11, 13, 15, 18, 21, 23, 24, 25, 27, 29, 31, 34, 36, 38,
280 41, 43, 45, 47, 50, 52, 54, 57, 59, 61, 63, 66, 68, 70, 73,
281 75, 77, 79, 82, 84, 86, 89, 91, 93, 95, 98, 100, 102, 105,
282 107, 109, 111, 114, 116, 118, 121, 123, 125, 127, 130, 132,
283 134, 137, 139, 141, 143, 146, 148, 150,
284 };
285
286 static const u8 tclkpostctl[] = {
287 8, 21, 34, 48, 61, 74, 88, 101, 114, 128, 141, 150,
288 };
289
290 static const u8 tclktrailctl[] = {
291 14, 25, 37, 48, 59, 71, 82, 94, 105, 117, 128, 139, 150,
292 };
293
294 static const u8 thsprprctl[] = {
295 11, 19, 29, 40, 50, 61, 72, 82, 93, 103, 114, 125, 135, 146, 150,
296 };
297
298 static const u8 thszeroctl[] = {
299 18, 24, 29, 35, 40, 46, 51, 57, 62, 68, 73, 79, 84, 90,
300 95, 101, 106, 112, 117, 123, 128, 134, 139, 145, 150,
301 };
302
303 static const u8 thstrailctl[] = {
304 10, 21, 32, 42, 53, 64, 75, 85, 96, 107, 118, 128, 139, 150,
305 };
306
307 static const u8 tlpxctl[] = {
308 13, 26, 39, 53, 66, 79, 93, 106, 119, 133, 146, 150,
309 };
310
311 static const u8 thsexitctl[] = {
312 15, 23, 31, 39, 47, 55, 63, 71, 79, 87,
313 95, 103, 111, 119, 127, 135, 143, 150,
314 };
315
316 /*
317 * rzv2h_dsi_timings_tables - main timing parameter lookup table
318 * Maps timing parameter enum to its frequency table, array length and
319 * base register offset value.
320 */
321 static const struct rzv2h_mipi_dsi_timings rzv2h_dsi_timings_tables[] = {
322 [TCLKPRPRCTL] = {
323 .hsfreq = tclkprprctl,
324 .len = ARRAY_SIZE(tclkprprctl),
325 .base_value = 0,
326 },
327 [TCLKZEROCTL] = {
328 .hsfreq = tclkzeroctl,
329 .len = ARRAY_SIZE(tclkzeroctl),
330 .base_value = 2,
331 },
332 [TCLKPOSTCTL] = {
333 .hsfreq = tclkpostctl,
334 .len = ARRAY_SIZE(tclkpostctl),
335 .base_value = 6,
336 },
337 [TCLKTRAILCTL] = {
338 .hsfreq = tclktrailctl,
339 .len = ARRAY_SIZE(tclktrailctl),
340 .base_value = 1,
341 },
342 [THSPRPRCTL] = {
343 .hsfreq = thsprprctl,
344 .len = ARRAY_SIZE(thsprprctl),
345 .base_value = 0,
346 },
347 [THSZEROCTL] = {
348 .hsfreq = thszeroctl,
349 .len = ARRAY_SIZE(thszeroctl),
350 .base_value = 0,
351 },
352 [THSTRAILCTL] = {
353 .hsfreq = thstrailctl,
354 .len = ARRAY_SIZE(thstrailctl),
355 .base_value = 3,
356 },
357 [TLPXCTL] = {
358 .hsfreq = tlpxctl,
359 .len = ARRAY_SIZE(tlpxctl),
360 .base_value = 0,
361 },
362 [THSEXITCTL] = {
363 .hsfreq = thsexitctl,
364 .len = ARRAY_SIZE(thsexitctl),
365 .base_value = 1,
366 },
367 };
368
369 /**
370 * rzv2h_dphy_find_ulpsexit - Find ULP Exit timing value based on frequency
371 * The function maps frequency ranges to ULP exit timing values.
372 * Thresholds in the local hsfreq[] are expressed in Hz already.
373 *
374 * @freq: Input frequency in Hz
375 *
376 * Return: ULP exit timing value
377 */
rzv2h_dphy_find_ulpsexit(unsigned long freq)378 static u16 rzv2h_dphy_find_ulpsexit(unsigned long freq)
379 {
380 /* Frequency thresholds in Hz for ULP exit timing selection */
381 static const unsigned long hsfreq[] = {
382 1953125UL,
383 3906250UL,
384 7812500UL,
385 15625000UL,
386 };
387 /* Corresponding ULP exit timing values for each frequency range */
388 static const u16 ulpsexit[] = {49, 98, 195, 391};
389 unsigned int i;
390
391 /* Find the appropriate frequency range */
392 for (i = 0; i < ARRAY_SIZE(hsfreq); i++) {
393 if (freq <= hsfreq[i])
394 break;
395 }
396
397 /* If frequency exceeds all thresholds, use the highest range */
398 if (i == ARRAY_SIZE(hsfreq))
399 i--;
400
401 return ulpsexit[i];
402 }
403
404 /**
405 * rzv2h_dphy_find_timings_val - Find timing parameter value from lookup tables
406 * @freq: Input frequency in Hz
407 * @index: Index to select timing parameter table (see enum rzv2h_dsi_timing_idx)
408 *
409 * Selects the timing table for the requested parameter, finds the
410 * frequency range entry and returns the register value to program:
411 *
412 * register_value = timings->base_value + table_index
413 *
414 * Note: frequency table entries are stored as small integers (units of 10):
415 * threshold_in_hz = (unsigned long)table_entry * 10 * MEGA
416 *
417 * Return: timing register value to be programmed into hardware
418 */
rzv2h_dphy_find_timings_val(unsigned long freq,u8 index)419 static u16 rzv2h_dphy_find_timings_val(unsigned long freq, u8 index)
420 {
421 const struct rzv2h_mipi_dsi_timings *timings;
422 u16 i;
423
424 /* Get the timing table structure for the requested parameter */
425 timings = &rzv2h_dsi_timings_tables[index];
426
427 /*
428 * Search through frequency table to find appropriate range
429 * timings->hsfreq[i] contains frequency values from HW manual
430 * Convert to Hz by multiplying by 10 * MEGA.
431 */
432 for (i = 0; i < timings->len; i++) {
433 unsigned long hsfreq = timings->hsfreq[i] * 10 * MEGA;
434
435 if (freq <= hsfreq)
436 break;
437 }
438
439 /* If frequency exceeds table range, use the last entry */
440 if (i == timings->len)
441 i--;
442
443 /*
444 * Calculate final register value:
445 * - timings->base_value: base value for this timing parameter
446 * - i: index into frequency table (0-based)
447 * Combined they give the exact register value to program
448 */
449 return timings->base_value + i;
450 };
451
rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi * dsi,u32 reg,u32 data)452 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
453 {
454 iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg);
455 }
456
rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi * dsi,u32 reg,u32 data)457 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
458 {
459 iowrite32(data, dsi->mmio + dsi->info->link_reg_offset + reg);
460 }
461
rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi * dsi,u32 reg)462 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
463 {
464 return ioread32(dsi->mmio + dsi->info->phy_reg_offset + reg);
465 }
466
rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi * dsi,u32 reg)467 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
468 {
469 return ioread32(dsi->mmio + dsi->info->link_reg_offset + reg);
470 }
471
472 /* -----------------------------------------------------------------------------
473 * Hardware Setup
474 */
475
rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi * dsi,u64 hsfreq_millihz)476 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
477 u64 hsfreq_millihz)
478 {
479 unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
480 const struct rzg2l_mipi_dsi_timings *dphy_timings;
481 unsigned int i;
482 u32 dphyctrl0;
483 u32 dphytim0;
484 u32 dphytim1;
485 u32 dphytim2;
486 u32 dphytim3;
487 int ret;
488
489 /* All DSI global operation timings are set with recommended setting */
490 for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) {
491 dphy_timings = &rzg2l_mipi_dsi_global_timings[i];
492 if (hsfreq <= dphy_timings->hsfreq_max)
493 break;
494 }
495
496 /* Initializing DPHY before accessing LINK */
497 dphyctrl0 = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN |
498 DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR;
499
500 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
501 usleep_range(20, 30);
502
503 dphyctrl0 |= DSIDPHYCTRL0_EN_LDO1200;
504 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
505 usleep_range(10, 20);
506
507 dphytim0 = DSIDPHYTIM0_TCLK_MISS(0) |
508 DSIDPHYTIM0_T_INIT(dphy_timings->t_init);
509 dphytim1 = DSIDPHYTIM1_THS_PREPARE(dphy_timings->ths_prepare) |
510 DSIDPHYTIM1_TCLK_PREPARE(dphy_timings->tclk_prepare) |
511 DSIDPHYTIM1_THS_SETTLE(0) |
512 DSIDPHYTIM1_TCLK_SETTLE(0);
513 dphytim2 = DSIDPHYTIM2_TCLK_TRAIL(dphy_timings->tclk_trail) |
514 DSIDPHYTIM2_TCLK_POST(dphy_timings->tclk_post) |
515 DSIDPHYTIM2_TCLK_PRE(dphy_timings->tclk_pre) |
516 DSIDPHYTIM2_TCLK_ZERO(dphy_timings->tclk_zero);
517 dphytim3 = DSIDPHYTIM3_TLPX(dphy_timings->tlpx) |
518 DSIDPHYTIM3_THS_EXIT(dphy_timings->ths_exit) |
519 DSIDPHYTIM3_THS_TRAIL(dphy_timings->ths_trail) |
520 DSIDPHYTIM3_THS_ZERO(dphy_timings->ths_zero);
521
522 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM0, dphytim0);
523 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM1, dphytim1);
524 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2);
525 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3);
526
527 ret = reset_control_deassert(dsi->rstc);
528 if (ret < 0)
529 return ret;
530
531 udelay(1);
532
533 return 0;
534 }
535
rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi * dsi)536 static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
537 {
538 u32 dphyctrl0;
539
540 dphyctrl0 = rzg2l_mipi_dsi_phy_read(dsi, DSIDPHYCTRL0);
541
542 dphyctrl0 &= ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR);
543 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
544
545 reset_control_assert(dsi->rstc);
546 }
547
rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi * dsi,unsigned long mode_freq,u64 * hsfreq_millihz)548 static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
549 u64 *hsfreq_millihz)
550 {
551 unsigned long vclk_rate;
552 unsigned int bpp;
553
554 clk_set_rate(dsi->vclk, mode_freq * KILO);
555 vclk_rate = clk_get_rate(dsi->vclk);
556 if (vclk_rate != mode_freq * KILO)
557 dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",
558 mode_freq * KILO, vclk_rate);
559 /*
560 * Relationship between hsclk and vclk must follow
561 * vclk * bpp = hsclk * 8 * lanes
562 * where vclk: video clock (Hz)
563 * bpp: video pixel bit depth
564 * hsclk: DSI HS Byte clock frequency (Hz)
565 * lanes: number of data lanes
566 *
567 * hsclk(bit) = hsclk(byte) * 8 = hsfreq
568 */
569 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
570 *hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI),
571 dsi->lanes);
572
573 return 0;
574 }
575
rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi * dsi,unsigned long mode_freq)576 static unsigned int rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi *dsi,
577 unsigned long mode_freq)
578 {
579 u64 hsfreq_millihz, mode_freq_hz, mode_freq_millihz;
580 struct rzv2h_pll_div_pars cpg_dsi_parameters;
581 struct rzv2h_pll_pars dsi_parameters;
582 bool parameters_found;
583 unsigned int bpp;
584
585 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
586 mode_freq_hz = mul_u32_u32(mode_freq, KILO);
587 mode_freq_millihz = mode_freq_hz * MILLI;
588 parameters_found =
589 rzv2h_get_pll_divs_pars(dsi->info->cpg_plldsi.limits[0],
590 &cpg_dsi_parameters,
591 dsi->info->cpg_plldsi.table,
592 dsi->info->cpg_plldsi.table_size,
593 mode_freq_millihz);
594 if (!parameters_found)
595 return MODE_CLOCK_RANGE;
596
597 hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(cpg_dsi_parameters.div.freq_millihz * bpp,
598 dsi->lanes);
599 parameters_found = rzv2h_get_pll_pars(&rzv2h_plldsi_div_limits,
600 &dsi_parameters, hsfreq_millihz);
601 if (!parameters_found)
602 return MODE_CLOCK_RANGE;
603
604 if (abs(dsi_parameters.error_millihz) >= 500)
605 return MODE_CLOCK_RANGE;
606
607 memcpy(&dsi->mode_calc.dsi_parameters, &dsi_parameters, sizeof(dsi_parameters));
608 dsi->mode_calc.mode_freq_khz = mode_freq;
609
610 return MODE_OK;
611 }
612
rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi * dsi,unsigned long mode_freq,u64 * hsfreq_millihz)613 static int rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
614 u64 *hsfreq_millihz)
615 {
616 struct rzv2h_pll_pars *dsi_parameters = &dsi->mode_calc.dsi_parameters;
617 unsigned long status;
618
619 if (dsi->mode_calc.mode_freq_khz != mode_freq) {
620 status = rzv2h_dphy_mode_clk_check(dsi, mode_freq);
621 if (status != MODE_OK) {
622 dev_err(dsi->dev, "No PLL parameters found for mode clk %lu\n",
623 mode_freq);
624 return -EINVAL;
625 }
626 }
627
628 *hsfreq_millihz = dsi_parameters->freq_millihz;
629
630 return 0;
631 }
632
rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi * dsi,u64 hsfreq_millihz)633 static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
634 u64 hsfreq_millihz)
635 {
636 struct rzv2h_pll_pars *dsi_parameters = &dsi->mode_calc.dsi_parameters;
637 unsigned long lpclk_rate = clk_get_rate(dsi->lpclk);
638 u32 phytclksetr, phythssetr, phytlpxsetr, phycr;
639 struct rzg2l_mipi_dsi_timings dphy_timings;
640 u16 ulpsexit;
641 u64 hsfreq;
642
643 hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
644
645 if (dsi_parameters->freq_millihz != hsfreq_millihz &&
646 !rzv2h_get_pll_pars(&rzv2h_plldsi_div_limits, dsi_parameters,
647 hsfreq_millihz)) {
648 dev_err(dsi->dev, "No PLL parameters found for HSFREQ %lluHz\n", hsfreq);
649 return -EINVAL;
650 }
651
652 dphy_timings.tclk_trail =
653 rzv2h_dphy_find_timings_val(hsfreq, TCLKTRAILCTL);
654 dphy_timings.tclk_post =
655 rzv2h_dphy_find_timings_val(hsfreq, TCLKPOSTCTL);
656 dphy_timings.tclk_zero =
657 rzv2h_dphy_find_timings_val(hsfreq, TCLKZEROCTL);
658 dphy_timings.tclk_prepare =
659 rzv2h_dphy_find_timings_val(hsfreq, TCLKPRPRCTL);
660 dphy_timings.ths_exit =
661 rzv2h_dphy_find_timings_val(hsfreq, THSEXITCTL);
662 dphy_timings.ths_trail =
663 rzv2h_dphy_find_timings_val(hsfreq, THSTRAILCTL);
664 dphy_timings.ths_zero =
665 rzv2h_dphy_find_timings_val(hsfreq, THSZEROCTL);
666 dphy_timings.ths_prepare =
667 rzv2h_dphy_find_timings_val(hsfreq, THSPRPRCTL);
668 dphy_timings.tlpx =
669 rzv2h_dphy_find_timings_val(hsfreq, TLPXCTL);
670 ulpsexit = rzv2h_dphy_find_ulpsexit(lpclk_rate);
671
672 phytclksetr = FIELD_PREP(PHYTCLKSETR_TCLKTRAILCTL, dphy_timings.tclk_trail) |
673 FIELD_PREP(PHYTCLKSETR_TCLKPOSTCTL, dphy_timings.tclk_post) |
674 FIELD_PREP(PHYTCLKSETR_TCLKZEROCTL, dphy_timings.tclk_zero) |
675 FIELD_PREP(PHYTCLKSETR_TCLKPRPRCTL, dphy_timings.tclk_prepare);
676 phythssetr = FIELD_PREP(PHYTHSSETR_THSEXITCTL, dphy_timings.ths_exit) |
677 FIELD_PREP(PHYTHSSETR_THSTRAILCTL, dphy_timings.ths_trail) |
678 FIELD_PREP(PHYTHSSETR_THSZEROCTL, dphy_timings.ths_zero) |
679 FIELD_PREP(PHYTHSSETR_THSPRPRCTL, dphy_timings.ths_prepare);
680 phytlpxsetr = rzg2l_mipi_dsi_phy_read(dsi, PHYTLPXSETR) & ~PHYTLPXSETR_TLPXCTL;
681 phytlpxsetr |= FIELD_PREP(PHYTLPXSETR_TLPXCTL, dphy_timings.tlpx);
682 phycr = rzg2l_mipi_dsi_phy_read(dsi, PHYCR) & ~GENMASK(9, 0);
683 phycr |= FIELD_PREP(PHYCR_ULPSEXIT, ulpsexit);
684
685 /* Setting all D-PHY Timings Registers */
686 rzg2l_mipi_dsi_phy_write(dsi, PHYTCLKSETR, phytclksetr);
687 rzg2l_mipi_dsi_phy_write(dsi, PHYTHSSETR, phythssetr);
688 rzg2l_mipi_dsi_phy_write(dsi, PHYTLPXSETR, phytlpxsetr);
689 rzg2l_mipi_dsi_phy_write(dsi, PHYCR, phycr);
690
691 rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET0R,
692 FIELD_PREP(PLLCLKSET0R_PLL_S, dsi_parameters->s) |
693 FIELD_PREP(PLLCLKSET0R_PLL_P, dsi_parameters->p) |
694 FIELD_PREP(PLLCLKSET0R_PLL_M, dsi_parameters->m));
695 rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R,
696 FIELD_PREP(PLLCLKSET1R_PLL_K, dsi_parameters->k));
697
698 /*
699 * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
700 * (C) After write to D-PHY registers we need to wait for more than 1 x tp
701 *
702 * tp = 1 / (PLLREFCLK / PLLCLKSET0R.PLL_P)
703 * PLLREFCLK = 24MHz
704 * PLLCLKSET0R.PLL_P = {1, 2, 3, 4}
705 *
706 * To handle all the cases lets use PLLCLKSET0R.PLL_P = 4
707 * tp = 1 / (24MHz / 4) = 1 / 6MHz = 166.67ns
708 */
709 ndelay(200);
710
711 rzg2l_mipi_dsi_phy_write(dsi, PLLENR, PLLENR_PLLEN);
712 /*
713 * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
714 * (D) After write to PLLENR.PLLEN we need to wait for more than 3000 x tp
715 *
716 * 3000 x tp = 3000 x 0.16667 ns = 500.01 microseconds
717 */
718 usleep_range(510, 520);
719
720 return 0;
721 }
722
rzv2h_mipi_dsi_dphy_startup_late_init(struct rzg2l_mipi_dsi * dsi)723 static void rzv2h_mipi_dsi_dphy_startup_late_init(struct rzg2l_mipi_dsi *dsi)
724 {
725 /*
726 * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
727 * (E) After write to TXSETR we need to wait for more than 200 microseconds
728 * and then write to PHYRSTR
729 */
730 usleep_range(210, 220);
731 rzg2l_mipi_dsi_phy_write(dsi, PHYRSTR, PHYRSTR_PHYMRSTN);
732 }
733
rzv2h_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi * dsi)734 static void rzv2h_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
735 {
736 rzg2l_mipi_dsi_phy_write(dsi, PLLENR, 0);
737 }
738
rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi * dsi,const struct drm_display_mode * mode)739 static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
740 const struct drm_display_mode *mode)
741 {
742 unsigned long hsfreq;
743 u64 hsfreq_millihz;
744 u32 txsetr;
745 u32 clstptsetr;
746 u32 lptrnstsetr;
747 u32 clkkpt;
748 u32 clkbfht;
749 u32 clkstpt;
750 u32 golpbkt;
751 u32 dsisetr;
752 int ret;
753
754 ret = pm_runtime_resume_and_get(dsi->dev);
755 if (ret < 0)
756 return ret;
757
758 ret = dsi->info->dphy_conf_clks(dsi, mode->clock, &hsfreq_millihz);
759 if (ret < 0)
760 goto err_phy;
761
762 ret = dsi->info->dphy_init(dsi, hsfreq_millihz);
763 if (ret < 0)
764 goto err_phy;
765
766 /* Enable Data lanes and Clock lanes */
767 txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
768 rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
769
770 if (dsi->info->dphy_startup_late_init)
771 dsi->info->dphy_startup_late_init(dsi);
772
773 hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
774 /*
775 * Global timings characteristic depends on high speed Clock Frequency
776 * Currently MIPI DSI-IF just supports maximum FHD@60 with:
777 * - videoclock = 148.5 (MHz)
778 * - bpp: maximum 24bpp
779 * - data lanes: maximum 4 lanes
780 * Therefore maximum hsclk will be 891 Mbps.
781 */
782 if (hsfreq > 445500000) {
783 clkkpt = 12;
784 clkbfht = 15;
785 clkstpt = 48;
786 golpbkt = 75;
787 } else if (hsfreq > 250000000) {
788 clkkpt = 7;
789 clkbfht = 8;
790 clkstpt = 27;
791 golpbkt = 40;
792 } else {
793 clkkpt = 8;
794 clkbfht = 6;
795 clkstpt = 24;
796 golpbkt = 29;
797 }
798
799 clstptsetr = CLSTPTSETR_CLKKPT(clkkpt) | CLSTPTSETR_CLKBFHT(clkbfht) |
800 CLSTPTSETR_CLKSTPT(clkstpt);
801 rzg2l_mipi_dsi_link_write(dsi, CLSTPTSETR, clstptsetr);
802
803 lptrnstsetr = LPTRNSTSETR_GOLPBKT(golpbkt);
804 rzg2l_mipi_dsi_link_write(dsi, LPTRNSTSETR, lptrnstsetr);
805
806 /*
807 * Increase MRPSZ as the default value of 1 will result in long read
808 * commands payload not being saved to memory.
809 */
810 dsisetr = rzg2l_mipi_dsi_link_read(dsi, DSISETR);
811 FIELD_MODIFY(DSISETR_MRPSZ, &dsisetr, RZG2L_DCS_BUF_SIZE);
812 rzg2l_mipi_dsi_link_write(dsi, DSISETR, dsisetr);
813
814 return 0;
815
816 err_phy:
817 dsi->info->dphy_exit(dsi);
818 pm_runtime_put(dsi->dev);
819
820 return ret;
821 }
822
rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi * dsi)823 static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi)
824 {
825 dsi->info->dphy_exit(dsi);
826 pm_runtime_put(dsi->dev);
827 }
828
rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi * dsi,const struct drm_display_mode * mode)829 static void rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi *dsi,
830 const struct drm_display_mode *mode)
831 {
832 u32 vich1ppsetr;
833 u32 vich1vssetr;
834 u32 vich1vpsetr;
835 u32 vich1hssetr;
836 u32 vich1hpsetr;
837 int dsi_format;
838 u32 delay[2];
839 u8 index;
840
841 /* Configuration for Pixel Packet */
842 dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
843 switch (dsi_format) {
844 case 24:
845 vich1ppsetr = VICH1PPSETR_DT_RGB24;
846 break;
847 case 18:
848 vich1ppsetr = VICH1PPSETR_DT_RGB18;
849 break;
850 case 16:
851 vich1ppsetr = VICH1PPSETR_DT_RGB16;
852 break;
853 }
854
855 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) &&
856 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
857 vich1ppsetr |= VICH1PPSETR_TXESYNC_PULSE;
858
859 rzg2l_mipi_dsi_link_write(dsi, VICH1PPSETR, vich1ppsetr);
860
861 /* Configuration for Video Parameters */
862 vich1vssetr = VICH1VSSETR_VACTIVE(mode->vdisplay) |
863 VICH1VSSETR_VSA(mode->vsync_end - mode->vsync_start);
864 vich1vssetr |= (mode->flags & DRM_MODE_FLAG_PVSYNC) ?
865 VICH1VSSETR_VSPOL_HIGH : VICH1VSSETR_VSPOL_LOW;
866
867 vich1vpsetr = VICH1VPSETR_VFP(mode->vsync_start - mode->vdisplay) |
868 VICH1VPSETR_VBP(mode->vtotal - mode->vsync_end);
869
870 vich1hssetr = VICH1HSSETR_HACTIVE(mode->hdisplay) |
871 VICH1HSSETR_HSA(mode->hsync_end - mode->hsync_start);
872 vich1hssetr |= (mode->flags & DRM_MODE_FLAG_PHSYNC) ?
873 VICH1HSSETR_HSPOL_HIGH : VICH1HSSETR_HSPOL_LOW;
874
875 vich1hpsetr = VICH1HPSETR_HFP(mode->hsync_start - mode->hdisplay) |
876 VICH1HPSETR_HBP(mode->htotal - mode->hsync_end);
877
878 rzg2l_mipi_dsi_link_write(dsi, VICH1VSSETR, vich1vssetr);
879 rzg2l_mipi_dsi_link_write(dsi, VICH1VPSETR, vich1vpsetr);
880 rzg2l_mipi_dsi_link_write(dsi, VICH1HSSETR, vich1hssetr);
881 rzg2l_mipi_dsi_link_write(dsi, VICH1HPSETR, vich1hpsetr);
882
883 /*
884 * Configuration for Delay Value
885 * Delay value based on 2 ranges of video clock.
886 * 74.25MHz is videoclock of HD@60p or FHD@30p
887 */
888 if (mode->clock > 74250) {
889 delay[0] = 231;
890 delay[1] = 216;
891 } else {
892 delay[0] = 220;
893 delay[1] = 212;
894 }
895
896 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
897 index = 0;
898 else
899 index = 1;
900
901 rzg2l_mipi_dsi_link_write(dsi, VICH1SET1R,
902 VICH1SET1R_DLY(delay[index]));
903 }
904
rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi * dsi)905 static int rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi *dsi)
906 {
907 bool is_clk_cont;
908 u32 hsclksetr;
909 u32 status;
910 int ret;
911
912 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
913
914 /* Start HS clock */
915 hsclksetr = HSCLKSETR_HSCLKRUN_HS | (is_clk_cont ?
916 HSCLKSETR_HSCLKMODE_CONT :
917 HSCLKSETR_HSCLKMODE_NON_CONT);
918 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR, hsclksetr);
919
920 if (is_clk_cont) {
921 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
922 status & PLSR_CLLP2HS,
923 2000, 20000, false, dsi, PLSR);
924 if (ret < 0) {
925 dev_err(dsi->dev, "failed to start HS clock\n");
926 return ret;
927 }
928 }
929
930 dev_dbg(dsi->dev, "Start High Speed Clock with %s clock mode",
931 is_clk_cont ? "continuous" : "non-continuous");
932
933 return 0;
934 }
935
rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi * dsi)936 static int rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi *dsi)
937 {
938 bool is_clk_cont;
939 u32 status;
940 int ret;
941
942 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
943
944 /* Stop HS clock */
945 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR,
946 is_clk_cont ? HSCLKSETR_HSCLKMODE_CONT :
947 HSCLKSETR_HSCLKMODE_NON_CONT);
948
949 if (is_clk_cont) {
950 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
951 status & PLSR_CLHS2LP,
952 2000, 20000, false, dsi, PLSR);
953 if (ret < 0) {
954 dev_err(dsi->dev, "failed to stop HS clock\n");
955 return ret;
956 }
957 }
958
959 return 0;
960 }
961
rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi * dsi)962 static int rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi *dsi)
963 {
964 u32 vich1set0r;
965 u32 status;
966 int ret;
967
968 /* Configuration for Blanking sequence and start video input */
969 vich1set0r = VICH1SET0R_HFPNOLP | VICH1SET0R_HBPNOLP |
970 VICH1SET0R_HSANOLP | VICH1SET0R_VSTART;
971 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, vich1set0r);
972
973 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
974 status & VICH1SR_VIRDY,
975 2000, 20000, false, dsi, VICH1SR);
976 if (ret < 0)
977 dev_err(dsi->dev, "Failed to start video signal input\n");
978
979 return ret;
980 }
981
rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi * dsi)982 static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi)
983 {
984 u32 status;
985 int ret;
986
987 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, VICH1SET0R_VSTPAFT);
988 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
989 (status & VICH1SR_STOP) && (!(status & VICH1SR_RUNNING)),
990 2000, 20000, false, dsi, VICH1SR);
991 if (ret < 0)
992 goto err;
993
994 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
995 !(status & LINKSR_HSBUSY),
996 2000, 20000, false, dsi, LINKSR);
997 if (ret < 0)
998 goto err;
999
1000 return 0;
1001
1002 err:
1003 dev_err(dsi->dev, "Failed to stop video signal input\n");
1004 return ret;
1005 }
1006
1007 /* -----------------------------------------------------------------------------
1008 * Bridge
1009 */
1010
rzg2l_mipi_dsi_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)1011 static int rzg2l_mipi_dsi_attach(struct drm_bridge *bridge,
1012 struct drm_encoder *encoder,
1013 enum drm_bridge_attach_flags flags)
1014 {
1015 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1016
1017 return drm_bridge_attach(encoder, dsi->next_bridge, bridge,
1018 flags);
1019 }
1020
rzg2l_mipi_dsi_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1021 static void rzg2l_mipi_dsi_atomic_pre_enable(struct drm_bridge *bridge,
1022 struct drm_atomic_state *state)
1023 {
1024 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1025 const struct drm_display_mode *mode;
1026 struct drm_connector *connector;
1027 struct drm_crtc *crtc;
1028 int ret;
1029
1030 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
1031 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
1032 mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
1033
1034 ret = rzg2l_mipi_dsi_startup(dsi, mode);
1035 if (ret < 0)
1036 return;
1037
1038 rzg2l_mipi_dsi_set_display_timing(dsi, mode);
1039 }
1040
rzg2l_mipi_dsi_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1041 static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
1042 struct drm_atomic_state *state)
1043 {
1044 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1045 int ret;
1046
1047 ret = rzg2l_mipi_dsi_start_hs_clock(dsi);
1048 if (ret < 0)
1049 goto err_stop;
1050
1051 ret = rzg2l_mipi_dsi_start_video(dsi);
1052 if (ret < 0)
1053 goto err_stop_clock;
1054
1055 return;
1056
1057 err_stop_clock:
1058 rzg2l_mipi_dsi_stop_hs_clock(dsi);
1059 err_stop:
1060 rzg2l_mipi_dsi_stop(dsi);
1061 }
1062
rzg2l_mipi_dsi_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1063 static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
1064 struct drm_atomic_state *state)
1065 {
1066 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1067
1068 rzg2l_mipi_dsi_stop_video(dsi);
1069 rzg2l_mipi_dsi_stop_hs_clock(dsi);
1070 }
1071
rzg2l_mipi_dsi_atomic_post_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1072 static void rzg2l_mipi_dsi_atomic_post_disable(struct drm_bridge *bridge,
1073 struct drm_atomic_state *state)
1074 {
1075 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1076
1077 rzg2l_mipi_dsi_stop(dsi);
1078 }
1079
1080 static enum drm_mode_status
rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1081 rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
1082 const struct drm_display_info *info,
1083 const struct drm_display_mode *mode)
1084 {
1085 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1086
1087 if (mode->clock > dsi->info->max_dclk)
1088 return MODE_CLOCK_HIGH;
1089
1090 if (mode->clock < dsi->info->min_dclk)
1091 return MODE_CLOCK_LOW;
1092
1093 if (dsi->info->dphy_mode_clk_check) {
1094 enum drm_mode_status status;
1095
1096 status = dsi->info->dphy_mode_clk_check(dsi, mode->clock);
1097 if (status != MODE_OK)
1098 return status;
1099 }
1100
1101 return MODE_OK;
1102 }
1103
1104 static const struct drm_bridge_funcs rzg2l_mipi_dsi_bridge_ops = {
1105 .attach = rzg2l_mipi_dsi_attach,
1106 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1107 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1108 .atomic_reset = drm_atomic_helper_bridge_reset,
1109 .atomic_pre_enable = rzg2l_mipi_dsi_atomic_pre_enable,
1110 .atomic_enable = rzg2l_mipi_dsi_atomic_enable,
1111 .atomic_disable = rzg2l_mipi_dsi_atomic_disable,
1112 .atomic_post_disable = rzg2l_mipi_dsi_atomic_post_disable,
1113 .mode_valid = rzg2l_mipi_dsi_bridge_mode_valid,
1114 };
1115
1116 /* -----------------------------------------------------------------------------
1117 * Host setting
1118 */
1119
rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1120 static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
1121 struct mipi_dsi_device *device)
1122 {
1123 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
1124 int bpp;
1125 int ret;
1126
1127 if (device->lanes > dsi->num_data_lanes) {
1128 dev_err(dsi->dev,
1129 "Number of lines of device (%u) exceeds host (%u)\n",
1130 device->lanes, dsi->num_data_lanes);
1131 return -EINVAL;
1132 }
1133
1134 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
1135 switch (bpp) {
1136 case 24:
1137 break;
1138 case 18:
1139 break;
1140 case 16:
1141 if (!(dsi->info->features & RZ_MIPI_DSI_FEATURE_16BPP)) {
1142 dev_err(dsi->dev, "Unsupported format 0x%04x\n",
1143 device->format);
1144 return -EINVAL;
1145 }
1146 break;
1147 default:
1148 dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);
1149 return -EINVAL;
1150 }
1151
1152 dsi->lanes = device->lanes;
1153 dsi->format = device->format;
1154 dsi->mode_flags = device->mode_flags;
1155
1156 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
1157 1, 0);
1158 if (IS_ERR(dsi->next_bridge)) {
1159 ret = PTR_ERR(dsi->next_bridge);
1160 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
1161 return ret;
1162 }
1163
1164 drm_bridge_add(&dsi->bridge);
1165
1166 /*
1167 * Report the required division ratio setting for the MIPI clock dividers.
1168 *
1169 * vclk * bpp = hsclk * 8 * num_lanes
1170 *
1171 * vclk * DSI_AB_divider = hsclk * 16
1172 *
1173 * which simplifies to...
1174 * DSI_AB_divider = bpp * 2 / num_lanes
1175 */
1176 rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, PLL5_TARGET_DSI);
1177
1178 return 0;
1179 }
1180
rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1181 static int rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host *host,
1182 struct mipi_dsi_device *device)
1183 {
1184 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
1185
1186 drm_bridge_remove(&dsi->bridge);
1187
1188 return 0;
1189 }
1190
rzg2l_mipi_dsi_read_response(struct rzg2l_mipi_dsi * dsi,const struct mipi_dsi_msg * msg)1191 static ssize_t rzg2l_mipi_dsi_read_response(struct rzg2l_mipi_dsi *dsi,
1192 const struct mipi_dsi_msg *msg)
1193 {
1194 u8 *msg_rx = msg->rx_buf;
1195 u8 datatype;
1196 u32 result;
1197 u16 size;
1198
1199 result = rzg2l_mipi_dsi_link_read(dsi, RXRSS0R);
1200 if (result & RXRSS0R_RXPKTDFAIL) {
1201 dev_err(dsi->dev, "packet rx data did not save correctly\n");
1202 return -EPROTO;
1203 }
1204
1205 if (result & RXRSS0R_RXFAIL) {
1206 dev_err(dsi->dev, "packet rx failure\n");
1207 return -EPROTO;
1208 }
1209
1210 if (!(result & RXRSS0R_RXSUC))
1211 return -EPROTO;
1212
1213 datatype = FIELD_GET(RXRSS0R_DT, result);
1214
1215 switch (datatype) {
1216 case 0:
1217 dev_dbg(dsi->dev, "ACK\n");
1218 return 0;
1219 case MIPI_DSI_RX_END_OF_TRANSMISSION:
1220 dev_dbg(dsi->dev, "EoTp\n");
1221 return 0;
1222 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1223 dev_dbg(dsi->dev, "Acknowledge and error report: $%02x%02x\n",
1224 (u8)FIELD_GET(RXRSS0R_DATA1, result),
1225 (u8)FIELD_GET(RXRSS0R_DATA0, result));
1226 return 0;
1227 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1228 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1229 msg_rx[0] = FIELD_GET(RXRSS0R_DATA0, result);
1230 return 1;
1231 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1232 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1233 msg_rx[0] = FIELD_GET(RXRSS0R_DATA0, result);
1234 msg_rx[1] = FIELD_GET(RXRSS0R_DATA1, result);
1235 return 2;
1236 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1237 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1238 size = FIELD_GET(RXRSS0R_WC, result);
1239
1240 if (size > msg->rx_len) {
1241 dev_err(dsi->dev, "rx buffer too small");
1242 return -ENOSPC;
1243 }
1244
1245 memcpy(msg_rx, dsi->dcs_buf_virt, size);
1246 return size;
1247 default:
1248 dev_err(dsi->dev, "unhandled response type: %02x\n", datatype);
1249 return -EPROTO;
1250 }
1251 }
1252
rzg2l_mipi_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1253 static ssize_t rzg2l_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
1254 const struct mipi_dsi_msg *msg)
1255 {
1256 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
1257 struct mipi_dsi_packet packet;
1258 bool need_bta;
1259 u32 value;
1260 int ret;
1261
1262 ret = mipi_dsi_create_packet(&packet, msg);
1263 if (ret < 0)
1264 return ret;
1265
1266 /* Terminate operation after this descriptor is finished */
1267 value = SQCH0DSC0AR_NXACT_TERM;
1268
1269 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
1270 need_bta = true; /* Message with explicitly requested ACK */
1271 value |= FIELD_PREP(SQCH0DSC0AR_BTA, SQCH0DSC0AR_BTA_NON_READ);
1272 } else if (msg->rx_buf && msg->rx_len > 0) {
1273 need_bta = true; /* Read request */
1274 value |= FIELD_PREP(SQCH0DSC0AR_BTA, SQCH0DSC0AR_BTA_READ);
1275 } else {
1276 need_bta = false;
1277 value |= FIELD_PREP(SQCH0DSC0AR_BTA, SQCH0DSC0AR_BTA_NONE);
1278 }
1279
1280 /* Set transmission speed */
1281 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1282 value |= SQCH0DSC0AR_SPD_LOW;
1283 else
1284 value |= SQCH0DSC0AR_SPD_HIGH;
1285
1286 /* Write TX packet header */
1287 value |= FIELD_PREP(SQCH0DSC0AR_DT, packet.header[0]) |
1288 FIELD_PREP(SQCH0DSC0AR_DATA0, packet.header[1]) |
1289 FIELD_PREP(SQCH0DSC0AR_DATA1, packet.header[2]);
1290
1291 if (mipi_dsi_packet_format_is_long(msg->type)) {
1292 value |= SQCH0DSC0AR_FMT_LONG;
1293
1294 if (packet.payload_length > RZG2L_DCS_BUF_SIZE) {
1295 dev_err(dsi->dev, "Packet Tx payload size (%d) too large",
1296 (unsigned int)packet.payload_length);
1297 return -ENOSPC;
1298 }
1299
1300 /* Copy TX packet payload data to memory space */
1301 memcpy(dsi->dcs_buf_virt, packet.payload, packet.payload_length);
1302 } else {
1303 value |= SQCH0DSC0AR_FMT_SHORT;
1304 }
1305
1306 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0AR, value);
1307
1308 /*
1309 * Write: specify payload data source location, only used for
1310 * long packet.
1311 * Read: specify payload data storage location of response
1312 * packet. Note: a read packet is always a short packet.
1313 * If the response packet is a short packet or a long packet
1314 * with WC = 0 (no payload), DTSEL is meaningless.
1315 */
1316 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0BR, SQCH0DSC0BR_DTSEL_MEM_SPACE);
1317
1318 /*
1319 * Set SQCHxSR.AACTFIN bit when descriptor actions are finished.
1320 * Read: set Rx result save slot number to 0 (ACTCODE).
1321 */
1322 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0CR, SQCH0DSC0CR_FINACT);
1323
1324 /* Set rx/tx payload data address, only relevant for long packet. */
1325 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0DR, (u32)dsi->dcs_buf_phys);
1326
1327 /* Start sequence 0 operation */
1328 value = rzg2l_mipi_dsi_link_read(dsi, SQCH0SET0R);
1329 value |= SQCH0SET0R_START;
1330 rzg2l_mipi_dsi_link_write(dsi, SQCH0SET0R, value);
1331
1332 /* Wait for operation to finish */
1333 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read,
1334 value, value & SQCH0SR_ADESFIN,
1335 2000, 20000, false, dsi, SQCH0SR);
1336 if (ret == 0) {
1337 /* Success: clear status bit */
1338 rzg2l_mipi_dsi_link_write(dsi, SQCH0SCR, SQCH0SCR_ADESFIN);
1339
1340 if (need_bta)
1341 ret = rzg2l_mipi_dsi_read_response(dsi, msg);
1342 else
1343 ret = packet.payload_length;
1344 }
1345
1346 return ret;
1347 }
1348
1349 static const struct mipi_dsi_host_ops rzg2l_mipi_dsi_host_ops = {
1350 .attach = rzg2l_mipi_dsi_host_attach,
1351 .detach = rzg2l_mipi_dsi_host_detach,
1352 .transfer = rzg2l_mipi_dsi_host_transfer,
1353 };
1354
1355 /* -----------------------------------------------------------------------------
1356 * Power Management
1357 */
1358
rzg2l_mipi_pm_runtime_suspend(struct device * dev)1359 static int rzg2l_mipi_pm_runtime_suspend(struct device *dev)
1360 {
1361 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
1362
1363 reset_control_assert(dsi->prstc);
1364 reset_control_assert(dsi->arstc);
1365
1366 return 0;
1367 }
1368
rzg2l_mipi_pm_runtime_resume(struct device * dev)1369 static int rzg2l_mipi_pm_runtime_resume(struct device *dev)
1370 {
1371 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
1372 int ret;
1373
1374 ret = reset_control_deassert(dsi->arstc);
1375 if (ret < 0)
1376 return ret;
1377
1378 ret = reset_control_deassert(dsi->prstc);
1379 if (ret < 0)
1380 reset_control_assert(dsi->arstc);
1381
1382 return ret;
1383 }
1384
1385 static const struct dev_pm_ops rzg2l_mipi_pm_ops = {
1386 RUNTIME_PM_OPS(rzg2l_mipi_pm_runtime_suspend, rzg2l_mipi_pm_runtime_resume, NULL)
1387 };
1388
1389 /* -----------------------------------------------------------------------------
1390 * Probe & Remove
1391 */
1392
rzg2l_mipi_dsi_probe(struct platform_device * pdev)1393 static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
1394 {
1395 unsigned int num_data_lanes;
1396 struct rzg2l_mipi_dsi *dsi;
1397 u32 txsetr;
1398 int ret;
1399
1400 dsi = devm_drm_bridge_alloc(&pdev->dev, struct rzg2l_mipi_dsi, bridge,
1401 &rzg2l_mipi_dsi_bridge_ops);
1402 if (IS_ERR(dsi))
1403 return PTR_ERR(dsi);
1404
1405 platform_set_drvdata(pdev, dsi);
1406 dsi->dev = &pdev->dev;
1407
1408 dsi->info = of_device_get_match_data(&pdev->dev);
1409
1410 ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
1411 if (ret < 0)
1412 return dev_err_probe(dsi->dev, ret,
1413 "missing or invalid data-lanes property\n");
1414
1415 num_data_lanes = ret;
1416
1417 dsi->mmio = devm_platform_ioremap_resource(pdev, 0);
1418 if (IS_ERR(dsi->mmio))
1419 return PTR_ERR(dsi->mmio);
1420
1421 dsi->vclk = devm_clk_get(dsi->dev, "vclk");
1422 if (IS_ERR(dsi->vclk))
1423 return PTR_ERR(dsi->vclk);
1424
1425 dsi->lpclk = devm_clk_get(dsi->dev, "lpclk");
1426 if (IS_ERR(dsi->lpclk))
1427 return PTR_ERR(dsi->lpclk);
1428
1429 dsi->rstc = devm_reset_control_get_optional_exclusive(dsi->dev, "rst");
1430 if (IS_ERR(dsi->rstc))
1431 return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
1432 "failed to get rst\n");
1433
1434 dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst");
1435 if (IS_ERR(dsi->arstc))
1436 return dev_err_probe(&pdev->dev, PTR_ERR(dsi->arstc),
1437 "failed to get arst\n");
1438
1439 dsi->prstc = devm_reset_control_get_exclusive(dsi->dev, "prst");
1440 if (IS_ERR(dsi->prstc))
1441 return dev_err_probe(dsi->dev, PTR_ERR(dsi->prstc),
1442 "failed to get prst\n");
1443
1444 platform_set_drvdata(pdev, dsi);
1445
1446 pm_runtime_enable(dsi->dev);
1447
1448 ret = pm_runtime_resume_and_get(dsi->dev);
1449 if (ret < 0)
1450 goto err_pm_disable;
1451
1452 /*
1453 * TXSETR register can be read only after DPHY init. But during probe
1454 * mode->clock and format are not available. So initialize DPHY with
1455 * timing parameters for 80Mbps.
1456 */
1457 ret = dsi->info->dphy_init(dsi, 80000000ULL * MILLI);
1458 if (ret < 0)
1459 goto err_phy;
1460
1461 txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR);
1462 dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes);
1463 dsi->info->dphy_exit(dsi);
1464 pm_runtime_put(dsi->dev);
1465
1466 /* Initialize the DRM bridge. */
1467 dsi->bridge.of_node = dsi->dev->of_node;
1468
1469 /* Init host device */
1470 dsi->host.dev = dsi->dev;
1471 dsi->host.ops = &rzg2l_mipi_dsi_host_ops;
1472 ret = mipi_dsi_host_register(&dsi->host);
1473 if (ret < 0)
1474 goto err_pm_disable;
1475
1476 dsi->dcs_buf_virt = dma_alloc_coherent(dsi->host.dev, RZG2L_DCS_BUF_SIZE,
1477 &dsi->dcs_buf_phys, GFP_KERNEL);
1478 if (!dsi->dcs_buf_virt)
1479 return -ENOMEM;
1480
1481 return 0;
1482
1483 err_phy:
1484 dsi->info->dphy_exit(dsi);
1485 pm_runtime_put(dsi->dev);
1486 err_pm_disable:
1487 pm_runtime_disable(dsi->dev);
1488 return ret;
1489 }
1490
rzg2l_mipi_dsi_remove(struct platform_device * pdev)1491 static void rzg2l_mipi_dsi_remove(struct platform_device *pdev)
1492 {
1493 struct rzg2l_mipi_dsi *dsi = platform_get_drvdata(pdev);
1494
1495 dma_free_coherent(dsi->host.dev, RZG2L_DCS_BUF_SIZE, dsi->dcs_buf_virt,
1496 dsi->dcs_buf_phys);
1497 mipi_dsi_host_unregister(&dsi->host);
1498 pm_runtime_disable(&pdev->dev);
1499 }
1500
1501 RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);
1502
1503 static const struct rzv2h_pll_limits *rzv2h_plldsi_limits[] = {
1504 &rzv2h_cpg_pll_dsi_limits,
1505 };
1506
1507 static const u8 rzv2h_cpg_div_table[] = {
1508 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32,
1509 };
1510
1511 static const struct rzg2l_mipi_dsi_hw_info rzv2h_mipi_dsi_info = {
1512 .dphy_init = rzv2h_mipi_dsi_dphy_init,
1513 .dphy_startup_late_init = rzv2h_mipi_dsi_dphy_startup_late_init,
1514 .dphy_exit = rzv2h_mipi_dsi_dphy_exit,
1515 .dphy_mode_clk_check = rzv2h_dphy_mode_clk_check,
1516 .dphy_conf_clks = rzv2h_dphy_conf_clks,
1517 .cpg_plldsi.limits = rzv2h_plldsi_limits,
1518 .cpg_plldsi.table = rzv2h_cpg_div_table,
1519 .cpg_plldsi.table_size = ARRAY_SIZE(rzv2h_cpg_div_table),
1520 .phy_reg_offset = 0x10000,
1521 .link_reg_offset = 0,
1522 .min_dclk = 5440,
1523 .max_dclk = 187500,
1524 .features = RZ_MIPI_DSI_FEATURE_16BPP,
1525 };
1526
1527 static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = {
1528 .dphy_init = rzg2l_mipi_dsi_dphy_init,
1529 .dphy_exit = rzg2l_mipi_dsi_dphy_exit,
1530 .dphy_conf_clks = rzg2l_dphy_conf_clks,
1531 .link_reg_offset = 0x10000,
1532 .min_dclk = 5803,
1533 .max_dclk = 148500,
1534 };
1535
1536 static const struct of_device_id rzg2l_mipi_dsi_of_table[] = {
1537 { .compatible = "renesas,r9a09g057-mipi-dsi", .data = &rzv2h_mipi_dsi_info, },
1538 { .compatible = "renesas,rzg2l-mipi-dsi", .data = &rzg2l_mipi_dsi_info, },
1539 { /* sentinel */ }
1540 };
1541
1542 MODULE_DEVICE_TABLE(of, rzg2l_mipi_dsi_of_table);
1543
1544 static struct platform_driver rzg2l_mipi_dsi_platform_driver = {
1545 .probe = rzg2l_mipi_dsi_probe,
1546 .remove = rzg2l_mipi_dsi_remove,
1547 .driver = {
1548 .name = "rzg2l-mipi-dsi",
1549 .pm = pm_ptr(&rzg2l_mipi_pm_ops),
1550 .of_match_table = rzg2l_mipi_dsi_of_table,
1551 },
1552 };
1553
1554 module_platform_driver(rzg2l_mipi_dsi_platform_driver);
1555
1556 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
1557 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI DSI Encoder Driver");
1558 MODULE_LICENSE("GPL");
1559