1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Intel HDMI codec support
4 */
5
6 #include <linux/init.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <sound/core.h>
10 #include <sound/hdaudio.h>
11 #include <sound/hda_i915.h>
12 #include <sound/hda_codec.h>
13 #include "hda_local.h"
14 #include "hdmi_local.h"
15
16 static bool enable_silent_stream =
17 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
18 module_param(enable_silent_stream, bool, 0644);
19 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
20
21 enum {
22 MODEL_HSW,
23 MODEL_GLK,
24 MODEL_ICL,
25 MODEL_TGL,
26 MODEL_ADLP,
27 MODEL_BYT,
28 MODEL_CPT,
29 };
30
31 #define INTEL_GET_VENDOR_VERB 0xf81
32 #define INTEL_SET_VENDOR_VERB 0x781
33 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
34 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
35
intel_haswell_enable_all_pins(struct hda_codec * codec,bool update_tree)36 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
37 bool update_tree)
38 {
39 unsigned int vendor_param;
40 struct hdmi_spec *spec = codec->spec;
41
42 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
43 INTEL_GET_VENDOR_VERB, 0);
44 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
45 return;
46
47 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
48 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
49 INTEL_SET_VENDOR_VERB, vendor_param);
50 if (vendor_param == -1)
51 return;
52
53 if (update_tree)
54 snd_hda_codec_update_widgets(codec);
55 }
56
intel_haswell_fixup_enable_dp12(struct hda_codec * codec)57 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
58 {
59 unsigned int vendor_param;
60 struct hdmi_spec *spec = codec->spec;
61
62 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
63 INTEL_GET_VENDOR_VERB, 0);
64 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
65 return;
66
67 /* enable DP1.2 mode */
68 vendor_param |= INTEL_EN_DP12;
69 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
70 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
71 INTEL_SET_VENDOR_VERB, vendor_param);
72 }
73
74 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
75 * Otherwise you may get severe h/w communication errors.
76 */
haswell_set_power_state(struct hda_codec * codec,hda_nid_t fg,unsigned int power_state)77 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
78 unsigned int power_state)
79 {
80 /* check codec->spec: it can be called before the probe gets called */
81 if (codec->spec) {
82 if (power_state == AC_PWRST_D0) {
83 intel_haswell_enable_all_pins(codec, false);
84 intel_haswell_fixup_enable_dp12(codec);
85 }
86 }
87
88 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
89 snd_hda_codec_set_power_to_all(codec, fg, power_state);
90 }
91
92 /* There is a fixed mapping between audio pin node and display port.
93 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
94 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
95 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
96 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
97 *
98 * on VLV, ILK:
99 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
100 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
101 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
102 */
intel_base_nid(struct hda_codec * codec)103 static int intel_base_nid(struct hda_codec *codec)
104 {
105 switch (codec->core.vendor_id) {
106 case 0x80860054: /* ILK */
107 case 0x80862804: /* ILK */
108 case 0x80862882: /* VLV */
109 return 4;
110 default:
111 return 5;
112 }
113 }
114
intel_pin2port(void * audio_ptr,int pin_nid)115 static int intel_pin2port(void *audio_ptr, int pin_nid)
116 {
117 struct hda_codec *codec = audio_ptr;
118 struct hdmi_spec *spec = codec->spec;
119 int base_nid, i;
120
121 if (!spec->port_num) {
122 base_nid = intel_base_nid(codec);
123 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
124 return -1;
125 return pin_nid - base_nid + 1;
126 }
127
128 /*
129 * looking for the pin number in the mapping table and return
130 * the index which indicate the port number
131 */
132 for (i = 0; i < spec->port_num; i++) {
133 if (pin_nid == spec->port_map[i])
134 return i;
135 }
136
137 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
138 return -1;
139 }
140
intel_port2pin(struct hda_codec * codec,int port)141 static int intel_port2pin(struct hda_codec *codec, int port)
142 {
143 struct hdmi_spec *spec = codec->spec;
144
145 if (!spec->port_num) {
146 /* we assume only from port-B to port-D */
147 if (port < 1 || port > 3)
148 return 0;
149 return port + intel_base_nid(codec) - 1;
150 }
151
152 if (port < 0 || port >= spec->port_num)
153 return 0;
154 return spec->port_map[port];
155 }
156
intel_pin_eld_notify(void * audio_ptr,int port,int pipe)157 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
158 {
159 struct hda_codec *codec = audio_ptr;
160 int pin_nid;
161 int dev_id = pipe;
162
163 pin_nid = intel_port2pin(codec, port);
164 if (!pin_nid)
165 return;
166 /* skip notification during system suspend (but not in runtime PM);
167 * the state will be updated at resume
168 */
169 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
170 return;
171
172 snd_hdac_i915_set_bclk(&codec->bus->core);
173 snd_hda_hdmi_check_presence_and_report(codec, pin_nid, dev_id);
174 }
175
176 static const struct drm_audio_component_audio_ops intel_audio_ops = {
177 .pin2port = intel_pin2port,
178 .pin_eld_notify = intel_pin_eld_notify,
179 };
180
181 /* register i915 component pin_eld_notify callback */
register_i915_notifier(struct hda_codec * codec)182 static void register_i915_notifier(struct hda_codec *codec)
183 {
184 struct hdmi_spec *spec = codec->spec;
185
186 spec->use_acomp_notifier = true;
187 spec->port2pin = intel_port2pin;
188 snd_hda_hdmi_setup_drm_audio_ops(codec, &intel_audio_ops);
189 snd_hdac_acomp_register_notifier(&codec->bus->core,
190 &spec->drm_audio_ops);
191 /* no need for forcible resume for jack check thanks to notifier */
192 codec->relaxed_resume = 1;
193 }
194
195 #define I915_SILENT_RATE 48000
196 #define I915_SILENT_CHANNELS 2
197 #define I915_SILENT_FORMAT_BITS 16
198 #define I915_SILENT_FMT_MASK 0xf
199
silent_stream_enable_i915(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin)200 static void silent_stream_enable_i915(struct hda_codec *codec,
201 struct hdmi_spec_per_pin *per_pin)
202 {
203 unsigned int format;
204
205 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
206 per_pin->dev_id, I915_SILENT_RATE);
207
208 /* trigger silent stream generation in hw */
209 format = snd_hdac_stream_format(I915_SILENT_CHANNELS, I915_SILENT_FORMAT_BITS,
210 I915_SILENT_RATE);
211 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
212 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
213 usleep_range(100, 200);
214 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
215
216 per_pin->channels = I915_SILENT_CHANNELS;
217 snd_hda_hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
218 }
219
silent_stream_set_kae(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,bool enable)220 static void silent_stream_set_kae(struct hda_codec *codec,
221 struct hdmi_spec_per_pin *per_pin,
222 bool enable)
223 {
224 unsigned int param;
225
226 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
227
228 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
229 param = (param >> 16) & 0xff;
230
231 if (enable)
232 param |= AC_DIG3_KAE;
233 else
234 param &= ~AC_DIG3_KAE;
235
236 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
237 }
238
i915_set_silent_stream(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,bool enable)239 static void i915_set_silent_stream(struct hda_codec *codec,
240 struct hdmi_spec_per_pin *per_pin,
241 bool enable)
242 {
243 struct hdmi_spec *spec = codec->spec;
244
245 switch (spec->silent_stream_type) {
246 case SILENT_STREAM_KAE:
247 if (enable) {
248 silent_stream_enable_i915(codec, per_pin);
249 silent_stream_set_kae(codec, per_pin, true);
250 } else {
251 silent_stream_set_kae(codec, per_pin, false);
252 }
253 break;
254 case SILENT_STREAM_I915:
255 if (enable) {
256 silent_stream_enable_i915(codec, per_pin);
257 snd_hda_power_up_pm(codec);
258 } else {
259 /* release ref taken in silent_stream_enable() */
260 snd_hda_power_down_pm(codec);
261 }
262 break;
263 default:
264 break;
265 }
266 }
267
haswell_verify_D0(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t nid)268 static void haswell_verify_D0(struct hda_codec *codec,
269 hda_nid_t cvt_nid, hda_nid_t nid)
270 {
271 int pwr;
272
273 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
274 * thus pins could only choose converter 0 for use. Make sure the
275 * converters are in correct power state
276 */
277 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
278 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
279
280 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
281 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
282 AC_PWRST_D0);
283 msleep(40);
284 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
285 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
286 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
287 }
288 }
289
290 /* Assure the pin select the right convetor */
intel_verify_pin_cvt_connect(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin)291 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
292 struct hdmi_spec_per_pin *per_pin)
293 {
294 hda_nid_t pin_nid = per_pin->pin_nid;
295 int mux_idx, curr;
296
297 mux_idx = per_pin->mux_idx;
298 curr = snd_hda_codec_read(codec, pin_nid, 0,
299 AC_VERB_GET_CONNECT_SEL, 0);
300 if (curr != mux_idx)
301 snd_hda_codec_write_cache(codec, pin_nid, 0,
302 AC_VERB_SET_CONNECT_SEL,
303 mux_idx);
304 }
305
306 /* get the mux index for the converter of the pins
307 * converter's mux index is the same for all pins on Intel platform
308 */
intel_cvt_id_to_mux_idx(struct hdmi_spec * spec,hda_nid_t cvt_nid)309 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
310 hda_nid_t cvt_nid)
311 {
312 int i;
313
314 for (i = 0; i < spec->num_cvts; i++)
315 if (spec->cvt_nids[i] == cvt_nid)
316 return i;
317 return -EINVAL;
318 }
319
320 /* Intel HDMI workaround to fix audio routing issue:
321 * For some Intel display codecs, pins share the same connection list.
322 * So a conveter can be selected by multiple pins and playback on any of these
323 * pins will generate sound on the external display, because audio flows from
324 * the same converter to the display pipeline. Also muting one pin may make
325 * other pins have no sound output.
326 * So this function assures that an assigned converter for a pin is not selected
327 * by any other pins.
328 */
intel_not_share_assigned_cvt(struct hda_codec * codec,hda_nid_t pin_nid,int dev_id,int mux_idx)329 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
330 hda_nid_t pin_nid,
331 int dev_id, int mux_idx)
332 {
333 struct hdmi_spec *spec = codec->spec;
334 hda_nid_t nid;
335 int cvt_idx, curr;
336 struct hdmi_spec_per_cvt *per_cvt;
337 struct hdmi_spec_per_pin *per_pin;
338 int pin_idx;
339
340 /* configure the pins connections */
341 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
342 int dev_id_saved;
343 int dev_num;
344
345 per_pin = get_pin(spec, pin_idx);
346 /*
347 * pin not connected to monitor
348 * no need to operate on it
349 */
350 if (!per_pin->pcm)
351 continue;
352
353 if ((per_pin->pin_nid == pin_nid) &&
354 (per_pin->dev_id == dev_id))
355 continue;
356
357 /*
358 * if per_pin->dev_id >= dev_num,
359 * snd_hda_get_dev_select() will fail,
360 * and the following operation is unpredictable.
361 * So skip this situation.
362 */
363 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
364 if (per_pin->dev_id >= dev_num)
365 continue;
366
367 nid = per_pin->pin_nid;
368
369 /*
370 * Calling this function should not impact
371 * on the device entry selection
372 * So let's save the dev id for each pin,
373 * and restore it when return
374 */
375 dev_id_saved = snd_hda_get_dev_select(codec, nid);
376 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
377 curr = snd_hda_codec_read(codec, nid, 0,
378 AC_VERB_GET_CONNECT_SEL, 0);
379 if (curr != mux_idx) {
380 snd_hda_set_dev_select(codec, nid, dev_id_saved);
381 continue;
382 }
383
384
385 /* choose an unassigned converter. The conveters in the
386 * connection list are in the same order as in the codec.
387 */
388 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
389 per_cvt = get_cvt(spec, cvt_idx);
390 if (!per_cvt->assigned) {
391 codec_dbg(codec,
392 "choose cvt %d for pin NID 0x%x\n",
393 cvt_idx, nid);
394 snd_hda_codec_write_cache(codec, nid, 0,
395 AC_VERB_SET_CONNECT_SEL,
396 cvt_idx);
397 break;
398 }
399 }
400 snd_hda_set_dev_select(codec, nid, dev_id_saved);
401 }
402 }
403
404 /* A wrapper of intel_not_share_asigned_cvt() */
intel_not_share_assigned_cvt_nid(struct hda_codec * codec,hda_nid_t pin_nid,int dev_id,hda_nid_t cvt_nid)405 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
406 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
407 {
408 int mux_idx;
409 struct hdmi_spec *spec = codec->spec;
410
411 /* On Intel platform, the mapping of converter nid to
412 * mux index of the pins are always the same.
413 * The pin nid may be 0, this means all pins will not
414 * share the converter.
415 */
416 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
417 if (mux_idx >= 0)
418 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
419 }
420
421 /* setup_stream ops override for HSW+ */
i915_hsw_setup_stream(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid,int dev_id,u32 stream_tag,int format)422 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
423 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
424 int format)
425 {
426 struct hdmi_spec *spec = codec->spec;
427 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
428 struct hdmi_spec_per_pin *per_pin;
429 int res;
430
431 if (pin_idx < 0)
432 per_pin = NULL;
433 else
434 per_pin = get_pin(spec, pin_idx);
435
436 haswell_verify_D0(codec, cvt_nid, pin_nid);
437
438 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
439 silent_stream_set_kae(codec, per_pin, false);
440 /* wait for pending transfers in codec to clear */
441 usleep_range(100, 200);
442 }
443
444 res = snd_hda_hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
445 stream_tag, format);
446
447 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
448 usleep_range(100, 200);
449 silent_stream_set_kae(codec, per_pin, true);
450 }
451
452 return res;
453 }
454
455 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
i915_pin_cvt_fixup(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,hda_nid_t cvt_nid)456 static void i915_pin_cvt_fixup(struct hda_codec *codec,
457 struct hdmi_spec_per_pin *per_pin,
458 hda_nid_t cvt_nid)
459 {
460 if (per_pin) {
461 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
462 snd_hda_set_dev_select(codec, per_pin->pin_nid,
463 per_pin->dev_id);
464 intel_verify_pin_cvt_connect(codec, per_pin);
465 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
466 per_pin->dev_id, per_pin->mux_idx);
467 } else {
468 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
469 }
470 }
471
i915_hdmi_suspend(struct hda_codec * codec)472 static int i915_hdmi_suspend(struct hda_codec *codec)
473 {
474 struct hdmi_spec *spec = codec->spec;
475 bool silent_streams = false;
476 int pin_idx, res;
477
478 res = snd_hda_hdmi_generic_suspend(codec);
479 if (spec->silent_stream_type != SILENT_STREAM_KAE)
480 return res;
481
482 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
483 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
484
485 if (per_pin->silent_stream) {
486 silent_streams = true;
487 break;
488 }
489 }
490
491 if (silent_streams) {
492 /*
493 * stream-id should remain programmed when codec goes
494 * to runtime suspend
495 */
496 codec->no_stream_clean_at_suspend = 1;
497
498 /*
499 * the system might go to S3, in which case keep-alive
500 * must be reprogrammed upon resume
501 */
502 codec->forced_resume = 1;
503
504 codec_dbg(codec, "HDMI: KAE active at suspend\n");
505 } else {
506 codec->no_stream_clean_at_suspend = 0;
507 codec->forced_resume = 0;
508 }
509
510 return res;
511 }
512
i915_hdmi_resume(struct hda_codec * codec)513 static int i915_hdmi_resume(struct hda_codec *codec)
514 {
515 struct hdmi_spec *spec = codec->spec;
516 int pin_idx, res;
517
518 res = snd_hda_hdmi_generic_resume(codec);
519 if (spec->silent_stream_type != SILENT_STREAM_KAE)
520 return res;
521
522 /* KAE not programmed at suspend, nothing to do here */
523 if (!codec->no_stream_clean_at_suspend)
524 return res;
525
526 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
527 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
528
529 /*
530 * If system was in suspend with monitor connected,
531 * the codec setting may have been lost. Re-enable
532 * keep-alive.
533 */
534 if (per_pin->silent_stream) {
535 unsigned int param;
536
537 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
538 AC_VERB_GET_CONV, 0);
539 if (!param) {
540 codec_dbg(codec, "HDMI: KAE: restore stream id\n");
541 silent_stream_enable_i915(codec, per_pin);
542 }
543
544 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
545 AC_VERB_GET_DIGI_CONVERT_1, 0);
546 if (!(param & (AC_DIG3_KAE << 16))) {
547 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
548 silent_stream_set_kae(codec, per_pin, true);
549 }
550 }
551 }
552
553 return res;
554 }
555
556 /* precondition and allocation for Intel codecs */
alloc_intel_hdmi(struct hda_codec * codec)557 static int alloc_intel_hdmi(struct hda_codec *codec)
558 {
559 /* requires i915 binding */
560 if (!codec->bus->core.audio_component) {
561 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
562 /* set probe_id here to prevent generic fallback binding */
563 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
564 return -ENODEV;
565 }
566
567 return snd_hda_hdmi_generic_alloc(codec);
568 }
569
570 /* parse and post-process for Intel codecs */
parse_intel_hdmi(struct hda_codec * codec)571 static int parse_intel_hdmi(struct hda_codec *codec)
572 {
573 int err, retries = 3;
574
575 do {
576 err = snd_hda_hdmi_parse_codec(codec);
577 } while (err < 0 && retries--);
578
579 if (err < 0)
580 return err;
581
582 snd_hda_hdmi_generic_init_per_pins(codec);
583 register_i915_notifier(codec);
584 return 0;
585 }
586
587 /* Intel Haswell and onwards; audio component with eld notifier */
intel_hsw_common_init(struct hda_codec * codec,hda_nid_t vendor_nid,const int * port_map,int port_num,int dev_num,bool send_silent_stream)588 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
589 const int *port_map, int port_num, int dev_num,
590 bool send_silent_stream)
591 {
592 struct hdmi_spec *spec;
593
594 spec = codec->spec;
595 codec->dp_mst = true;
596 spec->vendor_nid = vendor_nid;
597 spec->port_map = port_map;
598 spec->port_num = port_num;
599 spec->intel_hsw_fixup = true;
600 spec->dev_num = dev_num;
601
602 intel_haswell_enable_all_pins(codec, true);
603 intel_haswell_fixup_enable_dp12(codec);
604
605 codec->display_power_control = 1;
606
607 codec->depop_delay = 0;
608 codec->auto_runtime_pm = 1;
609
610 spec->ops.setup_stream = i915_hsw_setup_stream;
611 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
612 spec->ops.silent_stream = i915_set_silent_stream;
613
614 /*
615 * Enable silent stream feature, if it is enabled via
616 * module param or Kconfig option
617 */
618 if (send_silent_stream)
619 spec->silent_stream_type = SILENT_STREAM_I915;
620
621 return parse_intel_hdmi(codec);
622 }
623
probe_i915_hsw_hdmi(struct hda_codec * codec)624 static int probe_i915_hsw_hdmi(struct hda_codec *codec)
625 {
626 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
627 enable_silent_stream);
628 }
629
probe_i915_glk_hdmi(struct hda_codec * codec)630 static int probe_i915_glk_hdmi(struct hda_codec *codec)
631 {
632 /*
633 * Silent stream calls audio component .get_power() from
634 * .pin_eld_notify(). On GLK this will deadlock in i915 due
635 * to the audio vs. CDCLK workaround.
636 */
637 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
638 }
639
probe_i915_icl_hdmi(struct hda_codec * codec)640 static int probe_i915_icl_hdmi(struct hda_codec *codec)
641 {
642 /*
643 * pin to port mapping table where the value indicate the pin number and
644 * the index indicate the port number.
645 */
646 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
647
648 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
649 enable_silent_stream);
650 }
651
probe_i915_tgl_hdmi(struct hda_codec * codec)652 static int probe_i915_tgl_hdmi(struct hda_codec *codec)
653 {
654 /*
655 * pin to port mapping table where the value indicate the pin number and
656 * the index indicate the port number.
657 */
658 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
659
660 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
661 enable_silent_stream);
662 }
663
probe_i915_adlp_hdmi(struct hda_codec * codec)664 static int probe_i915_adlp_hdmi(struct hda_codec *codec)
665 {
666 struct hdmi_spec *spec;
667 int res;
668
669 res = probe_i915_tgl_hdmi(codec);
670 if (!res) {
671 spec = codec->spec;
672
673 if (spec->silent_stream_type)
674 spec->silent_stream_type = SILENT_STREAM_KAE;
675 }
676
677 return res;
678 }
679
680 /* Intel Baytrail and Braswell; with eld notifier */
probe_i915_byt_hdmi(struct hda_codec * codec)681 static int probe_i915_byt_hdmi(struct hda_codec *codec)
682 {
683 struct hdmi_spec *spec;
684
685 spec = codec->spec;
686
687 /* For Valleyview/Cherryview, only the display codec is in the display
688 * power well and can use link_power ops to request/release the power.
689 */
690 codec->display_power_control = 1;
691
692 codec->depop_delay = 0;
693 codec->auto_runtime_pm = 1;
694
695 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
696
697 return parse_intel_hdmi(codec);
698 }
699
700 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
probe_i915_cpt_hdmi(struct hda_codec * codec)701 static int probe_i915_cpt_hdmi(struct hda_codec *codec)
702 {
703 return parse_intel_hdmi(codec);
704 }
705
706 /*
707 * common driver probe
708 */
intelhdmi_probe(struct hda_codec * codec,const struct hda_device_id * id)709 static int intelhdmi_probe(struct hda_codec *codec, const struct hda_device_id *id)
710 {
711 int err;
712
713 err = alloc_intel_hdmi(codec);
714 if (err < 0)
715 return err;
716
717 switch (id->driver_data) {
718 case MODEL_HSW:
719 err = probe_i915_hsw_hdmi(codec);
720 break;
721 case MODEL_GLK:
722 err = probe_i915_glk_hdmi(codec);
723 break;
724 case MODEL_ICL:
725 err = probe_i915_icl_hdmi(codec);
726 break;
727 case MODEL_TGL:
728 err = probe_i915_tgl_hdmi(codec);
729 break;
730 case MODEL_ADLP:
731 err = probe_i915_adlp_hdmi(codec);
732 break;
733 case MODEL_BYT:
734 err = probe_i915_byt_hdmi(codec);
735 break;
736 case MODEL_CPT:
737 err = probe_i915_cpt_hdmi(codec);
738 break;
739 default:
740 err = -EINVAL;
741 break;
742 }
743
744 if (err < 0) {
745 snd_hda_hdmi_generic_spec_free(codec);
746 return err;
747 }
748
749 return 0;
750 }
751
752 static const struct hda_codec_ops intelhdmi_codec_ops = {
753 .probe = intelhdmi_probe,
754 .remove = snd_hda_hdmi_generic_remove,
755 .init = snd_hda_hdmi_generic_init,
756 .build_pcms = snd_hda_hdmi_generic_build_pcms,
757 .build_controls = snd_hda_hdmi_generic_build_controls,
758 .unsol_event = snd_hda_hdmi_generic_unsol_event,
759 .suspend = i915_hdmi_suspend,
760 .resume = i915_hdmi_resume,
761 .set_power_state = haswell_set_power_state,
762 };
763
764 /*
765 * driver entries
766 */
767 static const struct hda_device_id snd_hda_id_intelhdmi[] = {
768 HDA_CODEC_ID_MODEL(0x80860054, "IbexPeak HDMI", MODEL_CPT),
769 HDA_CODEC_ID_MODEL(0x80862800, "Geminilake HDMI", MODEL_GLK),
770 HDA_CODEC_ID_MODEL(0x80862804, "IbexPeak HDMI", MODEL_CPT),
771 HDA_CODEC_ID_MODEL(0x80862805, "CougarPoint HDMI", MODEL_CPT),
772 HDA_CODEC_ID_MODEL(0x80862806, "PantherPoint HDMI", MODEL_CPT),
773 HDA_CODEC_ID_MODEL(0x80862807, "Haswell HDMI", MODEL_HSW),
774 HDA_CODEC_ID_MODEL(0x80862808, "Broadwell HDMI", MODEL_HSW),
775 HDA_CODEC_ID_MODEL(0x80862809, "Skylake HDMI", MODEL_HSW),
776 HDA_CODEC_ID_MODEL(0x8086280a, "Broxton HDMI", MODEL_HSW),
777 HDA_CODEC_ID_MODEL(0x8086280b, "Kabylake HDMI", MODEL_HSW),
778 HDA_CODEC_ID_MODEL(0x8086280c, "Cannonlake HDMI", MODEL_GLK),
779 HDA_CODEC_ID_MODEL(0x8086280d, "Geminilake HDMI", MODEL_GLK),
780 HDA_CODEC_ID_MODEL(0x8086280f, "Icelake HDMI", MODEL_ICL),
781 HDA_CODEC_ID_MODEL(0x80862812, "Tigerlake HDMI", MODEL_TGL),
782 HDA_CODEC_ID_MODEL(0x80862814, "DG1 HDMI", MODEL_TGL),
783 HDA_CODEC_ID_MODEL(0x80862815, "Alderlake HDMI", MODEL_TGL),
784 HDA_CODEC_ID_MODEL(0x80862816, "Rocketlake HDMI", MODEL_TGL),
785 HDA_CODEC_ID_MODEL(0x80862818, "Raptorlake HDMI", MODEL_TGL),
786 HDA_CODEC_ID_MODEL(0x80862819, "DG2 HDMI", MODEL_TGL),
787 HDA_CODEC_ID_MODEL(0x8086281a, "Jasperlake HDMI", MODEL_ICL),
788 HDA_CODEC_ID_MODEL(0x8086281b, "Elkhartlake HDMI", MODEL_ICL),
789 HDA_CODEC_ID_MODEL(0x8086281c, "Alderlake-P HDMI", MODEL_ADLP),
790 HDA_CODEC_ID_MODEL(0x8086281d, "Meteor Lake HDMI", MODEL_ADLP),
791 HDA_CODEC_ID_MODEL(0x8086281e, "Battlemage HDMI", MODEL_ADLP),
792 HDA_CODEC_ID_MODEL(0x8086281f, "Raptor Lake P HDMI", MODEL_ADLP),
793 HDA_CODEC_ID_MODEL(0x80862820, "Lunar Lake HDMI", MODEL_ADLP),
794 HDA_CODEC_ID_MODEL(0x80862822, "Panther Lake HDMI", MODEL_ADLP),
795 HDA_CODEC_ID_MODEL(0x80862823, "Wildcat Lake HDMI", MODEL_ADLP),
796 HDA_CODEC_ID_MODEL(0x80862882, "Valleyview2 HDMI", MODEL_BYT),
797 HDA_CODEC_ID_MODEL(0x80862883, "Braswell HDMI", MODEL_BYT),
798 {} /* terminator */
799 };
800 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_intelhdmi);
801
802 MODULE_LICENSE("GPL");
803 MODULE_DESCRIPTION("Intel HDMI HD-audio codec");
804 MODULE_IMPORT_NS("SND_HDA_CODEC_HDMI");
805
806 static struct hda_codec_driver intelhdmi_driver = {
807 .id = snd_hda_id_intelhdmi,
808 .ops = &intelhdmi_codec_ops,
809 };
810
811 module_hda_codec_driver(intelhdmi_driver);
812