1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/cpumask.h>
4 #include <linux/gpio/driver.h>
5 #include <linux/gpio/generic.h>
6 #include <linux/irq.h>
7 #include <linux/minmax.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/property.h>
11
12 /*
13 * Total register block size is 0x1C for one bank of four ports (A, B, C, D).
14 * An optional second bank, with ports E, F, G, and H, may be present, starting
15 * at register offset 0x1C.
16 */
17
18 /*
19 * Pin select: (0) "normal", (1) "dedicate peripheral"
20 * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits
21 * in the peripheral registers.
22 */
23 #define REALTEK_GPIO_REG_CNR 0x00
24 /* Clear bit (0) for input, set bit (1) for output */
25 #define REALTEK_GPIO_REG_DIR 0x08
26 #define REALTEK_GPIO_REG_DATA 0x0C
27 /* Read bit for IRQ status, write 1 to clear IRQ */
28 #define REALTEK_GPIO_REG_ISR 0x10
29 /* Two bits per GPIO in IMR registers */
30 #define REALTEK_GPIO_REG_IMR 0x14
31 #define REALTEK_GPIO_REG_IMR_AB 0x14
32 #define REALTEK_GPIO_REG_IMR_CD 0x18
33 #define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0)
34 #define REALTEK_GPIO_IRQ_EDGE_FALLING 1
35 #define REALTEK_GPIO_IRQ_EDGE_RISING 2
36 #define REALTEK_GPIO_IRQ_EDGE_BOTH 3
37
38 #define REALTEK_GPIO_MAX 32
39 #define REALTEK_GPIO_PORTS_PER_BANK 4
40
41 /**
42 * struct realtek_gpio_ctrl - Realtek Otto GPIO driver data
43 *
44 * @chip: Associated gpio_generic_chip instance
45 * @base: Base address of the register block for a GPIO bank
46 * @cpumask_base: Base address of the per-CPU interrupt mask registers
47 * @cpu_irq_maskable: CPUs that can receive GPIO interrupts
48 * @lock: Lock for accessing the IRQ registers and values
49 * @intr_mask: Mask for interrupts lines
50 * @intr_type: Interrupt type selection
51 * @bank_read: Read a bank setting as a single 32-bit value
52 * @bank_write: Write a bank setting as a single 32-bit value
53 * @line_imr_pos: Bit shift of an IRQ line's IMR value.
54 *
55 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
56 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
57 * a value from (to) these registers. The IMR register consists of four 16-bit
58 * port values, packed into two 32-bit registers. Use @imr_line_pos to get the
59 * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
60 * 32 overflow into the second register.
61 *
62 * Because the interrupt mask register (IMR) combines the function of IRQ type
63 * selection and masking, two extra values are stored. @intr_mask is used to
64 * mask/unmask the interrupts for a GPIO line, and @intr_type is used to store
65 * the selected interrupt types. The logical AND of these values is written to
66 * IMR on changes.
67 */
68 struct realtek_gpio_ctrl {
69 struct gpio_generic_chip chip;
70 void __iomem *base;
71 void __iomem *cpumask_base;
72 struct cpumask cpu_irq_maskable;
73 raw_spinlock_t lock;
74 u8 intr_mask[REALTEK_GPIO_MAX];
75 u8 intr_type[REALTEK_GPIO_MAX];
76 u32 (*bank_read)(void __iomem *reg);
77 void (*bank_write)(void __iomem *reg, u32 value);
78 unsigned int (*line_imr_pos)(unsigned int line);
79 };
80
81 /* Expand with more flags as devices with other quirks are added */
82 enum realtek_gpio_flags {
83 /*
84 * Allow disabling interrupts, for cases where the port order is
85 * unknown. This may result in a port mismatch between ISR and IMR.
86 * An interrupt would appear to come from a different line than the
87 * line the IRQ handler was assigned to, causing uncaught interrupts.
88 */
89 GPIO_INTERRUPTS_DISABLED = BIT(0),
90 /*
91 * Port order is reversed, meaning DCBA register layout for 1-bit
92 * fields, and [BA, DC] for 2-bit fields.
93 */
94 GPIO_PORTS_REVERSED = BIT(1),
95 /*
96 * Interrupts can be enabled per cpu. This requires a secondary IO
97 * range, where the per-cpu enable masks are located.
98 */
99 GPIO_INTERRUPTS_PER_CPU = BIT(2),
100 };
101
irq_data_to_ctrl(struct irq_data * data)102 static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
103 {
104 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
105
106 return container_of(to_gpio_generic_chip(gc), struct realtek_gpio_ctrl, chip);
107 }
108
109 /*
110 * Normal port order register access
111 *
112 * Port information is stored with the first port at offset 0, followed by the
113 * second, etc. Most registers store one bit per GPIO and use a u8 value per
114 * port. The two interrupt mask registers store two bits per GPIO, so use u16
115 * values.
116 */
realtek_gpio_bank_read_swapped(void __iomem * reg)117 static u32 realtek_gpio_bank_read_swapped(void __iomem *reg)
118 {
119 return ioread32be(reg);
120 }
121
realtek_gpio_bank_write_swapped(void __iomem * reg,u32 value)122 static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value)
123 {
124 iowrite32be(value, reg);
125 }
126
realtek_gpio_line_imr_pos_swapped(unsigned int line)127 static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line)
128 {
129 unsigned int port_pin = line % 8;
130 unsigned int port = line / 8;
131
132 return 2 * (8 * (port ^ 1) + port_pin);
133 }
134
135 /*
136 * Reversed port order register access
137 *
138 * For registers with one bit per GPIO, all ports are stored as u8-s in one
139 * register in reversed order. The two interrupt mask registers store two bits
140 * per GPIO, so use u16 values. The first register contains ports 1 and 0, the
141 * second ports 3 and 2.
142 */
realtek_gpio_bank_read(void __iomem * reg)143 static u32 realtek_gpio_bank_read(void __iomem *reg)
144 {
145 return ioread32(reg);
146 }
147
realtek_gpio_bank_write(void __iomem * reg,u32 value)148 static void realtek_gpio_bank_write(void __iomem *reg, u32 value)
149 {
150 iowrite32(value, reg);
151 }
152
realtek_gpio_line_imr_pos(unsigned int line)153 static unsigned int realtek_gpio_line_imr_pos(unsigned int line)
154 {
155 return 2 * line;
156 }
157
realtek_gpio_clear_isr(struct realtek_gpio_ctrl * ctrl,u32 mask)158 static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask)
159 {
160 ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask);
161 }
162
realtek_gpio_read_isr(struct realtek_gpio_ctrl * ctrl)163 static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl)
164 {
165 return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR);
166 }
167
168 /* Set the rising and falling edge mask bits for a GPIO pin */
realtek_gpio_update_line_imr(struct realtek_gpio_ctrl * ctrl,unsigned int line)169 static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line)
170 {
171 void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR;
172 unsigned int line_shift = ctrl->line_imr_pos(line);
173 unsigned int shift = line_shift % 32;
174 u32 irq_type = ctrl->intr_type[line];
175 u32 irq_mask = ctrl->intr_mask[line];
176 u32 reg_val;
177
178 reg += 4 * (line_shift / 32);
179 reg_val = ioread32(reg);
180 reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift);
181 reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift;
182 iowrite32(reg_val, reg);
183 }
184
realtek_gpio_irq_ack(struct irq_data * data)185 static void realtek_gpio_irq_ack(struct irq_data *data)
186 {
187 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
188 irq_hw_number_t line = irqd_to_hwirq(data);
189
190 realtek_gpio_clear_isr(ctrl, BIT(line));
191 }
192
realtek_gpio_irq_unmask(struct irq_data * data)193 static void realtek_gpio_irq_unmask(struct irq_data *data)
194 {
195 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
196 unsigned int line = irqd_to_hwirq(data);
197 unsigned long flags;
198
199 gpiochip_enable_irq(&ctrl->chip.gc, line);
200
201 raw_spin_lock_irqsave(&ctrl->lock, flags);
202 ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK;
203 realtek_gpio_update_line_imr(ctrl, line);
204 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
205 }
206
realtek_gpio_irq_mask(struct irq_data * data)207 static void realtek_gpio_irq_mask(struct irq_data *data)
208 {
209 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
210 unsigned int line = irqd_to_hwirq(data);
211 unsigned long flags;
212
213 raw_spin_lock_irqsave(&ctrl->lock, flags);
214 ctrl->intr_mask[line] = 0;
215 realtek_gpio_update_line_imr(ctrl, line);
216 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
217
218 gpiochip_disable_irq(&ctrl->chip.gc, line);
219 }
220
realtek_gpio_irq_set_type(struct irq_data * data,unsigned int flow_type)221 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
222 {
223 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
224 unsigned int line = irqd_to_hwirq(data);
225 unsigned long flags;
226 u8 type;
227
228 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
229 case IRQ_TYPE_EDGE_FALLING:
230 type = REALTEK_GPIO_IRQ_EDGE_FALLING;
231 break;
232 case IRQ_TYPE_EDGE_RISING:
233 type = REALTEK_GPIO_IRQ_EDGE_RISING;
234 break;
235 case IRQ_TYPE_EDGE_BOTH:
236 type = REALTEK_GPIO_IRQ_EDGE_BOTH;
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 irq_set_handler_locked(data, handle_edge_irq);
243
244 raw_spin_lock_irqsave(&ctrl->lock, flags);
245 ctrl->intr_type[line] = type;
246 realtek_gpio_update_line_imr(ctrl, line);
247 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
248
249 return 0;
250 }
251
realtek_gpio_irq_handler(struct irq_desc * desc)252 static void realtek_gpio_irq_handler(struct irq_desc *desc)
253 {
254 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
255 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
256 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
257 unsigned long status;
258 int offset;
259
260 chained_irq_enter(irq_chip, desc);
261
262 status = realtek_gpio_read_isr(ctrl);
263 for_each_set_bit(offset, &status, gc->ngpio)
264 generic_handle_domain_irq(gc->irq.domain, offset);
265
266 chained_irq_exit(irq_chip, desc);
267 }
268
realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl * ctrl,int cpu)269 static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu)
270 {
271 return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu;
272 }
273
realtek_gpio_irq_set_affinity(struct irq_data * data,const struct cpumask * dest,bool force)274 static int realtek_gpio_irq_set_affinity(struct irq_data *data,
275 const struct cpumask *dest, bool force)
276 {
277 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
278 unsigned int line = irqd_to_hwirq(data);
279 void __iomem *irq_cpu_mask;
280 unsigned long flags;
281 int cpu;
282 u32 v;
283
284 if (!ctrl->cpumask_base)
285 return -ENXIO;
286
287 raw_spin_lock_irqsave(&ctrl->lock, flags);
288
289 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) {
290 irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu);
291 v = ctrl->bank_read(irq_cpu_mask);
292
293 if (cpumask_test_cpu(cpu, dest))
294 v |= BIT(line);
295 else
296 v &= ~BIT(line);
297
298 ctrl->bank_write(irq_cpu_mask, v);
299 }
300
301 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
302
303 irq_data_update_effective_affinity(data, dest);
304
305 return 0;
306 }
307
realtek_gpio_irq_init(struct gpio_chip * gc)308 static int realtek_gpio_irq_init(struct gpio_chip *gc)
309 {
310 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
311 u32 mask_all = GENMASK(gc->ngpio - 1, 0);
312 unsigned int line;
313 int cpu;
314
315 for (line = 0; line < gc->ngpio; line++)
316 realtek_gpio_update_line_imr(ctrl, line);
317
318 realtek_gpio_clear_isr(ctrl, mask_all);
319
320 for_each_cpu(cpu, &ctrl->cpu_irq_maskable)
321 ctrl->bank_write(realtek_gpio_irq_cpu_mask(ctrl, cpu), mask_all);
322
323 return 0;
324 }
325
326 static const struct irq_chip realtek_gpio_irq_chip = {
327 .name = "realtek-otto-gpio",
328 .irq_ack = realtek_gpio_irq_ack,
329 .irq_mask = realtek_gpio_irq_mask,
330 .irq_unmask = realtek_gpio_irq_unmask,
331 .irq_set_type = realtek_gpio_irq_set_type,
332 .irq_set_affinity = realtek_gpio_irq_set_affinity,
333 .flags = IRQCHIP_IMMUTABLE,
334 GPIOCHIP_IRQ_RESOURCE_HELPERS,
335 };
336
337 static const struct of_device_id realtek_gpio_of_match[] = {
338 {
339 .compatible = "realtek,otto-gpio",
340 .data = (void *)GPIO_INTERRUPTS_DISABLED,
341 },
342 {
343 .compatible = "realtek,rtl8380-gpio",
344 },
345 {
346 .compatible = "realtek,rtl8390-gpio",
347 },
348 {
349 .compatible = "realtek,rtl9300-gpio",
350 .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)
351 },
352 {
353 .compatible = "realtek,rtl9310-gpio",
354 },
355 {
356 .compatible = "realtek,rtl9607-gpio",
357 .data = (void *)GPIO_PORTS_REVERSED,
358 },
359 {}
360 };
361 MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);
362
realtek_gpio_probe(struct platform_device * pdev)363 static int realtek_gpio_probe(struct platform_device *pdev)
364 {
365 struct gpio_generic_chip_config config;
366 struct device *dev = &pdev->dev;
367 unsigned long gen_gc_flags, dev_flags;
368 struct gpio_irq_chip *girq;
369 struct realtek_gpio_ctrl *ctrl;
370 struct resource *res;
371 u32 ngpios;
372 unsigned int nr_cpus;
373 int cpu, err, irq;
374
375 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
376 if (!ctrl)
377 return -ENOMEM;
378
379 dev_flags = (uintptr_t)device_get_match_data(dev);
380
381 ngpios = REALTEK_GPIO_MAX;
382 device_property_read_u32(dev, "ngpios", &ngpios);
383
384 if (ngpios > REALTEK_GPIO_MAX) {
385 dev_err(&pdev->dev, "invalid ngpios (max. %d)\n",
386 REALTEK_GPIO_MAX);
387 return -EINVAL;
388 }
389
390 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
391 if (IS_ERR(ctrl->base))
392 return PTR_ERR(ctrl->base);
393
394 raw_spin_lock_init(&ctrl->lock);
395
396 if (dev_flags & GPIO_PORTS_REVERSED) {
397 gen_gc_flags = 0;
398 ctrl->bank_read = realtek_gpio_bank_read;
399 ctrl->bank_write = realtek_gpio_bank_write;
400 ctrl->line_imr_pos = realtek_gpio_line_imr_pos;
401 } else {
402 gen_gc_flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
403 ctrl->bank_read = realtek_gpio_bank_read_swapped;
404 ctrl->bank_write = realtek_gpio_bank_write_swapped;
405 ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped;
406 }
407
408 config = (struct gpio_generic_chip_config) {
409 .dev = dev,
410 .sz = 4,
411 .dat = ctrl->base + REALTEK_GPIO_REG_DATA,
412 .dirout = ctrl->base + REALTEK_GPIO_REG_DIR,
413 .flags = gen_gc_flags,
414 };
415
416 err = gpio_generic_chip_init(&ctrl->chip, &config);
417 if (err) {
418 dev_err(dev, "unable to init generic GPIO");
419 return err;
420 }
421
422 ctrl->chip.gc.ngpio = ngpios;
423 ctrl->chip.gc.owner = THIS_MODULE;
424
425 irq = platform_get_irq_optional(pdev, 0);
426 if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
427 girq = &ctrl->chip.gc.irq;
428 gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip);
429 girq->default_type = IRQ_TYPE_NONE;
430 girq->handler = handle_bad_irq;
431 girq->parent_handler = realtek_gpio_irq_handler;
432 girq->num_parents = 1;
433 girq->parents = devm_kcalloc(dev, girq->num_parents,
434 sizeof(*girq->parents), GFP_KERNEL);
435 if (!girq->parents)
436 return -ENOMEM;
437 girq->parents[0] = irq;
438 girq->init_hw = realtek_gpio_irq_init;
439 }
440
441 cpumask_clear(&ctrl->cpu_irq_maskable);
442
443 if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) {
444 ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
445 if (IS_ERR(ctrl->cpumask_base))
446 return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base),
447 "missing CPU IRQ mask registers");
448
449 nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK;
450 nr_cpus = min(nr_cpus, num_present_cpus());
451
452 for (cpu = 0; cpu < nr_cpus; cpu++)
453 cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable);
454 }
455
456 return devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl);
457 }
458
459 static struct platform_driver realtek_gpio_driver = {
460 .driver = {
461 .name = "realtek-otto-gpio",
462 .of_match_table = realtek_gpio_of_match,
463 },
464 .probe = realtek_gpio_probe,
465 };
466 module_platform_driver(realtek_gpio_driver);
467
468 MODULE_DESCRIPTION("Realtek Otto GPIO support");
469 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
470 MODULE_LICENSE("GPL v2");
471