1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 4 */ 5 /* 6 * QCOM BAM DMA engine driver 7 * 8 * QCOM BAM DMA blocks are distributed amongst a number of the on-chip 9 * peripherals on the MSM 8x74. The configuration of the channels are dependent 10 * on the way they are hard wired to that specific peripheral. The peripheral 11 * device tree entries specify the configuration of each channel. 12 * 13 * The DMA controller requires the use of external memory for storage of the 14 * hardware descriptors for each channel. The descriptor FIFO is accessed as a 15 * circular buffer and operations are managed according to the offset within the 16 * FIFO. After pipe/channel reset, all of the pipe registers and internal state 17 * are back to defaults. 18 * 19 * During DMA operations, we write descriptors to the FIFO, being careful to 20 * handle wrapping and then write the last FIFO offset to that channel's 21 * P_EVNT_REG register to kick off the transaction. The P_SW_OFSTS register 22 * indicates the current FIFO offset that is being processed, so there is some 23 * indication of where the hardware is currently working. 24 */ 25 26 #include <linux/circ_buf.h> 27 #include <linux/cleanup.h> 28 #include <linux/clk.h> 29 #include <linux/device.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/init.h> 33 #include <linux/interrupt.h> 34 #include <linux/io.h> 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of_address.h> 38 #include <linux/of_dma.h> 39 #include <linux/of_irq.h> 40 #include <linux/of.h> 41 #include <linux/platform_device.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/scatterlist.h> 44 #include <linux/slab.h> 45 46 #include "../dmaengine.h" 47 #include "../virt-dma.h" 48 49 struct bam_desc_hw { 50 __le32 addr; /* Buffer physical address */ 51 __le16 size; /* Buffer size in bytes */ 52 __le16 flags; 53 }; 54 55 #define BAM_DMA_AUTOSUSPEND_DELAY 100 56 57 #define DESC_FLAG_INT BIT(15) 58 #define DESC_FLAG_EOT BIT(14) 59 #define DESC_FLAG_EOB BIT(13) 60 #define DESC_FLAG_NWD BIT(12) 61 #define DESC_FLAG_CMD BIT(11) 62 63 struct bam_async_desc { 64 struct virt_dma_desc vd; 65 66 u32 num_desc; 67 u32 xfer_len; 68 69 /* transaction flags, EOT|EOB|NWD */ 70 u16 flags; 71 72 struct bam_desc_hw *curr_desc; 73 74 /* list node for the desc in the bam_chan list of descriptors */ 75 struct list_head desc_node; 76 enum dma_transfer_direction dir; 77 size_t length; 78 struct bam_desc_hw desc[] __counted_by(num_desc); 79 }; 80 81 enum bam_reg { 82 BAM_CTRL, 83 BAM_REVISION, 84 BAM_NUM_PIPES, 85 BAM_DESC_CNT_TRSHLD, 86 BAM_IRQ_SRCS, 87 BAM_IRQ_SRCS_MSK, 88 BAM_IRQ_SRCS_UNMASKED, 89 BAM_IRQ_STTS, 90 BAM_IRQ_CLR, 91 BAM_IRQ_EN, 92 BAM_CNFG_BITS, 93 BAM_IRQ_SRCS_EE, 94 BAM_IRQ_SRCS_MSK_EE, 95 BAM_P_CTRL, 96 BAM_P_RST, 97 BAM_P_HALT, 98 BAM_P_IRQ_STTS, 99 BAM_P_IRQ_CLR, 100 BAM_P_IRQ_EN, 101 BAM_P_EVNT_DEST_ADDR, 102 BAM_P_EVNT_REG, 103 BAM_P_SW_OFSTS, 104 BAM_P_DATA_FIFO_ADDR, 105 BAM_P_DESC_FIFO_ADDR, 106 BAM_P_EVNT_GEN_TRSHLD, 107 BAM_P_FIFO_SIZES, 108 }; 109 110 struct reg_offset_data { 111 u32 base_offset; 112 unsigned int pipe_mult, evnt_mult, ee_mult; 113 }; 114 115 static const struct reg_offset_data bam_v1_3_reg_info[] = { 116 [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, 117 [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, 118 [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 }, 119 [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 }, 120 [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 }, 121 [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 }, 122 [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 }, 123 [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 }, 124 [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 }, 125 [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 }, 126 [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 }, 127 [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 }, 128 [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 }, 129 [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 }, 130 [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 }, 131 [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 }, 132 [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 }, 133 [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 }, 134 [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 }, 135 [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 }, 136 [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 }, 137 [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 }, 138 [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 }, 139 [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 }, 140 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 }, 141 [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 }, 142 }; 143 144 static const struct reg_offset_data bam_v1_4_reg_info[] = { 145 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, 146 [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, 147 [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 }, 148 [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 }, 149 [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 }, 150 [BAM_IRQ_SRCS_MSK] = { 0x0010, 0x00, 0x00, 0x00 }, 151 [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 }, 152 [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 }, 153 [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 }, 154 [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 }, 155 [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 }, 156 [BAM_IRQ_SRCS_EE] = { 0x0800, 0x00, 0x00, 0x80 }, 157 [BAM_IRQ_SRCS_MSK_EE] = { 0x0804, 0x00, 0x00, 0x80 }, 158 [BAM_P_CTRL] = { 0x1000, 0x1000, 0x00, 0x00 }, 159 [BAM_P_RST] = { 0x1004, 0x1000, 0x00, 0x00 }, 160 [BAM_P_HALT] = { 0x1008, 0x1000, 0x00, 0x00 }, 161 [BAM_P_IRQ_STTS] = { 0x1010, 0x1000, 0x00, 0x00 }, 162 [BAM_P_IRQ_CLR] = { 0x1014, 0x1000, 0x00, 0x00 }, 163 [BAM_P_IRQ_EN] = { 0x1018, 0x1000, 0x00, 0x00 }, 164 [BAM_P_EVNT_DEST_ADDR] = { 0x182C, 0x00, 0x1000, 0x00 }, 165 [BAM_P_EVNT_REG] = { 0x1818, 0x00, 0x1000, 0x00 }, 166 [BAM_P_SW_OFSTS] = { 0x1800, 0x00, 0x1000, 0x00 }, 167 [BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 }, 168 [BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 }, 169 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 }, 170 [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 }, 171 }; 172 173 static const struct reg_offset_data bam_v1_7_reg_info[] = { 174 [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, 175 [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, 176 [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 }, 177 [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 }, 178 [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 }, 179 [BAM_IRQ_SRCS_MSK] = { 0x03014, 0x00, 0x00, 0x00 }, 180 [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 }, 181 [BAM_IRQ_STTS] = { 0x00014, 0x00, 0x00, 0x00 }, 182 [BAM_IRQ_CLR] = { 0x00018, 0x00, 0x00, 0x00 }, 183 [BAM_IRQ_EN] = { 0x0001C, 0x00, 0x00, 0x00 }, 184 [BAM_CNFG_BITS] = { 0x0007C, 0x00, 0x00, 0x00 }, 185 [BAM_IRQ_SRCS_EE] = { 0x03000, 0x00, 0x00, 0x1000 }, 186 [BAM_IRQ_SRCS_MSK_EE] = { 0x03004, 0x00, 0x00, 0x1000 }, 187 [BAM_P_CTRL] = { 0x13000, 0x1000, 0x00, 0x00 }, 188 [BAM_P_RST] = { 0x13004, 0x1000, 0x00, 0x00 }, 189 [BAM_P_HALT] = { 0x13008, 0x1000, 0x00, 0x00 }, 190 [BAM_P_IRQ_STTS] = { 0x13010, 0x1000, 0x00, 0x00 }, 191 [BAM_P_IRQ_CLR] = { 0x13014, 0x1000, 0x00, 0x00 }, 192 [BAM_P_IRQ_EN] = { 0x13018, 0x1000, 0x00, 0x00 }, 193 [BAM_P_EVNT_DEST_ADDR] = { 0x1382C, 0x00, 0x1000, 0x00 }, 194 [BAM_P_EVNT_REG] = { 0x13818, 0x00, 0x1000, 0x00 }, 195 [BAM_P_SW_OFSTS] = { 0x13800, 0x00, 0x1000, 0x00 }, 196 [BAM_P_DATA_FIFO_ADDR] = { 0x13824, 0x00, 0x1000, 0x00 }, 197 [BAM_P_DESC_FIFO_ADDR] = { 0x1381C, 0x00, 0x1000, 0x00 }, 198 [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 }, 199 [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 }, 200 }; 201 202 static const struct reg_offset_data bam_v2_0_reg_info[] = { 203 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, 204 [BAM_REVISION] = { 0x1000, 0x00, 0x00, 0x00 }, 205 [BAM_NUM_PIPES] = { 0x1008, 0x00, 0x00, 0x00 }, 206 [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 }, 207 [BAM_IRQ_SRCS] = { 0x3010, 0x00, 0x00, 0x00 }, 208 [BAM_IRQ_SRCS_MSK] = { 0x3014, 0x00, 0x00, 0x00 }, 209 [BAM_IRQ_SRCS_UNMASKED] = { 0x3018, 0x00, 0x00, 0x00 }, 210 [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 }, 211 [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 }, 212 [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 }, 213 [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 }, 214 [BAM_IRQ_SRCS_EE] = { 0x3000, 0x00, 0x00, 0x1000 }, 215 [BAM_IRQ_SRCS_MSK_EE] = { 0x3004, 0x00, 0x00, 0x1000 }, 216 [BAM_P_CTRL] = { 0xC000, 0x1000, 0x00, 0x00 }, 217 [BAM_P_RST] = { 0xC004, 0x1000, 0x00, 0x00 }, 218 [BAM_P_HALT] = { 0xC008, 0x1000, 0x00, 0x00 }, 219 [BAM_P_IRQ_STTS] = { 0xC010, 0x1000, 0x00, 0x00 }, 220 [BAM_P_IRQ_CLR] = { 0xC014, 0x1000, 0x00, 0x00 }, 221 [BAM_P_IRQ_EN] = { 0xC018, 0x1000, 0x00, 0x00 }, 222 [BAM_P_EVNT_DEST_ADDR] = { 0xC82C, 0x00, 0x1000, 0x00 }, 223 [BAM_P_EVNT_REG] = { 0xC818, 0x00, 0x1000, 0x00 }, 224 [BAM_P_SW_OFSTS] = { 0xC800, 0x00, 0x1000, 0x00 }, 225 [BAM_P_DATA_FIFO_ADDR] = { 0xC824, 0x00, 0x1000, 0x00 }, 226 [BAM_P_DESC_FIFO_ADDR] = { 0xC81C, 0x00, 0x1000, 0x00 }, 227 [BAM_P_EVNT_GEN_TRSHLD] = { 0xC828, 0x00, 0x1000, 0x00 }, 228 [BAM_P_FIFO_SIZES] = { 0xC820, 0x00, 0x1000, 0x00 }, 229 }; 230 231 /* BAM CTRL */ 232 #define BAM_SW_RST BIT(0) 233 #define BAM_EN BIT(1) 234 #define BAM_EN_ACCUM BIT(4) 235 #define BAM_TESTBUS_SEL_SHIFT 5 236 #define BAM_TESTBUS_SEL_MASK 0x3F 237 #define BAM_DESC_CACHE_SEL_SHIFT 13 238 #define BAM_DESC_CACHE_SEL_MASK 0x3 239 #define BAM_CACHED_DESC_STORE BIT(15) 240 #define IBC_DISABLE BIT(16) 241 242 /* BAM REVISION */ 243 #define REVISION_SHIFT 0 244 #define REVISION_MASK 0xFF 245 #define NUM_EES_SHIFT 8 246 #define NUM_EES_MASK 0xF 247 #define CE_BUFFER_SIZE BIT(13) 248 #define AXI_ACTIVE BIT(14) 249 #define USE_VMIDMT BIT(15) 250 #define SECURED BIT(16) 251 #define BAM_HAS_NO_BYPASS BIT(17) 252 #define HIGH_FREQUENCY_BAM BIT(18) 253 #define INACTIV_TMRS_EXST BIT(19) 254 #define NUM_INACTIV_TMRS BIT(20) 255 #define DESC_CACHE_DEPTH_SHIFT 21 256 #define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT) 257 #define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT) 258 #define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT) 259 #define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT) 260 #define CMD_DESC_EN BIT(23) 261 #define INACTIV_TMR_BASE_SHIFT 24 262 #define INACTIV_TMR_BASE_MASK 0xFF 263 264 /* BAM NUM PIPES */ 265 #define BAM_NUM_PIPES_SHIFT 0 266 #define BAM_NUM_PIPES_MASK 0xFF 267 #define PERIPH_NON_PIPE_GRP_SHIFT 16 268 #define PERIPH_NON_PIP_GRP_MASK 0xFF 269 #define BAM_NON_PIPE_GRP_SHIFT 24 270 #define BAM_NON_PIPE_GRP_MASK 0xFF 271 272 /* BAM CNFG BITS */ 273 #define BAM_PIPE_CNFG BIT(2) 274 #define BAM_FULL_PIPE BIT(11) 275 #define BAM_NO_EXT_P_RST BIT(12) 276 #define BAM_IBC_DISABLE BIT(13) 277 #define BAM_SB_CLK_REQ BIT(14) 278 #define BAM_PSM_CSW_REQ BIT(15) 279 #define BAM_PSM_P_RES BIT(16) 280 #define BAM_AU_P_RES BIT(17) 281 #define BAM_SI_P_RES BIT(18) 282 #define BAM_WB_P_RES BIT(19) 283 #define BAM_WB_BLK_CSW BIT(20) 284 #define BAM_WB_CSW_ACK_IDL BIT(21) 285 #define BAM_WB_RETR_SVPNT BIT(22) 286 #define BAM_WB_DSC_AVL_P_RST BIT(23) 287 #define BAM_REG_P_EN BIT(24) 288 #define BAM_PSM_P_HD_DATA BIT(25) 289 #define BAM_AU_ACCUMED BIT(26) 290 #define BAM_CMD_ENABLE BIT(27) 291 292 #define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \ 293 BAM_NO_EXT_P_RST | \ 294 BAM_IBC_DISABLE | \ 295 BAM_SB_CLK_REQ | \ 296 BAM_PSM_CSW_REQ | \ 297 BAM_PSM_P_RES | \ 298 BAM_AU_P_RES | \ 299 BAM_SI_P_RES | \ 300 BAM_WB_P_RES | \ 301 BAM_WB_BLK_CSW | \ 302 BAM_WB_CSW_ACK_IDL | \ 303 BAM_WB_RETR_SVPNT | \ 304 BAM_WB_DSC_AVL_P_RST | \ 305 BAM_REG_P_EN | \ 306 BAM_PSM_P_HD_DATA | \ 307 BAM_AU_ACCUMED | \ 308 BAM_CMD_ENABLE) 309 310 /* PIPE CTRL */ 311 #define P_EN BIT(1) 312 #define P_DIRECTION BIT(3) 313 #define P_SYS_STRM BIT(4) 314 #define P_SYS_MODE BIT(5) 315 #define P_AUTO_EOB BIT(6) 316 #define P_AUTO_EOB_SEL_SHIFT 7 317 #define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT) 318 #define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT) 319 #define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT) 320 #define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT) 321 #define P_PREFETCH_LIMIT_SHIFT 9 322 #define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT) 323 #define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT) 324 #define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT) 325 #define P_WRITE_NWD BIT(11) 326 #define P_LOCK_GROUP_SHIFT 16 327 #define P_LOCK_GROUP_MASK 0x1F 328 329 /* BAM_DESC_CNT_TRSHLD */ 330 #define CNT_TRSHLD 0xffff 331 #define DEFAULT_CNT_THRSHLD 0x4 332 333 /* BAM_IRQ_SRCS */ 334 #define BAM_IRQ BIT(31) 335 #define P_IRQ 0x7fffffff 336 337 /* BAM_IRQ_SRCS_MSK */ 338 #define BAM_IRQ_MSK BAM_IRQ 339 #define P_IRQ_MSK P_IRQ 340 341 /* BAM_IRQ_STTS */ 342 #define BAM_TIMER_IRQ BIT(4) 343 #define BAM_EMPTY_IRQ BIT(3) 344 #define BAM_ERROR_IRQ BIT(2) 345 #define BAM_HRESP_ERR_IRQ BIT(1) 346 347 /* BAM_IRQ_CLR */ 348 #define BAM_TIMER_CLR BIT(4) 349 #define BAM_EMPTY_CLR BIT(3) 350 #define BAM_ERROR_CLR BIT(2) 351 #define BAM_HRESP_ERR_CLR BIT(1) 352 353 /* BAM_IRQ_EN */ 354 #define BAM_TIMER_EN BIT(4) 355 #define BAM_EMPTY_EN BIT(3) 356 #define BAM_ERROR_EN BIT(2) 357 #define BAM_HRESP_ERR_EN BIT(1) 358 359 /* BAM_P_IRQ_EN */ 360 #define P_PRCSD_DESC_EN BIT(0) 361 #define P_TIMER_EN BIT(1) 362 #define P_WAKE_EN BIT(2) 363 #define P_OUT_OF_DESC_EN BIT(3) 364 #define P_ERR_EN BIT(4) 365 #define P_TRNSFR_END_EN BIT(5) 366 #define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN) 367 368 /* BAM_P_SW_OFSTS */ 369 #define P_SW_OFSTS_MASK 0xffff 370 371 #define BAM_DESC_FIFO_SIZE SZ_32K 372 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1) 373 #define BAM_FIFO_SIZE (SZ_32K - 8) 374 #define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\ 375 MAX_DESCRIPTORS + 1) == 0) 376 377 struct bam_chan { 378 struct virt_dma_chan vc; 379 380 struct bam_device *bdev; 381 382 /* configuration from device tree */ 383 u32 id; 384 385 /* runtime configuration */ 386 struct dma_slave_config slave; 387 388 /* fifo storage */ 389 struct bam_desc_hw *fifo_virt; 390 dma_addr_t fifo_phys; 391 392 /* fifo markers */ 393 unsigned short head; /* start of active descriptor entries */ 394 unsigned short tail; /* end of active descriptor entries */ 395 396 unsigned int initialized; /* is the channel hw initialized? */ 397 unsigned int paused; /* is the channel paused? */ 398 unsigned int reconfigure; /* new slave config? */ 399 /* list of descriptors currently processed */ 400 struct list_head desc_list; 401 402 struct list_head node; 403 }; 404 405 static inline struct bam_chan *to_bam_chan(struct dma_chan *common) 406 { 407 return container_of(common, struct bam_chan, vc.chan); 408 } 409 410 struct bam_device { 411 void __iomem *regs; 412 struct device *dev; 413 struct dma_device common; 414 struct bam_chan *channels; 415 u32 num_channels; 416 u32 num_ees; 417 418 /* execution environment ID, from DT */ 419 u32 ee; 420 bool controlled_remotely; 421 bool powered_remotely; 422 u32 active_channels; 423 424 const struct reg_offset_data *layout; 425 426 struct clk *bamclk; 427 int irq; 428 429 /* dma start transaction tasklet */ 430 struct tasklet_struct task; 431 }; 432 433 /** 434 * bam_addr - returns BAM register address 435 * @bdev: bam device 436 * @pipe: pipe instance (ignored when register doesn't have multiple instances) 437 * @reg: register enum 438 */ 439 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe, 440 enum bam_reg reg) 441 { 442 const struct reg_offset_data r = bdev->layout[reg]; 443 444 return bdev->regs + r.base_offset + 445 r.pipe_mult * pipe + 446 r.evnt_mult * pipe + 447 r.ee_mult * bdev->ee; 448 } 449 450 /** 451 * bam_reset() - reset and initialize BAM registers 452 * @bdev: bam device 453 */ 454 static void bam_reset(struct bam_device *bdev) 455 { 456 u32 val; 457 458 /* s/w reset bam */ 459 /* after reset all pipes are disabled and idle */ 460 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); 461 val |= BAM_SW_RST; 462 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 463 val &= ~BAM_SW_RST; 464 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 465 466 /* make sure previous stores are visible before enabling BAM */ 467 wmb(); 468 469 /* enable bam */ 470 val |= BAM_EN; 471 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 472 473 /* set descriptor threshold, start with 4 bytes */ 474 writel_relaxed(DEFAULT_CNT_THRSHLD, 475 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD)); 476 477 /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */ 478 writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS)); 479 480 /* enable irqs for errors */ 481 writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN, 482 bam_addr(bdev, 0, BAM_IRQ_EN)); 483 484 /* unmask global bam interrupt */ 485 writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 486 } 487 488 /** 489 * bam_reset_channel - Reset individual BAM DMA channel 490 * @bchan: bam channel 491 * 492 * This function resets a specific BAM channel 493 */ 494 static void bam_reset_channel(struct bam_chan *bchan) 495 { 496 struct bam_device *bdev = bchan->bdev; 497 498 lockdep_assert_held(&bchan->vc.lock); 499 500 /* reset channel */ 501 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST)); 502 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST)); 503 504 /* don't allow cpu to reorder BAM register accesses done after this */ 505 wmb(); 506 507 /* make sure hw is initialized when channel is used the first time */ 508 bchan->initialized = 0; 509 } 510 511 /** 512 * bam_chan_init_hw - Initialize channel hardware 513 * @bchan: bam channel 514 * @dir: DMA transfer direction 515 * 516 * This function resets and initializes the BAM channel 517 */ 518 static void bam_chan_init_hw(struct bam_chan *bchan, 519 enum dma_transfer_direction dir) 520 { 521 struct bam_device *bdev = bchan->bdev; 522 u32 val; 523 524 /* Reset the channel to clear internal state of the FIFO */ 525 bam_reset_channel(bchan); 526 527 /* 528 * write out 8 byte aligned address. We have enough space for this 529 * because we allocated 1 more descriptor (8 bytes) than we can use 530 */ 531 writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), 532 bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR)); 533 writel_relaxed(BAM_FIFO_SIZE, 534 bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES)); 535 536 /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */ 537 writel_relaxed(P_DEFAULT_IRQS_EN, 538 bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); 539 540 /* unmask the specific pipe and EE combo */ 541 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 542 val |= BIT(bchan->id); 543 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 544 545 /* don't allow cpu to reorder the channel enable done below */ 546 wmb(); 547 548 /* set fixed direction and mode, then enable channel */ 549 val = P_EN | P_SYS_MODE; 550 if (dir == DMA_DEV_TO_MEM) 551 val |= P_DIRECTION; 552 553 writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL)); 554 555 bchan->initialized = 1; 556 557 /* init FIFO pointers */ 558 bchan->head = 0; 559 bchan->tail = 0; 560 } 561 562 /** 563 * bam_alloc_chan - Allocate channel resources for DMA channel. 564 * @chan: specified channel 565 * 566 * This function allocates the FIFO descriptor memory 567 */ 568 static int bam_alloc_chan(struct dma_chan *chan) 569 { 570 struct bam_chan *bchan = to_bam_chan(chan); 571 struct bam_device *bdev = bchan->bdev; 572 573 if (bchan->fifo_virt) 574 return 0; 575 576 /* allocate FIFO descriptor space, but only if necessary */ 577 bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE, 578 &bchan->fifo_phys, GFP_KERNEL); 579 580 if (!bchan->fifo_virt) { 581 dev_err(bdev->dev, "Failed to allocate desc fifo\n"); 582 return -ENOMEM; 583 } 584 585 if (bdev->active_channels++ == 0 && bdev->powered_remotely) 586 bam_reset(bdev); 587 588 return 0; 589 } 590 591 /** 592 * bam_free_chan - Frees dma resources associated with specific channel 593 * @chan: specified channel 594 * 595 * Free the allocated fifo descriptor memory and channel resources 596 * 597 */ 598 static void bam_free_chan(struct dma_chan *chan) 599 { 600 struct bam_chan *bchan = to_bam_chan(chan); 601 struct bam_device *bdev = bchan->bdev; 602 u32 val; 603 int ret; 604 605 ret = pm_runtime_get_sync(bdev->dev); 606 if (ret < 0) 607 return; 608 609 vchan_free_chan_resources(to_virt_chan(chan)); 610 611 if (!list_empty(&bchan->desc_list)) { 612 dev_err(bchan->bdev->dev, "Cannot free busy channel\n"); 613 goto err; 614 } 615 616 scoped_guard(spinlock_irqsave, &bchan->vc.lock) 617 bam_reset_channel(bchan); 618 619 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt, 620 bchan->fifo_phys); 621 bchan->fifo_virt = NULL; 622 623 /* mask irq for pipe/channel */ 624 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 625 val &= ~BIT(bchan->id); 626 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 627 628 /* disable irq */ 629 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); 630 631 if (--bdev->active_channels == 0 && bdev->powered_remotely) { 632 /* s/w reset bam */ 633 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); 634 val |= BAM_SW_RST; 635 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 636 } 637 638 err: 639 pm_runtime_mark_last_busy(bdev->dev); 640 pm_runtime_put_autosuspend(bdev->dev); 641 } 642 643 /** 644 * bam_slave_config - set slave configuration for channel 645 * @chan: dma channel 646 * @cfg: slave configuration 647 * 648 * Sets slave configuration for channel 649 * 650 */ 651 static int bam_slave_config(struct dma_chan *chan, 652 struct dma_slave_config *cfg) 653 { 654 struct bam_chan *bchan = to_bam_chan(chan); 655 656 guard(spinlock_irqsave)(&bchan->vc.lock); 657 658 memcpy(&bchan->slave, cfg, sizeof(*cfg)); 659 bchan->reconfigure = 1; 660 661 return 0; 662 } 663 664 /** 665 * bam_prep_slave_sg - Prep slave sg transaction 666 * 667 * @chan: dma channel 668 * @sgl: scatter gather list 669 * @sg_len: length of sg 670 * @direction: DMA transfer direction 671 * @flags: DMA flags 672 * @context: transfer context (unused) 673 */ 674 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, 675 struct scatterlist *sgl, unsigned int sg_len, 676 enum dma_transfer_direction direction, unsigned long flags, 677 void *context) 678 { 679 struct bam_chan *bchan = to_bam_chan(chan); 680 struct bam_device *bdev = bchan->bdev; 681 struct bam_async_desc *async_desc; 682 struct scatterlist *sg; 683 u32 i; 684 struct bam_desc_hw *desc; 685 unsigned int num_alloc; 686 687 if (!is_slave_direction(direction)) { 688 dev_err(bdev->dev, "invalid dma direction\n"); 689 return NULL; 690 } 691 692 /* allocate enough room to accommodate the number of entries */ 693 num_alloc = sg_nents_for_dma(sgl, sg_len, BAM_FIFO_SIZE); 694 async_desc = kzalloc_flex(*async_desc, desc, num_alloc, GFP_NOWAIT); 695 if (!async_desc) 696 return NULL; 697 698 if (flags & DMA_PREP_FENCE) 699 async_desc->flags |= DESC_FLAG_NWD; 700 701 if (flags & DMA_PREP_INTERRUPT) 702 async_desc->flags |= DESC_FLAG_EOT; 703 704 async_desc->num_desc = num_alloc; 705 async_desc->curr_desc = async_desc->desc; 706 async_desc->dir = direction; 707 708 /* fill in temporary descriptors */ 709 desc = async_desc->desc; 710 for_each_sg(sgl, sg, sg_len, i) { 711 unsigned int remainder = sg_dma_len(sg); 712 unsigned int curr_offset = 0; 713 714 do { 715 if (flags & DMA_PREP_CMD) 716 desc->flags |= cpu_to_le16(DESC_FLAG_CMD); 717 718 desc->addr = cpu_to_le32(sg_dma_address(sg) + 719 curr_offset); 720 721 if (remainder > BAM_FIFO_SIZE) { 722 desc->size = cpu_to_le16(BAM_FIFO_SIZE); 723 remainder -= BAM_FIFO_SIZE; 724 curr_offset += BAM_FIFO_SIZE; 725 } else { 726 desc->size = cpu_to_le16(remainder); 727 remainder = 0; 728 } 729 730 async_desc->length += le16_to_cpu(desc->size); 731 desc++; 732 } while (remainder > 0); 733 } 734 735 return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags); 736 } 737 738 /** 739 * bam_dma_terminate_all - terminate all transactions on a channel 740 * @chan: bam dma channel 741 * 742 * Dequeues and frees all transactions 743 * No callbacks are done 744 * 745 */ 746 static int bam_dma_terminate_all(struct dma_chan *chan) 747 { 748 struct bam_chan *bchan = to_bam_chan(chan); 749 struct bam_async_desc *async_desc, *tmp; 750 LIST_HEAD(head); 751 752 /* remove all transactions, including active transaction */ 753 scoped_guard(spinlock_irqsave, &bchan->vc.lock) { 754 /* 755 * If we have transactions queued, then some might be committed to the 756 * hardware in the desc fifo. The only way to reset the desc fifo is 757 * to do a hardware reset (either by pipe or the entire block). 758 * bam_chan_init_hw() will trigger a pipe reset, and also reinit the 759 * pipe. If the pipe is left disabled (default state after pipe reset) 760 * and is accessed by a connected hardware engine, a fatal error in 761 * the BAM will occur. There is a small window where this could happen 762 * with bam_chan_init_hw(), but it is assumed that the caller has 763 * stopped activity on any attached hardware engine. Make sure to do 764 * this first so that the BAM hardware doesn't cause memory corruption 765 * by accessing freed resources. 766 */ 767 if (!list_empty(&bchan->desc_list)) { 768 async_desc = list_first_entry(&bchan->desc_list, 769 struct bam_async_desc, desc_node); 770 bam_chan_init_hw(bchan, async_desc->dir); 771 } 772 773 list_for_each_entry_safe(async_desc, tmp, 774 &bchan->desc_list, desc_node) { 775 list_add(&async_desc->vd.node, &bchan->vc.desc_issued); 776 list_del(&async_desc->desc_node); 777 } 778 779 vchan_get_all_descriptors(&bchan->vc, &head); 780 } 781 782 vchan_dma_desc_free_list(&bchan->vc, &head); 783 784 return 0; 785 } 786 787 /** 788 * bam_pause - Pause DMA channel 789 * @chan: dma channel 790 * 791 */ 792 static int bam_pause(struct dma_chan *chan) 793 { 794 struct bam_chan *bchan = to_bam_chan(chan); 795 struct bam_device *bdev = bchan->bdev; 796 int ret; 797 798 ret = pm_runtime_get_sync(bdev->dev); 799 if (ret < 0) 800 return ret; 801 802 scoped_guard(spinlock_irqsave, &bchan->vc.lock) { 803 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT)); 804 bchan->paused = 1; 805 } 806 pm_runtime_mark_last_busy(bdev->dev); 807 pm_runtime_put_autosuspend(bdev->dev); 808 809 return 0; 810 } 811 812 /** 813 * bam_resume - Resume DMA channel operations 814 * @chan: dma channel 815 * 816 */ 817 static int bam_resume(struct dma_chan *chan) 818 { 819 struct bam_chan *bchan = to_bam_chan(chan); 820 struct bam_device *bdev = bchan->bdev; 821 int ret; 822 823 ret = pm_runtime_get_sync(bdev->dev); 824 if (ret < 0) 825 return ret; 826 827 scoped_guard(spinlock_irqsave, &bchan->vc.lock) { 828 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT)); 829 bchan->paused = 0; 830 } 831 pm_runtime_mark_last_busy(bdev->dev); 832 pm_runtime_put_autosuspend(bdev->dev); 833 834 return 0; 835 } 836 837 /** 838 * process_channel_irqs - processes the channel interrupts 839 * @bdev: bam controller 840 * 841 * This function processes the channel interrupts 842 * 843 */ 844 static u32 process_channel_irqs(struct bam_device *bdev) 845 { 846 u32 i, srcs, pipe_stts, offset, avail; 847 struct bam_async_desc *async_desc, *tmp; 848 849 srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE)); 850 851 /* return early if no pipe/channel interrupts are present */ 852 if (!(srcs & P_IRQ)) 853 return srcs; 854 855 for (i = 0; i < bdev->num_channels; i++) { 856 struct bam_chan *bchan = &bdev->channels[i]; 857 858 if (!(srcs & BIT(i))) 859 continue; 860 861 /* clear pipe irq */ 862 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS)); 863 864 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR)); 865 866 guard(spinlock_irqsave)(&bchan->vc.lock); 867 868 offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) & 869 P_SW_OFSTS_MASK; 870 offset /= sizeof(struct bam_desc_hw); 871 872 /* Number of bytes available to read */ 873 avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1); 874 875 if (offset < bchan->head) 876 avail--; 877 878 list_for_each_entry_safe(async_desc, tmp, 879 &bchan->desc_list, desc_node) { 880 /* Not enough data to read */ 881 if (avail < async_desc->xfer_len) 882 break; 883 884 /* manage FIFO */ 885 bchan->head += async_desc->xfer_len; 886 bchan->head %= MAX_DESCRIPTORS; 887 888 async_desc->num_desc -= async_desc->xfer_len; 889 async_desc->curr_desc += async_desc->xfer_len; 890 avail -= async_desc->xfer_len; 891 892 /* 893 * if complete, process cookie. Otherwise 894 * push back to front of desc_issued so that 895 * it gets restarted by the tasklet 896 */ 897 if (!async_desc->num_desc) { 898 vchan_cookie_complete(&async_desc->vd); 899 } else { 900 list_add(&async_desc->vd.node, 901 &bchan->vc.desc_issued); 902 } 903 list_del(&async_desc->desc_node); 904 } 905 } 906 907 return srcs; 908 } 909 910 /** 911 * bam_dma_irq - irq handler for bam controller 912 * @irq: IRQ of interrupt 913 * @data: callback data 914 * 915 * IRQ handler for the bam controller 916 */ 917 static irqreturn_t bam_dma_irq(int irq, void *data) 918 { 919 struct bam_device *bdev = data; 920 u32 clr_mask = 0, srcs = 0; 921 int ret; 922 923 srcs |= process_channel_irqs(bdev); 924 925 /* kick off tasklet to start next dma transfer */ 926 if (srcs & P_IRQ) 927 tasklet_schedule(&bdev->task); 928 929 ret = pm_runtime_get_sync(bdev->dev); 930 if (ret < 0) 931 return IRQ_NONE; 932 933 if (srcs & BAM_IRQ) { 934 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); 935 936 /* 937 * don't allow reorder of the various accesses to the BAM 938 * registers 939 */ 940 mb(); 941 942 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); 943 } 944 945 pm_runtime_mark_last_busy(bdev->dev); 946 pm_runtime_put_autosuspend(bdev->dev); 947 948 return IRQ_HANDLED; 949 } 950 951 /** 952 * bam_tx_status - returns status of transaction 953 * @chan: dma channel 954 * @cookie: transaction cookie 955 * @txstate: DMA transaction state 956 * 957 * Return status of dma transaction 958 */ 959 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 960 struct dma_tx_state *txstate) 961 { 962 struct bam_chan *bchan = to_bam_chan(chan); 963 struct bam_async_desc *async_desc; 964 struct virt_dma_desc *vd; 965 int ret; 966 size_t residue = 0; 967 unsigned int i; 968 969 ret = dma_cookie_status(chan, cookie, txstate); 970 if (ret == DMA_COMPLETE) 971 return ret; 972 973 if (!txstate) 974 return bchan->paused ? DMA_PAUSED : ret; 975 976 scoped_guard(spinlock_irqsave, &bchan->vc.lock) { 977 vd = vchan_find_desc(&bchan->vc, cookie); 978 if (vd) { 979 residue = container_of(vd, struct bam_async_desc, vd)->length; 980 } else { 981 list_for_each_entry(async_desc, &bchan->desc_list, desc_node) { 982 if (async_desc->vd.tx.cookie != cookie) 983 continue; 984 985 for (i = 0; i < async_desc->num_desc; i++) 986 residue += le16_to_cpu( 987 async_desc->curr_desc[i].size); 988 } 989 } 990 } 991 992 dma_set_residue(txstate, residue); 993 994 if (ret == DMA_IN_PROGRESS && bchan->paused) 995 ret = DMA_PAUSED; 996 997 return ret; 998 } 999 1000 /** 1001 * bam_apply_new_config 1002 * @bchan: bam dma channel 1003 * @dir: DMA direction 1004 */ 1005 static void bam_apply_new_config(struct bam_chan *bchan, 1006 enum dma_transfer_direction dir) 1007 { 1008 struct bam_device *bdev = bchan->bdev; 1009 u32 maxburst; 1010 1011 if (!bdev->controlled_remotely) { 1012 if (dir == DMA_DEV_TO_MEM) 1013 maxburst = bchan->slave.src_maxburst; 1014 else 1015 maxburst = bchan->slave.dst_maxburst; 1016 1017 writel_relaxed(maxburst, 1018 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD)); 1019 } 1020 1021 bchan->reconfigure = 0; 1022 } 1023 1024 /** 1025 * bam_start_dma - start next transaction 1026 * @bchan: bam dma channel 1027 */ 1028 static void bam_start_dma(struct bam_chan *bchan) 1029 { 1030 struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc); 1031 struct bam_device *bdev = bchan->bdev; 1032 struct bam_async_desc *async_desc = NULL; 1033 struct bam_desc_hw *desc; 1034 struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt, 1035 sizeof(struct bam_desc_hw)); 1036 int ret; 1037 unsigned int avail; 1038 struct dmaengine_desc_callback cb; 1039 1040 lockdep_assert_held(&bchan->vc.lock); 1041 1042 if (!vd) 1043 return; 1044 1045 ret = pm_runtime_get_sync(bdev->dev); 1046 if (ret < 0) 1047 return; 1048 1049 while (vd && !IS_BUSY(bchan)) { 1050 list_del(&vd->node); 1051 1052 async_desc = container_of(vd, struct bam_async_desc, vd); 1053 1054 /* on first use, initialize the channel hardware */ 1055 if (!bchan->initialized) 1056 bam_chan_init_hw(bchan, async_desc->dir); 1057 1058 /* apply new slave config changes, if necessary */ 1059 if (bchan->reconfigure) 1060 bam_apply_new_config(bchan, async_desc->dir); 1061 1062 desc = async_desc->curr_desc; 1063 avail = CIRC_SPACE(bchan->tail, bchan->head, 1064 MAX_DESCRIPTORS + 1); 1065 1066 if (async_desc->num_desc > avail) 1067 async_desc->xfer_len = avail; 1068 else 1069 async_desc->xfer_len = async_desc->num_desc; 1070 1071 /* set any special flags on the last descriptor */ 1072 if (async_desc->num_desc == async_desc->xfer_len) 1073 desc[async_desc->xfer_len - 1].flags |= 1074 cpu_to_le16(async_desc->flags); 1075 1076 vd = vchan_next_desc(&bchan->vc); 1077 1078 dmaengine_desc_get_callback(&async_desc->vd.tx, &cb); 1079 1080 /* 1081 * An interrupt is generated at this desc, if 1082 * - FIFO is FULL. 1083 * - No more descriptors to add. 1084 * - If a callback completion was requested for this DESC, 1085 * In this case, BAM will deliver the completion callback 1086 * for this desc and continue processing the next desc. 1087 */ 1088 if (((avail <= async_desc->xfer_len) || !vd || 1089 dmaengine_desc_callback_valid(&cb)) && 1090 !(async_desc->flags & DESC_FLAG_EOT)) 1091 desc[async_desc->xfer_len - 1].flags |= 1092 cpu_to_le16(DESC_FLAG_INT); 1093 1094 if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) { 1095 u32 partial = MAX_DESCRIPTORS - bchan->tail; 1096 1097 memcpy(&fifo[bchan->tail], desc, 1098 partial * sizeof(struct bam_desc_hw)); 1099 memcpy(fifo, &desc[partial], 1100 (async_desc->xfer_len - partial) * 1101 sizeof(struct bam_desc_hw)); 1102 } else { 1103 memcpy(&fifo[bchan->tail], desc, 1104 async_desc->xfer_len * 1105 sizeof(struct bam_desc_hw)); 1106 } 1107 1108 bchan->tail += async_desc->xfer_len; 1109 bchan->tail %= MAX_DESCRIPTORS; 1110 list_add_tail(&async_desc->desc_node, &bchan->desc_list); 1111 } 1112 1113 /* ensure descriptor writes and dma start not reordered */ 1114 wmb(); 1115 writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw), 1116 bam_addr(bdev, bchan->id, BAM_P_EVNT_REG)); 1117 1118 pm_runtime_mark_last_busy(bdev->dev); 1119 pm_runtime_put_autosuspend(bdev->dev); 1120 } 1121 1122 /** 1123 * dma_tasklet - DMA IRQ tasklet 1124 * @t: tasklet argument (bam controller structure) 1125 * 1126 * Sets up next DMA operation and then processes all completed transactions 1127 */ 1128 static void dma_tasklet(struct tasklet_struct *t) 1129 { 1130 struct bam_device *bdev = from_tasklet(bdev, t, task); 1131 struct bam_chan *bchan; 1132 unsigned int i; 1133 1134 /* go through the channels and kick off transactions */ 1135 for (i = 0; i < bdev->num_channels; i++) { 1136 bchan = &bdev->channels[i]; 1137 1138 guard(spinlock_irqsave)(&bchan->vc.lock); 1139 1140 if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan)) 1141 bam_start_dma(bchan); 1142 } 1143 1144 } 1145 1146 /** 1147 * bam_issue_pending - starts pending transactions 1148 * @chan: dma channel 1149 * 1150 * Calls tasklet directly which in turn starts any pending transactions 1151 */ 1152 static void bam_issue_pending(struct dma_chan *chan) 1153 { 1154 struct bam_chan *bchan = to_bam_chan(chan); 1155 1156 guard(spinlock_irqsave)(&bchan->vc.lock); 1157 1158 /* if work pending and idle, start a transaction */ 1159 if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan)) 1160 bam_start_dma(bchan); 1161 } 1162 1163 /** 1164 * bam_dma_free_desc - free descriptor memory 1165 * @vd: virtual descriptor 1166 * 1167 */ 1168 static void bam_dma_free_desc(struct virt_dma_desc *vd) 1169 { 1170 struct bam_async_desc *async_desc = container_of(vd, 1171 struct bam_async_desc, vd); 1172 1173 kfree(async_desc); 1174 } 1175 1176 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec, 1177 struct of_dma *of) 1178 { 1179 struct bam_device *bdev = container_of(of->of_dma_data, 1180 struct bam_device, common); 1181 unsigned int request; 1182 1183 if (dma_spec->args_count != 1) 1184 return NULL; 1185 1186 request = dma_spec->args[0]; 1187 if (request >= bdev->num_channels) 1188 return NULL; 1189 1190 return dma_get_slave_channel(&(bdev->channels[request].vc.chan)); 1191 } 1192 1193 /** 1194 * bam_init 1195 * @bdev: bam device 1196 * 1197 * Initialization helper for global bam registers 1198 */ 1199 static int bam_init(struct bam_device *bdev) 1200 { 1201 u32 val; 1202 1203 /* read revision and configuration information */ 1204 if (!bdev->num_ees) { 1205 val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)); 1206 bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK; 1207 } 1208 1209 /* check that configured EE is within range */ 1210 if (bdev->ee >= bdev->num_ees) 1211 return -EINVAL; 1212 1213 if (!bdev->num_channels) { 1214 val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES)); 1215 bdev->num_channels = val & BAM_NUM_PIPES_MASK; 1216 } 1217 1218 /* Reset BAM now if fully controlled locally */ 1219 if (!bdev->controlled_remotely && !bdev->powered_remotely) 1220 bam_reset(bdev); 1221 1222 return 0; 1223 } 1224 1225 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan, 1226 u32 index) 1227 { 1228 bchan->id = index; 1229 bchan->bdev = bdev; 1230 1231 vchan_init(&bchan->vc, &bdev->common); 1232 bchan->vc.desc_free = bam_dma_free_desc; 1233 INIT_LIST_HEAD(&bchan->desc_list); 1234 } 1235 1236 static const struct of_device_id bam_of_match[] = { 1237 { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info }, 1238 { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info }, 1239 { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info }, 1240 { .compatible = "qcom,bam-v2.0.0", .data = &bam_v2_0_reg_info }, 1241 {} 1242 }; 1243 1244 MODULE_DEVICE_TABLE(of, bam_of_match); 1245 1246 static int bam_dma_probe(struct platform_device *pdev) 1247 { 1248 struct bam_device *bdev; 1249 const struct of_device_id *match; 1250 int ret, i; 1251 1252 bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL); 1253 if (!bdev) 1254 return -ENOMEM; 1255 1256 bdev->dev = &pdev->dev; 1257 1258 match = of_match_node(bam_of_match, pdev->dev.of_node); 1259 if (!match) { 1260 dev_err(&pdev->dev, "Unsupported BAM module\n"); 1261 return -ENODEV; 1262 } 1263 1264 bdev->layout = match->data; 1265 1266 bdev->regs = devm_platform_ioremap_resource(pdev, 0); 1267 if (IS_ERR(bdev->regs)) 1268 return PTR_ERR(bdev->regs); 1269 1270 bdev->irq = platform_get_irq(pdev, 0); 1271 if (bdev->irq < 0) 1272 return bdev->irq; 1273 1274 ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee); 1275 if (ret) { 1276 dev_err(bdev->dev, "Execution environment unspecified\n"); 1277 return ret; 1278 } 1279 1280 bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node, 1281 "qcom,controlled-remotely"); 1282 bdev->powered_remotely = of_property_read_bool(pdev->dev.of_node, 1283 "qcom,powered-remotely"); 1284 1285 if (bdev->controlled_remotely || bdev->powered_remotely) 1286 bdev->bamclk = devm_clk_get_optional(bdev->dev, "bam_clk"); 1287 else 1288 bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk"); 1289 1290 if (IS_ERR(bdev->bamclk)) 1291 return PTR_ERR(bdev->bamclk); 1292 1293 if (!bdev->bamclk) { 1294 ret = of_property_read_u32(pdev->dev.of_node, "num-channels", 1295 &bdev->num_channels); 1296 if (ret) { 1297 dev_err(bdev->dev, "num-channels unspecified in dt\n"); 1298 return ret; 1299 } 1300 1301 ret = of_property_read_u32(pdev->dev.of_node, "qcom,num-ees", 1302 &bdev->num_ees); 1303 if (ret) { 1304 dev_err(bdev->dev, "num-ees unspecified in dt\n"); 1305 return ret; 1306 } 1307 } 1308 1309 ret = clk_prepare_enable(bdev->bamclk); 1310 if (ret) { 1311 dev_err(bdev->dev, "failed to prepare/enable clock\n"); 1312 return ret; 1313 } 1314 1315 ret = bam_init(bdev); 1316 if (ret) 1317 goto err_disable_clk; 1318 1319 tasklet_setup(&bdev->task, dma_tasklet); 1320 1321 bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels, 1322 sizeof(*bdev->channels), GFP_KERNEL); 1323 1324 if (!bdev->channels) { 1325 ret = -ENOMEM; 1326 goto err_tasklet_kill; 1327 } 1328 1329 /* allocate and initialize channels */ 1330 INIT_LIST_HEAD(&bdev->common.channels); 1331 1332 for (i = 0; i < bdev->num_channels; i++) 1333 bam_channel_init(bdev, &bdev->channels[i], i); 1334 1335 ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq, 1336 IRQF_TRIGGER_HIGH, "bam_dma", bdev); 1337 if (ret) 1338 goto err_bam_channel_exit; 1339 1340 /* set max dma segment size */ 1341 bdev->common.dev = bdev->dev; 1342 dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE); 1343 1344 platform_set_drvdata(pdev, bdev); 1345 1346 /* set capabilities */ 1347 dma_cap_zero(bdev->common.cap_mask); 1348 dma_cap_set(DMA_SLAVE, bdev->common.cap_mask); 1349 1350 /* initialize dmaengine apis */ 1351 bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1352 bdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 1353 bdev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; 1354 bdev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; 1355 bdev->common.device_alloc_chan_resources = bam_alloc_chan; 1356 bdev->common.device_free_chan_resources = bam_free_chan; 1357 bdev->common.device_prep_slave_sg = bam_prep_slave_sg; 1358 bdev->common.device_config = bam_slave_config; 1359 bdev->common.device_pause = bam_pause; 1360 bdev->common.device_resume = bam_resume; 1361 bdev->common.device_terminate_all = bam_dma_terminate_all; 1362 bdev->common.device_issue_pending = bam_issue_pending; 1363 bdev->common.device_tx_status = bam_tx_status; 1364 bdev->common.dev = bdev->dev; 1365 1366 ret = dma_async_device_register(&bdev->common); 1367 if (ret) { 1368 dev_err(bdev->dev, "failed to register dma async device\n"); 1369 goto err_bam_channel_exit; 1370 } 1371 1372 ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate, 1373 &bdev->common); 1374 if (ret) 1375 goto err_unregister_dma; 1376 1377 pm_runtime_irq_safe(&pdev->dev); 1378 pm_runtime_set_autosuspend_delay(&pdev->dev, BAM_DMA_AUTOSUSPEND_DELAY); 1379 pm_runtime_use_autosuspend(&pdev->dev); 1380 pm_runtime_mark_last_busy(&pdev->dev); 1381 pm_runtime_set_active(&pdev->dev); 1382 pm_runtime_enable(&pdev->dev); 1383 1384 return 0; 1385 1386 err_unregister_dma: 1387 dma_async_device_unregister(&bdev->common); 1388 err_bam_channel_exit: 1389 for (i = 0; i < bdev->num_channels; i++) 1390 tasklet_kill(&bdev->channels[i].vc.task); 1391 err_tasklet_kill: 1392 tasklet_kill(&bdev->task); 1393 err_disable_clk: 1394 clk_disable_unprepare(bdev->bamclk); 1395 1396 return ret; 1397 } 1398 1399 static void bam_dma_remove(struct platform_device *pdev) 1400 { 1401 struct bam_device *bdev = platform_get_drvdata(pdev); 1402 u32 i; 1403 1404 pm_runtime_force_suspend(&pdev->dev); 1405 1406 of_dma_controller_free(pdev->dev.of_node); 1407 dma_async_device_unregister(&bdev->common); 1408 1409 /* mask all interrupts for this execution environment */ 1410 writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 1411 1412 devm_free_irq(bdev->dev, bdev->irq, bdev); 1413 1414 for (i = 0; i < bdev->num_channels; i++) { 1415 bam_dma_terminate_all(&bdev->channels[i].vc.chan); 1416 tasklet_kill(&bdev->channels[i].vc.task); 1417 1418 if (!bdev->channels[i].fifo_virt) 1419 continue; 1420 1421 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, 1422 bdev->channels[i].fifo_virt, 1423 bdev->channels[i].fifo_phys); 1424 } 1425 1426 tasklet_kill(&bdev->task); 1427 1428 clk_disable_unprepare(bdev->bamclk); 1429 } 1430 1431 static int __maybe_unused bam_dma_runtime_suspend(struct device *dev) 1432 { 1433 struct bam_device *bdev = dev_get_drvdata(dev); 1434 1435 clk_disable(bdev->bamclk); 1436 1437 return 0; 1438 } 1439 1440 static int __maybe_unused bam_dma_runtime_resume(struct device *dev) 1441 { 1442 struct bam_device *bdev = dev_get_drvdata(dev); 1443 int ret; 1444 1445 ret = clk_enable(bdev->bamclk); 1446 if (ret < 0) { 1447 dev_err(dev, "clk_enable failed: %d\n", ret); 1448 return ret; 1449 } 1450 1451 return 0; 1452 } 1453 1454 static int __maybe_unused bam_dma_suspend(struct device *dev) 1455 { 1456 struct bam_device *bdev = dev_get_drvdata(dev); 1457 1458 pm_runtime_force_suspend(dev); 1459 clk_unprepare(bdev->bamclk); 1460 1461 return 0; 1462 } 1463 1464 static int __maybe_unused bam_dma_resume(struct device *dev) 1465 { 1466 struct bam_device *bdev = dev_get_drvdata(dev); 1467 int ret; 1468 1469 ret = clk_prepare(bdev->bamclk); 1470 if (ret) 1471 return ret; 1472 1473 pm_runtime_force_resume(dev); 1474 1475 return 0; 1476 } 1477 1478 static const struct dev_pm_ops bam_dma_pm_ops = { 1479 SET_LATE_SYSTEM_SLEEP_PM_OPS(bam_dma_suspend, bam_dma_resume) 1480 SET_RUNTIME_PM_OPS(bam_dma_runtime_suspend, bam_dma_runtime_resume, 1481 NULL) 1482 }; 1483 1484 static struct platform_driver bam_dma_driver = { 1485 .probe = bam_dma_probe, 1486 .remove = bam_dma_remove, 1487 .driver = { 1488 .name = "bam-dma-engine", 1489 .pm = &bam_dma_pm_ops, 1490 .of_match_table = bam_of_match, 1491 }, 1492 }; 1493 1494 module_platform_driver(bam_dma_driver); 1495 1496 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); 1497 MODULE_DESCRIPTION("QCOM BAM DMA engine driver"); 1498 MODULE_LICENSE("GPL v2"); 1499