1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF RX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/spinlock.h> 16 17 #include <sound/dmaengine_pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 21 /* 22 * ---- S/PDIF Receiver Controller Register map ---- 23 */ 24 #define SPDIFRX_CR 0x00 /* Control Register */ 25 #define SPDIFRX_MR 0x04 /* Mode Register */ 26 27 #define SPDIFRX_IER 0x10 /* Interrupt Enable Register */ 28 #define SPDIFRX_IDR 0x14 /* Interrupt Disable Register */ 29 #define SPDIFRX_IMR 0x18 /* Interrupt Mask Register */ 30 #define SPDIFRX_ISR 0x1c /* Interrupt Status Register */ 31 #define SPDIFRX_RSR 0x20 /* Status Register */ 32 #define SPDIFRX_RHR 0x24 /* Holding Register */ 33 34 #define SPDIFRX_CHSR(channel, reg) \ 35 (0x30 + (channel) * 0x30 + (reg) * 4) /* Channel x Status Registers */ 36 37 #define SPDIFRX_CHUD(channel, reg) \ 38 (0x48 + (channel) * 0x30 + (reg) * 4) /* Channel x User Data Registers */ 39 40 #define SPDIFRX_WPMR 0xE4 /* Write Protection Mode Register */ 41 #define SPDIFRX_WPSR 0xE8 /* Write Protection Status Register */ 42 43 #define SPDIFRX_VERSION 0xFC /* Version Register */ 44 45 46 /* 32-bit word byte masks */ 47 #define SPDIFRX_BYTE_0_MASK GENMASK(7, 0) 48 #define SPDIFRX_BYTE_1_MASK GENMASK(15, 8) 49 #define SPDIFRX_BYTE_2_MASK GENMASK(23, 16) 50 #define SPDIFRX_BYTE_3_MASK GENMASK(31, 24) 51 52 /* 53 * ---- Control Register (Write-only) ---- 54 */ 55 #define SPDIFRX_CR_SWRST BIT(0) /* Software Reset */ 56 57 /* 58 * ---- Mode Register (Read/Write) ---- 59 */ 60 /* Receive Enable */ 61 #define SPDIFRX_MR_RXEN_MASK GENMASK(0, 0) 62 #define SPDIFRX_MR_RXEN_DISABLE (0 << 0) /* SPDIF Receiver Disabled */ 63 #define SPDIFRX_MR_RXEN_ENABLE (1 << 0) /* SPDIF Receiver Enabled */ 64 65 /* Validity Bit Mode */ 66 #define SPDIFRX_MR_VBMODE_MASK GENMASK(1, 1) 67 #define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \ 68 (0 << 1) /* Load sample regardless of validity bit value */ 69 #define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \ 70 (1 << 1) /* Load sample only if validity bit is 0 */ 71 72 /* Data Word Endian Mode */ 73 #define SPDIFRX_MR_ENDIAN_MASK GENMASK(2, 2) 74 #define SPDIFRX_MR_ENDIAN_LITTLE (0 << 2) /* Little Endian Mode */ 75 #define SPDIFRX_MR_ENDIAN_BIG (1 << 2) /* Big Endian Mode */ 76 77 /* Parity Bit Mode */ 78 #define SPDIFRX_MR_PBMODE_MASK GENMASK(3, 3) 79 #define SPDIFRX_MR_PBMODE_PARCHECK (0 << 3) /* Parity Check Enabled */ 80 #define SPDIFRX_MR_PBMODE_NOPARCHECK (1 << 3) /* Parity Check Disabled */ 81 82 /* Sample Data Width */ 83 #define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4) 84 #define SPDIFRX_MR_DATAWIDTH(width) \ 85 FIELD_PREP(SPDIFRX_MR_DATAWIDTH_MASK, 6 - ((width) / 4)) 86 87 /* Packed Data Mode in Receive Holding Register */ 88 #define SPDIFRX_MR_PACK_MASK GENMASK(7, 7) 89 #define SPDIFRX_MR_PACK_DISABLED (0 << 7) 90 #define SPDIFRX_MR_PACK_ENABLED (1 << 7) 91 92 /* Start of Block Bit Mode */ 93 #define SPDIFRX_MR_SBMODE_MASK GENMASK(8, 8) 94 #define SPDIFRX_MR_SBMODE_ALWAYS_LOAD (0 << 8) 95 #define SPDIFRX_MR_SBMODE_DISCARD (1 << 8) 96 97 /* Consecutive Preamble Error Threshold Automatic Restart */ 98 #define SPDIFRX_MR_AUTORST_MASK GENMASK(24, 24) 99 #define SPDIFRX_MR_AUTORST_NOACTION (0 << 24) 100 #define SPDIFRX_MR_AUTORST_UNLOCK_ON_PRE_ERR (1 << 24) 101 102 /* 103 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 104 */ 105 #define SPDIFRX_IR_RXRDY BIT(0) 106 #define SPDIFRX_IR_LOCKED BIT(1) 107 #define SPDIFRX_IR_LOSS BIT(2) 108 #define SPDIFRX_IR_BLOCKEND BIT(3) 109 #define SPDIFRX_IR_SFE BIT(4) 110 #define SPDIFRX_IR_PAR_ERR BIT(5) 111 #define SPDIFRX_IR_OVERRUN BIT(6) 112 #define SPDIFRX_IR_RXFULL BIT(7) 113 #define SPDIFRX_IR_CSC(ch) BIT((ch) + 8) 114 #define SPDIFRX_IR_SECE BIT(10) 115 #define SPDIFRX_IR_BLOCKST BIT(11) 116 #define SPDIFRX_IR_NRZ_ERR BIT(12) 117 #define SPDIFRX_IR_PRE_ERR BIT(13) 118 #define SPDIFRX_IR_CP_ERR BIT(14) 119 120 /* 121 * ---- Receiver Status Register (Read/Write) ---- 122 */ 123 /* Enable Status */ 124 #define SPDIFRX_RSR_ULOCK BIT(0) 125 #define SPDIFRX_RSR_BADF BIT(1) 126 #define SPDIFRX_RSR_LOWF BIT(2) 127 #define SPDIFRX_RSR_NOSIGNAL BIT(3) 128 #define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16) 129 #define SPDIFRX_RSR_IFS(reg) FIELD_GET(SPDIFRX_RSR_IFS_MASK, reg) 130 131 /* 132 * ---- Version Register (Read-only) ---- 133 */ 134 #define SPDIFRX_VERSION_MASK GENMASK(11, 0) 135 #define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16) 136 #define SPDIFRX_VERSION_MFN(reg) FIELD_GET(SPDIFRX_VERSION_MFN_MASK, reg) 137 138 static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg) 139 { 140 switch (reg) { 141 case SPDIFRX_MR: 142 case SPDIFRX_IMR: 143 case SPDIFRX_ISR: 144 case SPDIFRX_RSR: 145 case SPDIFRX_CHSR(0, 0): 146 case SPDIFRX_CHSR(0, 1): 147 case SPDIFRX_CHSR(0, 2): 148 case SPDIFRX_CHSR(0, 3): 149 case SPDIFRX_CHSR(0, 4): 150 case SPDIFRX_CHSR(0, 5): 151 case SPDIFRX_CHUD(0, 0): 152 case SPDIFRX_CHUD(0, 1): 153 case SPDIFRX_CHUD(0, 2): 154 case SPDIFRX_CHUD(0, 3): 155 case SPDIFRX_CHUD(0, 4): 156 case SPDIFRX_CHUD(0, 5): 157 case SPDIFRX_CHSR(1, 0): 158 case SPDIFRX_CHSR(1, 1): 159 case SPDIFRX_CHSR(1, 2): 160 case SPDIFRX_CHSR(1, 3): 161 case SPDIFRX_CHSR(1, 4): 162 case SPDIFRX_CHSR(1, 5): 163 case SPDIFRX_CHUD(1, 0): 164 case SPDIFRX_CHUD(1, 1): 165 case SPDIFRX_CHUD(1, 2): 166 case SPDIFRX_CHUD(1, 3): 167 case SPDIFRX_CHUD(1, 4): 168 case SPDIFRX_CHUD(1, 5): 169 case SPDIFRX_WPMR: 170 case SPDIFRX_WPSR: 171 case SPDIFRX_VERSION: 172 return true; 173 default: 174 return false; 175 } 176 } 177 178 static bool mchp_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 179 { 180 switch (reg) { 181 case SPDIFRX_CR: 182 case SPDIFRX_MR: 183 case SPDIFRX_IER: 184 case SPDIFRX_IDR: 185 case SPDIFRX_WPMR: 186 return true; 187 default: 188 return false; 189 } 190 } 191 192 static bool mchp_spdifrx_precious_reg(struct device *dev, unsigned int reg) 193 { 194 switch (reg) { 195 case SPDIFRX_ISR: 196 case SPDIFRX_RHR: 197 return true; 198 default: 199 return false; 200 } 201 } 202 203 static bool mchp_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 204 { 205 switch (reg) { 206 case SPDIFRX_IMR: 207 case SPDIFRX_ISR: 208 case SPDIFRX_RSR: 209 case SPDIFRX_CHSR(0, 0): 210 case SPDIFRX_CHSR(0, 1): 211 case SPDIFRX_CHSR(0, 2): 212 case SPDIFRX_CHSR(0, 3): 213 case SPDIFRX_CHSR(0, 4): 214 case SPDIFRX_CHSR(0, 5): 215 case SPDIFRX_CHUD(0, 0): 216 case SPDIFRX_CHUD(0, 1): 217 case SPDIFRX_CHUD(0, 2): 218 case SPDIFRX_CHUD(0, 3): 219 case SPDIFRX_CHUD(0, 4): 220 case SPDIFRX_CHUD(0, 5): 221 case SPDIFRX_CHSR(1, 0): 222 case SPDIFRX_CHSR(1, 1): 223 case SPDIFRX_CHSR(1, 2): 224 case SPDIFRX_CHSR(1, 3): 225 case SPDIFRX_CHSR(1, 4): 226 case SPDIFRX_CHSR(1, 5): 227 case SPDIFRX_CHUD(1, 0): 228 case SPDIFRX_CHUD(1, 1): 229 case SPDIFRX_CHUD(1, 2): 230 case SPDIFRX_CHUD(1, 3): 231 case SPDIFRX_CHUD(1, 4): 232 case SPDIFRX_CHUD(1, 5): 233 case SPDIFRX_VERSION: 234 return true; 235 default: 236 return false; 237 } 238 } 239 240 static const struct regmap_config mchp_spdifrx_regmap_config = { 241 .reg_bits = 32, 242 .reg_stride = 4, 243 .val_bits = 32, 244 .max_register = SPDIFRX_VERSION, 245 .readable_reg = mchp_spdifrx_readable_reg, 246 .writeable_reg = mchp_spdifrx_writeable_reg, 247 .precious_reg = mchp_spdifrx_precious_reg, 248 .volatile_reg = mchp_spdifrx_volatile_reg, 249 .cache_type = REGCACHE_FLAT, 250 }; 251 252 #define SPDIFRX_GCLK_RATIO_MIN (12 * 64) 253 254 #define SPDIFRX_CS_BITS 192 255 #define SPDIFRX_UD_BITS 192 256 257 #define SPDIFRX_CHANNELS 2 258 259 /** 260 * struct mchp_spdifrx_ch_stat: MCHP SPDIFRX channel status 261 * @data: channel status bits 262 * @done: completion to signal channel status bits acquisition done 263 */ 264 struct mchp_spdifrx_ch_stat { 265 unsigned char data[SPDIFRX_CS_BITS / 8]; 266 struct completion done; 267 }; 268 269 /** 270 * struct mchp_spdifrx_user_data: MCHP SPDIFRX user data 271 * @data: user data bits 272 * @done: completion to signal user data bits acquisition done 273 */ 274 struct mchp_spdifrx_user_data { 275 unsigned char data[SPDIFRX_UD_BITS / 8]; 276 struct completion done; 277 }; 278 279 /** 280 * struct mchp_spdifrx_mixer_control: MCHP SPDIFRX mixer control data structure 281 * @ch_stat: array of channel statuses 282 * @user_data: array of user data 283 * @ulock: ulock bit status 284 * @badf: badf bit status 285 * @signal: signal bit status 286 */ 287 struct mchp_spdifrx_mixer_control { 288 struct mchp_spdifrx_ch_stat ch_stat[SPDIFRX_CHANNELS]; 289 struct mchp_spdifrx_user_data user_data[SPDIFRX_CHANNELS]; 290 bool ulock; 291 bool badf; 292 bool signal; 293 }; 294 295 /** 296 * struct mchp_spdifrx_dev: MCHP SPDIFRX device data structure 297 * @capture: DAI DMA configuration data 298 * @control: mixer controls 299 * @mlock: mutex to protect concurency b/w configuration and control APIs 300 * @dev: struct device 301 * @regmap: regmap for this device 302 * @pclk: peripheral clock 303 * @gclk: generic clock 304 * @trigger_enabled: true if enabled though trigger() ops 305 */ 306 struct mchp_spdifrx_dev { 307 struct snd_dmaengine_dai_dma_data capture; 308 struct mchp_spdifrx_mixer_control control; 309 struct mutex mlock; 310 struct device *dev; 311 struct regmap *regmap; 312 struct clk *pclk; 313 struct clk *gclk; 314 unsigned int trigger_enabled; 315 }; 316 317 static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev, 318 int channel) 319 { 320 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 321 u8 *ch_stat = &ctrl->ch_stat[channel].data[0]; 322 u32 val; 323 int i; 324 325 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) { 326 regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val); 327 *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_0_MASK, val); 328 *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_1_MASK, val); 329 *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_2_MASK, val); 330 *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_3_MASK, val); 331 } 332 } 333 334 static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev, 335 int channel) 336 { 337 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 338 u8 *user_data = &ctrl->user_data[channel].data[0]; 339 u32 val; 340 int i; 341 342 for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) { 343 regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val); 344 *user_data++ = FIELD_GET(SPDIFRX_BYTE_0_MASK, val); 345 *user_data++ = FIELD_GET(SPDIFRX_BYTE_1_MASK, val); 346 *user_data++ = FIELD_GET(SPDIFRX_BYTE_2_MASK, val); 347 *user_data++ = FIELD_GET(SPDIFRX_BYTE_3_MASK, val); 348 } 349 } 350 351 static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id) 352 { 353 struct mchp_spdifrx_dev *dev = dev_id; 354 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 355 u32 sr, imr, pending; 356 irqreturn_t ret = IRQ_NONE; 357 int ch; 358 359 regmap_read(dev->regmap, SPDIFRX_ISR, &sr); 360 regmap_read(dev->regmap, SPDIFRX_IMR, &imr); 361 pending = sr & imr; 362 dev_dbg(dev->dev, "ISR: %#x, IMR: %#x, pending: %#x\n", sr, imr, 363 pending); 364 365 if (!pending) 366 return IRQ_NONE; 367 368 if (pending & SPDIFRX_IR_BLOCKEND) { 369 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 370 mchp_spdifrx_channel_user_data_read(dev, ch); 371 complete(&ctrl->user_data[ch].done); 372 } 373 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); 374 ret = IRQ_HANDLED; 375 } 376 377 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 378 if (pending & SPDIFRX_IR_CSC(ch)) { 379 mchp_spdifrx_channel_status_read(dev, ch); 380 complete(&ctrl->ch_stat[ch].done); 381 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(ch)); 382 ret = IRQ_HANDLED; 383 } 384 } 385 386 if (pending & SPDIFRX_IR_OVERRUN) { 387 dev_warn(dev->dev, "Overrun detected\n"); 388 ret = IRQ_HANDLED; 389 } 390 391 return ret; 392 } 393 394 static int mchp_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 395 struct snd_soc_dai *dai) 396 { 397 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 398 int ret = 0; 399 400 switch (cmd) { 401 case SNDRV_PCM_TRIGGER_START: 402 case SNDRV_PCM_TRIGGER_RESUME: 403 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 404 mutex_lock(&dev->mlock); 405 /* Enable overrun interrupts */ 406 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_OVERRUN); 407 408 /* Enable receiver. */ 409 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 410 SPDIFRX_MR_RXEN_ENABLE); 411 dev->trigger_enabled = true; 412 mutex_unlock(&dev->mlock); 413 break; 414 case SNDRV_PCM_TRIGGER_STOP: 415 case SNDRV_PCM_TRIGGER_SUSPEND: 416 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 417 mutex_lock(&dev->mlock); 418 /* Disable overrun interrupts */ 419 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_OVERRUN); 420 421 /* Disable receiver. */ 422 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 423 SPDIFRX_MR_RXEN_DISABLE); 424 dev->trigger_enabled = false; 425 mutex_unlock(&dev->mlock); 426 break; 427 default: 428 ret = -EINVAL; 429 } 430 431 return ret; 432 } 433 434 static int mchp_spdifrx_hw_params(struct snd_pcm_substream *substream, 435 struct snd_pcm_hw_params *params, 436 struct snd_soc_dai *dai) 437 { 438 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 439 u32 mr = 0; 440 int ret; 441 442 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 443 __func__, params_rate(params), params_format(params), 444 params_width(params), params_channels(params)); 445 446 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 447 dev_err(dev->dev, "Playback is not supported\n"); 448 return -EINVAL; 449 } 450 451 if (params_channels(params) != SPDIFRX_CHANNELS) { 452 dev_err(dev->dev, "unsupported number of channels: %d\n", 453 params_channels(params)); 454 return -EINVAL; 455 } 456 457 switch (params_format(params)) { 458 case SNDRV_PCM_FORMAT_S16_BE: 459 case SNDRV_PCM_FORMAT_S20_3BE: 460 case SNDRV_PCM_FORMAT_S24_3BE: 461 case SNDRV_PCM_FORMAT_S24_BE: 462 mr |= SPDIFRX_MR_ENDIAN_BIG; 463 fallthrough; 464 case SNDRV_PCM_FORMAT_S16_LE: 465 case SNDRV_PCM_FORMAT_S20_3LE: 466 case SNDRV_PCM_FORMAT_S24_3LE: 467 case SNDRV_PCM_FORMAT_S24_LE: 468 mr |= SPDIFRX_MR_DATAWIDTH(params_width(params)); 469 break; 470 default: 471 dev_err(dev->dev, "unsupported PCM format: %d\n", 472 params_format(params)); 473 return -EINVAL; 474 } 475 476 mutex_lock(&dev->mlock); 477 if (dev->trigger_enabled) { 478 dev_err(dev->dev, "PCM already running\n"); 479 ret = -EBUSY; 480 goto unlock; 481 } 482 483 /* GCLK is enabled by runtime PM. */ 484 clk_disable_unprepare(dev->gclk); 485 486 ret = clk_set_min_rate(dev->gclk, params_rate(params) * 487 SPDIFRX_GCLK_RATIO_MIN + 1); 488 if (ret) { 489 dev_err(dev->dev, 490 "unable to set gclk min rate: rate %u * ratio %u + 1\n", 491 params_rate(params), SPDIFRX_GCLK_RATIO_MIN); 492 /* Restore runtime PM state. */ 493 clk_prepare_enable(dev->gclk); 494 goto unlock; 495 } 496 ret = clk_prepare_enable(dev->gclk); 497 if (ret) { 498 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 499 goto unlock; 500 } 501 502 dev_dbg(dev->dev, "GCLK range min set to %d\n", 503 params_rate(params) * SPDIFRX_GCLK_RATIO_MIN + 1); 504 505 ret = regmap_write(dev->regmap, SPDIFRX_MR, mr); 506 507 unlock: 508 mutex_unlock(&dev->mlock); 509 510 return ret; 511 } 512 513 #define MCHP_SPDIF_RATES SNDRV_PCM_RATE_8000_192000 514 515 #define MCHP_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 516 SNDRV_PCM_FMTBIT_U16_BE | \ 517 SNDRV_PCM_FMTBIT_S20_3LE | \ 518 SNDRV_PCM_FMTBIT_S20_3BE | \ 519 SNDRV_PCM_FMTBIT_S24_3LE | \ 520 SNDRV_PCM_FMTBIT_S24_3BE | \ 521 SNDRV_PCM_FMTBIT_S24_LE | \ 522 SNDRV_PCM_FMTBIT_S24_BE \ 523 ) 524 525 static int mchp_spdifrx_info(struct snd_kcontrol *kcontrol, 526 struct snd_ctl_elem_info *uinfo) 527 { 528 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 529 uinfo->count = 1; 530 531 return 0; 532 } 533 534 static int mchp_spdifrx_cs_get(struct mchp_spdifrx_dev *dev, 535 int channel, 536 struct snd_ctl_elem_value *uvalue) 537 { 538 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 539 struct mchp_spdifrx_ch_stat *ch_stat = &ctrl->ch_stat[channel]; 540 int ret = 0; 541 542 mutex_lock(&dev->mlock); 543 544 ret = pm_runtime_resume_and_get(dev->dev); 545 if (ret < 0) 546 goto unlock; 547 548 /* 549 * We may reach this point with both clocks enabled but the receiver 550 * still disabled. To void waiting for completion and return with 551 * timeout check the dev->trigger_enabled. 552 * 553 * To retrieve data: 554 * - if the receiver is enabled CSC IRQ will update the data in software 555 * caches (ch_stat->data) 556 * - otherwise we just update it here the software caches with latest 557 * available information and return it; in this case we don't need 558 * spin locking as the IRQ is disabled and will not be raised from 559 * anywhere else. 560 */ 561 562 if (dev->trigger_enabled) { 563 reinit_completion(&ch_stat->done); 564 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel)); 565 /* Check for new data available */ 566 ret = wait_for_completion_interruptible_timeout(&ch_stat->done, 567 msecs_to_jiffies(100)); 568 /* Valid stream might not be present */ 569 if (ret <= 0) { 570 dev_dbg(dev->dev, "channel status for channel %d timeout\n", 571 channel); 572 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(channel)); 573 ret = ret ? : -ETIMEDOUT; 574 goto pm_runtime_put; 575 } else { 576 ret = 0; 577 } 578 } else { 579 /* Update software cache with latest channel status. */ 580 mchp_spdifrx_channel_status_read(dev, channel); 581 } 582 583 memcpy(uvalue->value.iec958.status, ch_stat->data, 584 sizeof(ch_stat->data)); 585 586 pm_runtime_put: 587 pm_runtime_put_autosuspend(dev->dev); 588 unlock: 589 mutex_unlock(&dev->mlock); 590 return ret; 591 } 592 593 static int mchp_spdifrx_cs1_get(struct snd_kcontrol *kcontrol, 594 struct snd_ctl_elem_value *uvalue) 595 { 596 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 597 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 598 599 return mchp_spdifrx_cs_get(dev, 0, uvalue); 600 } 601 602 static int mchp_spdifrx_cs2_get(struct snd_kcontrol *kcontrol, 603 struct snd_ctl_elem_value *uvalue) 604 { 605 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 606 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 607 608 return mchp_spdifrx_cs_get(dev, 1, uvalue); 609 } 610 611 static int mchp_spdifrx_cs_mask(struct snd_kcontrol *kcontrol, 612 struct snd_ctl_elem_value *uvalue) 613 { 614 memset(uvalue->value.iec958.status, 0xff, 615 sizeof(uvalue->value.iec958.status)); 616 617 return 0; 618 } 619 620 static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev, 621 int channel, 622 struct snd_ctl_elem_value *uvalue) 623 { 624 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 625 struct mchp_spdifrx_user_data *user_data = &ctrl->user_data[channel]; 626 int ret = 0; 627 628 mutex_lock(&dev->mlock); 629 630 ret = pm_runtime_resume_and_get(dev->dev); 631 if (ret < 0) 632 goto unlock; 633 634 /* 635 * We may reach this point with both clocks enabled but the receiver 636 * still disabled. To void waiting for completion to just timeout we 637 * check here the dev->trigger_enabled flag. 638 * 639 * To retrieve data: 640 * - if the receiver is enabled we need to wait for blockend IRQ to read 641 * data to and update it for us in software caches 642 * - otherwise reading the SPDIFRX_CHUD() registers is enough. 643 */ 644 645 if (dev->trigger_enabled) { 646 reinit_completion(&user_data->done); 647 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND); 648 ret = wait_for_completion_interruptible_timeout(&user_data->done, 649 msecs_to_jiffies(100)); 650 /* Valid stream might not be present. */ 651 if (ret <= 0) { 652 dev_dbg(dev->dev, "user data for channel %d timeout\n", 653 channel); 654 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); 655 ret = ret ? : -ETIMEDOUT; 656 goto pm_runtime_put; 657 } else { 658 ret = 0; 659 } 660 } else { 661 /* Update software cache with last available data. */ 662 mchp_spdifrx_channel_user_data_read(dev, channel); 663 } 664 665 memcpy(uvalue->value.iec958.subcode, user_data->data, 666 sizeof(user_data->data)); 667 668 pm_runtime_put: 669 pm_runtime_put_autosuspend(dev->dev); 670 unlock: 671 mutex_unlock(&dev->mlock); 672 return ret; 673 } 674 675 static int mchp_spdifrx_subcode_ch1_get(struct snd_kcontrol *kcontrol, 676 struct snd_ctl_elem_value *uvalue) 677 { 678 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 679 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 680 681 return mchp_spdifrx_subcode_ch_get(dev, 0, uvalue); 682 } 683 684 static int mchp_spdifrx_subcode_ch2_get(struct snd_kcontrol *kcontrol, 685 struct snd_ctl_elem_value *uvalue) 686 { 687 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 688 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 689 690 return mchp_spdifrx_subcode_ch_get(dev, 1, uvalue); 691 } 692 693 static int mchp_spdifrx_boolean_info(struct snd_kcontrol *kcontrol, 694 struct snd_ctl_elem_info *uinfo) 695 { 696 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 697 uinfo->count = 1; 698 uinfo->value.integer.min = 0; 699 uinfo->value.integer.max = 1; 700 701 return 0; 702 } 703 704 static int mchp_spdifrx_ulock_get(struct snd_kcontrol *kcontrol, 705 struct snd_ctl_elem_value *uvalue) 706 { 707 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 708 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 709 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 710 u32 val; 711 int ret; 712 bool ulock_old = ctrl->ulock; 713 714 mutex_lock(&dev->mlock); 715 716 ret = pm_runtime_resume_and_get(dev->dev); 717 if (ret < 0) 718 goto unlock; 719 720 /* 721 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 722 * and the receiver is disabled. Thus we take into account the 723 * dev->trigger_enabled here to return a real status. 724 */ 725 if (dev->trigger_enabled) { 726 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 727 ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK); 728 } else { 729 ctrl->ulock = 0; 730 } 731 732 uvalue->value.integer.value[0] = ctrl->ulock; 733 734 pm_runtime_put_autosuspend(dev->dev); 735 unlock: 736 mutex_unlock(&dev->mlock); 737 738 return ulock_old != ctrl->ulock; 739 } 740 741 static int mchp_spdifrx_badf_get(struct snd_kcontrol *kcontrol, 742 struct snd_ctl_elem_value *uvalue) 743 { 744 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 745 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 746 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 747 u32 val; 748 int ret; 749 bool badf_old = ctrl->badf; 750 751 mutex_lock(&dev->mlock); 752 753 ret = pm_runtime_resume_and_get(dev->dev); 754 if (ret < 0) 755 goto unlock; 756 757 /* 758 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 759 * and the receiver is disabled. Thus we take into account the 760 * dev->trigger_enabled here to return a real status. 761 */ 762 if (dev->trigger_enabled) { 763 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 764 ctrl->badf = !!(val & SPDIFRX_RSR_BADF); 765 } else { 766 ctrl->badf = 0; 767 } 768 769 pm_runtime_put_autosuspend(dev->dev); 770 unlock: 771 mutex_unlock(&dev->mlock); 772 773 uvalue->value.integer.value[0] = ctrl->badf; 774 775 return badf_old != ctrl->badf; 776 } 777 778 static int mchp_spdifrx_signal_get(struct snd_kcontrol *kcontrol, 779 struct snd_ctl_elem_value *uvalue) 780 { 781 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 782 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 783 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 784 u32 val = ~0U, loops = 10; 785 int ret; 786 bool signal_old = ctrl->signal; 787 788 mutex_lock(&dev->mlock); 789 790 ret = pm_runtime_resume_and_get(dev->dev); 791 if (ret < 0) 792 goto unlock; 793 794 /* 795 * To get the signal we need to have receiver enabled. This 796 * could be enabled also from trigger() function thus we need to 797 * take care of not disabling the receiver when it runs. 798 */ 799 if (!dev->trigger_enabled) { 800 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 801 SPDIFRX_MR_RXEN_ENABLE); 802 803 /* Wait for RSR.ULOCK bit. */ 804 while (--loops) { 805 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 806 if (!(val & SPDIFRX_RSR_ULOCK)) 807 break; 808 usleep_range(100, 150); 809 } 810 811 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 812 SPDIFRX_MR_RXEN_DISABLE); 813 } else { 814 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 815 } 816 817 pm_runtime_put_autosuspend(dev->dev); 818 819 unlock: 820 mutex_unlock(&dev->mlock); 821 822 if (!(val & SPDIFRX_RSR_ULOCK)) 823 ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL); 824 else 825 ctrl->signal = 0; 826 uvalue->value.integer.value[0] = ctrl->signal; 827 828 return signal_old != ctrl->signal; 829 } 830 831 static int mchp_spdifrx_rate_info(struct snd_kcontrol *kcontrol, 832 struct snd_ctl_elem_info *uinfo) 833 { 834 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 835 uinfo->count = 1; 836 uinfo->value.integer.min = 0; 837 uinfo->value.integer.max = 192000; 838 839 return 0; 840 } 841 842 static int mchp_spdifrx_rate_get(struct snd_kcontrol *kcontrol, 843 struct snd_ctl_elem_value *ucontrol) 844 { 845 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 846 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 847 unsigned long rate; 848 u32 val; 849 int ret; 850 851 mutex_lock(&dev->mlock); 852 853 ret = pm_runtime_resume_and_get(dev->dev); 854 if (ret < 0) 855 goto unlock; 856 857 /* 858 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 859 * and the receiver is disabled. Thus we take into account the 860 * dev->trigger_enabled here to return a real status. 861 */ 862 if (dev->trigger_enabled) { 863 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 864 /* If the receiver is not locked, ISF data is invalid. */ 865 if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) { 866 ucontrol->value.integer.value[0] = 0; 867 goto pm_runtime_put; 868 } 869 } else { 870 /* Reveicer is not locked, IFS data is invalid. */ 871 ucontrol->value.integer.value[0] = 0; 872 goto pm_runtime_put; 873 } 874 875 rate = clk_get_rate(dev->gclk); 876 877 ucontrol->value.integer.value[0] = rate / (32 * SPDIFRX_RSR_IFS(val)); 878 879 pm_runtime_put: 880 pm_runtime_put_autosuspend(dev->dev); 881 unlock: 882 mutex_unlock(&dev->mlock); 883 return ret; 884 } 885 886 static struct snd_kcontrol_new mchp_spdifrx_ctrls[] = { 887 /* Channel status controller */ 888 { 889 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 890 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 891 " Channel 1", 892 .access = SNDRV_CTL_ELEM_ACCESS_READ | 893 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 894 .info = mchp_spdifrx_info, 895 .get = mchp_spdifrx_cs1_get, 896 }, 897 { 898 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 899 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 900 " Channel 2", 901 .access = SNDRV_CTL_ELEM_ACCESS_READ | 902 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 903 .info = mchp_spdifrx_info, 904 .get = mchp_spdifrx_cs2_get, 905 }, 906 { 907 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 908 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), 909 .access = SNDRV_CTL_ELEM_ACCESS_READ, 910 .info = mchp_spdifrx_info, 911 .get = mchp_spdifrx_cs_mask, 912 }, 913 /* User bits controller */ 914 { 915 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 916 .name = "IEC958 Subcode Capture Default Channel 1", 917 .access = SNDRV_CTL_ELEM_ACCESS_READ | 918 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 919 .info = mchp_spdifrx_info, 920 .get = mchp_spdifrx_subcode_ch1_get, 921 }, 922 { 923 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 924 .name = "IEC958 Subcode Capture Default Channel 2", 925 .access = SNDRV_CTL_ELEM_ACCESS_READ | 926 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 927 .info = mchp_spdifrx_info, 928 .get = mchp_spdifrx_subcode_ch2_get, 929 }, 930 /* Lock status */ 931 { 932 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 933 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Unlocked", 934 .access = SNDRV_CTL_ELEM_ACCESS_READ | 935 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 936 .info = mchp_spdifrx_boolean_info, 937 .get = mchp_spdifrx_ulock_get, 938 }, 939 /* Bad format */ 940 { 941 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 942 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE)"Bad Format", 943 .access = SNDRV_CTL_ELEM_ACCESS_READ | 944 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 945 .info = mchp_spdifrx_boolean_info, 946 .get = mchp_spdifrx_badf_get, 947 }, 948 /* Signal */ 949 { 950 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 951 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Signal", 952 .access = SNDRV_CTL_ELEM_ACCESS_READ | 953 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 954 .info = mchp_spdifrx_boolean_info, 955 .get = mchp_spdifrx_signal_get, 956 }, 957 /* Sampling rate */ 958 { 959 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 960 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Rate", 961 .access = SNDRV_CTL_ELEM_ACCESS_READ | 962 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 963 .info = mchp_spdifrx_rate_info, 964 .get = mchp_spdifrx_rate_get, 965 }, 966 }; 967 968 static int mchp_spdifrx_dai_probe(struct snd_soc_dai *dai) 969 { 970 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 971 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 972 int ch; 973 974 snd_soc_dai_init_dma_data(dai, NULL, &dev->capture); 975 976 /* Software reset the IP */ 977 regmap_write(dev->regmap, SPDIFRX_CR, SPDIFRX_CR_SWRST); 978 979 /* Default configuration */ 980 regmap_write(dev->regmap, SPDIFRX_MR, 981 SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 | 982 SPDIFRX_MR_SBMODE_DISCARD | 983 SPDIFRX_MR_AUTORST_NOACTION | 984 SPDIFRX_MR_PACK_DISABLED); 985 986 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 987 init_completion(&ctrl->ch_stat[ch].done); 988 init_completion(&ctrl->user_data[ch].done); 989 } 990 991 /* Add controls */ 992 snd_soc_add_dai_controls(dai, mchp_spdifrx_ctrls, 993 ARRAY_SIZE(mchp_spdifrx_ctrls)); 994 995 return 0; 996 } 997 998 static int mchp_spdifrx_dai_remove(struct snd_soc_dai *dai) 999 { 1000 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 1001 1002 /* Disable interrupts */ 1003 regmap_write(dev->regmap, SPDIFRX_IDR, GENMASK(14, 0)); 1004 1005 return 0; 1006 } 1007 1008 static const struct snd_soc_dai_ops mchp_spdifrx_dai_ops = { 1009 .probe = mchp_spdifrx_dai_probe, 1010 .remove = mchp_spdifrx_dai_remove, 1011 .trigger = mchp_spdifrx_trigger, 1012 .hw_params = mchp_spdifrx_hw_params, 1013 }; 1014 1015 static struct snd_soc_dai_driver mchp_spdifrx_dai = { 1016 .name = "mchp-spdifrx", 1017 .capture = { 1018 .stream_name = "Capture", 1019 .channels_min = SPDIFRX_CHANNELS, 1020 .channels_max = SPDIFRX_CHANNELS, 1021 .rates = MCHP_SPDIF_RATES, 1022 .formats = MCHP_SPDIF_FORMATS, 1023 }, 1024 .ops = &mchp_spdifrx_dai_ops, 1025 }; 1026 1027 static const struct snd_soc_component_driver mchp_spdifrx_component = { 1028 .name = "mchp-spdifrx", 1029 .legacy_dai_naming = 1, 1030 }; 1031 1032 static const struct of_device_id mchp_spdifrx_dt_ids[] = { 1033 { 1034 .compatible = "microchip,sama7g5-spdifrx", 1035 }, 1036 { /* sentinel */ } 1037 }; 1038 MODULE_DEVICE_TABLE(of, mchp_spdifrx_dt_ids); 1039 1040 static int mchp_spdifrx_runtime_suspend(struct device *dev) 1041 { 1042 struct mchp_spdifrx_dev *spdifrx = dev_get_drvdata(dev); 1043 1044 regcache_cache_only(spdifrx->regmap, true); 1045 clk_disable_unprepare(spdifrx->gclk); 1046 clk_disable_unprepare(spdifrx->pclk); 1047 1048 return 0; 1049 } 1050 1051 static int mchp_spdifrx_runtime_resume(struct device *dev) 1052 { 1053 struct mchp_spdifrx_dev *spdifrx = dev_get_drvdata(dev); 1054 int ret; 1055 1056 ret = clk_prepare_enable(spdifrx->pclk); 1057 if (ret) 1058 return ret; 1059 1060 ret = clk_prepare_enable(spdifrx->gclk); 1061 if (ret) 1062 goto disable_pclk; 1063 1064 regcache_cache_only(spdifrx->regmap, false); 1065 regcache_mark_dirty(spdifrx->regmap); 1066 ret = regcache_sync(spdifrx->regmap); 1067 if (ret) { 1068 regcache_cache_only(spdifrx->regmap, true); 1069 clk_disable_unprepare(spdifrx->gclk); 1070 disable_pclk: 1071 clk_disable_unprepare(spdifrx->pclk); 1072 } 1073 1074 return ret; 1075 } 1076 1077 static const struct dev_pm_ops mchp_spdifrx_pm_ops = { 1078 RUNTIME_PM_OPS(mchp_spdifrx_runtime_suspend, mchp_spdifrx_runtime_resume, 1079 NULL) 1080 }; 1081 1082 static int mchp_spdifrx_probe(struct platform_device *pdev) 1083 { 1084 struct mchp_spdifrx_dev *dev; 1085 struct resource *mem; 1086 struct regmap *regmap; 1087 void __iomem *base; 1088 int irq; 1089 int err; 1090 u32 vers; 1091 1092 /* Get memory for driver data. */ 1093 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1094 if (!dev) 1095 return -ENOMEM; 1096 1097 /* Map I/O registers. */ 1098 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 1099 if (IS_ERR(base)) 1100 return PTR_ERR(base); 1101 1102 regmap = devm_regmap_init_mmio(&pdev->dev, base, 1103 &mchp_spdifrx_regmap_config); 1104 if (IS_ERR(regmap)) 1105 return PTR_ERR(regmap); 1106 1107 /* Request IRQ. */ 1108 irq = platform_get_irq(pdev, 0); 1109 if (irq < 0) 1110 return irq; 1111 1112 err = devm_request_irq(&pdev->dev, irq, mchp_spdif_interrupt, 0, 1113 dev_name(&pdev->dev), dev); 1114 if (err) 1115 return err; 1116 1117 /* Get the peripheral clock */ 1118 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 1119 if (IS_ERR(dev->pclk)) { 1120 err = PTR_ERR(dev->pclk); 1121 dev_err(&pdev->dev, "failed to get the peripheral clock: %d\n", 1122 err); 1123 return err; 1124 } 1125 1126 /* Get the generated clock */ 1127 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 1128 if (IS_ERR(dev->gclk)) { 1129 err = PTR_ERR(dev->gclk); 1130 dev_err(&pdev->dev, 1131 "failed to get the PMC generated clock: %d\n", err); 1132 return err; 1133 } 1134 1135 /* 1136 * Signal control need a valid rate on gclk. hw_params() configures 1137 * it propertly but requesting signal before any hw_params() has been 1138 * called lead to invalid value returned for signal. Thus, configure 1139 * gclk at a valid rate, here, in initialization, to simplify the 1140 * control path. 1141 */ 1142 clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1); 1143 1144 mutex_init(&dev->mlock); 1145 1146 dev->dev = &pdev->dev; 1147 dev->regmap = regmap; 1148 platform_set_drvdata(pdev, dev); 1149 1150 pm_runtime_enable(dev->dev); 1151 if (!pm_runtime_enabled(dev->dev)) { 1152 err = mchp_spdifrx_runtime_resume(dev->dev); 1153 if (err) 1154 goto pm_runtime_disable; 1155 } 1156 1157 dev->capture.addr = (dma_addr_t)mem->start + SPDIFRX_RHR; 1158 dev->capture.maxburst = 1; 1159 1160 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1161 if (err) { 1162 dev_err(&pdev->dev, "failed to register PCM: %d\n", err); 1163 goto pm_runtime_suspend; 1164 } 1165 1166 err = devm_snd_soc_register_component(&pdev->dev, 1167 &mchp_spdifrx_component, 1168 &mchp_spdifrx_dai, 1); 1169 if (err) { 1170 dev_err(&pdev->dev, "fail to register dai\n"); 1171 goto pm_runtime_suspend; 1172 } 1173 1174 regmap_read(regmap, SPDIFRX_VERSION, &vers); 1175 dev_info(&pdev->dev, "hw version: %#lx\n", vers & SPDIFRX_VERSION_MASK); 1176 1177 return 0; 1178 1179 pm_runtime_suspend: 1180 if (!pm_runtime_status_suspended(dev->dev)) 1181 mchp_spdifrx_runtime_suspend(dev->dev); 1182 pm_runtime_disable: 1183 pm_runtime_disable(dev->dev); 1184 return err; 1185 } 1186 1187 static void mchp_spdifrx_remove(struct platform_device *pdev) 1188 { 1189 struct mchp_spdifrx_dev *dev = platform_get_drvdata(pdev); 1190 1191 pm_runtime_disable(dev->dev); 1192 if (!pm_runtime_status_suspended(dev->dev)) 1193 mchp_spdifrx_runtime_suspend(dev->dev); 1194 } 1195 1196 static struct platform_driver mchp_spdifrx_driver = { 1197 .probe = mchp_spdifrx_probe, 1198 .remove = mchp_spdifrx_remove, 1199 .driver = { 1200 .name = "mchp_spdifrx", 1201 .of_match_table = mchp_spdifrx_dt_ids, 1202 .pm = pm_ptr(&mchp_spdifrx_pm_ops), 1203 }, 1204 }; 1205 1206 module_platform_driver(mchp_spdifrx_driver); 1207 1208 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 1209 MODULE_DESCRIPTION("Microchip S/PDIF RX Controller Driver"); 1210 MODULE_LICENSE("GPL v2"); 1211