1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 #include <linux/dmi.h> 41 42 #ifdef CONFIG_X86 43 /* for snoop control */ 44 #include <asm/set_memory.h> 45 #include <asm/cpufeature.h> 46 #endif 47 #include <sound/core.h> 48 #include <sound/initval.h> 49 #include <sound/hdaudio.h> 50 #include <sound/hda_i915.h> 51 #include <sound/intel-dsp-config.h> 52 #include <linux/vgaarb.h> 53 #include <linux/vga_switcheroo.h> 54 #include <linux/apple-gmux.h> 55 #include <linux/firmware.h> 56 #include <sound/hda_codec.h> 57 #include "intel.h" 58 59 #define CREATE_TRACE_POINTS 60 #include "intel_trace.h" 61 62 /* position fix mode */ 63 enum { 64 POS_FIX_AUTO, 65 POS_FIX_LPIB, 66 POS_FIX_POSBUF, 67 POS_FIX_VIACOMBO, 68 POS_FIX_COMBO, 69 POS_FIX_SKL, 70 POS_FIX_FIFO, 71 }; 72 73 /* Defines for ATI HD Audio support in SB450 south bridge */ 74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 76 77 /* Defines for Nvidia HDA support */ 78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 80 #define NVIDIA_HDA_ISTRM_COH 0x4d 81 #define NVIDIA_HDA_OSTRM_COH 0x4c 82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 83 84 /* Defines for Intel SCH HDA snoop control */ 85 #define INTEL_HDA_CGCTL 0x48 86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 87 #define INTEL_SCH_HDA_DEVC 0x78 88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 89 90 /* max number of SDs */ 91 /* ICH, ATI and VIA have 4 playback and 4 capture */ 92 #define ICH6_NUM_CAPTURE 4 93 #define ICH6_NUM_PLAYBACK 4 94 95 /* ULI has 6 playback and 5 capture */ 96 #define ULI_NUM_CAPTURE 5 97 #define ULI_NUM_PLAYBACK 6 98 99 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 100 #define ATIHDMI_NUM_CAPTURE 0 101 #define ATIHDMI_NUM_PLAYBACK 8 102 103 104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 107 static char *model[SNDRV_CARDS]; 108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_only[SNDRV_CARDS]; 112 static int jackpoll_ms[SNDRV_CARDS]; 113 static int single_cmd = -1; 114 static int enable_msi = -1; 115 #ifdef CONFIG_SND_HDA_PATCH_LOADER 116 static char *patch[SNDRV_CARDS]; 117 #endif 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP 119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 120 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 121 #endif 122 static bool dmic_detect = 1; 123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 124 125 module_param_array(index, int, NULL, 0444); 126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 127 module_param_array(id, charp, NULL, 0444); 128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 129 module_param_array(enable, bool, NULL, 0444); 130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 131 module_param_array(model, charp, NULL, 0444); 132 MODULE_PARM_DESC(model, "Use the given board model."); 133 module_param_array(position_fix, int, NULL, 0444); 134 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 136 module_param_array(bdl_pos_adj, int, NULL, 0644); 137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 138 module_param_array(probe_mask, int, NULL, 0444); 139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 140 module_param_array(probe_only, int, NULL, 0444); 141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 142 module_param_array(jackpoll_ms, int, NULL, 0444); 143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 144 module_param(single_cmd, bint, 0444); 145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 146 "(for debugging only)."); 147 module_param(enable_msi, bint, 0444); 148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 149 #ifdef CONFIG_SND_HDA_PATCH_LOADER 150 module_param_array(patch, charp, NULL, 0444); 151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 152 #endif 153 #ifdef CONFIG_SND_HDA_INPUT_BEEP 154 module_param_array(beep_mode, bool, NULL, 0444); 155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 156 "(0=off, 1=on) (default=1)."); 157 #endif 158 module_param(dmic_detect, bool, 0444); 159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 160 "(0=off, 1=on) (default=1); " 161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 162 module_param(ctl_dev_id, bool, 0444); 163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 164 165 #ifdef CONFIG_PM 166 static int param_set_xint(const char *val, const struct kernel_param *kp); 167 static const struct kernel_param_ops param_ops_xint = { 168 .set = param_set_xint, 169 .get = param_get_int, 170 }; 171 #define param_check_xint param_check_int 172 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 174 module_param(power_save, xint, 0644); 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 176 "(in second, 0 = disable)."); 177 178 static int pm_blacklist = -1; 179 module_param(pm_blacklist, bint, 0644); 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else /* CONFIG_PM */ 190 #define power_save 0 191 #define pm_blacklist 0 192 #define power_save_controller false 193 #endif /* CONFIG_PM */ 194 195 static int align_buffer_size = -1; 196 module_param(align_buffer_size, bint, 0644); 197 MODULE_PARM_DESC(align_buffer_size, 198 "Force buffer and period sizes to be multiple of 128 bytes."); 199 200 #ifdef CONFIG_X86 201 static int hda_snoop = -1; 202 module_param_named(snoop, hda_snoop, bint, 0444); 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 204 #else 205 #define hda_snoop true 206 #endif 207 208 209 MODULE_LICENSE("GPL"); 210 MODULE_DESCRIPTION("Intel HDA driver"); 211 212 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 213 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 214 #define SUPPORT_VGA_SWITCHEROO 215 #endif 216 #endif 217 218 219 /* 220 */ 221 222 /* driver types */ 223 enum { 224 AZX_DRIVER_ICH, 225 AZX_DRIVER_PCH, 226 AZX_DRIVER_SCH, 227 AZX_DRIVER_SKL, 228 AZX_DRIVER_HDMI, 229 AZX_DRIVER_ATI, 230 AZX_DRIVER_ATIHDMI, 231 AZX_DRIVER_ATIHDMI_NS, 232 AZX_DRIVER_GFHDMI, 233 AZX_DRIVER_VIA, 234 AZX_DRIVER_SIS, 235 AZX_DRIVER_ULI, 236 AZX_DRIVER_NVIDIA, 237 AZX_DRIVER_TERA, 238 AZX_DRIVER_CTX, 239 AZX_DRIVER_CTHDA, 240 AZX_DRIVER_CMEDIA, 241 AZX_DRIVER_ZHAOXIN, 242 AZX_DRIVER_ZHAOXINHDMI, 243 AZX_DRIVER_LOONGSON, 244 AZX_DRIVER_GENERIC, 245 AZX_NUM_DRIVERS, /* keep this as last entry */ 246 }; 247 248 #define azx_get_snoop_type(chip) \ 249 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 250 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 251 252 /* quirks for old Intel chipsets */ 253 #define AZX_DCAPS_INTEL_ICH \ 254 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 255 256 /* quirks for Intel PCH */ 257 #define AZX_DCAPS_INTEL_PCH_BASE \ 258 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 259 AZX_DCAPS_SNOOP_TYPE(SCH)) 260 261 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 262 #define AZX_DCAPS_INTEL_PCH_NOPM \ 263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 264 265 /* PCH for HSW/BDW; with runtime PM */ 266 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 267 #define AZX_DCAPS_INTEL_PCH \ 268 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 269 270 /* HSW HDMI */ 271 #define AZX_DCAPS_INTEL_HASWELL \ 272 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 273 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 274 AZX_DCAPS_SNOOP_TYPE(SCH)) 275 276 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 277 #define AZX_DCAPS_INTEL_BROADWELL \ 278 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 279 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 280 AZX_DCAPS_SNOOP_TYPE(SCH)) 281 282 #define AZX_DCAPS_INTEL_BAYTRAIL \ 283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 284 285 #define AZX_DCAPS_INTEL_BRASWELL \ 286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 287 AZX_DCAPS_I915_COMPONENT) 288 289 #define AZX_DCAPS_INTEL_SKYLAKE \ 290 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 291 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 292 293 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 294 295 #define AZX_DCAPS_INTEL_LNL \ 296 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS) 297 298 #define AZX_DCAPS_INTEL_NVL \ 299 (AZX_DCAPS_INTEL_LNL & ~AZX_DCAPS_NO_ALIGN_BUFSIZE) 300 301 /* quirks for ATI SB / AMD Hudson */ 302 #define AZX_DCAPS_PRESET_ATI_SB \ 303 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 304 AZX_DCAPS_SNOOP_TYPE(ATI)) 305 306 /* quirks for ATI/AMD HDMI */ 307 #define AZX_DCAPS_PRESET_ATI_HDMI \ 308 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 309 AZX_DCAPS_NO_MSI64) 310 311 /* quirks for ATI HDMI with snoop off */ 312 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 313 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 314 315 /* quirks for AMD SB */ 316 #define AZX_DCAPS_PRESET_AMD_SB \ 317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 318 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 319 AZX_DCAPS_RETRY_PROBE) 320 321 /* quirks for Nvidia */ 322 #define AZX_DCAPS_PRESET_NVIDIA \ 323 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 324 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 325 326 #define AZX_DCAPS_PRESET_CTHDA \ 327 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 328 AZX_DCAPS_NO_64BIT |\ 329 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 330 331 /* 332 * vga_switcheroo support 333 */ 334 #ifdef SUPPORT_VGA_SWITCHEROO 335 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 336 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 337 #else 338 #define use_vga_switcheroo(chip) 0 339 #define needs_eld_notify_link(chip) false 340 #endif 341 342 static const char * const driver_short_names[] = { 343 [AZX_DRIVER_ICH] = "HDA Intel", 344 [AZX_DRIVER_PCH] = "HDA Intel PCH", 345 [AZX_DRIVER_SCH] = "HDA Intel MID", 346 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 348 [AZX_DRIVER_ATI] = "HDA ATI SB", 349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 351 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 352 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 353 [AZX_DRIVER_SIS] = "HDA SIS966", 354 [AZX_DRIVER_ULI] = "HDA ULI M5461", 355 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 356 [AZX_DRIVER_TERA] = "HDA Teradici", 357 [AZX_DRIVER_CTX] = "HDA Creative", 358 [AZX_DRIVER_CTHDA] = "HDA Creative", 359 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 360 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 361 [AZX_DRIVER_ZHAOXINHDMI] = "HDA Zhaoxin HDMI", 362 [AZX_DRIVER_LOONGSON] = "HDA Loongson", 363 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 364 }; 365 366 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 367 static void set_default_power_save(struct azx *chip); 368 369 /* 370 * initialize the PCI registers 371 */ 372 /* update bits in a PCI register byte */ 373 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 374 unsigned char mask, unsigned char val) 375 { 376 unsigned char data; 377 378 pci_read_config_byte(pci, reg, &data); 379 data &= ~mask; 380 data |= (val & mask); 381 pci_write_config_byte(pci, reg, data); 382 } 383 384 static void azx_init_pci(struct azx *chip) 385 { 386 int snoop_type = azx_get_snoop_type(chip); 387 388 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 389 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 390 * Ensuring these bits are 0 clears playback static on some HD Audio 391 * codecs. 392 * The PCI register TCSEL is defined in the Intel manuals. 393 */ 394 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 395 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 396 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 397 } 398 399 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 400 * we need to enable snoop. 401 */ 402 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 403 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 404 azx_snoop(chip)); 405 update_pci_byte(chip->pci, 406 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 407 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 408 } 409 410 /* For NVIDIA HDA, enable snoop */ 411 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 412 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 413 azx_snoop(chip)); 414 update_pci_byte(chip->pci, 415 NVIDIA_HDA_TRANSREG_ADDR, 416 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 417 update_pci_byte(chip->pci, 418 NVIDIA_HDA_ISTRM_COH, 419 0x01, NVIDIA_HDA_ENABLE_COHBIT); 420 update_pci_byte(chip->pci, 421 NVIDIA_HDA_OSTRM_COH, 422 0x01, NVIDIA_HDA_ENABLE_COHBIT); 423 } 424 425 /* Enable SCH/PCH snoop if needed */ 426 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 427 unsigned short snoop; 428 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 429 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 430 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 431 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 432 if (!azx_snoop(chip)) 433 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 434 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 435 pci_read_config_word(chip->pci, 436 INTEL_SCH_HDA_DEVC, &snoop); 437 } 438 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 439 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 440 "Disabled" : "Enabled"); 441 } 442 } 443 444 /* 445 * In BXT-P A0, HD-Audio DMA requests is later than expected, 446 * and makes an audio stream sensitive to system latencies when 447 * 24/32 bits are playing. 448 * Adjusting threshold of DMA fifo to force the DMA request 449 * sooner to improve latency tolerance at the expense of power. 450 */ 451 static void bxt_reduce_dma_latency(struct azx *chip) 452 { 453 u32 val; 454 455 val = azx_readl(chip, VS_EM4L); 456 val &= (0x3 << 20); 457 azx_writel(chip, VS_EM4L, val); 458 } 459 460 /* 461 * ML_LCAP bits: 462 * bit 0: 6 MHz Supported 463 * bit 1: 12 MHz Supported 464 * bit 2: 24 MHz Supported 465 * bit 3: 48 MHz Supported 466 * bit 4: 96 MHz Supported 467 * bit 5: 192 MHz Supported 468 */ 469 static int intel_get_lctl_scf(struct azx *chip) 470 { 471 struct hdac_bus *bus = azx_bus(chip); 472 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 473 u32 val, t; 474 int i; 475 476 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 477 478 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 479 t = preferred_bits[i]; 480 if (val & (1 << t)) 481 return t; 482 } 483 484 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 485 return 0; 486 } 487 488 static int intel_ml_lctl_set_power(struct azx *chip, int state) 489 { 490 struct hdac_bus *bus = azx_bus(chip); 491 u32 val; 492 int timeout; 493 494 /* 495 * Changes to LCTL.SCF are only needed for the first multi-link dealing 496 * with external codecs 497 */ 498 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 499 val &= ~AZX_ML_LCTL_SPA; 500 val |= state << AZX_ML_LCTL_SPA_SHIFT; 501 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 502 /* wait for CPA */ 503 timeout = 50; 504 while (timeout) { 505 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 506 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 507 return 0; 508 timeout--; 509 udelay(10); 510 } 511 512 return -1; 513 } 514 515 static void intel_init_lctl(struct azx *chip) 516 { 517 struct hdac_bus *bus = azx_bus(chip); 518 u32 val; 519 int ret; 520 521 /* 0. check lctl register value is correct or not */ 522 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 523 /* only perform additional configurations if the SCF is initially based on 6MHz */ 524 if ((val & AZX_ML_LCTL_SCF) != 0) 525 return; 526 527 /* 528 * Before operating on SPA, CPA must match SPA. 529 * Any deviation may result in undefined behavior. 530 */ 531 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 532 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 533 return; 534 535 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 536 ret = intel_ml_lctl_set_power(chip, 0); 537 udelay(100); 538 if (ret) 539 goto set_spa; 540 541 /* 2. update SCF to select an audio clock different from 6MHz */ 542 val &= ~AZX_ML_LCTL_SCF; 543 val |= intel_get_lctl_scf(chip); 544 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 545 546 set_spa: 547 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 548 intel_ml_lctl_set_power(chip, 1); 549 udelay(100); 550 } 551 552 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 553 { 554 struct hdac_bus *bus = azx_bus(chip); 555 struct pci_dev *pci = chip->pci; 556 u32 val; 557 558 snd_hdac_set_codec_wakeup(bus, true); 559 if (chip->driver_type == AZX_DRIVER_SKL) { 560 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 561 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 562 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 563 } 564 azx_init_chip(chip, full_reset); 565 if (chip->driver_type == AZX_DRIVER_SKL) { 566 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 567 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 568 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 569 } 570 571 snd_hdac_set_codec_wakeup(bus, false); 572 573 /* reduce dma latency to avoid noise */ 574 if (HDA_CONTROLLER_IS_APL(pci)) 575 bxt_reduce_dma_latency(chip); 576 577 if (bus->mlcap != NULL) 578 intel_init_lctl(chip); 579 } 580 581 /* calculate runtime delay from LPIB */ 582 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 583 unsigned int pos) 584 { 585 struct snd_pcm_substream *substream = azx_dev->core.substream; 586 int stream = substream->stream; 587 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 588 int delay; 589 590 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 591 delay = pos - lpib_pos; 592 else 593 delay = lpib_pos - pos; 594 if (delay < 0) { 595 if (delay >= azx_dev->core.delay_negative_threshold) 596 delay = 0; 597 else 598 delay += azx_dev->core.bufsize; 599 } 600 601 if (delay >= azx_dev->core.period_bytes) { 602 dev_info(chip->card->dev, 603 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 604 delay, azx_dev->core.period_bytes); 605 delay = 0; 606 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 607 chip->get_delay[stream] = NULL; 608 } 609 610 return bytes_to_frames(substream->runtime, delay); 611 } 612 613 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 614 615 /* called from IRQ */ 616 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 617 { 618 struct hda_intel_stream *istream = azx_dev_to_istream(azx_dev); 619 int ok; 620 621 ok = azx_position_ok(chip, azx_dev); 622 if (ok == 1) { 623 istream->irq_pending = false; 624 return ok; 625 } else if (ok == 0) { 626 /* bogus IRQ, process it later */ 627 istream->irq_pending = true; 628 schedule_work(&istream->irq_pending_work); 629 } 630 return 0; 631 } 632 633 #define display_power(chip, enable) \ 634 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 635 636 /* 637 * Check whether the current DMA position is acceptable for updating 638 * periods. Returns non-zero if it's OK. 639 * 640 * Many HD-audio controllers appear pretty inaccurate about 641 * the update-IRQ timing. The IRQ is issued before actually the 642 * data is processed. So, we need to process it afterwords in a 643 * workqueue. 644 * 645 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 646 */ 647 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 648 { 649 struct snd_pcm_substream *substream = azx_dev->core.substream; 650 struct snd_pcm_runtime *runtime = substream->runtime; 651 int stream = substream->stream; 652 u32 wallclk; 653 unsigned int pos; 654 snd_pcm_uframes_t hwptr, target; 655 656 /* 657 * The value of the WALLCLK register is always 0 658 * on the Loongson controller, so we return directly. 659 */ 660 if (chip->driver_type == AZX_DRIVER_LOONGSON) 661 return 1; 662 663 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 664 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 665 return -1; /* bogus (too early) interrupt */ 666 667 if (chip->get_position[stream]) 668 pos = chip->get_position[stream](chip, azx_dev); 669 else { /* use the position buffer as default */ 670 pos = azx_get_pos_posbuf(chip, azx_dev); 671 if (!pos || pos == (u32)-1) { 672 dev_info(chip->card->dev, 673 "Invalid position buffer, using LPIB read method instead.\n"); 674 chip->get_position[stream] = azx_get_pos_lpib; 675 if (chip->get_position[0] == azx_get_pos_lpib && 676 chip->get_position[1] == azx_get_pos_lpib) 677 azx_bus(chip)->use_posbuf = false; 678 pos = azx_get_pos_lpib(chip, azx_dev); 679 chip->get_delay[stream] = NULL; 680 } else { 681 chip->get_position[stream] = azx_get_pos_posbuf; 682 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 683 chip->get_delay[stream] = azx_get_delay_from_lpib; 684 } 685 } 686 687 if (pos >= azx_dev->core.bufsize) 688 pos = 0; 689 690 if (WARN_ONCE(!azx_dev->core.period_bytes, 691 "hda-intel: zero azx_dev->period_bytes")) 692 return -1; /* this shouldn't happen! */ 693 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 694 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 695 /* NG - it's below the first next period boundary */ 696 return chip->bdl_pos_adj ? 0 : -1; 697 azx_dev->core.start_wallclk += wallclk; 698 699 if (azx_dev->core.no_period_wakeup) 700 return 1; /* OK, no need to check period boundary */ 701 702 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 703 return 1; /* OK, already in hwptr updating process */ 704 705 /* check whether the period gets really elapsed */ 706 pos = bytes_to_frames(runtime, pos); 707 hwptr = runtime->hw_ptr_base + pos; 708 if (hwptr < runtime->status->hw_ptr) 709 hwptr += runtime->buffer_size; 710 target = runtime->hw_ptr_interrupt + runtime->period_size; 711 if (hwptr < target) { 712 /* too early wakeup, process it later */ 713 return chip->bdl_pos_adj ? 0 : -1; 714 } 715 716 return 1; /* OK, it's fine */ 717 } 718 719 /* 720 * The work for pending PCM period updates. 721 */ 722 static void azx_irq_pending_work(struct work_struct *work) 723 { 724 struct hda_intel_stream *istream = 725 container_of(work, struct hda_intel_stream, irq_pending_work); 726 struct azx_dev *azx_dev = &istream->azx_dev; 727 struct hda_intel *hda = istream->hda; 728 struct azx *chip = &hda->chip; 729 struct hdac_bus *bus = azx_bus(chip); 730 int ok; 731 732 if (!hda->irq_pending_warned) { 733 dev_info(chip->card->dev, 734 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 735 chip->card->number); 736 hda->irq_pending_warned = 1; 737 } 738 739 for (;;) { 740 scoped_guard(spinlock_irq, &bus->reg_lock) { 741 if (!istream->irq_pending || 742 !azx_dev->core.substream || 743 !azx_dev->core.running) { 744 return; 745 } 746 747 ok = azx_position_ok(chip, azx_dev); 748 if (ok < 0) 749 return; /* too early */ 750 if (ok > 0) 751 istream->irq_pending = false; 752 } 753 754 if (ok) { 755 snd_pcm_period_elapsed(azx_dev->core.substream); 756 return; 757 } 758 759 msleep(1); 760 } 761 } 762 763 /* clear irq_pending flags and assure no on-going workq */ 764 static void hda_intel_stream_clear_irq_pending(struct azx_dev *azx_dev) 765 { 766 struct hda_intel_stream *istream = azx_dev_to_istream(azx_dev); 767 768 istream->irq_pending = false; 769 cancel_work_sync(&istream->irq_pending_work); 770 } 771 772 /* called at PCM close */ 773 static void hda_intel_pcm_close(struct azx *chip, struct azx_dev *azx_dev) 774 { 775 hda_intel_stream_clear_irq_pending(azx_dev); 776 } 777 778 static void azx_clear_irq_pending(struct azx *chip) 779 { 780 struct hdac_bus *bus = azx_bus(chip); 781 struct hdac_stream *s; 782 783 list_for_each_entry(s, &bus->stream_list, list) { 784 hda_intel_stream_clear_irq_pending(stream_to_azx_dev(s)); 785 } 786 } 787 788 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 789 { 790 struct hdac_bus *bus = azx_bus(chip); 791 int ret; 792 793 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) { 794 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX); 795 if (ret < 0) 796 return ret; 797 chip->msi = 0; 798 } 799 800 if (request_irq(chip->pci->irq, azx_interrupt, 801 chip->msi ? 0 : IRQF_SHARED, 802 chip->card->irq_descr, chip)) { 803 dev_err(chip->card->dev, 804 "unable to grab IRQ %d, disabling device\n", 805 chip->pci->irq); 806 if (do_disconnect) 807 snd_card_disconnect(chip->card); 808 return -1; 809 } 810 bus->irq = chip->pci->irq; 811 chip->card->sync_irq = bus->irq; 812 return 0; 813 } 814 815 /* get the current DMA position with correction on VIA chips */ 816 static unsigned int azx_via_get_position(struct azx *chip, 817 struct azx_dev *azx_dev) 818 { 819 unsigned int link_pos, mini_pos, bound_pos; 820 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 821 unsigned int fifo_size; 822 823 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 824 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 825 /* Playback, no problem using link position */ 826 return link_pos; 827 } 828 829 /* Capture */ 830 /* For new chipset, 831 * use mod to get the DMA position just like old chipset 832 */ 833 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 834 mod_dma_pos %= azx_dev->core.period_bytes; 835 836 fifo_size = azx_stream(azx_dev)->fifo_size; 837 838 if (azx_dev->insufficient) { 839 /* Link position never gather than FIFO size */ 840 if (link_pos <= fifo_size) 841 return 0; 842 843 azx_dev->insufficient = 0; 844 } 845 846 if (link_pos <= fifo_size) 847 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 848 else 849 mini_pos = link_pos - fifo_size; 850 851 /* Find nearest previous boudary */ 852 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 853 mod_link_pos = link_pos % azx_dev->core.period_bytes; 854 if (mod_link_pos >= fifo_size) 855 bound_pos = link_pos - mod_link_pos; 856 else if (mod_dma_pos >= mod_mini_pos) 857 bound_pos = mini_pos - mod_mini_pos; 858 else { 859 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 860 if (bound_pos >= azx_dev->core.bufsize) 861 bound_pos = 0; 862 } 863 864 /* Calculate real DMA position we want */ 865 return bound_pos + mod_dma_pos; 866 } 867 868 #define AMD_FIFO_SIZE 32 869 870 /* get the current DMA position with FIFO size correction */ 871 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 872 { 873 struct snd_pcm_substream *substream = azx_dev->core.substream; 874 struct snd_pcm_runtime *runtime = substream->runtime; 875 unsigned int pos, delay; 876 877 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 878 if (!runtime) 879 return pos; 880 881 runtime->delay = AMD_FIFO_SIZE; 882 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 883 if (azx_dev->insufficient) { 884 if (pos < delay) { 885 delay = pos; 886 runtime->delay = bytes_to_frames(runtime, pos); 887 } else { 888 azx_dev->insufficient = 0; 889 } 890 } 891 892 /* correct the DMA position for capture stream */ 893 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 894 if (pos < delay) 895 pos += azx_dev->core.bufsize; 896 pos -= delay; 897 } 898 899 return pos; 900 } 901 902 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 903 unsigned int pos) 904 { 905 struct snd_pcm_substream *substream = azx_dev->core.substream; 906 907 /* just read back the calculated value in the above */ 908 return substream->runtime->delay; 909 } 910 911 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 912 { 913 azx_stop_chip(chip); 914 if (!skip_link_reset) 915 azx_enter_link_reset(chip); 916 azx_clear_irq_pending(chip); 917 display_power(chip, false); 918 } 919 920 static DEFINE_MUTEX(card_list_lock); 921 static LIST_HEAD(card_list); 922 923 static void azx_shutdown_chip(struct azx *chip) 924 { 925 __azx_shutdown_chip(chip, false); 926 } 927 928 static void azx_add_card_list(struct azx *chip) 929 { 930 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 931 932 guard(mutex)(&card_list_lock); 933 list_add(&hda->list, &card_list); 934 } 935 936 static void azx_del_card_list(struct azx *chip) 937 { 938 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 939 940 guard(mutex)(&card_list_lock); 941 list_del_init(&hda->list); 942 } 943 944 /* trigger power-save check at writing parameter */ 945 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp) 946 { 947 struct hda_intel *hda; 948 struct azx *chip; 949 int prev = power_save; 950 int ret = param_set_int(val, kp); 951 952 if (ret || prev == power_save) 953 return ret; 954 955 if (pm_blacklist > 0) 956 return 0; 957 958 guard(mutex)(&card_list_lock); 959 list_for_each_entry(hda, &card_list, list) { 960 chip = &hda->chip; 961 if (!hda->probe_continued || chip->disabled || 962 hda->runtime_pm_disabled) 963 continue; 964 snd_hda_set_power_save(&chip->bus, power_save * 1000); 965 } 966 return 0; 967 } 968 969 /* 970 * power management 971 */ 972 static bool azx_is_pm_ready(struct snd_card *card) 973 { 974 struct azx *chip; 975 struct hda_intel *hda; 976 977 if (!card) 978 return false; 979 chip = card->private_data; 980 hda = container_of(chip, struct hda_intel, chip); 981 if (chip->disabled || hda->init_failed || !chip->running) 982 return false; 983 return true; 984 } 985 986 static void __azx_runtime_resume(struct azx *chip) 987 { 988 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 989 struct hdac_bus *bus = azx_bus(chip); 990 struct hda_codec *codec; 991 int status; 992 993 display_power(chip, true); 994 if (hda->need_i915_power) 995 snd_hdac_i915_set_bclk(bus); 996 997 /* Read STATESTS before controller reset */ 998 status = azx_readw(chip, STATESTS); 999 1000 azx_init_pci(chip); 1001 hda_intel_init_chip(chip, true); 1002 1003 /* Avoid codec resume if runtime resume is for system suspend */ 1004 if (!chip->pm_prepared) { 1005 list_for_each_codec(codec, &chip->bus) { 1006 if (codec->relaxed_resume) 1007 continue; 1008 1009 if (codec->forced_resume || (status & (1 << codec->addr))) 1010 pm_request_resume(hda_codec_dev(codec)); 1011 } 1012 } 1013 1014 /* power down again for link-controlled chips */ 1015 if (!hda->need_i915_power) 1016 display_power(chip, false); 1017 } 1018 1019 static int azx_prepare(struct device *dev) 1020 { 1021 struct snd_card *card = dev_get_drvdata(dev); 1022 struct azx *chip; 1023 1024 if (!azx_is_pm_ready(card)) 1025 return 0; 1026 1027 chip = card->private_data; 1028 chip->pm_prepared = 1; 1029 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1030 1031 flush_work(&azx_bus(chip)->unsol_work); 1032 1033 /* HDA controller always requires different WAKEEN for runtime suspend 1034 * and system suspend, so don't use direct-complete here. 1035 */ 1036 return 0; 1037 } 1038 1039 static void azx_complete(struct device *dev) 1040 { 1041 struct snd_card *card = dev_get_drvdata(dev); 1042 struct azx *chip; 1043 1044 if (!azx_is_pm_ready(card)) 1045 return; 1046 1047 chip = card->private_data; 1048 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1049 chip->pm_prepared = 0; 1050 } 1051 1052 static int azx_suspend(struct device *dev) 1053 { 1054 struct snd_card *card = dev_get_drvdata(dev); 1055 struct azx *chip; 1056 1057 if (!azx_is_pm_ready(card)) 1058 return 0; 1059 1060 chip = card->private_data; 1061 azx_shutdown_chip(chip); 1062 1063 trace_azx_suspend(chip); 1064 return 0; 1065 } 1066 1067 static int azx_resume(struct device *dev) 1068 { 1069 struct snd_card *card = dev_get_drvdata(dev); 1070 struct azx *chip; 1071 1072 if (!azx_is_pm_ready(card)) 1073 return 0; 1074 1075 chip = card->private_data; 1076 1077 __azx_runtime_resume(chip); 1078 1079 trace_azx_resume(chip); 1080 return 0; 1081 } 1082 1083 /* put codec down to D3 at hibernation for Intel SKL+; 1084 * otherwise BIOS may still access the codec and screw up the driver 1085 */ 1086 static int azx_freeze_noirq(struct device *dev) 1087 { 1088 struct snd_card *card = dev_get_drvdata(dev); 1089 struct azx *chip = card->private_data; 1090 struct pci_dev *pci = to_pci_dev(dev); 1091 1092 if (!azx_is_pm_ready(card)) 1093 return 0; 1094 if (chip->driver_type == AZX_DRIVER_SKL) 1095 pci_set_power_state(pci, PCI_D3hot); 1096 1097 return 0; 1098 } 1099 1100 static int azx_thaw_noirq(struct device *dev) 1101 { 1102 struct snd_card *card = dev_get_drvdata(dev); 1103 struct azx *chip = card->private_data; 1104 struct pci_dev *pci = to_pci_dev(dev); 1105 1106 if (!azx_is_pm_ready(card)) 1107 return 0; 1108 if (chip->driver_type == AZX_DRIVER_SKL) 1109 pci_set_power_state(pci, PCI_D0); 1110 1111 return 0; 1112 } 1113 1114 static int azx_runtime_suspend(struct device *dev) 1115 { 1116 struct snd_card *card = dev_get_drvdata(dev); 1117 struct azx *chip; 1118 1119 if (!azx_is_pm_ready(card)) 1120 return 0; 1121 chip = card->private_data; 1122 1123 /* enable controller wake up event */ 1124 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1125 1126 azx_shutdown_chip(chip); 1127 trace_azx_runtime_suspend(chip); 1128 return 0; 1129 } 1130 1131 static int azx_runtime_resume(struct device *dev) 1132 { 1133 struct snd_card *card = dev_get_drvdata(dev); 1134 struct azx *chip; 1135 1136 if (!azx_is_pm_ready(card)) 1137 return 0; 1138 chip = card->private_data; 1139 __azx_runtime_resume(chip); 1140 1141 /* disable controller Wake Up event*/ 1142 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1143 1144 trace_azx_runtime_resume(chip); 1145 return 0; 1146 } 1147 1148 static int azx_runtime_idle(struct device *dev) 1149 { 1150 struct snd_card *card = dev_get_drvdata(dev); 1151 struct azx *chip; 1152 struct hda_intel *hda; 1153 1154 if (!card) 1155 return 0; 1156 1157 chip = card->private_data; 1158 hda = container_of(chip, struct hda_intel, chip); 1159 if (chip->disabled || hda->init_failed) 1160 return 0; 1161 1162 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1163 azx_bus(chip)->codec_powered || !chip->running) 1164 return -EBUSY; 1165 1166 /* ELD notification gets broken when HD-audio bus is off */ 1167 if (needs_eld_notify_link(chip)) 1168 return -EBUSY; 1169 1170 return 0; 1171 } 1172 1173 static const struct dev_pm_ops azx_pm = { 1174 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1175 .prepare = pm_sleep_ptr(azx_prepare), 1176 .complete = pm_sleep_ptr(azx_complete), 1177 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq), 1178 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq), 1179 RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1180 }; 1181 1182 1183 static int azx_probe_continue(struct azx *chip); 1184 1185 #ifdef SUPPORT_VGA_SWITCHEROO 1186 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1187 1188 static void azx_vs_set_state(struct pci_dev *pci, 1189 enum vga_switcheroo_state state) 1190 { 1191 struct snd_card *card = pci_get_drvdata(pci); 1192 struct azx *chip = card->private_data; 1193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1194 struct hda_codec *codec; 1195 bool disabled; 1196 1197 wait_for_completion(&hda->probe_wait); 1198 if (hda->init_failed) 1199 return; 1200 1201 disabled = (state == VGA_SWITCHEROO_OFF); 1202 if (chip->disabled == disabled) 1203 return; 1204 1205 if (!hda->probe_continued) { 1206 chip->disabled = disabled; 1207 if (!disabled) { 1208 dev_info(chip->card->dev, 1209 "Start delayed initialization\n"); 1210 if (azx_probe_continue(chip) < 0) 1211 dev_err(chip->card->dev, "initialization error\n"); 1212 } 1213 } else { 1214 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1215 disabled ? "Disabling" : "Enabling"); 1216 if (disabled) { 1217 list_for_each_codec(codec, &chip->bus) { 1218 pm_runtime_suspend(hda_codec_dev(codec)); 1219 pm_runtime_disable(hda_codec_dev(codec)); 1220 } 1221 pm_runtime_suspend(card->dev); 1222 pm_runtime_disable(card->dev); 1223 /* when we get suspended by vga_switcheroo we end up in D3cold, 1224 * however we have no ACPI handle, so pci/acpi can't put us there, 1225 * put ourselves there */ 1226 pci->current_state = PCI_D3cold; 1227 chip->disabled = true; 1228 if (snd_hda_lock_devices(&chip->bus)) 1229 dev_warn(chip->card->dev, 1230 "Cannot lock devices!\n"); 1231 } else { 1232 snd_hda_unlock_devices(&chip->bus); 1233 chip->disabled = false; 1234 pm_runtime_enable(card->dev); 1235 list_for_each_codec(codec, &chip->bus) { 1236 pm_runtime_enable(hda_codec_dev(codec)); 1237 pm_runtime_resume(hda_codec_dev(codec)); 1238 } 1239 } 1240 } 1241 } 1242 1243 static bool azx_vs_can_switch(struct pci_dev *pci) 1244 { 1245 struct snd_card *card = pci_get_drvdata(pci); 1246 struct azx *chip = card->private_data; 1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1248 1249 wait_for_completion(&hda->probe_wait); 1250 if (hda->init_failed) 1251 return false; 1252 if (chip->disabled || !hda->probe_continued) 1253 return true; 1254 if (snd_hda_lock_devices(&chip->bus)) 1255 return false; 1256 snd_hda_unlock_devices(&chip->bus); 1257 return true; 1258 } 1259 1260 /* 1261 * The discrete GPU cannot power down unless the HDA controller runtime 1262 * suspends, so activate runtime PM on codecs even if power_save == 0. 1263 */ 1264 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1265 { 1266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1267 struct hda_codec *codec; 1268 1269 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1270 list_for_each_codec(codec, &chip->bus) 1271 codec->auto_runtime_pm = 1; 1272 /* reset the power save setup */ 1273 if (chip->running) 1274 set_default_power_save(chip); 1275 } 1276 } 1277 1278 static void azx_vs_gpu_bound(struct pci_dev *pci, 1279 enum vga_switcheroo_client_id client_id) 1280 { 1281 struct snd_card *card = pci_get_drvdata(pci); 1282 struct azx *chip = card->private_data; 1283 1284 if (client_id == VGA_SWITCHEROO_DIS) 1285 chip->bus.keep_power = 0; 1286 setup_vga_switcheroo_runtime_pm(chip); 1287 } 1288 1289 static void init_vga_switcheroo(struct azx *chip) 1290 { 1291 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1292 struct pci_dev *p = get_bound_vga(chip->pci); 1293 struct pci_dev *parent; 1294 if (p) { 1295 dev_info(chip->card->dev, 1296 "Handle vga_switcheroo audio client\n"); 1297 hda->use_vga_switcheroo = 1; 1298 1299 /* cleared in either gpu_bound op or codec probe, or when its 1300 * upstream port has _PR3 (i.e. dGPU). 1301 */ 1302 parent = pci_upstream_bridge(p); 1303 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1304 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1305 pci_dev_put(p); 1306 } 1307 } 1308 1309 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1310 .set_gpu_state = azx_vs_set_state, 1311 .can_switch = azx_vs_can_switch, 1312 .gpu_bound = azx_vs_gpu_bound, 1313 }; 1314 1315 static int register_vga_switcheroo(struct azx *chip) 1316 { 1317 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1318 struct pci_dev *p; 1319 int err; 1320 1321 if (!hda->use_vga_switcheroo) 1322 return 0; 1323 1324 p = get_bound_vga(chip->pci); 1325 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1326 pci_dev_put(p); 1327 1328 if (err < 0) 1329 return err; 1330 hda->vga_switcheroo_registered = 1; 1331 1332 return 0; 1333 } 1334 #else 1335 #define init_vga_switcheroo(chip) /* NOP */ 1336 #define register_vga_switcheroo(chip) 0 1337 #define check_hdmi_disabled(pci) false 1338 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1339 #endif /* SUPPORT_VGA_SWITCHER */ 1340 1341 /* 1342 * destructor 1343 */ 1344 static void azx_free(struct azx *chip) 1345 { 1346 struct pci_dev *pci = chip->pci; 1347 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1348 struct hdac_bus *bus = azx_bus(chip); 1349 1350 if (hda->freed) 1351 return; 1352 1353 if (azx_has_pm_runtime(chip) && chip->running) { 1354 pm_runtime_get_noresume(&pci->dev); 1355 pm_runtime_forbid(&pci->dev); 1356 pm_runtime_dont_use_autosuspend(&pci->dev); 1357 } 1358 1359 chip->running = 0; 1360 1361 azx_del_card_list(chip); 1362 1363 hda->init_failed = 1; /* to be sure */ 1364 complete_all(&hda->probe_wait); 1365 1366 if (use_vga_switcheroo(hda)) { 1367 if (chip->disabled && hda->probe_continued) 1368 snd_hda_unlock_devices(&chip->bus); 1369 if (hda->vga_switcheroo_registered) { 1370 vga_switcheroo_unregister_client(chip->pci); 1371 1372 /* Some GPUs don't have sound, and azx_first_init fails, 1373 * leaving the device probed but non-functional. As long 1374 * as it's probed, the PCI subsystem keeps its runtime 1375 * PM status as active. Force it to suspended (as we 1376 * actually stop the chip) to allow GPU to suspend via 1377 * vga_switcheroo, and print a warning. 1378 */ 1379 dev_warn(&pci->dev, "GPU sound probed, but not operational: please add a quirk to driver_denylist\n"); 1380 pm_runtime_disable(&pci->dev); 1381 pm_runtime_set_suspended(&pci->dev); 1382 pm_runtime_enable(&pci->dev); 1383 } 1384 } 1385 1386 if (bus->chip_init) { 1387 azx_clear_irq_pending(chip); 1388 azx_stop_all_streams(chip); 1389 azx_stop_chip(chip); 1390 } 1391 1392 if (bus->irq >= 0) 1393 free_irq(bus->irq, (void*)chip); 1394 1395 azx_free_stream_pages(chip); 1396 azx_free_streams(chip); 1397 snd_hdac_bus_exit(bus); 1398 1399 display_power(chip, false); 1400 1401 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1402 snd_hdac_i915_exit(bus); 1403 1404 hda->freed = 1; 1405 } 1406 1407 static int azx_dev_disconnect(struct snd_device *device) 1408 { 1409 struct azx *chip = device->device_data; 1410 struct hdac_bus *bus = azx_bus(chip); 1411 1412 chip->bus.shutdown = 1; 1413 cancel_work_sync(&bus->unsol_work); 1414 1415 return 0; 1416 } 1417 1418 static int azx_dev_free(struct snd_device *device) 1419 { 1420 azx_free(device->device_data); 1421 return 0; 1422 } 1423 1424 #ifdef SUPPORT_VGA_SWITCHEROO 1425 #ifdef CONFIG_ACPI 1426 /* ATPX is in the integrated GPU's namespace */ 1427 static bool atpx_present(void) 1428 { 1429 struct pci_dev *pdev = NULL; 1430 acpi_handle dhandle, atpx_handle; 1431 acpi_status status; 1432 1433 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) { 1434 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) && 1435 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8)) 1436 continue; 1437 1438 dhandle = ACPI_HANDLE(&pdev->dev); 1439 if (dhandle) { 1440 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1441 if (ACPI_SUCCESS(status)) { 1442 pci_dev_put(pdev); 1443 return true; 1444 } 1445 } 1446 } 1447 return false; 1448 } 1449 #else 1450 static bool atpx_present(void) 1451 { 1452 return false; 1453 } 1454 #endif 1455 1456 /* 1457 * Check of disabled HDMI controller by vga_switcheroo 1458 */ 1459 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1460 { 1461 struct pci_dev *p; 1462 1463 /* check only discrete GPU */ 1464 switch (pci->vendor) { 1465 case PCI_VENDOR_ID_ATI: 1466 case PCI_VENDOR_ID_AMD: 1467 if (pci->devfn == 1) { 1468 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1469 pci->bus->number, 0); 1470 if (p) { 1471 /* ATPX is in the integrated GPU's ACPI namespace 1472 * rather than the dGPU's namespace. However, 1473 * the dGPU is the one who is involved in 1474 * vgaswitcheroo. 1475 */ 1476 if (pci_is_display(p) && 1477 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1478 return p; 1479 pci_dev_put(p); 1480 } 1481 } 1482 break; 1483 case PCI_VENDOR_ID_NVIDIA: 1484 if (pci->devfn == 1) { 1485 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1486 pci->bus->number, 0); 1487 if (p) { 1488 if (pci_is_display(p)) 1489 return p; 1490 pci_dev_put(p); 1491 } 1492 } 1493 break; 1494 } 1495 return NULL; 1496 } 1497 1498 static bool check_hdmi_disabled(struct pci_dev *pci) 1499 { 1500 bool vga_inactive = false; 1501 struct pci_dev *p = get_bound_vga(pci); 1502 1503 if (p) { 1504 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1505 vga_inactive = true; 1506 pci_dev_put(p); 1507 } 1508 return vga_inactive; 1509 } 1510 #endif /* SUPPORT_VGA_SWITCHEROO */ 1511 1512 /* 1513 * allow/deny-listing for position_fix 1514 */ 1515 static const struct snd_pci_quirk position_fix_list[] = { 1516 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1519 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1520 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1521 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1522 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1523 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1524 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1525 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1526 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1527 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1528 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1529 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1530 {} 1531 }; 1532 1533 static int check_position_fix(struct azx *chip, int fix) 1534 { 1535 const struct snd_pci_quirk *q; 1536 1537 switch (fix) { 1538 case POS_FIX_AUTO: 1539 case POS_FIX_LPIB: 1540 case POS_FIX_POSBUF: 1541 case POS_FIX_VIACOMBO: 1542 case POS_FIX_COMBO: 1543 case POS_FIX_SKL: 1544 case POS_FIX_FIFO: 1545 return fix; 1546 } 1547 1548 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1549 if (q) { 1550 dev_info(chip->card->dev, 1551 "position_fix set to %d for device %04x:%04x\n", 1552 q->value, q->subvendor, q->subdevice); 1553 return q->value; 1554 } 1555 1556 /* Check VIA/ATI HD Audio Controller exist */ 1557 if (chip->driver_type == AZX_DRIVER_VIA) { 1558 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1559 return POS_FIX_VIACOMBO; 1560 } 1561 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1562 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1563 return POS_FIX_FIFO; 1564 } 1565 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1566 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1567 return POS_FIX_LPIB; 1568 } 1569 if (chip->driver_type == AZX_DRIVER_SKL) { 1570 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1571 return POS_FIX_SKL; 1572 } 1573 return POS_FIX_AUTO; 1574 } 1575 1576 static void assign_position_fix(struct azx *chip, int fix) 1577 { 1578 static const azx_get_pos_callback_t callbacks[] = { 1579 [POS_FIX_AUTO] = NULL, 1580 [POS_FIX_LPIB] = azx_get_pos_lpib, 1581 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1582 [POS_FIX_VIACOMBO] = azx_via_get_position, 1583 [POS_FIX_COMBO] = azx_get_pos_lpib, 1584 [POS_FIX_SKL] = azx_get_pos_posbuf, 1585 [POS_FIX_FIFO] = azx_get_pos_fifo, 1586 }; 1587 1588 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1589 1590 /* combo mode uses LPIB only for playback */ 1591 if (fix == POS_FIX_COMBO) 1592 chip->get_position[1] = NULL; 1593 1594 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1595 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1596 chip->get_delay[0] = chip->get_delay[1] = 1597 azx_get_delay_from_lpib; 1598 } 1599 1600 if (fix == POS_FIX_FIFO) 1601 chip->get_delay[0] = chip->get_delay[1] = 1602 azx_get_delay_from_fifo; 1603 } 1604 1605 /* 1606 * deny-lists for probe_mask 1607 */ 1608 static const struct snd_pci_quirk probe_mask_list[] = { 1609 /* Thinkpad often breaks the controller communication when accessing 1610 * to the non-working (or non-existing) modem codec slot. 1611 */ 1612 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1613 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1614 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1615 /* broken BIOS */ 1616 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1617 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1618 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1619 /* forced codec slots */ 1620 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1621 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1622 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1623 /* WinFast VP200 H (Teradici) user reported broken communication */ 1624 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1625 {} 1626 }; 1627 1628 #define AZX_FORCE_CODEC_MASK 0x100 1629 1630 static void check_probe_mask(struct azx *chip, int dev) 1631 { 1632 const struct snd_pci_quirk *q; 1633 1634 chip->codec_probe_mask = probe_mask[dev]; 1635 if (chip->codec_probe_mask == -1) { 1636 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1637 if (q) { 1638 dev_info(chip->card->dev, 1639 "probe_mask set to 0x%x for device %04x:%04x\n", 1640 q->value, q->subvendor, q->subdevice); 1641 chip->codec_probe_mask = q->value; 1642 } 1643 } 1644 1645 /* check forced option */ 1646 if (chip->codec_probe_mask != -1 && 1647 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1648 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1649 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1650 (int)azx_bus(chip)->codec_mask); 1651 } 1652 } 1653 1654 /* 1655 * allow/deny-list for enable_msi 1656 */ 1657 static const struct snd_pci_quirk msi_deny_list[] = { 1658 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1659 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1660 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1661 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1662 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1663 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1664 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1665 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1666 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1667 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1668 {} 1669 }; 1670 1671 static void check_msi(struct azx *chip) 1672 { 1673 const struct snd_pci_quirk *q; 1674 1675 if (enable_msi >= 0) { 1676 chip->msi = !!enable_msi; 1677 return; 1678 } 1679 chip->msi = 1; /* enable MSI as default */ 1680 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1681 if (q) { 1682 dev_info(chip->card->dev, 1683 "msi for device %04x:%04x set to %d\n", 1684 q->subvendor, q->subdevice, q->value); 1685 chip->msi = q->value; 1686 return; 1687 } 1688 1689 /* NVidia chipsets seem to cause troubles with MSI */ 1690 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1691 dev_info(chip->card->dev, "Disabling MSI\n"); 1692 chip->msi = 0; 1693 } 1694 } 1695 1696 /* check the snoop mode availability */ 1697 static void azx_check_snoop_available(struct azx *chip) 1698 { 1699 int snoop = hda_snoop; 1700 1701 if (snoop >= 0) { 1702 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1703 snoop ? "snoop" : "non-snoop"); 1704 chip->snoop = snoop; 1705 chip->uc_buffer = !snoop; 1706 return; 1707 } 1708 1709 snoop = true; 1710 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1711 chip->driver_type == AZX_DRIVER_VIA) { 1712 /* force to non-snoop mode for a new VIA controller 1713 * when BIOS is set 1714 */ 1715 u8 val; 1716 pci_read_config_byte(chip->pci, 0x42, &val); 1717 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1718 chip->pci->revision == 0x20)) 1719 snoop = false; 1720 } 1721 1722 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1723 snoop = false; 1724 1725 chip->snoop = snoop; 1726 if (!snoop) { 1727 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1728 /* C-Media requires non-cached pages only for CORB/RIRB */ 1729 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1730 chip->uc_buffer = true; 1731 } 1732 } 1733 1734 static void azx_probe_work(struct work_struct *work) 1735 { 1736 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1737 azx_probe_continue(&hda->chip); 1738 } 1739 1740 static int default_bdl_pos_adj(struct azx *chip) 1741 { 1742 /* some exceptions: Atoms seem problematic with value 1 */ 1743 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1744 switch (chip->pci->device) { 1745 case PCI_DEVICE_ID_INTEL_HDA_BYT: 1746 case PCI_DEVICE_ID_INTEL_HDA_BSW: 1747 return 32; 1748 case PCI_DEVICE_ID_INTEL_HDA_APL: 1749 return 64; 1750 } 1751 } 1752 1753 switch (chip->driver_type) { 1754 /* 1755 * increase the bdl size for Glenfly Gpus for hardware 1756 * limitation on hdac interrupt interval 1757 */ 1758 case AZX_DRIVER_GFHDMI: 1759 return 128; 1760 case AZX_DRIVER_ICH: 1761 case AZX_DRIVER_PCH: 1762 return 1; 1763 case AZX_DRIVER_ZHAOXINHDMI: 1764 return 128; 1765 case AZX_DRIVER_NVIDIA: 1766 return 64; 1767 default: 1768 return 32; 1769 } 1770 } 1771 1772 /* 1773 * constructor 1774 */ 1775 static const struct hda_controller_ops pci_hda_ops; 1776 1777 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1778 int dev, unsigned int driver_caps, 1779 struct azx **rchip) 1780 { 1781 static const struct snd_device_ops ops = { 1782 .dev_disconnect = azx_dev_disconnect, 1783 .dev_free = azx_dev_free, 1784 }; 1785 struct hda_intel *hda; 1786 struct azx *chip; 1787 int err; 1788 1789 *rchip = NULL; 1790 1791 err = pcim_enable_device(pci); 1792 if (err < 0) 1793 return err; 1794 1795 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1796 if (!hda) 1797 return -ENOMEM; 1798 1799 chip = &hda->chip; 1800 mutex_init(&chip->open_mutex); 1801 chip->card = card; 1802 chip->pci = pci; 1803 chip->ops = &pci_hda_ops; 1804 chip->driver_caps = driver_caps; 1805 chip->driver_type = driver_caps & 0xff; 1806 check_msi(chip); 1807 chip->dev_index = dev; 1808 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1809 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1810 INIT_LIST_HEAD(&chip->pcm_list); 1811 INIT_LIST_HEAD(&hda->list); 1812 init_vga_switcheroo(chip); 1813 init_completion(&hda->probe_wait); 1814 1815 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1816 1817 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1818 chip->fallback_to_single_cmd = 1; 1819 else /* explicitly set to single_cmd or not */ 1820 chip->single_cmd = single_cmd; 1821 1822 azx_check_snoop_available(chip); 1823 1824 if (bdl_pos_adj[dev] < 0) 1825 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1826 else 1827 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1828 1829 err = azx_bus_init(chip, model[dev]); 1830 if (err < 0) 1831 return err; 1832 1833 /* use the non-cached pages in non-snoop mode */ 1834 if (!azx_snoop(chip)) 1835 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC; 1836 1837 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1838 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1839 chip->bus.core.needs_damn_long_delay = 1; 1840 } 1841 1842 check_probe_mask(chip, dev); 1843 1844 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1845 if (err < 0) { 1846 dev_err(card->dev, "Error creating device [card]!\n"); 1847 azx_free(chip); 1848 return err; 1849 } 1850 1851 /* continue probing in work context as may trigger request module */ 1852 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1853 1854 *rchip = chip; 1855 1856 return 0; 1857 } 1858 1859 /* create and assign streams */ 1860 static int hda_init_streams(struct azx *chip) 1861 { 1862 int i; 1863 int stream_tags[2] = { 0, 0 }; 1864 1865 for (i = 0; i < chip->num_streams; i++) { 1866 struct hda_intel_stream *s = kzalloc_obj(*s); 1867 int tag, dir; 1868 1869 if (!s) 1870 return -ENOMEM; 1871 1872 s->hda = container_of(chip, struct hda_intel, chip); 1873 INIT_WORK(&s->irq_pending_work, azx_irq_pending_work); 1874 1875 /* stream tag must be unique throughout 1876 * the stream direction group, 1877 * valid values 1...15 1878 * use separate stream tag if the flag 1879 * AZX_DCAPS_SEPARATE_STREAM_TAG is used 1880 */ 1881 dir = azx_stream_direction(chip, i); 1882 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) 1883 tag = ++stream_tags[dir]; 1884 else 1885 tag = i + 1; 1886 azx_add_stream(chip, &s->azx_dev, i, tag); 1887 } 1888 1889 return 0; 1890 } 1891 1892 static int azx_first_init(struct azx *chip) 1893 { 1894 int dev = chip->dev_index; 1895 struct pci_dev *pci = chip->pci; 1896 struct snd_card *card = chip->card; 1897 struct hdac_bus *bus = azx_bus(chip); 1898 int err; 1899 unsigned short gcap; 1900 unsigned int dma_bits = 64; 1901 1902 #if BITS_PER_LONG != 64 1903 /* Fix up base address on ULI M5461 */ 1904 if (chip->driver_type == AZX_DRIVER_ULI) { 1905 u16 tmp3; 1906 pci_read_config_word(pci, 0x40, &tmp3); 1907 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1908 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1909 } 1910 #endif 1911 /* 1912 * Fix response write request not synced to memory when handle 1913 * hdac interrupt on Glenfly Gpus 1914 */ 1915 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1916 bus->polling_mode = 1; 1917 1918 if (chip->driver_type == AZX_DRIVER_LOONGSON) { 1919 bus->polling_mode = 1; 1920 bus->not_use_interrupts = 1; 1921 bus->access_sdnctl_in_dword = 1; 1922 if (!chip->jackpoll_interval) 1923 chip->jackpoll_interval = msecs_to_jiffies(1500); 1924 } 1925 1926 if (chip->driver_type == AZX_DRIVER_ZHAOXINHDMI) 1927 bus->polling_mode = 1; 1928 1929 bus->remap_addr = pcim_iomap_region(pci, 0, "ICH HD audio"); 1930 if (IS_ERR(bus->remap_addr)) 1931 return PTR_ERR(bus->remap_addr); 1932 1933 bus->addr = pci_resource_start(pci, 0); 1934 1935 if (chip->driver_type == AZX_DRIVER_SKL) 1936 snd_hdac_bus_parse_capabilities(bus); 1937 1938 /* 1939 * Some Intel CPUs has always running timer (ART) feature and 1940 * controller may have Global time sync reporting capability, so 1941 * check both of these before declaring synchronized time reporting 1942 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1943 */ 1944 chip->gts_present = false; 1945 1946 #ifdef CONFIG_X86 1947 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1948 chip->gts_present = true; 1949 #endif 1950 1951 pci_set_master(pci); 1952 1953 gcap = azx_readw(chip, GCAP); 1954 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1955 1956 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1957 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1958 dma_bits = 40; 1959 1960 /* disable SB600 64bit support for safety */ 1961 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1962 struct pci_dev *p_smbus; 1963 dma_bits = 40; 1964 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1965 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1966 NULL); 1967 if (p_smbus) { 1968 if (p_smbus->revision < 0x30) 1969 gcap &= ~AZX_GCAP_64OK; 1970 pci_dev_put(p_smbus); 1971 } 1972 } 1973 1974 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1975 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1976 dma_bits = 40; 1977 1978 /* disable 64bit DMA address on some devices */ 1979 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1980 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1981 gcap &= ~AZX_GCAP_64OK; 1982 } 1983 1984 /* disable buffer size rounding to 128-byte multiples if supported */ 1985 if (align_buffer_size >= 0) 1986 chip->align_buffer_size = !!align_buffer_size; 1987 else { 1988 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1989 chip->align_buffer_size = 0; 1990 else 1991 chip->align_buffer_size = 1; 1992 } 1993 1994 /* allow 64bit DMA address if supported by H/W */ 1995 if (!(gcap & AZX_GCAP_64OK)) 1996 dma_bits = 32; 1997 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1998 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1999 dma_set_max_seg_size(&pci->dev, UINT_MAX); 2000 2001 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { 2002 dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); 2003 pci->msi_addr_mask = DMA_BIT_MASK(dma_bits); 2004 } 2005 2006 /* read number of streams from GCAP register instead of using 2007 * hardcoded value 2008 */ 2009 chip->capture_streams = (gcap >> 8) & 0x0f; 2010 chip->playback_streams = (gcap >> 12) & 0x0f; 2011 if (!chip->playback_streams && !chip->capture_streams) { 2012 /* gcap didn't give any info, switching to old method */ 2013 2014 switch (chip->driver_type) { 2015 case AZX_DRIVER_ULI: 2016 chip->playback_streams = ULI_NUM_PLAYBACK; 2017 chip->capture_streams = ULI_NUM_CAPTURE; 2018 break; 2019 case AZX_DRIVER_ATIHDMI: 2020 case AZX_DRIVER_ATIHDMI_NS: 2021 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 2022 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 2023 break; 2024 case AZX_DRIVER_GFHDMI: 2025 case AZX_DRIVER_ZHAOXINHDMI: 2026 case AZX_DRIVER_GENERIC: 2027 default: 2028 chip->playback_streams = ICH6_NUM_PLAYBACK; 2029 chip->capture_streams = ICH6_NUM_CAPTURE; 2030 break; 2031 } 2032 } 2033 chip->capture_index_offset = 0; 2034 chip->playback_index_offset = chip->capture_streams; 2035 chip->num_streams = chip->playback_streams + chip->capture_streams; 2036 2037 /* sanity check for the SDxCTL.STRM field overflow */ 2038 if (chip->num_streams > 15 && 2039 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 2040 dev_warn(chip->card->dev, "number of I/O streams is %d, " 2041 "forcing separate stream tags", chip->num_streams); 2042 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 2043 } 2044 2045 /* initialize streams */ 2046 err = hda_init_streams(chip); 2047 if (err < 0) 2048 return err; 2049 2050 err = azx_alloc_stream_pages(chip); 2051 if (err < 0) 2052 return err; 2053 2054 /* initialize chip */ 2055 azx_init_pci(chip); 2056 2057 snd_hdac_i915_set_bclk(bus); 2058 2059 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2060 2061 /* codec detection */ 2062 if (!azx_bus(chip)->codec_mask) { 2063 dev_err(card->dev, "no codecs found!\n"); 2064 /* keep running the rest for the runtime PM */ 2065 } 2066 2067 if (azx_acquire_irq(chip, 0) < 0) 2068 return -EBUSY; 2069 2070 strscpy(card->driver, "HDA-Intel"); 2071 strscpy(card->shortname, driver_short_names[chip->driver_type], 2072 sizeof(card->shortname)); 2073 snprintf(card->longname, sizeof(card->longname), 2074 "%s at 0x%lx irq %i", 2075 card->shortname, bus->addr, bus->irq); 2076 2077 return 0; 2078 } 2079 2080 static int disable_msi_reset_irq(struct azx *chip) 2081 { 2082 struct hdac_bus *bus = azx_bus(chip); 2083 int err; 2084 2085 free_irq(bus->irq, chip); 2086 bus->irq = -1; 2087 chip->card->sync_irq = -1; 2088 pci_free_irq_vectors(chip->pci); 2089 chip->msi = 0; 2090 err = azx_acquire_irq(chip, 1); 2091 if (err < 0) 2092 return err; 2093 2094 return 0; 2095 } 2096 2097 /* Denylist for skipping the whole probe: 2098 * some HD-audio PCI entries are exposed without any codecs, and such devices 2099 * should be ignored from the beginning. 2100 */ 2101 static const struct pci_device_id driver_denylist[] = { 2102 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2103 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2104 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2105 {} 2106 }; 2107 2108 static struct pci_device_id driver_denylist_ideapad_z570[] = { 2109 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */ 2110 {} 2111 }; 2112 2113 static struct pci_device_id driver_denylist_msi_x870e[] = { 2114 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1462, 0xee59) }, /* MSI X870E Tomahawk WiFi */ 2115 {} 2116 }; 2117 2118 /* DMI-based denylist, to be used when: 2119 * - PCI subsystem IDs are zero, impossible to distinguish from valid sound cards. 2120 * - Different modifications of the same laptop use different GPU models. 2121 */ 2122 static const struct dmi_system_id driver_denylist_dmi[] = { 2123 { 2124 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */ 2125 .matches = { 2126 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 2127 DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"), 2128 }, 2129 .driver_data = &driver_denylist_ideapad_z570, 2130 }, 2131 { 2132 /* PCI device matching alone incorrectly matches some laptops */ 2133 .matches = { 2134 DMI_MATCH(DMI_BOARD_VENDOR, "Micro-Star International Co., Ltd."), 2135 DMI_MATCH(DMI_BOARD_NAME, "MAG X870E TOMAHAWK WIFI (MS-7E59)"), 2136 }, 2137 .driver_data = &driver_denylist_msi_x870e, 2138 }, 2139 {} 2140 }; 2141 2142 static const struct hda_controller_ops pci_hda_ops = { 2143 .disable_msi_reset_irq = disable_msi_reset_irq, 2144 .position_check = azx_position_check, 2145 .pcm_close = hda_intel_pcm_close, 2146 }; 2147 2148 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2149 2150 static int azx_probe(struct pci_dev *pci, 2151 const struct pci_device_id *pci_id) 2152 { 2153 const struct dmi_system_id *dmi; 2154 struct snd_card *card; 2155 struct hda_intel *hda; 2156 struct azx *chip; 2157 int dev; 2158 int err; 2159 2160 if (pci_match_id(driver_denylist, pci)) { 2161 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2162 return -ENODEV; 2163 } 2164 2165 dmi = dmi_first_match(driver_denylist_dmi); 2166 if (dmi && pci_match_id(dmi->driver_data, pci)) { 2167 dev_info(&pci->dev, "Skipping the device on the DMI denylist\n"); 2168 return -ENODEV; 2169 } 2170 2171 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2172 if (dev >= SNDRV_CARDS) 2173 return -ENODEV; 2174 if (!enable[dev]) { 2175 set_bit(dev, probed_devs); 2176 return -ENOENT; 2177 } 2178 2179 /* 2180 * stop probe if another Intel's DSP driver should be activated 2181 */ 2182 if (dmic_detect) { 2183 err = snd_intel_dsp_driver_probe(pci); 2184 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2185 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2186 return -ENODEV; 2187 } 2188 } else { 2189 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2190 } 2191 2192 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2193 0, &card); 2194 if (err < 0) { 2195 dev_err(&pci->dev, "Error creating card!\n"); 2196 return err; 2197 } 2198 2199 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2200 if (err < 0) 2201 goto out_free; 2202 card->private_data = chip; 2203 hda = container_of(chip, struct hda_intel, chip); 2204 2205 pci_set_drvdata(pci, card); 2206 2207 #ifdef CONFIG_SND_HDA_I915 2208 /* bind with i915 if needed */ 2209 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2210 err = snd_hdac_i915_init(azx_bus(chip)); 2211 if (err < 0) { 2212 if (err == -EPROBE_DEFER) 2213 goto out_free; 2214 2215 /* if the controller is bound only with HDMI/DP 2216 * (for HSW and BDW), we need to abort the probe; 2217 * for other chips, still continue probing as other 2218 * codecs can be on the same link. 2219 */ 2220 if (HDA_CONTROLLER_IN_GPU(pci)) { 2221 dev_err_probe(card->dev, err, 2222 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2223 2224 goto out_free; 2225 } else { 2226 /* don't bother any longer */ 2227 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2228 } 2229 } 2230 2231 /* HSW/BDW controllers need this power */ 2232 if (HDA_CONTROLLER_IN_GPU(pci)) 2233 hda->need_i915_power = true; 2234 } 2235 #else 2236 if (HDA_CONTROLLER_IN_GPU(pci)) 2237 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2238 #endif 2239 2240 err = register_vga_switcheroo(chip); 2241 if (err < 0) { 2242 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2243 goto out_free; 2244 } 2245 2246 if (check_hdmi_disabled(pci)) { 2247 dev_info(card->dev, "VGA controller is disabled\n"); 2248 dev_info(card->dev, "Delaying initialization\n"); 2249 chip->disabled = true; 2250 } 2251 2252 if (!chip->disabled) 2253 schedule_delayed_work(&hda->probe_work, 0); 2254 2255 set_bit(dev, probed_devs); 2256 if (chip->disabled) 2257 complete_all(&hda->probe_wait); 2258 return 0; 2259 2260 out_free: 2261 pci_set_drvdata(pci, NULL); 2262 snd_card_free(card); 2263 return err; 2264 } 2265 2266 /* On some boards setting power_save to a non 0 value leads to clicking / 2267 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2268 * figure out how to avoid these sounds, but that is not always feasible. 2269 * So we keep a list of devices where we disable powersaving as its known 2270 * to causes problems on these devices. 2271 */ 2272 static const struct snd_pci_quirk power_save_denylist[] = { 2273 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2274 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2275 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2276 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2277 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2278 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2279 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2280 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2281 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2282 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2283 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2284 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2285 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2286 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2287 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2288 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2289 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2290 /* https://bugs.launchpad.net/bugs/1821663 */ 2291 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2292 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2293 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2294 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2295 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2296 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2297 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2298 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2299 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2300 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2301 /* https://bugs.launchpad.net/bugs/1821663 */ 2302 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2303 /* KONTRON SinglePC may cause a stall at runtime resume */ 2304 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2305 /* Dell ALC3271 */ 2306 SND_PCI_QUIRK(0x1028, 0x0962, "Dell ALC3271", 0), 2307 /* https://bugzilla.kernel.org/show_bug.cgi?id=220210 */ 2308 SND_PCI_QUIRK(0x17aa, 0x5079, "Lenovo Thinkpad E15", 0), 2309 {} 2310 }; 2311 2312 static void set_default_power_save(struct azx *chip) 2313 { 2314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2315 int val = power_save; 2316 2317 if (pm_blacklist < 0) { 2318 const struct snd_pci_quirk *q; 2319 2320 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2321 if (q && val) { 2322 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2323 q->subvendor, q->subdevice); 2324 val = 0; 2325 hda->runtime_pm_disabled = 1; 2326 } 2327 } else if (pm_blacklist > 0) { 2328 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n"); 2329 val = 0; 2330 } 2331 snd_hda_set_power_save(&chip->bus, val * 1000); 2332 } 2333 2334 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2335 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2336 [AZX_DRIVER_NVIDIA] = 8, 2337 [AZX_DRIVER_TERA] = 1, 2338 }; 2339 2340 static int azx_probe_continue(struct azx *chip) 2341 { 2342 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2343 struct hdac_bus *bus = azx_bus(chip); 2344 struct pci_dev *pci = chip->pci; 2345 int dev = chip->dev_index; 2346 int err; 2347 2348 if (chip->disabled || hda->init_failed) 2349 return -EIO; 2350 if (hda->probe_retry) 2351 goto probe_retry; 2352 2353 to_hda_bus(bus)->bus_probing = 1; 2354 hda->probe_continued = 1; 2355 2356 /* Request display power well for the HDA controller or codec. For 2357 * Haswell/Broadwell, both the display HDA controller and codec need 2358 * this power. For other platforms, like Baytrail/Braswell, only the 2359 * display codec needs the power and it can be released after probe. 2360 */ 2361 display_power(chip, true); 2362 2363 err = azx_first_init(chip); 2364 if (err < 0) 2365 goto out_free; 2366 2367 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2368 chip->beep_mode = beep_mode[dev]; 2369 #endif 2370 2371 chip->ctl_dev_id = ctl_dev_id; 2372 2373 /* create codec instances */ 2374 if (bus->codec_mask) { 2375 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2376 if (err < 0) 2377 goto out_free; 2378 } 2379 2380 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2381 if (patch[dev] && *patch[dev]) { 2382 const struct firmware *fw = NULL; 2383 2384 dev_info(&pci->dev, "Applying patch firmware '%s'\n", 2385 patch[dev]); 2386 if (request_firmware(&fw, patch[dev], &pci->dev) < 0) { 2387 dev_err(&pci->dev, 2388 "Cannot load firmware, continue without patching\n"); 2389 } else { 2390 err = snd_hda_load_patch(&chip->bus, fw->size, fw->data); 2391 release_firmware(fw); 2392 if (err < 0) 2393 goto out_free; 2394 } 2395 } 2396 #endif 2397 2398 probe_retry: 2399 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2400 err = azx_codec_configure(chip); 2401 if (err) { 2402 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2403 ++hda->probe_retry < 60) { 2404 schedule_delayed_work(&hda->probe_work, 2405 msecs_to_jiffies(1000)); 2406 return 0; /* keep things up */ 2407 } 2408 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2409 goto out_free; 2410 } 2411 } 2412 2413 err = snd_card_register(chip->card); 2414 if (err < 0) 2415 goto out_free; 2416 2417 setup_vga_switcheroo_runtime_pm(chip); 2418 2419 chip->running = 1; 2420 azx_add_card_list(chip); 2421 2422 set_default_power_save(chip); 2423 2424 if (azx_has_pm_runtime(chip)) { 2425 pm_runtime_use_autosuspend(&pci->dev); 2426 pm_runtime_allow(&pci->dev); 2427 pm_runtime_put_autosuspend(&pci->dev); 2428 } 2429 2430 out_free: 2431 if (err < 0) { 2432 pci_set_drvdata(pci, NULL); 2433 snd_card_free(chip->card); 2434 return err; 2435 } 2436 2437 if (!hda->need_i915_power) 2438 display_power(chip, false); 2439 complete_all(&hda->probe_wait); 2440 to_hda_bus(bus)->bus_probing = 0; 2441 hda->probe_retry = 0; 2442 return 0; 2443 } 2444 2445 static void azx_remove(struct pci_dev *pci) 2446 { 2447 struct snd_card *card = pci_get_drvdata(pci); 2448 struct azx *chip; 2449 struct hda_intel *hda; 2450 2451 if (card) { 2452 /* cancel the pending probing work */ 2453 chip = card->private_data; 2454 hda = container_of(chip, struct hda_intel, chip); 2455 cancel_delayed_work_sync(&hda->probe_work); 2456 2457 clear_bit(chip->dev_index, probed_devs); 2458 pci_set_drvdata(pci, NULL); 2459 snd_card_free(card); 2460 } 2461 } 2462 2463 static void azx_shutdown(struct pci_dev *pci) 2464 { 2465 struct snd_card *card = pci_get_drvdata(pci); 2466 struct azx *chip; 2467 2468 if (!card) 2469 return; 2470 chip = card->private_data; 2471 if (chip && chip->running) 2472 __azx_shutdown_chip(chip, true); 2473 } 2474 2475 /* PCI IDs */ 2476 static const struct pci_device_id azx_ids[] = { 2477 /* CPT */ 2478 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2479 /* PBG */ 2480 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2481 /* Panther Point */ 2482 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2483 /* Lynx Point */ 2484 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2485 /* 9 Series */ 2486 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2487 /* Wellsburg */ 2488 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2489 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2490 /* Lewisburg */ 2491 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2492 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2493 /* Lynx Point-LP */ 2494 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2495 /* Lynx Point-LP */ 2496 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2497 /* Wildcat Point-LP */ 2498 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2499 /* Skylake (Sunrise Point) */ 2500 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2501 /* Skylake-LP (Sunrise Point-LP) */ 2502 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2503 /* Kabylake */ 2504 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2505 /* Kabylake-LP */ 2506 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2507 /* Kabylake-H */ 2508 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2509 /* Coffelake */ 2510 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2511 /* Cannonlake */ 2512 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2513 /* CometLake-LP */ 2514 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2515 /* CometLake-H */ 2516 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2517 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2518 /* CometLake-S */ 2519 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2520 /* CometLake-R */ 2521 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2522 /* Icelake */ 2523 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2524 /* Icelake-H */ 2525 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2526 /* Jasperlake */ 2527 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2528 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2529 /* Tigerlake */ 2530 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2531 /* Tigerlake-H */ 2532 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2533 /* DG1 */ 2534 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2535 /* DG2 */ 2536 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2537 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2538 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2539 /* Alderlake-S */ 2540 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2541 /* Alderlake-P */ 2542 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2543 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2544 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2545 /* Alderlake-M */ 2546 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2547 /* Alderlake-N */ 2548 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2549 /* Elkhart Lake */ 2550 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2551 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2552 /* Raptor Lake */ 2553 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2554 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2555 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2556 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2557 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2558 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2559 /* Battlemage */ 2560 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2561 /* Lunarlake-P */ 2562 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2563 /* Arrow Lake-S */ 2564 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2565 /* Arrow Lake */ 2566 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2567 /* Panther Lake */ 2568 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2569 /* Panther Lake-H */ 2570 { PCI_DEVICE_DATA(INTEL, HDA_PTL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2571 /* Wildcat Lake */ 2572 { PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2573 /* Nova Lake */ 2574 { PCI_DEVICE_DATA(INTEL, HDA_NVL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) }, 2575 { PCI_DEVICE_DATA(INTEL, HDA_NVL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) }, 2576 /* Apollolake (Broxton-P) */ 2577 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2578 /* Gemini-Lake */ 2579 { PCI_DEVICE_DATA(INTEL, HDA_GLK, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2580 /* Haswell */ 2581 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2582 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2583 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2584 /* Broadwell */ 2585 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, 2586 /* 5 Series/3400 */ 2587 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2588 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2589 /* Poulsbo */ 2590 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2591 AZX_DCAPS_POSFIX_LPIB) }, 2592 /* Oaktrail */ 2593 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, 2594 /* BayTrail */ 2595 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, 2596 /* Braswell */ 2597 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, 2598 /* ICH6 */ 2599 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2600 /* ICH7 */ 2601 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2602 /* ESB2 */ 2603 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2604 /* ICH8 */ 2605 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2606 /* ICH9 */ 2607 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2608 /* ICH9 */ 2609 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2610 /* ICH10 */ 2611 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2612 /* ICH10 */ 2613 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2614 /* Generic Intel */ 2615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2616 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2617 .class_mask = 0xffffff, 2618 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2619 /* ATI SB 450/600/700/800/900 */ 2620 { PCI_VDEVICE(ATI, 0x437b), 2621 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2622 { PCI_VDEVICE(ATI, 0x4383), 2623 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2624 /* AMD Hudson */ 2625 { PCI_VDEVICE(AMD, 0x780d), 2626 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2627 /* AMD, X370 & co */ 2628 { PCI_VDEVICE(AMD, 0x1457), 2629 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2630 /* AMD, X570 & co */ 2631 { PCI_VDEVICE(AMD, 0x1487), 2632 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2633 /* AMD Stoney */ 2634 { PCI_VDEVICE(AMD, 0x157a), 2635 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2636 AZX_DCAPS_PM_RUNTIME }, 2637 /* AMD Raven */ 2638 { PCI_VDEVICE(AMD, 0x15e3), 2639 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2640 /* ATI HDMI */ 2641 { PCI_VDEVICE(ATI, 0x0002), 2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2643 AZX_DCAPS_PM_RUNTIME }, 2644 { PCI_VDEVICE(ATI, 0x1308), 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2646 { PCI_VDEVICE(ATI, 0x157a), 2647 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2648 { PCI_VDEVICE(ATI, 0x15b3), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2650 { PCI_VDEVICE(ATI, 0x793b), 2651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2652 { PCI_VDEVICE(ATI, 0x7919), 2653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2654 { PCI_VDEVICE(ATI, 0x960f), 2655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2656 { PCI_VDEVICE(ATI, 0x970f), 2657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2658 { PCI_VDEVICE(ATI, 0x9840), 2659 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2660 { PCI_VDEVICE(ATI, 0xaa00), 2661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2662 { PCI_VDEVICE(ATI, 0xaa08), 2663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2664 { PCI_VDEVICE(ATI, 0xaa10), 2665 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2666 { PCI_VDEVICE(ATI, 0xaa18), 2667 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2668 { PCI_VDEVICE(ATI, 0xaa20), 2669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2670 { PCI_VDEVICE(ATI, 0xaa28), 2671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2672 { PCI_VDEVICE(ATI, 0xaa30), 2673 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2674 { PCI_VDEVICE(ATI, 0xaa38), 2675 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2676 { PCI_VDEVICE(ATI, 0xaa40), 2677 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2678 { PCI_VDEVICE(ATI, 0xaa48), 2679 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2680 { PCI_VDEVICE(ATI, 0xaa50), 2681 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2682 { PCI_VDEVICE(ATI, 0xaa58), 2683 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2684 { PCI_VDEVICE(ATI, 0xaa60), 2685 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2686 { PCI_VDEVICE(ATI, 0xaa68), 2687 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2688 { PCI_VDEVICE(ATI, 0xaa80), 2689 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2690 { PCI_VDEVICE(ATI, 0xaa88), 2691 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2692 { PCI_VDEVICE(ATI, 0xaa90), 2693 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2694 { PCI_VDEVICE(ATI, 0xaa98), 2695 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2696 { PCI_VDEVICE(ATI, 0x9902), 2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2698 { PCI_VDEVICE(ATI, 0xaaa0), 2699 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2700 { PCI_VDEVICE(ATI, 0xaaa8), 2701 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2702 { PCI_VDEVICE(ATI, 0xaab0), 2703 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2704 { PCI_VDEVICE(ATI, 0xaac0), 2705 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2706 AZX_DCAPS_PM_RUNTIME }, 2707 { PCI_VDEVICE(ATI, 0xaac8), 2708 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2709 AZX_DCAPS_PM_RUNTIME }, 2710 { PCI_VDEVICE(ATI, 0xaad8), 2711 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2712 AZX_DCAPS_PM_RUNTIME }, 2713 { PCI_VDEVICE(ATI, 0xaae0), 2714 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2715 AZX_DCAPS_PM_RUNTIME }, 2716 { PCI_VDEVICE(ATI, 0xaae8), 2717 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2718 AZX_DCAPS_PM_RUNTIME }, 2719 { PCI_VDEVICE(ATI, 0xaaf0), 2720 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2721 AZX_DCAPS_PM_RUNTIME }, 2722 { PCI_VDEVICE(ATI, 0xaaf8), 2723 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2724 AZX_DCAPS_PM_RUNTIME }, 2725 { PCI_VDEVICE(ATI, 0xab00), 2726 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2727 AZX_DCAPS_PM_RUNTIME }, 2728 { PCI_VDEVICE(ATI, 0xab08), 2729 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2730 AZX_DCAPS_PM_RUNTIME }, 2731 { PCI_VDEVICE(ATI, 0xab10), 2732 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2733 AZX_DCAPS_PM_RUNTIME }, 2734 { PCI_VDEVICE(ATI, 0xab18), 2735 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2736 AZX_DCAPS_PM_RUNTIME }, 2737 { PCI_VDEVICE(ATI, 0xab20), 2738 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2739 AZX_DCAPS_PM_RUNTIME }, 2740 { PCI_VDEVICE(ATI, 0xab28), 2741 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2742 AZX_DCAPS_PM_RUNTIME }, 2743 { PCI_VDEVICE(ATI, 0xab30), 2744 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2745 AZX_DCAPS_PM_RUNTIME }, 2746 { PCI_VDEVICE(ATI, 0xab38), 2747 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2748 AZX_DCAPS_PM_RUNTIME }, 2749 { PCI_VDEVICE(ATI, 0xab40), 2750 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2751 AZX_DCAPS_PM_RUNTIME }, 2752 /* GLENFLY */ 2753 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID), 2754 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2755 .class_mask = 0xffffff, 2756 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2757 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2758 /* VIA VT8251/VT8237A */ 2759 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2760 /* VIA GFX VT7122/VX900 */ 2761 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2762 /* VIA GFX VT6122/VX11 */ 2763 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2764 /* SIS966 */ 2765 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2766 /* ULI M5461 */ 2767 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2768 /* NVIDIA MCP */ 2769 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2770 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2771 .class_mask = 0xffffff, 2772 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2773 /* Teradici */ 2774 { PCI_DEVICE(0x6549, 0x1200), 2775 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2776 { PCI_DEVICE(0x6549, 0x2200), 2777 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2778 /* Creative X-Fi (CA0110-IBG) */ 2779 /* CTHDA chips */ 2780 { PCI_VDEVICE(CREATIVE, 0x0010), 2781 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2782 { PCI_VDEVICE(CREATIVE, 0x0012), 2783 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2784 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2785 /* the following entry conflicts with snd-ctxfi driver, 2786 * as ctxfi driver mutates from HD-audio to native mode with 2787 * a special command sequence. 2788 */ 2789 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2790 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2791 .class_mask = 0xffffff, 2792 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2793 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2794 #else 2795 /* this entry seems still valid -- i.e. without emu20kx chip */ 2796 { PCI_VDEVICE(CREATIVE, 0x0009), 2797 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2798 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2799 #endif 2800 /* CM8888 */ 2801 { PCI_VDEVICE(CMEDIA, 0x5011), 2802 .driver_data = AZX_DRIVER_CMEDIA | 2803 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2804 /* Vortex86MX */ 2805 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2806 /* VMware HDAudio */ 2807 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2808 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2809 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2810 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2811 .class_mask = 0xffffff, 2812 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2813 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2814 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2815 .class_mask = 0xffffff, 2816 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2817 /* Zhaoxin */ 2818 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2819 { PCI_VDEVICE(ZHAOXIN, 0x9141), 2820 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2821 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2822 { PCI_VDEVICE(ZHAOXIN, 0x9142), 2823 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2824 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2825 { PCI_VDEVICE(ZHAOXIN, 0x9144), 2826 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2827 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2828 { PCI_VDEVICE(ZHAOXIN, 0x9145), 2829 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2830 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2831 { PCI_VDEVICE(ZHAOXIN, 0x9146), 2832 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2833 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2834 /* Loongson HDAudio*/ 2835 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), 2836 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, 2837 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), 2838 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, 2839 { 0, } 2840 }; 2841 MODULE_DEVICE_TABLE(pci, azx_ids); 2842 2843 /* pci_driver definition */ 2844 static struct pci_driver azx_driver = { 2845 .name = KBUILD_MODNAME, 2846 .id_table = azx_ids, 2847 .probe = azx_probe, 2848 .remove = azx_remove, 2849 .shutdown = azx_shutdown, 2850 .driver = { 2851 .pm = pm_ptr(&azx_pm), 2852 }, 2853 }; 2854 2855 module_pci_driver(azx_driver); 2856