1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ADXL371/ADXL372 3-Axis Digital Accelerometer core driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/module.h>
14 #include <linux/regmap.h>
15 #include <linux/spi/spi.h>
16
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/events.h>
21 #include <linux/iio/trigger.h>
22 #include <linux/iio/trigger_consumer.h>
23 #include <linux/iio/triggered_buffer.h>
24
25 #include "adxl372.h"
26
27 /* ADXL372 registers definition */
28 #define ADXL372_DEVID 0x00
29 #define ADXL372_DEVID_MST 0x01
30 #define ADXL372_PARTID 0x02
31 #define ADXL372_STATUS_1 0x04
32 #define ADXL372_STATUS_2 0x05
33 #define ADXL372_FIFO_ENTRIES_2 0x06
34 #define ADXL372_FIFO_ENTRIES_1 0x07
35 #define ADXL372_X_DATA_H 0x08
36 #define ADXL372_X_DATA_L 0x09
37 #define ADXL372_Y_DATA_H 0x0A
38 #define ADXL372_Y_DATA_L 0x0B
39 #define ADXL372_Z_DATA_H 0x0C
40 #define ADXL372_Z_DATA_L 0x0D
41 #define ADXL372_X_MAXPEAK_H 0x15
42 #define ADXL372_X_MAXPEAK_L 0x16
43 #define ADXL372_Y_MAXPEAK_H 0x17
44 #define ADXL372_Y_MAXPEAK_L 0x18
45 #define ADXL372_Z_MAXPEAK_H 0x19
46 #define ADXL372_Z_MAXPEAK_L 0x1A
47 #define ADXL372_OFFSET_X 0x20
48 #define ADXL372_OFFSET_Y 0x21
49 #define ADXL372_OFFSET_Z 0x22
50 #define ADXL372_X_THRESH_ACT_H 0x23
51 #define ADXL372_X_THRESH_ACT_L 0x24
52 #define ADXL372_Y_THRESH_ACT_H 0x25
53 #define ADXL372_Y_THRESH_ACT_L 0x26
54 #define ADXL372_Z_THRESH_ACT_H 0x27
55 #define ADXL372_Z_THRESH_ACT_L 0x28
56 #define ADXL372_TIME_ACT 0x29
57 #define ADXL372_X_THRESH_INACT_H 0x2A
58 #define ADXL372_X_THRESH_INACT_L 0x2B
59 #define ADXL372_Y_THRESH_INACT_H 0x2C
60 #define ADXL372_Y_THRESH_INACT_L 0x2D
61 #define ADXL372_Z_THRESH_INACT_H 0x2E
62 #define ADXL372_Z_THRESH_INACT_L 0x2F
63 #define ADXL372_TIME_INACT_H 0x30
64 #define ADXL372_TIME_INACT_L 0x31
65 #define ADXL372_X_THRESH_ACT2_H 0x32
66 #define ADXL372_X_THRESH_ACT2_L 0x33
67 #define ADXL372_Y_THRESH_ACT2_H 0x34
68 #define ADXL372_Y_THRESH_ACT2_L 0x35
69 #define ADXL372_Z_THRESH_ACT2_H 0x36
70 #define ADXL372_Z_THRESH_ACT2_L 0x37
71 #define ADXL372_HPF 0x38
72 #define ADXL372_FIFO_SAMPLES 0x39
73 #define ADXL372_FIFO_CTL 0x3A
74 #define ADXL372_INT1_MAP 0x3B
75 #define ADXL372_INT2_MAP 0x3C
76 #define ADXL372_TIMING 0x3D
77 #define ADXL372_MEASURE 0x3E
78 #define ADXL372_POWER_CTL 0x3F
79 #define ADXL372_SELF_TEST 0x40
80 #define ADXL372_RESET 0x41
81 #define ADXL372_FIFO_DATA 0x42
82
83 #define ADXL372_DEVID_VAL 0xAD
84 #define ADXL372_PARTID_VAL 0xFA
85 #define ADXL372_RESET_CODE 0x52
86
87 /* ADXL372_POWER_CTL */
88 #define ADXL372_POWER_CTL_MODE_MSK GENMASK_ULL(1, 0)
89 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0)
90
91 /* ADXL372_MEASURE */
92 #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK_ULL(5, 4)
93 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4)
94 #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK_ULL(2, 0)
95 #define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0)
96
97 /* ADXL372_TIMING */
98 #define ADXL372_TIMING_ODR_MSK GENMASK_ULL(7, 5)
99 #define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5)
100
101 /* ADXL372_FIFO_CTL */
102 #define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3)
103 #define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3)
104 #define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1)
105 #define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1)
106 #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(1)
107 #define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0)
108
109 /* ADXL372_STATUS_1 */
110 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1)
111 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1)
112 #define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1)
113 #define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1)
114 #define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1)
115 #define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1)
116 #define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1)
117
118 /* ADXL372_STATUS_2 */
119 #define ADXL372_STATUS_2_INACT(x) (((x) >> 4) & 0x1)
120 #define ADXL372_STATUS_2_ACT(x) (((x) >> 5) & 0x1)
121 #define ADXL372_STATUS_2_AC2(x) (((x) >> 6) & 0x1)
122
123 /* ADXL372_INT1_MAP */
124 #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0)
125 #define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0)
126 #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1)
127 #define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1)
128 #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2)
129 #define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2)
130 #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3)
131 #define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3)
132 #define ADXL372_INT1_MAP_INACT_MSK BIT(4)
133 #define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4)
134 #define ADXL372_INT1_MAP_ACT_MSK BIT(5)
135 #define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5)
136 #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6)
137 #define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6)
138 #define ADXL372_INT1_MAP_LOW_MSK BIT(7)
139 #define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7)
140
141 /* ADX372_THRESH */
142 #define ADXL372_THRESH_VAL_H_MSK GENMASK(10, 3)
143 #define ADXL372_THRESH_VAL_H_SEL(x) FIELD_GET(ADXL372_THRESH_VAL_H_MSK, x)
144 #define ADXL372_THRESH_VAL_L_MSK GENMASK(2, 0)
145 #define ADXL372_THRESH_VAL_L_SEL(x) FIELD_GET(ADXL372_THRESH_VAL_L_MSK, x)
146
147 /* The ADXL372 includes a deep, 512 sample FIFO buffer */
148 #define ADXL372_FIFO_SIZE 512
149 #define ADXL372_X_AXIS_EN(x) ((x) & BIT(0))
150 #define ADXL372_Y_AXIS_EN(x) ((x) & BIT(1))
151 #define ADXL372_Z_AXIS_EN(x) ((x) & BIT(2))
152
153 /*
154 * At +/- 200g with 12-bit resolution, scale is computed as:
155 * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
156 */
157 #define ADXL372_USCALE 958241
158
159 enum adxl372_op_mode {
160 ADXL372_STANDBY,
161 ADXL372_WAKE_UP,
162 ADXL372_INSTANT_ON,
163 ADXL372_FULL_BW_MEASUREMENT,
164 };
165
166 enum adxl372_act_proc_mode {
167 ADXL372_DEFAULT,
168 ADXL372_LINKED,
169 ADXL372_LOOPED,
170 };
171
172 enum adxl372_th_activity {
173 ADXL372_ACTIVITY,
174 ADXL372_ACTIVITY2,
175 ADXL372_INACTIVITY,
176 };
177
178 enum adxl372_odr {
179 ADXL372_ODR_400HZ,
180 ADXL372_ODR_800HZ,
181 ADXL372_ODR_1600HZ,
182 ADXL372_ODR_3200HZ,
183 ADXL372_ODR_6400HZ,
184 ADXL372_ODR_NUM
185 };
186
187 enum adxl371_odr {
188 ADXL371_ODR_320HZ,
189 ADXL371_ODR_640HZ,
190 ADXL371_ODR_1280HZ,
191 ADXL371_ODR_2560HZ,
192 ADXL371_ODR_5120HZ,
193 ADXL371_ODR_NUM
194 };
195
196 enum adxl372_bandwidth {
197 ADXL372_BW_200HZ,
198 ADXL372_BW_400HZ,
199 ADXL372_BW_800HZ,
200 ADXL372_BW_1600HZ,
201 ADXL372_BW_3200HZ,
202 };
203
204 static const unsigned int adxl372_th_reg_high_addr[3] = {
205 [ADXL372_ACTIVITY] = ADXL372_X_THRESH_ACT_H,
206 [ADXL372_ACTIVITY2] = ADXL372_X_THRESH_ACT2_H,
207 [ADXL372_INACTIVITY] = ADXL372_X_THRESH_INACT_H,
208 };
209
210 enum adxl372_fifo_format {
211 ADXL372_XYZ_FIFO,
212 ADXL372_X_FIFO,
213 ADXL372_Y_FIFO,
214 ADXL372_XY_FIFO,
215 ADXL372_Z_FIFO,
216 ADXL372_XZ_FIFO,
217 ADXL372_YZ_FIFO,
218 ADXL372_XYZ_PEAK_FIFO,
219 };
220
221 enum adxl372_fifo_mode {
222 ADXL372_FIFO_BYPASSED,
223 ADXL372_FIFO_STREAMED,
224 ADXL372_FIFO_TRIGGERED,
225 ADXL372_FIFO_OLD_SAVED
226 };
227
228 static const int adxl372_samp_freq_tbl[ADXL372_ODR_NUM] = {
229 [ADXL372_ODR_400HZ] = 400,
230 [ADXL372_ODR_800HZ] = 800,
231 [ADXL372_ODR_1600HZ] = 1600,
232 [ADXL372_ODR_3200HZ] = 3200,
233 [ADXL372_ODR_6400HZ] = 6400,
234 };
235
236 static const int adxl372_bw_freq_tbl[ADXL372_ODR_NUM] = {
237 [ADXL372_BW_200HZ] = 200,
238 [ADXL372_BW_400HZ] = 400,
239 [ADXL372_BW_800HZ] = 800,
240 [ADXL372_BW_1600HZ] = 1600,
241 [ADXL372_BW_3200HZ] = 3200,
242 };
243
244 static const int adxl371_samp_freq_tbl[ADXL371_ODR_NUM] = {
245 [ADXL371_ODR_320HZ] = 320,
246 [ADXL371_ODR_640HZ] = 640,
247 [ADXL371_ODR_1280HZ] = 1280,
248 [ADXL371_ODR_2560HZ] = 2560,
249 [ADXL371_ODR_5120HZ] = 5120,
250 };
251
252 static const int adxl371_bw_freq_tbl[ADXL371_ODR_NUM] = {
253 [ADXL371_ODR_320HZ] = 160,
254 [ADXL371_ODR_640HZ] = 320,
255 [ADXL371_ODR_1280HZ] = 640,
256 [ADXL371_ODR_2560HZ] = 1280,
257 [ADXL371_ODR_5120HZ] = 2560,
258 };
259
260 const struct adxl372_chip_info adxl371_chip_info = {
261 .name = "adxl371",
262 .samp_freq_tbl = adxl371_samp_freq_tbl,
263 .bw_freq_tbl = adxl371_bw_freq_tbl,
264 .num_freqs = ARRAY_SIZE(adxl371_samp_freq_tbl),
265 .act_time_scale_us = 4125,
266 .act_time_scale_low_us = 8250,
267 .inact_time_scale_ms = 16,
268 .inact_time_scale_low_ms = 32,
269 .max_odr = ADXL371_ODR_5120HZ,
270 /* Silicon erratum (er001) causes FIFO data misalignment on ADXL371 */
271 .fifo_supported = false,
272 };
273 EXPORT_SYMBOL_NS_GPL(adxl371_chip_info, "IIO_ADXL372");
274
275 const struct adxl372_chip_info adxl372_chip_info = {
276 .name = "adxl372",
277 .samp_freq_tbl = adxl372_samp_freq_tbl,
278 .bw_freq_tbl = adxl372_bw_freq_tbl,
279 .num_freqs = ARRAY_SIZE(adxl372_samp_freq_tbl),
280 .act_time_scale_us = 3300,
281 .act_time_scale_low_us = 6600,
282 .inact_time_scale_ms = 13,
283 .inact_time_scale_low_ms = 26,
284 .max_odr = ADXL372_ODR_6400HZ,
285 .fifo_supported = true,
286 };
287 EXPORT_SYMBOL_NS_GPL(adxl372_chip_info, "IIO_ADXL372");
288
289 struct adxl372_axis_lookup {
290 unsigned int bits;
291 enum adxl372_fifo_format fifo_format;
292 };
293
294 static const struct adxl372_axis_lookup adxl372_axis_lookup_table[] = {
295 { BIT(0), ADXL372_X_FIFO },
296 { BIT(1), ADXL372_Y_FIFO },
297 { BIT(2), ADXL372_Z_FIFO },
298 { BIT(0) | BIT(1), ADXL372_XY_FIFO },
299 { BIT(0) | BIT(2), ADXL372_XZ_FIFO },
300 { BIT(1) | BIT(2), ADXL372_YZ_FIFO },
301 { BIT(0) | BIT(1) | BIT(2), ADXL372_XYZ_FIFO },
302 };
303
304 static const struct iio_event_spec adxl372_events[] = {
305 {
306 .type = IIO_EV_TYPE_THRESH,
307 .dir = IIO_EV_DIR_RISING,
308 .mask_separate = BIT(IIO_EV_INFO_VALUE),
309 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE),
310 }, {
311 .type = IIO_EV_TYPE_THRESH,
312 .dir = IIO_EV_DIR_FALLING,
313 .mask_separate = BIT(IIO_EV_INFO_VALUE),
314 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE),
315 },
316 };
317
318 #define ADXL372_ACCEL_CHANNEL(index, reg, axis) { \
319 .type = IIO_ACCEL, \
320 .address = reg, \
321 .modified = 1, \
322 .channel2 = IIO_MOD_##axis, \
323 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
324 .info_mask_shared_by_type = \
325 BIT(IIO_CHAN_INFO_SCALE) | \
326 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
327 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
328 .info_mask_shared_by_type_available = \
329 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
330 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
331 .scan_index = index, \
332 .scan_type = { \
333 .sign = 's', \
334 .realbits = 12, \
335 .storagebits = 16, \
336 .shift = 4, \
337 .endianness = IIO_BE, \
338 }, \
339 .event_spec = adxl372_events, \
340 .num_event_specs = ARRAY_SIZE(adxl372_events) \
341 }
342
343 static const struct iio_chan_spec adxl372_channels[] = {
344 ADXL372_ACCEL_CHANNEL(0, ADXL372_X_DATA_H, X),
345 ADXL372_ACCEL_CHANNEL(1, ADXL372_Y_DATA_H, Y),
346 ADXL372_ACCEL_CHANNEL(2, ADXL372_Z_DATA_H, Z),
347 };
348
349 struct adxl372_state {
350 const struct adxl372_chip_info *chip_info;
351 int irq;
352 struct device *dev;
353 struct regmap *regmap;
354 struct iio_trigger *dready_trig;
355 struct iio_trigger *peak_datardy_trig;
356 enum adxl372_fifo_mode fifo_mode;
357 enum adxl372_fifo_format fifo_format;
358 unsigned int fifo_axis_mask;
359 enum adxl372_op_mode op_mode;
360 enum adxl372_act_proc_mode act_proc_mode;
361 enum adxl372_odr odr;
362 enum adxl372_bandwidth bw;
363 u32 act_time_ms;
364 u32 inact_time_ms;
365 u8 fifo_set_size;
366 unsigned long int1_bitmask;
367 u16 watermark;
368 __be16 fifo_buf[ADXL372_FIFO_SIZE];
369 bool peak_fifo_mode_en;
370 struct mutex threshold_m; /* lock for threshold */
371 };
372
373 static const unsigned long adxl372_channel_masks[] = {
374 BIT(0), BIT(1), BIT(2),
375 BIT(0) | BIT(1),
376 BIT(0) | BIT(2),
377 BIT(1) | BIT(2),
378 BIT(0) | BIT(1) | BIT(2),
379 0
380 };
381
adxl372_read_threshold_value(struct iio_dev * indio_dev,unsigned int addr,u16 * threshold)382 static ssize_t adxl372_read_threshold_value(struct iio_dev *indio_dev, unsigned int addr,
383 u16 *threshold)
384 {
385 struct adxl372_state *st = iio_priv(indio_dev);
386 __be16 raw_regval;
387 u16 regval;
388 int ret;
389
390 ret = regmap_bulk_read(st->regmap, addr, &raw_regval, sizeof(raw_regval));
391 if (ret < 0)
392 return ret;
393
394 regval = be16_to_cpu(raw_regval);
395 regval >>= 5;
396
397 *threshold = regval;
398
399 return 0;
400 }
401
adxl372_write_threshold_value(struct iio_dev * indio_dev,unsigned int addr,u16 threshold)402 static ssize_t adxl372_write_threshold_value(struct iio_dev *indio_dev, unsigned int addr,
403 u16 threshold)
404 {
405 struct adxl372_state *st = iio_priv(indio_dev);
406 int ret;
407
408 guard(mutex)(&st->threshold_m);
409
410 ret = regmap_write(st->regmap, addr, ADXL372_THRESH_VAL_H_SEL(threshold));
411 if (ret < 0)
412 return ret;
413
414 return regmap_update_bits(st->regmap, addr + 1, GENMASK(7, 5),
415 ADXL372_THRESH_VAL_L_SEL(threshold) << 5);
416 }
417
adxl372_read_axis(struct adxl372_state * st,u8 addr)418 static int adxl372_read_axis(struct adxl372_state *st, u8 addr)
419 {
420 __be16 regval;
421 int ret;
422
423 ret = regmap_bulk_read(st->regmap, addr, ®val, sizeof(regval));
424 if (ret < 0)
425 return ret;
426
427 return be16_to_cpu(regval);
428 }
429
adxl372_set_op_mode(struct adxl372_state * st,enum adxl372_op_mode op_mode)430 static int adxl372_set_op_mode(struct adxl372_state *st,
431 enum adxl372_op_mode op_mode)
432 {
433 int ret;
434
435 ret = regmap_update_bits(st->regmap, ADXL372_POWER_CTL,
436 ADXL372_POWER_CTL_MODE_MSK,
437 ADXL372_POWER_CTL_MODE(op_mode));
438 if (ret < 0)
439 return ret;
440
441 st->op_mode = op_mode;
442
443 return ret;
444 }
445
adxl372_set_odr(struct adxl372_state * st,enum adxl372_odr odr)446 static int adxl372_set_odr(struct adxl372_state *st,
447 enum adxl372_odr odr)
448 {
449 int ret;
450
451 ret = regmap_update_bits(st->regmap, ADXL372_TIMING,
452 ADXL372_TIMING_ODR_MSK,
453 ADXL372_TIMING_ODR_MODE(odr));
454 if (ret < 0)
455 return ret;
456
457 st->odr = odr;
458
459 return ret;
460 }
461
adxl372_find_closest_match(const int * array,unsigned int size,int val)462 static int adxl372_find_closest_match(const int *array,
463 unsigned int size, int val)
464 {
465 int i;
466
467 for (i = 0; i < size; i++) {
468 if (val <= array[i])
469 return i;
470 }
471
472 return size - 1;
473 }
474
adxl372_set_bandwidth(struct adxl372_state * st,enum adxl372_bandwidth bw)475 static int adxl372_set_bandwidth(struct adxl372_state *st,
476 enum adxl372_bandwidth bw)
477 {
478 int ret;
479
480 ret = regmap_update_bits(st->regmap, ADXL372_MEASURE,
481 ADXL372_MEASURE_BANDWIDTH_MSK,
482 ADXL372_MEASURE_BANDWIDTH_MODE(bw));
483 if (ret < 0)
484 return ret;
485
486 st->bw = bw;
487
488 return ret;
489 }
490
adxl372_set_act_proc_mode(struct adxl372_state * st,enum adxl372_act_proc_mode mode)491 static int adxl372_set_act_proc_mode(struct adxl372_state *st,
492 enum adxl372_act_proc_mode mode)
493 {
494 int ret;
495
496 ret = regmap_update_bits(st->regmap,
497 ADXL372_MEASURE,
498 ADXL372_MEASURE_LINKLOOP_MSK,
499 ADXL372_MEASURE_LINKLOOP_MODE(mode));
500 if (ret < 0)
501 return ret;
502
503 st->act_proc_mode = mode;
504
505 return ret;
506 }
507
adxl372_set_activity_threshold(struct adxl372_state * st,enum adxl372_th_activity act,bool ref_en,bool enable,unsigned int threshold)508 static int adxl372_set_activity_threshold(struct adxl372_state *st,
509 enum adxl372_th_activity act,
510 bool ref_en, bool enable,
511 unsigned int threshold)
512 {
513 unsigned char buf[6];
514 unsigned char th_reg_high_val, th_reg_low_val, th_reg_high_addr;
515
516 /* scale factor is 100 mg/code */
517 th_reg_high_val = (threshold / 100) >> 3;
518 th_reg_low_val = ((threshold / 100) << 5) | (ref_en << 1) | enable;
519 th_reg_high_addr = adxl372_th_reg_high_addr[act];
520
521 buf[0] = th_reg_high_val;
522 buf[1] = th_reg_low_val;
523 buf[2] = th_reg_high_val;
524 buf[3] = th_reg_low_val;
525 buf[4] = th_reg_high_val;
526 buf[5] = th_reg_low_val;
527
528 return regmap_bulk_write(st->regmap, th_reg_high_addr,
529 buf, ARRAY_SIZE(buf));
530 }
531
adxl372_set_activity_time_ms(struct adxl372_state * st,unsigned int act_time_ms)532 static int adxl372_set_activity_time_ms(struct adxl372_state *st,
533 unsigned int act_time_ms)
534 {
535 unsigned int reg_val, scale_factor;
536 int ret;
537
538 /*
539 * The scale factor of the TIME_ACT register depends on the ODR.
540 * A higher scale factor is used at the maximum ODR and a lower
541 * one at all other rates.
542 */
543 if (st->odr == st->chip_info->max_odr)
544 scale_factor = st->chip_info->act_time_scale_us;
545 else
546 scale_factor = st->chip_info->act_time_scale_low_us;
547
548 reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor);
549
550 /* TIME_ACT register is 8 bits wide */
551 if (reg_val > 0xFF)
552 reg_val = 0xFF;
553
554 ret = regmap_write(st->regmap, ADXL372_TIME_ACT, reg_val);
555 if (ret < 0)
556 return ret;
557
558 st->act_time_ms = act_time_ms;
559
560 return ret;
561 }
562
adxl372_set_inactivity_time_ms(struct adxl372_state * st,unsigned int inact_time_ms)563 static int adxl372_set_inactivity_time_ms(struct adxl372_state *st,
564 unsigned int inact_time_ms)
565 {
566 unsigned int reg_val_h, reg_val_l, res, scale_factor;
567 int ret;
568
569 /*
570 * The scale factor of the TIME_INACT register depends on the ODR.
571 * A higher scale factor is used at the maximum ODR and a lower
572 * one at all other rates.
573 */
574 if (st->odr == st->chip_info->max_odr)
575 scale_factor = st->chip_info->inact_time_scale_ms;
576 else
577 scale_factor = st->chip_info->inact_time_scale_low_ms;
578
579 res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor);
580 reg_val_h = (res >> 8) & 0xFF;
581 reg_val_l = res & 0xFF;
582
583 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_H, reg_val_h);
584 if (ret < 0)
585 return ret;
586
587 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_L, reg_val_l);
588 if (ret < 0)
589 return ret;
590
591 st->inact_time_ms = inact_time_ms;
592
593 return ret;
594 }
595
adxl372_set_interrupts(struct adxl372_state * st,unsigned long int1_bitmask,unsigned long int2_bitmask)596 static int adxl372_set_interrupts(struct adxl372_state *st,
597 unsigned long int1_bitmask,
598 unsigned long int2_bitmask)
599 {
600 int ret;
601
602 ret = regmap_write(st->regmap, ADXL372_INT1_MAP, int1_bitmask);
603 if (ret < 0)
604 return ret;
605
606 return regmap_write(st->regmap, ADXL372_INT2_MAP, int2_bitmask);
607 }
608
adxl372_configure_fifo(struct adxl372_state * st)609 static int adxl372_configure_fifo(struct adxl372_state *st)
610 {
611 unsigned int fifo_samples, fifo_ctl;
612 int ret;
613
614 /* FIFO must be configured while in standby mode */
615 ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
616 if (ret < 0)
617 return ret;
618
619 /*
620 * watermark stores the number of sets; we need to write the FIFO
621 * registers with the number of samples
622 */
623 fifo_samples = (st->watermark * st->fifo_set_size);
624 fifo_ctl = ADXL372_FIFO_CTL_FORMAT_MODE(st->fifo_format) |
625 ADXL372_FIFO_CTL_MODE_MODE(st->fifo_mode) |
626 ADXL372_FIFO_CTL_SAMPLES_MODE(fifo_samples);
627
628 ret = regmap_write(st->regmap,
629 ADXL372_FIFO_SAMPLES, fifo_samples & 0xFF);
630 if (ret < 0)
631 return ret;
632
633 ret = regmap_write(st->regmap, ADXL372_FIFO_CTL, fifo_ctl);
634 if (ret < 0)
635 return ret;
636
637 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT);
638 }
639
adxl372_get_status(struct adxl372_state * st,u8 * status1,u8 * status2,u16 * fifo_entries)640 static int adxl372_get_status(struct adxl372_state *st,
641 u8 *status1, u8 *status2,
642 u16 *fifo_entries)
643 {
644 __be32 buf;
645 u32 val;
646 int ret;
647
648 /* STATUS1, STATUS2, FIFO_ENTRIES2 and FIFO_ENTRIES are adjacent regs */
649 ret = regmap_bulk_read(st->regmap, ADXL372_STATUS_1,
650 &buf, sizeof(buf));
651 if (ret < 0)
652 return ret;
653
654 val = be32_to_cpu(buf);
655
656 *status1 = (val >> 24) & 0x0F;
657 *status2 = (val >> 16) & 0x0F;
658 /*
659 * FIFO_ENTRIES contains the least significant byte, and FIFO_ENTRIES2
660 * contains the two most significant bits
661 */
662 *fifo_entries = val & 0x3FF;
663
664 return ret;
665 }
666
adxl372_arrange_axis_data(struct adxl372_state * st,__be16 * sample)667 static void adxl372_arrange_axis_data(struct adxl372_state *st, __be16 *sample)
668 {
669 __be16 axis_sample[3] = { };
670 int i = 0;
671
672 if (ADXL372_X_AXIS_EN(st->fifo_axis_mask))
673 axis_sample[i++] = sample[0];
674 if (ADXL372_Y_AXIS_EN(st->fifo_axis_mask))
675 axis_sample[i++] = sample[1];
676 if (ADXL372_Z_AXIS_EN(st->fifo_axis_mask))
677 axis_sample[i++] = sample[2];
678
679 memcpy(sample, axis_sample, 3 * sizeof(__be16));
680 }
681
adxl372_push_event(struct iio_dev * indio_dev,s64 timestamp,u8 status2)682 static void adxl372_push_event(struct iio_dev *indio_dev, s64 timestamp, u8 status2)
683 {
684 unsigned int ev_dir = IIO_EV_DIR_NONE;
685
686 if (ADXL372_STATUS_2_ACT(status2))
687 ev_dir = IIO_EV_DIR_RISING;
688
689 if (ADXL372_STATUS_2_INACT(status2))
690 ev_dir = IIO_EV_DIR_FALLING;
691
692 if (ev_dir != IIO_EV_DIR_NONE)
693 iio_push_event(indio_dev,
694 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
695 IIO_EV_TYPE_THRESH, ev_dir),
696 timestamp);
697 }
698
adxl372_trigger_handler(int irq,void * p)699 static irqreturn_t adxl372_trigger_handler(int irq, void *p)
700 {
701 struct iio_poll_func *pf = p;
702 struct iio_dev *indio_dev = pf->indio_dev;
703 struct adxl372_state *st = iio_priv(indio_dev);
704 u8 status1, status2;
705 u16 fifo_entries;
706 int i, ret;
707
708 ret = adxl372_get_status(st, &status1, &status2, &fifo_entries);
709 if (ret < 0)
710 goto err;
711
712 adxl372_push_event(indio_dev, iio_get_time_ns(indio_dev), status2);
713
714 if (st->fifo_mode != ADXL372_FIFO_BYPASSED &&
715 ADXL372_STATUS_1_FIFO_FULL(status1)) {
716 /*
717 * When reading data from multiple axes from the FIFO,
718 * to ensure that data is not overwritten and stored out
719 * of order at least one sample set must be left in the
720 * FIFO after every read.
721 */
722 fifo_entries -= st->fifo_set_size;
723
724 /* Read data from the FIFO */
725 ret = regmap_noinc_read(st->regmap, ADXL372_FIFO_DATA,
726 st->fifo_buf,
727 fifo_entries * sizeof(u16));
728 if (ret < 0)
729 goto err;
730
731 /* Each sample is 2 bytes */
732 for (i = 0; i < fifo_entries; i += st->fifo_set_size) {
733 /* filter peak detection data */
734 if (st->peak_fifo_mode_en)
735 adxl372_arrange_axis_data(st, &st->fifo_buf[i]);
736 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
737 }
738 }
739 err:
740 iio_trigger_notify_done(indio_dev->trig);
741 return IRQ_HANDLED;
742 }
743
adxl372_setup(struct adxl372_state * st)744 static int adxl372_setup(struct adxl372_state *st)
745 {
746 unsigned int regval;
747 int ret;
748
749 ret = regmap_read(st->regmap, ADXL372_DEVID, ®val);
750 if (ret < 0)
751 return ret;
752
753 if (regval != ADXL372_DEVID_VAL) {
754 dev_err(st->dev, "Invalid chip id %x\n", regval);
755 return -ENODEV;
756 }
757
758 /*
759 * Perform a software reset to make sure the device is in a consistent
760 * state after start up.
761 */
762 ret = regmap_write(st->regmap, ADXL372_RESET, ADXL372_RESET_CODE);
763 if (ret < 0)
764 return ret;
765
766 ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
767 if (ret < 0)
768 return ret;
769
770 /* Set threshold for activity detection to 1g */
771 ret = adxl372_set_activity_threshold(st, ADXL372_ACTIVITY,
772 true, true, 1000);
773 if (ret < 0)
774 return ret;
775
776 /* Set threshold for inactivity detection to 100mg */
777 ret = adxl372_set_activity_threshold(st, ADXL372_INACTIVITY,
778 true, true, 100);
779 if (ret < 0)
780 return ret;
781
782 /* Set activity processing in Looped mode */
783 ret = adxl372_set_act_proc_mode(st, ADXL372_LOOPED);
784 if (ret < 0)
785 return ret;
786
787 ret = adxl372_set_odr(st, st->chip_info->max_odr);
788 if (ret < 0)
789 return ret;
790
791 ret = adxl372_set_bandwidth(st, ADXL372_BW_3200HZ);
792 if (ret < 0)
793 return ret;
794
795 /* Set activity timer to 1ms */
796 ret = adxl372_set_activity_time_ms(st, 1);
797 if (ret < 0)
798 return ret;
799
800 /* Set inactivity timer to 10s */
801 ret = adxl372_set_inactivity_time_ms(st, 10000);
802 if (ret < 0)
803 return ret;
804
805 /* Set the mode of operation to full bandwidth measurement mode */
806 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT);
807 }
808
adxl372_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)809 static int adxl372_reg_access(struct iio_dev *indio_dev,
810 unsigned int reg,
811 unsigned int writeval,
812 unsigned int *readval)
813 {
814 struct adxl372_state *st = iio_priv(indio_dev);
815
816 if (readval)
817 return regmap_read(st->regmap, reg, readval);
818 else
819 return regmap_write(st->regmap, reg, writeval);
820 }
821
adxl372_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)822 static int adxl372_read_raw(struct iio_dev *indio_dev,
823 struct iio_chan_spec const *chan,
824 int *val, int *val2, long info)
825 {
826 struct adxl372_state *st = iio_priv(indio_dev);
827 int ret;
828
829 switch (info) {
830 case IIO_CHAN_INFO_RAW:
831 if (!iio_device_claim_direct(indio_dev))
832 return -EBUSY;
833
834 ret = adxl372_read_axis(st, chan->address);
835 iio_device_release_direct(indio_dev);
836 if (ret < 0)
837 return ret;
838
839 *val = sign_extend32(ret >> chan->scan_type.shift,
840 chan->scan_type.realbits - 1);
841 return IIO_VAL_INT;
842 case IIO_CHAN_INFO_SCALE:
843 *val = 0;
844 *val2 = ADXL372_USCALE;
845 return IIO_VAL_INT_PLUS_MICRO;
846 case IIO_CHAN_INFO_SAMP_FREQ:
847 *val = st->chip_info->samp_freq_tbl[st->odr];
848 return IIO_VAL_INT;
849 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
850 *val = st->chip_info->bw_freq_tbl[st->bw];
851 return IIO_VAL_INT;
852 }
853
854 return -EINVAL;
855 }
856
adxl372_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)857 static int adxl372_write_raw(struct iio_dev *indio_dev,
858 struct iio_chan_spec const *chan,
859 int val, int val2, long info)
860 {
861 struct adxl372_state *st = iio_priv(indio_dev);
862 int odr_index, bw_index, ret;
863
864 switch (info) {
865 case IIO_CHAN_INFO_SAMP_FREQ:
866 odr_index = adxl372_find_closest_match(st->chip_info->samp_freq_tbl,
867 st->chip_info->num_freqs,
868 val);
869 ret = adxl372_set_odr(st, odr_index);
870 if (ret < 0)
871 return ret;
872 /* Recalculate activity time as the timer period depends on ODR */
873 ret = adxl372_set_activity_time_ms(st, st->act_time_ms);
874 if (ret < 0)
875 return ret;
876 /* Recalculate inactivity time as the timer period depends on ODR */
877 ret = adxl372_set_inactivity_time_ms(st, st->inact_time_ms);
878 if (ret < 0)
879 return ret;
880 /*
881 * The maximum bandwidth is constrained to at most half of
882 * the ODR to ensure that the Nyquist criteria is not violated
883 */
884 if (st->bw > odr_index)
885 ret = adxl372_set_bandwidth(st, odr_index);
886
887 return ret;
888 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
889 bw_index = adxl372_find_closest_match(st->chip_info->bw_freq_tbl,
890 st->chip_info->num_freqs,
891 val);
892 return adxl372_set_bandwidth(st, bw_index);
893 default:
894 return -EINVAL;
895 }
896 }
897
adxl372_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)898 static int adxl372_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
899 enum iio_event_type type, enum iio_event_direction dir,
900 enum iio_event_info info, int *val, int *val2)
901 {
902 struct adxl372_state *st = iio_priv(indio_dev);
903 unsigned int addr;
904 u16 raw_value;
905 int ret;
906
907 switch (info) {
908 case IIO_EV_INFO_VALUE:
909 switch (dir) {
910 case IIO_EV_DIR_RISING:
911 addr = ADXL372_X_THRESH_ACT_H + 2 * chan->scan_index;
912 ret = adxl372_read_threshold_value(indio_dev, addr, &raw_value);
913 if (ret < 0)
914 return ret;
915 *val = raw_value * ADXL372_USCALE;
916 *val2 = 1000000;
917 return IIO_VAL_FRACTIONAL;
918 case IIO_EV_DIR_FALLING:
919 addr = ADXL372_X_THRESH_INACT_H + 2 * chan->scan_index;
920 ret = adxl372_read_threshold_value(indio_dev, addr, &raw_value);
921 if (ret < 0)
922 return ret;
923 *val = raw_value * ADXL372_USCALE;
924 *val2 = 1000000;
925 return IIO_VAL_FRACTIONAL;
926 default:
927 return -EINVAL;
928 }
929 case IIO_EV_INFO_PERIOD:
930 switch (dir) {
931 case IIO_EV_DIR_RISING:
932 *val = st->act_time_ms;
933 *val2 = 1000;
934 return IIO_VAL_FRACTIONAL;
935 case IIO_EV_DIR_FALLING:
936 *val = st->inact_time_ms;
937 *val2 = 1000;
938 return IIO_VAL_FRACTIONAL;
939 default:
940 return -EINVAL;
941 }
942 default:
943 return -EINVAL;
944 }
945 }
946
adxl372_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)947 static int adxl372_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
948 enum iio_event_type type, enum iio_event_direction dir,
949 enum iio_event_info info, int val, int val2)
950 {
951 struct adxl372_state *st = iio_priv(indio_dev);
952 unsigned int val_ms;
953 unsigned int addr;
954 u16 raw_val;
955
956 switch (info) {
957 case IIO_EV_INFO_VALUE:
958 raw_val = DIV_ROUND_UP(val * 1000000, ADXL372_USCALE);
959 switch (dir) {
960 case IIO_EV_DIR_RISING:
961 addr = ADXL372_X_THRESH_ACT_H + 2 * chan->scan_index;
962 return adxl372_write_threshold_value(indio_dev, addr, raw_val);
963 case IIO_EV_DIR_FALLING:
964 addr = ADXL372_X_THRESH_INACT_H + 2 * chan->scan_index;
965 return adxl372_write_threshold_value(indio_dev, addr, raw_val);
966 default:
967 return -EINVAL;
968 }
969 case IIO_EV_INFO_PERIOD:
970 val_ms = val * 1000 + DIV_ROUND_UP(val2, 1000);
971 switch (dir) {
972 case IIO_EV_DIR_RISING:
973 return adxl372_set_activity_time_ms(st, val_ms);
974 case IIO_EV_DIR_FALLING:
975 return adxl372_set_inactivity_time_ms(st, val_ms);
976 default:
977 return -EINVAL;
978 }
979 default:
980 return -EINVAL;
981 }
982 }
983
adxl372_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)984 static int adxl372_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
985 enum iio_event_type type, enum iio_event_direction dir)
986 {
987 struct adxl372_state *st = iio_priv(indio_dev);
988
989 switch (dir) {
990 case IIO_EV_DIR_RISING:
991 return FIELD_GET(ADXL372_INT1_MAP_ACT_MSK, st->int1_bitmask);
992 case IIO_EV_DIR_FALLING:
993 return FIELD_GET(ADXL372_INT1_MAP_INACT_MSK, st->int1_bitmask);
994 default:
995 return -EINVAL;
996 }
997 }
998
adxl372_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)999 static int adxl372_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
1000 enum iio_event_type type, enum iio_event_direction dir,
1001 bool state)
1002 {
1003 struct adxl372_state *st = iio_priv(indio_dev);
1004
1005 switch (dir) {
1006 case IIO_EV_DIR_RISING:
1007 set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_ACT_MSK,
1008 ADXL372_INT1_MAP_ACT_MODE(state));
1009 break;
1010 case IIO_EV_DIR_FALLING:
1011 set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_INACT_MSK,
1012 ADXL372_INT1_MAP_INACT_MODE(state));
1013 break;
1014 default:
1015 return -EINVAL;
1016 }
1017
1018 return adxl372_set_interrupts(st, st->int1_bitmask, 0);
1019 }
1020
adxl372_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)1021 static ssize_t adxl372_get_fifo_enabled(struct device *dev,
1022 struct device_attribute *attr,
1023 char *buf)
1024 {
1025 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1026 struct adxl372_state *st = iio_priv(indio_dev);
1027
1028 return sprintf(buf, "%d\n", st->fifo_mode);
1029 }
1030
adxl372_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)1031 static ssize_t adxl372_get_fifo_watermark(struct device *dev,
1032 struct device_attribute *attr,
1033 char *buf)
1034 {
1035 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1036 struct adxl372_state *st = iio_priv(indio_dev);
1037
1038 return sprintf(buf, "%d\n", st->watermark);
1039 }
1040
1041 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
1042 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
1043 __stringify(ADXL372_FIFO_SIZE));
1044 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1045 adxl372_get_fifo_watermark, NULL, 0);
1046 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1047 adxl372_get_fifo_enabled, NULL, 0);
1048
1049 static const struct iio_dev_attr *adxl372_fifo_attributes[] = {
1050 &iio_dev_attr_hwfifo_watermark_min,
1051 &iio_dev_attr_hwfifo_watermark_max,
1052 &iio_dev_attr_hwfifo_watermark,
1053 &iio_dev_attr_hwfifo_enabled,
1054 NULL,
1055 };
1056
adxl372_set_watermark(struct iio_dev * indio_dev,unsigned int val)1057 static int adxl372_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1058 {
1059 struct adxl372_state *st = iio_priv(indio_dev);
1060
1061 if (val > ADXL372_FIFO_SIZE)
1062 val = ADXL372_FIFO_SIZE;
1063
1064 st->watermark = val;
1065
1066 return 0;
1067 }
1068
adxl372_buffer_postenable(struct iio_dev * indio_dev)1069 static int adxl372_buffer_postenable(struct iio_dev *indio_dev)
1070 {
1071 struct adxl372_state *st = iio_priv(indio_dev);
1072 unsigned int mask;
1073 int i, ret;
1074
1075 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK;
1076 ret = adxl372_set_interrupts(st, st->int1_bitmask, 0);
1077 if (ret < 0)
1078 return ret;
1079
1080 mask = *indio_dev->active_scan_mask;
1081
1082 for (i = 0; i < ARRAY_SIZE(adxl372_axis_lookup_table); i++) {
1083 if (mask == adxl372_axis_lookup_table[i].bits)
1084 break;
1085 }
1086
1087 if (i == ARRAY_SIZE(adxl372_axis_lookup_table))
1088 return -EINVAL;
1089
1090 st->fifo_format = adxl372_axis_lookup_table[i].fifo_format;
1091 st->fifo_axis_mask = adxl372_axis_lookup_table[i].bits;
1092 st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask,
1093 iio_get_masklength(indio_dev));
1094
1095 /* Configure the FIFO to store sets of impact event peak. */
1096 if (st->peak_fifo_mode_en) {
1097 st->fifo_set_size = 3;
1098 st->fifo_format = ADXL372_XYZ_PEAK_FIFO;
1099 }
1100
1101 /*
1102 * The 512 FIFO samples can be allotted in several ways, such as:
1103 * 170 sample sets of concurrent 3-axis data
1104 * 256 sample sets of concurrent 2-axis data (user selectable)
1105 * 512 sample sets of single-axis data
1106 * 170 sets of impact event peak (x, y, z)
1107 */
1108 if ((st->watermark * st->fifo_set_size) > ADXL372_FIFO_SIZE)
1109 st->watermark = (ADXL372_FIFO_SIZE / st->fifo_set_size);
1110
1111 st->fifo_mode = ADXL372_FIFO_STREAMED;
1112
1113 ret = adxl372_configure_fifo(st);
1114 if (ret < 0) {
1115 st->fifo_mode = ADXL372_FIFO_BYPASSED;
1116 st->int1_bitmask &= ~ADXL372_INT1_MAP_FIFO_FULL_MSK;
1117 adxl372_set_interrupts(st, st->int1_bitmask, 0);
1118 return ret;
1119 }
1120
1121 return 0;
1122 }
1123
adxl372_buffer_predisable(struct iio_dev * indio_dev)1124 static int adxl372_buffer_predisable(struct iio_dev *indio_dev)
1125 {
1126 struct adxl372_state *st = iio_priv(indio_dev);
1127
1128 st->int1_bitmask &= ~ADXL372_INT1_MAP_FIFO_FULL_MSK;
1129 adxl372_set_interrupts(st, st->int1_bitmask, 0);
1130 st->fifo_mode = ADXL372_FIFO_BYPASSED;
1131 adxl372_configure_fifo(st);
1132
1133 return 0;
1134 }
1135
1136 static const struct iio_buffer_setup_ops adxl372_buffer_ops = {
1137 .postenable = adxl372_buffer_postenable,
1138 .predisable = adxl372_buffer_predisable,
1139 };
1140
adxl372_dready_trig_set_state(struct iio_trigger * trig,bool state)1141 static int adxl372_dready_trig_set_state(struct iio_trigger *trig,
1142 bool state)
1143 {
1144 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1145 struct adxl372_state *st = iio_priv(indio_dev);
1146
1147 if (state)
1148 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK;
1149
1150 return adxl372_set_interrupts(st, st->int1_bitmask, 0);
1151 }
1152
adxl372_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)1153 static int adxl372_validate_trigger(struct iio_dev *indio_dev,
1154 struct iio_trigger *trig)
1155 {
1156 struct adxl372_state *st = iio_priv(indio_dev);
1157
1158 if (st->dready_trig != trig && st->peak_datardy_trig != trig)
1159 return -EINVAL;
1160
1161 return 0;
1162 }
1163
1164 static const struct iio_trigger_ops adxl372_trigger_ops = {
1165 .validate_device = &iio_trigger_validate_own_device,
1166 .set_trigger_state = adxl372_dready_trig_set_state,
1167 };
1168
adxl372_peak_dready_trig_set_state(struct iio_trigger * trig,bool state)1169 static int adxl372_peak_dready_trig_set_state(struct iio_trigger *trig,
1170 bool state)
1171 {
1172 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1173 struct adxl372_state *st = iio_priv(indio_dev);
1174
1175 if (state)
1176 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK;
1177
1178 st->peak_fifo_mode_en = state;
1179
1180 return adxl372_set_interrupts(st, st->int1_bitmask, 0);
1181 }
1182
1183 static const struct iio_trigger_ops adxl372_peak_data_trigger_ops = {
1184 .validate_device = &iio_trigger_validate_own_device,
1185 .set_trigger_state = adxl372_peak_dready_trig_set_state,
1186 };
1187
adxl372_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1188 static int adxl372_read_avail(struct iio_dev *indio_dev,
1189 struct iio_chan_spec const *chan,
1190 const int **vals, int *type, int *length,
1191 long mask)
1192 {
1193 struct adxl372_state *st = iio_priv(indio_dev);
1194
1195 switch (mask) {
1196 case IIO_CHAN_INFO_SAMP_FREQ:
1197 *vals = st->chip_info->samp_freq_tbl;
1198 *type = IIO_VAL_INT;
1199 *length = st->chip_info->num_freqs;
1200 return IIO_AVAIL_LIST;
1201 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1202 *vals = st->chip_info->bw_freq_tbl;
1203 *type = IIO_VAL_INT;
1204 /*
1205 * Bandwidth cannot exceed half the sampling frequency
1206 * (Nyquist), so limit available values based on current ODR.
1207 */
1208 *length = st->odr + 1;
1209 return IIO_AVAIL_LIST;
1210 default:
1211 return -EINVAL;
1212 }
1213 }
1214
1215 static const struct iio_info adxl372_info = {
1216 .validate_trigger = &adxl372_validate_trigger,
1217 .read_raw = adxl372_read_raw,
1218 .write_raw = adxl372_write_raw,
1219 .read_avail = adxl372_read_avail,
1220 .read_event_config = adxl372_read_event_config,
1221 .write_event_config = adxl372_write_event_config,
1222 .read_event_value = adxl372_read_event_value,
1223 .write_event_value = adxl372_write_event_value,
1224 .debugfs_reg_access = &adxl372_reg_access,
1225 .hwfifo_set_watermark = adxl372_set_watermark,
1226 };
1227
adxl372_readable_noinc_reg(struct device * dev,unsigned int reg)1228 bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg)
1229 {
1230 return (reg == ADXL372_FIFO_DATA);
1231 }
1232 EXPORT_SYMBOL_NS_GPL(adxl372_readable_noinc_reg, "IIO_ADXL372");
1233
adxl372_buffer_setup(struct iio_dev * indio_dev)1234 static int adxl372_buffer_setup(struct iio_dev *indio_dev)
1235 {
1236 struct adxl372_state *st = iio_priv(indio_dev);
1237 struct device *dev = st->dev;
1238 int ret;
1239
1240 ret = devm_iio_triggered_buffer_setup_ext(dev, indio_dev, NULL,
1241 adxl372_trigger_handler,
1242 IIO_BUFFER_DIRECTION_IN,
1243 &adxl372_buffer_ops,
1244 adxl372_fifo_attributes);
1245 if (ret)
1246 return ret;
1247
1248 if (!st->irq)
1249 return 0;
1250
1251 st->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1252 indio_dev->name,
1253 iio_device_id(indio_dev));
1254 if (!st->dready_trig)
1255 return -ENOMEM;
1256
1257 st->peak_datardy_trig = devm_iio_trigger_alloc(dev, "%s-dev%d-peak",
1258 indio_dev->name,
1259 iio_device_id(indio_dev));
1260 if (!st->peak_datardy_trig)
1261 return -ENOMEM;
1262
1263 st->dready_trig->ops = &adxl372_trigger_ops;
1264 st->peak_datardy_trig->ops = &adxl372_peak_data_trigger_ops;
1265 iio_trigger_set_drvdata(st->dready_trig, indio_dev);
1266 iio_trigger_set_drvdata(st->peak_datardy_trig, indio_dev);
1267 ret = devm_iio_trigger_register(dev, st->dready_trig);
1268 if (ret)
1269 return ret;
1270
1271 ret = devm_iio_trigger_register(dev, st->peak_datardy_trig);
1272 if (ret)
1273 return ret;
1274
1275 indio_dev->trig = iio_trigger_get(st->dready_trig);
1276
1277 return devm_request_irq(dev, st->irq,
1278 iio_trigger_generic_data_rdy_poll,
1279 IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
1280 indio_dev->name, st->dready_trig);
1281 }
1282
adxl372_probe(struct device * dev,struct regmap * regmap,int irq,const struct adxl372_chip_info * chip_info)1283 int adxl372_probe(struct device *dev, struct regmap *regmap,
1284 int irq, const struct adxl372_chip_info *chip_info)
1285 {
1286 struct iio_dev *indio_dev;
1287 struct adxl372_state *st;
1288 int ret;
1289
1290 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1291 if (!indio_dev)
1292 return -ENOMEM;
1293
1294 st = iio_priv(indio_dev);
1295 dev_set_drvdata(dev, indio_dev);
1296
1297 st->dev = dev;
1298 st->regmap = regmap;
1299 st->irq = irq;
1300 st->chip_info = chip_info;
1301
1302 mutex_init(&st->threshold_m);
1303
1304 indio_dev->channels = adxl372_channels;
1305 indio_dev->num_channels = ARRAY_SIZE(adxl372_channels);
1306 indio_dev->name = chip_info->name;
1307 indio_dev->info = &adxl372_info;
1308
1309 if (chip_info->fifo_supported) {
1310 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1311 indio_dev->available_scan_masks = adxl372_channel_masks;
1312 } else {
1313 indio_dev->modes = INDIO_DIRECT_MODE;
1314 }
1315
1316 ret = adxl372_setup(st);
1317 if (ret < 0) {
1318 dev_err(dev, "ADXL372 setup failed\n");
1319 return ret;
1320 }
1321
1322 if (chip_info->fifo_supported) {
1323 ret = adxl372_buffer_setup(indio_dev);
1324 if (ret < 0)
1325 return ret;
1326 }
1327
1328 return devm_iio_device_register(dev, indio_dev);
1329 }
1330 EXPORT_SYMBOL_NS_GPL(adxl372_probe, "IIO_ADXL372");
1331
1332 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1333 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1334 MODULE_DESCRIPTION("Analog Devices ADXL371/ADXL372 3-axis accelerometer driver");
1335 MODULE_LICENSE("GPL");
1336