1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Richtek Technology Corp.
4 *
5 * ChiYuan Huang <cy_huang@richtek.com>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/property.h>
15 #include <linux/regmap.h>
16 #include <linux/sysfs.h>
17 #include <linux/types.h>
18 #include <linux/util_macros.h>
19
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
25
26 #define RTQ6056_REG_CONFIG 0x00
27 #define RTQ6056_REG_SHUNTVOLT 0x01
28 #define RTQ6056_REG_BUSVOLT 0x02
29 #define RTQ6056_REG_POWER 0x03
30 #define RTQ6056_REG_CURRENT 0x04
31 #define RTQ6056_REG_CALIBRATION 0x05
32 #define RTQ6056_REG_MASKENABLE 0x06
33 #define RTQ6056_REG_ALERTLIMIT 0x07
34 #define RTQ6056_REG_MANUFACTID 0xFE
35 #define RTQ6056_REG_DIEID 0xFF
36
37 #define RTQ6056_VENDOR_ID 0x1214
38 #define RTQ6056_DEFAULT_CONFIG 0x4127
39 #define RTQ6056_CONT_ALLON 7
40
41 #define RTQ6059_DEFAULT_CONFIG 0x3C47
42 #define RTQ6059_VBUS_LSB_OFFSET 3
43 #define RTQ6059_AVG_BASE 8
44
45 enum {
46 RTQ6056_CH_VSHUNT = 0,
47 RTQ6056_CH_VBUS,
48 RTQ6056_CH_POWER,
49 RTQ6056_CH_CURRENT,
50 RTQ6056_MAX_CHANNEL
51 };
52
53 /*
54 * The enum is to present the 0x00 CONFIG RG bitfield for the 16bit RG value
55 * field value order from LSB to MSB
56 * RTQ6053/6 is OPMODE->VSHUNTCT->VBUSCT->AVG->RESET
57 * RTQ6059 is OPMODE->SADC->BADC->PGA->RESET
58 */
59 enum {
60 F_OPMODE = 0,
61 F_VSHUNTCT,
62 F_RTQ6059_SADC = F_VSHUNTCT,
63 F_VBUSCT,
64 F_RTQ6059_BADC = F_VBUSCT,
65 F_AVG,
66 F_RTQ6059_PGA = F_AVG,
67 F_RESET,
68 F_MAX_FIELDS
69 };
70
71 struct rtq6056_priv;
72
73 struct richtek_dev_data {
74 bool fixed_samp_freq;
75 u8 vbus_offset;
76 int default_conv_time_us;
77 unsigned int default_config;
78 unsigned int calib_coefficient;
79 const int *avg_sample_list;
80 int avg_sample_list_length;
81 const struct reg_field *reg_fields;
82 const struct iio_chan_spec *channels;
83 int num_channels;
84 int (*read_scale)(struct iio_chan_spec const *ch, int *val, int *val2);
85 int (*set_average)(struct rtq6056_priv *priv, int val);
86 };
87
88 struct rtq6056_priv {
89 struct device *dev;
90 struct regmap *regmap;
91 struct regmap_field *rm_fields[F_MAX_FIELDS];
92 const struct richtek_dev_data *devdata;
93 u32 shunt_resistor_uohm;
94 int vshuntct_us;
95 int vbusct_us;
96 int avg_sample;
97 };
98
99 static const struct reg_field rtq6056_reg_fields[F_MAX_FIELDS] = {
100 [F_OPMODE] = REG_FIELD(RTQ6056_REG_CONFIG, 0, 2),
101 [F_VSHUNTCT] = REG_FIELD(RTQ6056_REG_CONFIG, 3, 5),
102 [F_VBUSCT] = REG_FIELD(RTQ6056_REG_CONFIG, 6, 8),
103 [F_AVG] = REG_FIELD(RTQ6056_REG_CONFIG, 9, 11),
104 [F_RESET] = REG_FIELD(RTQ6056_REG_CONFIG, 15, 15),
105 };
106
107 static const struct reg_field rtq6059_reg_fields[F_MAX_FIELDS] = {
108 [F_OPMODE] = REG_FIELD(RTQ6056_REG_CONFIG, 0, 2),
109 [F_RTQ6059_SADC] = REG_FIELD(RTQ6056_REG_CONFIG, 3, 6),
110 [F_RTQ6059_BADC] = REG_FIELD(RTQ6056_REG_CONFIG, 7, 10),
111 [F_RTQ6059_PGA] = REG_FIELD(RTQ6056_REG_CONFIG, 11, 12),
112 [F_RESET] = REG_FIELD(RTQ6056_REG_CONFIG, 15, 15),
113 };
114
115 static const struct iio_chan_spec rtq6056_channels[RTQ6056_MAX_CHANNEL + 1] = {
116 {
117 .type = IIO_VOLTAGE,
118 .indexed = 1,
119 .channel = 0,
120 .address = RTQ6056_REG_SHUNTVOLT,
121 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
122 BIT(IIO_CHAN_INFO_SCALE) |
123 BIT(IIO_CHAN_INFO_SAMP_FREQ),
124 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
125 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
126 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
127 .scan_index = 0,
128 .scan_type = {
129 .sign = 's',
130 .realbits = 16,
131 .storagebits = 16,
132 .endianness = IIO_CPU,
133 },
134 },
135 {
136 .type = IIO_VOLTAGE,
137 .indexed = 1,
138 .channel = 1,
139 .address = RTQ6056_REG_BUSVOLT,
140 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
141 BIT(IIO_CHAN_INFO_SCALE) |
142 BIT(IIO_CHAN_INFO_SAMP_FREQ),
143 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
144 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
145 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
146 .scan_index = 1,
147 .scan_type = {
148 .sign = 'u',
149 .realbits = 16,
150 .storagebits = 16,
151 .endianness = IIO_CPU,
152 },
153 },
154 {
155 .type = IIO_POWER,
156 .indexed = 1,
157 .channel = 2,
158 .address = RTQ6056_REG_POWER,
159 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
160 BIT(IIO_CHAN_INFO_SCALE) |
161 BIT(IIO_CHAN_INFO_SAMP_FREQ),
162 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
163 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
164 .scan_index = 2,
165 .scan_type = {
166 .sign = 'u',
167 .realbits = 16,
168 .storagebits = 16,
169 .endianness = IIO_CPU,
170 },
171 },
172 {
173 .type = IIO_CURRENT,
174 .indexed = 1,
175 .channel = 3,
176 .address = RTQ6056_REG_CURRENT,
177 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
178 BIT(IIO_CHAN_INFO_SAMP_FREQ),
179 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
180 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
181 .scan_index = 3,
182 .scan_type = {
183 .sign = 's',
184 .realbits = 16,
185 .storagebits = 16,
186 .endianness = IIO_CPU,
187 },
188 },
189 IIO_CHAN_SOFT_TIMESTAMP(RTQ6056_MAX_CHANNEL),
190 };
191
192 /*
193 * Difference between RTQ6056 and RTQ6059
194 * - Fixed sampling conversion time
195 * - Average sample numbers
196 * - Channel scale
197 * - calibration coefficient
198 */
199 static const struct iio_chan_spec rtq6059_channels[RTQ6056_MAX_CHANNEL + 1] = {
200 {
201 .type = IIO_VOLTAGE,
202 .indexed = 1,
203 .channel = 0,
204 .address = RTQ6056_REG_SHUNTVOLT,
205 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
206 BIT(IIO_CHAN_INFO_SCALE) |
207 BIT(IIO_CHAN_INFO_SAMP_FREQ),
208 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
209 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
210 .scan_index = 0,
211 .scan_type = {
212 .sign = 's',
213 .realbits = 16,
214 .storagebits = 16,
215 .endianness = IIO_CPU,
216 },
217 },
218 {
219 .type = IIO_VOLTAGE,
220 .indexed = 1,
221 .channel = 1,
222 .address = RTQ6056_REG_BUSVOLT,
223 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
224 BIT(IIO_CHAN_INFO_SCALE) |
225 BIT(IIO_CHAN_INFO_SAMP_FREQ),
226 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
227 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
228 .scan_index = 1,
229 .scan_type = {
230 .sign = 'u',
231 .realbits = 16,
232 .storagebits = 16,
233 .endianness = IIO_CPU,
234 },
235 },
236 {
237 .type = IIO_POWER,
238 .indexed = 1,
239 .channel = 2,
240 .address = RTQ6056_REG_POWER,
241 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
242 BIT(IIO_CHAN_INFO_SCALE) |
243 BIT(IIO_CHAN_INFO_SAMP_FREQ),
244 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
245 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
246 .scan_index = 2,
247 .scan_type = {
248 .sign = 'u',
249 .realbits = 16,
250 .storagebits = 16,
251 .endianness = IIO_CPU,
252 },
253 },
254 {
255 .type = IIO_CURRENT,
256 .indexed = 1,
257 .channel = 3,
258 .address = RTQ6056_REG_CURRENT,
259 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
260 BIT(IIO_CHAN_INFO_SAMP_FREQ),
261 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
262 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
263 .scan_index = 3,
264 .scan_type = {
265 .sign = 's',
266 .realbits = 16,
267 .storagebits = 16,
268 .endianness = IIO_CPU,
269 },
270 },
271 IIO_CHAN_SOFT_TIMESTAMP(RTQ6056_MAX_CHANNEL),
272 };
273
rtq6056_adc_read_channel(struct rtq6056_priv * priv,struct iio_chan_spec const * ch,int * val)274 static int rtq6056_adc_read_channel(struct rtq6056_priv *priv,
275 struct iio_chan_spec const *ch,
276 int *val)
277 {
278 const struct richtek_dev_data *devdata = priv->devdata;
279 struct device *dev = priv->dev;
280 unsigned int addr = ch->address;
281 unsigned int regval;
282 int ret;
283
284 pm_runtime_get_sync(dev);
285 ret = regmap_read(priv->regmap, addr, ®val);
286 pm_runtime_mark_last_busy(dev);
287 pm_runtime_put(dev);
288 if (ret)
289 return ret;
290
291 /* Power and VBUS is unsigned 16-bit, others are signed 16-bit */
292 switch (addr) {
293 case RTQ6056_REG_BUSVOLT:
294 regval >>= devdata->vbus_offset;
295 *val = regval;
296 return IIO_VAL_INT;
297 case RTQ6056_REG_POWER:
298 *val = regval;
299 return IIO_VAL_INT;
300 case RTQ6056_REG_SHUNTVOLT:
301 case RTQ6056_REG_CURRENT:
302 *val = sign_extend32(regval, 15);
303 return IIO_VAL_INT;
304 default:
305 return -EINVAL;
306 }
307 }
308
rtq6056_adc_read_scale(struct iio_chan_spec const * ch,int * val,int * val2)309 static int rtq6056_adc_read_scale(struct iio_chan_spec const *ch, int *val,
310 int *val2)
311 {
312 switch (ch->address) {
313 case RTQ6056_REG_SHUNTVOLT:
314 /* VSHUNT lsb 2.5uV */
315 *val = 2500;
316 *val2 = 1000000;
317 return IIO_VAL_FRACTIONAL;
318 case RTQ6056_REG_BUSVOLT:
319 /* VBUS lsb 1.25mV */
320 *val = 1250;
321 *val2 = 1000;
322 return IIO_VAL_FRACTIONAL;
323 case RTQ6056_REG_POWER:
324 /* Power lsb 25mW */
325 *val = 25;
326 return IIO_VAL_INT;
327 default:
328 return -EINVAL;
329 }
330 }
331
rtq6059_adc_read_scale(struct iio_chan_spec const * ch,int * val,int * val2)332 static int rtq6059_adc_read_scale(struct iio_chan_spec const *ch, int *val,
333 int *val2)
334 {
335 switch (ch->address) {
336 case RTQ6056_REG_SHUNTVOLT:
337 /* VSHUNT lsb 10uV */
338 *val = 10000;
339 *val2 = 1000000;
340 return IIO_VAL_FRACTIONAL;
341 case RTQ6056_REG_BUSVOLT:
342 /* VBUS lsb 4mV */
343 *val = 4;
344 return IIO_VAL_INT;
345 case RTQ6056_REG_POWER:
346 /* Power lsb 20mW */
347 *val = 20;
348 return IIO_VAL_INT;
349 default:
350 return -EINVAL;
351 }
352 }
353
354 /*
355 * Sample frequency for channel VSHUNT and VBUS. The indices correspond
356 * with the bit value expected by the chip. And it can be found at
357 * https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf
358 */
359 static const int rtq6056_samp_freq_list[] = {
360 7194, 4926, 3717, 1904, 964, 485, 243, 122,
361 };
362
rtq6056_adc_set_samp_freq(struct rtq6056_priv * priv,struct iio_chan_spec const * ch,int val)363 static int rtq6056_adc_set_samp_freq(struct rtq6056_priv *priv,
364 struct iio_chan_spec const *ch, int val)
365 {
366 struct regmap_field *rm_field;
367 unsigned int selector;
368 int *ct, ret;
369
370 if (val > 7194 || val < 122)
371 return -EINVAL;
372
373 if (ch->address == RTQ6056_REG_SHUNTVOLT) {
374 rm_field = priv->rm_fields[F_VSHUNTCT];
375 ct = &priv->vshuntct_us;
376 } else if (ch->address == RTQ6056_REG_BUSVOLT) {
377 rm_field = priv->rm_fields[F_VBUSCT];
378 ct = &priv->vbusct_us;
379 } else
380 return -EINVAL;
381
382 selector = find_closest_descending(val, rtq6056_samp_freq_list,
383 ARRAY_SIZE(rtq6056_samp_freq_list));
384
385 ret = regmap_field_write(rm_field, selector);
386 if (ret)
387 return ret;
388
389 *ct = 1000000 / rtq6056_samp_freq_list[selector];
390
391 return 0;
392 }
393
394 /*
395 * Available averaging rate for rtq6056. The indices correspond with the bit
396 * value expected by the chip. And it can be found at
397 * https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf
398 */
399 static const int rtq6056_avg_sample_list[] = {
400 1, 4, 16, 64, 128, 256, 512, 1024,
401 };
402
403 static const int rtq6059_avg_sample_list[] = {
404 1, 2, 4, 8, 16, 32, 64, 128,
405 };
406
rtq6056_adc_set_average(struct rtq6056_priv * priv,int val)407 static int rtq6056_adc_set_average(struct rtq6056_priv *priv, int val)
408 {
409 unsigned int selector;
410 int ret;
411
412 if (val > 1024 || val < 1)
413 return -EINVAL;
414
415 selector = find_closest(val, rtq6056_avg_sample_list,
416 ARRAY_SIZE(rtq6056_avg_sample_list));
417
418 ret = regmap_field_write(priv->rm_fields[F_AVG], selector);
419 if (ret)
420 return ret;
421
422 priv->avg_sample = rtq6056_avg_sample_list[selector];
423
424 return 0;
425 }
426
rtq6059_adc_set_average(struct rtq6056_priv * priv,int val)427 static int rtq6059_adc_set_average(struct rtq6056_priv *priv, int val)
428 {
429 unsigned int selector;
430 int ret;
431
432 if (val > 128 || val < 1)
433 return -EINVAL;
434
435 /* The supported average sample is 2^x (x from 0 to 7) */
436 selector = fls(val) - 1;
437
438 ret = regmap_field_write(priv->rm_fields[F_RTQ6059_BADC],
439 RTQ6059_AVG_BASE + selector);
440 if (ret)
441 return ret;
442
443 ret = regmap_field_write(priv->rm_fields[F_RTQ6059_SADC],
444 RTQ6059_AVG_BASE + selector);
445
446 priv->avg_sample = BIT(selector);
447
448 return 0;
449 }
450
rtq6056_adc_get_sample_freq(struct rtq6056_priv * priv,struct iio_chan_spec const * ch,int * val)451 static int rtq6056_adc_get_sample_freq(struct rtq6056_priv *priv,
452 struct iio_chan_spec const *ch, int *val)
453 {
454 int sample_time;
455
456 if (ch->address == RTQ6056_REG_SHUNTVOLT)
457 sample_time = priv->vshuntct_us;
458 else if (ch->address == RTQ6056_REG_BUSVOLT)
459 sample_time = priv->vbusct_us;
460 else {
461 sample_time = priv->vshuntct_us + priv->vbusct_us;
462 sample_time *= priv->avg_sample;
463 }
464
465 *val = 1000000 / sample_time;
466
467 return IIO_VAL_INT;
468 }
469
rtq6056_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)470 static int rtq6056_adc_read_raw(struct iio_dev *indio_dev,
471 struct iio_chan_spec const *chan, int *val,
472 int *val2, long mask)
473 {
474 struct rtq6056_priv *priv = iio_priv(indio_dev);
475 const struct richtek_dev_data *devdata = priv->devdata;
476
477 switch (mask) {
478 case IIO_CHAN_INFO_RAW:
479 return rtq6056_adc_read_channel(priv, chan, val);
480 case IIO_CHAN_INFO_SCALE:
481 return devdata->read_scale(chan, val, val2);
482 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
483 *val = priv->avg_sample;
484 return IIO_VAL_INT;
485 case IIO_CHAN_INFO_SAMP_FREQ:
486 return rtq6056_adc_get_sample_freq(priv, chan, val);
487 default:
488 return -EINVAL;
489 }
490 }
491
rtq6056_adc_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)492 static int rtq6056_adc_read_avail(struct iio_dev *indio_dev,
493 struct iio_chan_spec const *chan,
494 const int **vals, int *type, int *length,
495 long mask)
496 {
497 struct rtq6056_priv *priv = iio_priv(indio_dev);
498 const struct richtek_dev_data *devdata = priv->devdata;
499
500 switch (mask) {
501 case IIO_CHAN_INFO_SAMP_FREQ:
502 *vals = rtq6056_samp_freq_list;
503 *type = IIO_VAL_INT;
504 *length = ARRAY_SIZE(rtq6056_samp_freq_list);
505 return IIO_AVAIL_LIST;
506 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
507 *vals = devdata->avg_sample_list;
508 *length = devdata->avg_sample_list_length;
509 *type = IIO_VAL_INT;
510 return IIO_AVAIL_LIST;
511 default:
512 return -EINVAL;
513 }
514 }
515
__rtq6056_adc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,long mask)516 static int __rtq6056_adc_write_raw(struct iio_dev *indio_dev,
517 struct iio_chan_spec const *chan, int val,
518 long mask)
519 {
520 struct rtq6056_priv *priv = iio_priv(indio_dev);
521 const struct richtek_dev_data *devdata = priv->devdata;
522
523 switch (mask) {
524 case IIO_CHAN_INFO_SAMP_FREQ:
525 if (devdata->fixed_samp_freq)
526 return -EINVAL;
527 return rtq6056_adc_set_samp_freq(priv, chan, val);
528 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
529 return devdata->set_average(priv, val);
530 default:
531 return -EINVAL;
532 }
533 }
534
rtq6056_adc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)535 static int rtq6056_adc_write_raw(struct iio_dev *indio_dev,
536 struct iio_chan_spec const *chan, int val,
537 int val2, long mask)
538 {
539 int ret;
540
541 if (!iio_device_claim_direct(indio_dev))
542 return -EBUSY;
543
544 ret = __rtq6056_adc_write_raw(indio_dev, chan, val, mask);
545 iio_device_release_direct(indio_dev);
546 return ret;
547 }
548
549 static const char *rtq6056_channel_labels[RTQ6056_MAX_CHANNEL] = {
550 [RTQ6056_CH_VSHUNT] = "Vshunt",
551 [RTQ6056_CH_VBUS] = "Vbus",
552 [RTQ6056_CH_POWER] = "Power",
553 [RTQ6056_CH_CURRENT] = "Current",
554 };
555
rtq6056_adc_read_label(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,char * label)556 static int rtq6056_adc_read_label(struct iio_dev *indio_dev,
557 struct iio_chan_spec const *chan,
558 char *label)
559 {
560 return sysfs_emit(label, "%s\n", rtq6056_channel_labels[chan->channel]);
561 }
562
rtq6056_set_shunt_resistor(struct rtq6056_priv * priv,int resistor_uohm)563 static int rtq6056_set_shunt_resistor(struct rtq6056_priv *priv,
564 int resistor_uohm)
565 {
566 const struct richtek_dev_data *devdata = priv->devdata;
567 unsigned int calib_val;
568 int ret;
569
570 if (resistor_uohm <= 0) {
571 dev_err(priv->dev, "Invalid resistor [%d]\n", resistor_uohm);
572 return -EINVAL;
573 }
574
575 /* calibration = coefficient / (Rshunt (uOhm) * current lsb (1mA)) */
576 calib_val = devdata->calib_coefficient / resistor_uohm;
577 ret = regmap_write(priv->regmap, RTQ6056_REG_CALIBRATION, calib_val);
578 if (ret)
579 return ret;
580
581 priv->shunt_resistor_uohm = resistor_uohm;
582
583 return 0;
584 }
585
shunt_resistor_show(struct device * dev,struct device_attribute * attr,char * buf)586 static ssize_t shunt_resistor_show(struct device *dev,
587 struct device_attribute *attr, char *buf)
588 {
589 struct rtq6056_priv *priv = iio_priv(dev_to_iio_dev(dev));
590 int vals[2] = { priv->shunt_resistor_uohm, 1000000 };
591
592 return iio_format_value(buf, IIO_VAL_FRACTIONAL, 1, vals);
593 }
594
shunt_resistor_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)595 static ssize_t shunt_resistor_store(struct device *dev,
596 struct device_attribute *attr,
597 const char *buf, size_t len)
598 {
599 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
600 struct rtq6056_priv *priv = iio_priv(indio_dev);
601 int val, val_fract, ret;
602
603 if (!iio_device_claim_direct(indio_dev))
604 return -EBUSY;
605
606 ret = iio_str_to_fixpoint(buf, 100000, &val, &val_fract);
607 if (ret)
608 goto out_store;
609
610 ret = rtq6056_set_shunt_resistor(priv, val * 1000000 + val_fract);
611
612 out_store:
613 iio_device_release_direct(indio_dev);
614
615 return ret ?: len;
616 }
617
618 static IIO_DEVICE_ATTR_RW(shunt_resistor, 0);
619
620 static struct attribute *rtq6056_attributes[] = {
621 &iio_dev_attr_shunt_resistor.dev_attr.attr,
622 NULL
623 };
624
625 static const struct attribute_group rtq6056_attribute_group = {
626 .attrs = rtq6056_attributes,
627 };
628
629 static const struct iio_info rtq6056_info = {
630 .attrs = &rtq6056_attribute_group,
631 .read_raw = rtq6056_adc_read_raw,
632 .read_avail = rtq6056_adc_read_avail,
633 .write_raw = rtq6056_adc_write_raw,
634 .read_label = rtq6056_adc_read_label,
635 };
636
rtq6056_buffer_trigger_handler(int irq,void * p)637 static irqreturn_t rtq6056_buffer_trigger_handler(int irq, void *p)
638 {
639 struct iio_poll_func *pf = p;
640 struct iio_dev *indio_dev = pf->indio_dev;
641 struct rtq6056_priv *priv = iio_priv(indio_dev);
642 const struct richtek_dev_data *devdata = priv->devdata;
643 struct device *dev = priv->dev;
644 struct {
645 u16 vals[RTQ6056_MAX_CHANNEL];
646 aligned_s64 timestamp;
647 } data = { };
648 unsigned int raw;
649 int i = 0, bit, ret;
650
651 pm_runtime_get_sync(dev);
652
653 iio_for_each_active_channel(indio_dev, bit) {
654 unsigned int addr = rtq6056_channels[bit].address;
655
656 ret = regmap_read(priv->regmap, addr, &raw);
657 if (ret)
658 goto out;
659
660 if (addr == RTQ6056_REG_BUSVOLT)
661 raw >>= devdata->vbus_offset;
662
663 data.vals[i++] = raw;
664 }
665
666 iio_push_to_buffers_with_ts(indio_dev, &data, sizeof(data),
667 iio_get_time_ns(indio_dev));
668
669 out:
670 pm_runtime_mark_last_busy(dev);
671 pm_runtime_put(dev);
672
673 iio_trigger_notify_done(indio_dev->trig);
674
675 return IRQ_HANDLED;
676 }
677
rtq6056_enter_shutdown_state(void * dev)678 static void rtq6056_enter_shutdown_state(void *dev)
679 {
680 struct rtq6056_priv *priv = dev_get_drvdata(dev);
681
682 /* Enter shutdown state */
683 regmap_field_write(priv->rm_fields[F_OPMODE], 0);
684 }
685
rtq6056_is_readable_reg(struct device * dev,unsigned int reg)686 static bool rtq6056_is_readable_reg(struct device *dev, unsigned int reg)
687 {
688 switch (reg) {
689 case RTQ6056_REG_CONFIG ... RTQ6056_REG_ALERTLIMIT:
690 case RTQ6056_REG_MANUFACTID ... RTQ6056_REG_DIEID:
691 return true;
692 default:
693 return false;
694 }
695 }
696
rtq6056_is_writeable_reg(struct device * dev,unsigned int reg)697 static bool rtq6056_is_writeable_reg(struct device *dev, unsigned int reg)
698 {
699 switch (reg) {
700 case RTQ6056_REG_CONFIG:
701 case RTQ6056_REG_CALIBRATION ... RTQ6056_REG_ALERTLIMIT:
702 return true;
703 default:
704 return false;
705 }
706 }
707
708 static const struct regmap_config rtq6056_regmap_config = {
709 .reg_bits = 8,
710 .val_bits = 16,
711 .val_format_endian = REGMAP_ENDIAN_BIG,
712 .max_register = RTQ6056_REG_DIEID,
713 .readable_reg = rtq6056_is_readable_reg,
714 .writeable_reg = rtq6056_is_writeable_reg,
715 };
716
rtq6056_probe(struct i2c_client * i2c)717 static int rtq6056_probe(struct i2c_client *i2c)
718 {
719 struct iio_dev *indio_dev;
720 struct rtq6056_priv *priv;
721 struct device *dev = &i2c->dev;
722 struct regmap *regmap;
723 const struct richtek_dev_data *devdata;
724 unsigned int vendor_id, shunt_resistor_uohm;
725 int ret;
726
727 if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_WORD_DATA))
728 return -EOPNOTSUPP;
729
730 devdata = i2c_get_match_data(i2c);
731 if (!devdata)
732 return dev_err_probe(dev, -EINVAL, "Invalid dev data\n");
733
734 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
735 if (!indio_dev)
736 return -ENOMEM;
737
738 priv = iio_priv(indio_dev);
739 priv->dev = dev;
740 priv->vshuntct_us = priv->vbusct_us = devdata->default_conv_time_us;
741 priv->avg_sample = 1;
742 priv->devdata = devdata;
743 i2c_set_clientdata(i2c, priv);
744
745 regmap = devm_regmap_init_i2c(i2c, &rtq6056_regmap_config);
746 if (IS_ERR(regmap))
747 return dev_err_probe(dev, PTR_ERR(regmap),
748 "Failed to init regmap\n");
749
750 priv->regmap = regmap;
751
752 ret = regmap_read(regmap, RTQ6056_REG_MANUFACTID, &vendor_id);
753 if (ret)
754 return dev_err_probe(dev, ret,
755 "Failed to get manufacturer info\n");
756
757 if (vendor_id != RTQ6056_VENDOR_ID)
758 return dev_err_probe(dev, -ENODEV,
759 "Invalid vendor id 0x%04x\n", vendor_id);
760
761 ret = devm_regmap_field_bulk_alloc(dev, regmap, priv->rm_fields,
762 devdata->reg_fields, F_MAX_FIELDS);
763 if (ret)
764 return dev_err_probe(dev, ret, "Failed to init regmap field\n");
765
766 ret = regmap_write(regmap, RTQ6056_REG_CONFIG, devdata->default_config);
767 if (ret)
768 return dev_err_probe(dev, ret,
769 "Failed to enable continuous sensing\n");
770
771 ret = devm_add_action_or_reset(dev, rtq6056_enter_shutdown_state, dev);
772 if (ret)
773 return ret;
774
775 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
776 pm_runtime_use_autosuspend(dev);
777 pm_runtime_set_active(dev);
778 pm_runtime_mark_last_busy(dev);
779 ret = devm_pm_runtime_enable(dev);
780 if (ret)
781 return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n");
782
783 /* By default, use 2000 micro-Ohm resistor */
784 shunt_resistor_uohm = 2000;
785 device_property_read_u32(dev, "shunt-resistor-micro-ohms",
786 &shunt_resistor_uohm);
787
788 ret = rtq6056_set_shunt_resistor(priv, shunt_resistor_uohm);
789 if (ret)
790 return dev_err_probe(dev, ret,
791 "Failed to init shunt resistor\n");
792
793 indio_dev->name = "rtq6056";
794 indio_dev->modes = INDIO_DIRECT_MODE;
795 indio_dev->channels = devdata->channels;
796 indio_dev->num_channels = devdata->num_channels;
797 indio_dev->info = &rtq6056_info;
798
799 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
800 rtq6056_buffer_trigger_handler,
801 NULL);
802 if (ret)
803 return dev_err_probe(dev, ret,
804 "Failed to allocate iio trigger buffer\n");
805
806 return devm_iio_device_register(dev, indio_dev);
807 }
808
rtq6056_runtime_suspend(struct device * dev)809 static int rtq6056_runtime_suspend(struct device *dev)
810 {
811 struct rtq6056_priv *priv = dev_get_drvdata(dev);
812
813 /* Configure to shutdown mode */
814 return regmap_field_write(priv->rm_fields[F_OPMODE], 0);
815 }
816
rtq6056_runtime_resume(struct device * dev)817 static int rtq6056_runtime_resume(struct device *dev)
818 {
819 struct rtq6056_priv *priv = dev_get_drvdata(dev);
820 int sample_rdy_time_us, ret;
821
822 ret = regmap_field_write(priv->rm_fields[F_OPMODE], RTQ6056_CONT_ALLON);
823 if (ret)
824 return ret;
825
826 sample_rdy_time_us = priv->vbusct_us + priv->vshuntct_us;
827 sample_rdy_time_us *= priv->avg_sample;
828
829 usleep_range(sample_rdy_time_us, sample_rdy_time_us + 100);
830
831 return 0;
832 }
833
834 static DEFINE_RUNTIME_DEV_PM_OPS(rtq6056_pm_ops, rtq6056_runtime_suspend,
835 rtq6056_runtime_resume, NULL);
836
837 static const struct richtek_dev_data rtq6056_devdata = {
838 .default_conv_time_us = 1037,
839 .calib_coefficient = 5120000,
840 /*
841 * By default, configure average sample as 1, bus and shunt conversion
842 * time as 1037 microsecond, and operating mode to all on.
843 */
844 .default_config = RTQ6056_DEFAULT_CONFIG,
845 .avg_sample_list = rtq6056_avg_sample_list,
846 .avg_sample_list_length = ARRAY_SIZE(rtq6056_avg_sample_list),
847 .reg_fields = rtq6056_reg_fields,
848 .channels = rtq6056_channels,
849 .num_channels = ARRAY_SIZE(rtq6056_channels),
850 .read_scale = rtq6056_adc_read_scale,
851 .set_average = rtq6056_adc_set_average,
852 };
853
854 static const struct richtek_dev_data rtq6059_devdata = {
855 .fixed_samp_freq = true,
856 .vbus_offset = RTQ6059_VBUS_LSB_OFFSET,
857 .default_conv_time_us = 532,
858 .calib_coefficient = 40960000,
859 /*
860 * By default, configure average sample as 1, bus and shunt conversion
861 * time as 532 microsecond, and operating mode to all on.
862 */
863 .default_config = RTQ6059_DEFAULT_CONFIG,
864 .avg_sample_list = rtq6059_avg_sample_list,
865 .avg_sample_list_length = ARRAY_SIZE(rtq6059_avg_sample_list),
866 .reg_fields = rtq6059_reg_fields,
867 .channels = rtq6059_channels,
868 .num_channels = ARRAY_SIZE(rtq6059_channels),
869 .read_scale = rtq6059_adc_read_scale,
870 .set_average = rtq6059_adc_set_average,
871 };
872
873 static const struct i2c_device_id rtq6056_id[] = {
874 { .name = "rtq6056", .driver_data = (kernel_ulong_t)&rtq6056_devdata },
875 { .name = "rtq6059", .driver_data = (kernel_ulong_t)&rtq6059_devdata },
876 { }
877 };
878 MODULE_DEVICE_TABLE(i2c, rtq6056_id);
879
880 static const struct of_device_id rtq6056_device_match[] = {
881 { .compatible = "richtek,rtq6056", .data = &rtq6056_devdata },
882 { .compatible = "richtek,rtq6059", .data = &rtq6059_devdata },
883 { }
884 };
885 MODULE_DEVICE_TABLE(of, rtq6056_device_match);
886
887 static struct i2c_driver rtq6056_driver = {
888 .driver = {
889 .name = "rtq6056",
890 .of_match_table = rtq6056_device_match,
891 .pm = pm_ptr(&rtq6056_pm_ops),
892 },
893 .probe = rtq6056_probe,
894 .id_table = rtq6056_id,
895 };
896 module_i2c_driver(rtq6056_driver);
897
898 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
899 MODULE_DESCRIPTION("Richtek RTQ6056 Driver");
900 MODULE_LICENSE("GPL v2");
901