1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/auxiliary_bus.h>
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/cleanup.h>
10 #include <linux/completion.h>
11 #include <linux/container_of.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/device/devres.h>
15 #include <linux/dev_printk.h>
16 #include <linux/err.h>
17 #include <linux/export.h>
18 #include <linux/iio/adc/qcom-adc5-gen3-common.h>
19 #include <linux/iio/iio.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/mutex.h>
24 #include <linux/platform_device.h>
25 #include <linux/property.h>
26 #include <linux/regmap.h>
27 #include <linux/types.h>
28 #include <linux/unaligned.h>
29
30 #define ADC5_GEN3_VADC_SDAM 0x0
31
32 struct adc5_chip;
33
34 /**
35 * struct adc5_channel_prop - ADC channel structure
36 * @common_props: structure with ADC channel properties (common to TM usage).
37 * @adc_tm: indicates TM type if the channel is used for TM measurements.
38 * @chip: pointer to top-level ADC device structure.
39 */
40 struct adc5_channel_prop {
41 struct adc5_channel_common_prop common_props;
42 int adc_tm;
43 struct adc5_chip *chip;
44 };
45
46 /**
47 * struct adc5_chip - ADC private structure.
48 * @dev: SPMI ADC5 Gen3 device.
49 * @dev_data: Top-level ADC device data.
50 * @nchannels: number of ADC channels.
51 * @chan_props: array of ADC channel properties.
52 * @iio_chans: array of IIO channels specification.
53 * @complete: ADC result notification after interrupt is received.
54 * @lock: ADC lock for access to the peripheral, to prevent concurrent
55 * requests from multiple clients.
56 * @data: software configuration data.
57 * @n_tm_channels: number of ADC channels used for TM measurements.
58 */
59 struct adc5_chip {
60 struct device *dev;
61 struct adc5_device_data dev_data;
62 unsigned int nchannels;
63 struct adc5_channel_prop *chan_props;
64 struct iio_chan_spec *iio_chans;
65 struct completion complete;
66 struct mutex lock;
67 const struct adc5_data *data;
68 unsigned int n_tm_channels;
69 };
70
adc5_gen3_read(struct adc5_device_data * adc,unsigned int sdam_index,u16 offset,u8 * data,int len)71 int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index,
72 u16 offset, u8 *data, int len)
73 {
74 return regmap_bulk_read(adc->regmap,
75 adc->base[sdam_index].base_addr + offset,
76 data, len);
77 }
78 EXPORT_SYMBOL_NS_GPL(adc5_gen3_read, "QCOM_SPMI_ADC5_GEN3");
79
adc5_gen3_write(struct adc5_device_data * adc,unsigned int sdam_index,u16 offset,u8 * data,int len)80 int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index,
81 u16 offset, u8 *data, int len)
82 {
83 return regmap_bulk_write(adc->regmap,
84 adc->base[sdam_index].base_addr + offset,
85 data, len);
86 }
87 EXPORT_SYMBOL_NS_GPL(adc5_gen3_write, "QCOM_SPMI_ADC5_GEN3");
88
adc5_gen3_read_voltage_data(struct adc5_chip * adc,u16 * data)89 static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data)
90 {
91 u8 rslt[2];
92 int ret;
93
94 ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM,
95 ADC5_GEN3_CH_DATA0(0), rslt, sizeof(rslt));
96 if (ret)
97 return ret;
98
99 *data = get_unaligned_le16(rslt);
100
101 if (*data == ADC5_USR_DATA_CHECK) {
102 dev_err(adc->dev, "Invalid data:%#x\n", *data);
103 return -EINVAL;
104 }
105
106 dev_dbg(adc->dev, "voltage raw code:%#x\n", *data);
107
108 return 0;
109 }
110
adc5_gen3_update_dig_param(struct adc5_channel_common_prop * prop,u8 * data)111 void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data)
112 {
113 /* Update calibration select and decimation ratio select */
114 *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK);
115 *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method);
116 *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation);
117 }
118 EXPORT_SYMBOL_NS_GPL(adc5_gen3_update_dig_param, "QCOM_SPMI_ADC5_GEN3");
119
120 #define ADC5_GEN3_READ_CONFIG_REGS 7
121
adc5_gen3_configure(struct adc5_chip * adc,struct adc5_channel_common_prop * prop)122 static int adc5_gen3_configure(struct adc5_chip *adc,
123 struct adc5_channel_common_prop *prop)
124 {
125 u8 buf[ADC5_GEN3_READ_CONFIG_REGS];
126 u8 conv_req = 0;
127 int ret;
128
129 ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID,
130 buf, sizeof(buf));
131 if (ret)
132 return ret;
133
134 /* Write SID */
135 buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid);
136
137 /*
138 * Use channel 0 by default for immediate conversion and to indicate
139 * there is an actual conversion request
140 */
141 buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0;
142
143 buf[2] = ADC5_GEN3_TIME_IMMEDIATE;
144
145 /* Digital param selection */
146 adc5_gen3_update_dig_param(prop, &buf[3]);
147
148 /* Update fast average sample value */
149 buf[4] = FIELD_PREP(ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK,
150 prop->avg_samples) | ADC5_GEN3_FAST_AVG_CTL_EN;
151
152 /* Select ADC channel */
153 buf[5] = prop->channel;
154
155 /* Select HW settle delay for channel */
156 buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK,
157 prop->hw_settle_time_us);
158
159 reinit_completion(&adc->complete);
160
161 ret = adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID,
162 buf, sizeof(buf));
163 if (ret)
164 return ret;
165
166 conv_req = ADC5_GEN3_CONV_REQ_REQ;
167 return adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM,
168 ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req));
169 }
170
171 /*
172 * Worst case delay from PBS in readying handshake bit can be up to 15ms, when
173 * PBS is busy running other simultaneous transactions, while in the best case,
174 * it is already ready at this point. Assigning polling delay and retry count
175 * accordingly.
176 */
177
178 #define ADC5_GEN3_HS_DELAY_US 100
179 #define ADC5_GEN3_HS_RETRY_COUNT 150
180
adc5_gen3_poll_wait_hs(struct adc5_device_data * adc,unsigned int sdam_index)181 int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc,
182 unsigned int sdam_index)
183 {
184 u8 conv_req = ADC5_GEN3_CONV_REQ_REQ;
185 int ret, count;
186 u8 status = 0;
187
188 for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
189 ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, sizeof(status));
190 if (ret)
191 return ret;
192
193 if (status == ADC5_GEN3_HS_READY) {
194 ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ,
195 &conv_req, sizeof(conv_req));
196 if (ret)
197 return ret;
198
199 if (!conv_req)
200 return 0;
201 }
202
203 fsleep(ADC5_GEN3_HS_DELAY_US);
204 }
205
206 pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n",
207 sdam_index, status);
208 return -ETIMEDOUT;
209 }
210 EXPORT_SYMBOL_NS_GPL(adc5_gen3_poll_wait_hs, "QCOM_SPMI_ADC5_GEN3");
211
adc5_gen3_status_clear(struct adc5_device_data * adc,int sdam_index,u16 offset,u8 * val,int len)212 int adc5_gen3_status_clear(struct adc5_device_data *adc,
213 int sdam_index, u16 offset, u8 *val, int len)
214 {
215 u8 value;
216 int ret;
217
218 ret = adc5_gen3_write(adc, sdam_index, offset, val, len);
219 if (ret)
220 return ret;
221
222 /* To indicate conversion request is only to clear a status */
223 value = 0;
224 ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &value,
225 sizeof(value));
226 if (ret)
227 return ret;
228
229 value = ADC5_GEN3_CONV_REQ_REQ;
230 return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &value,
231 sizeof(value));
232 }
233 EXPORT_SYMBOL_NS_GPL(adc5_gen3_status_clear, "QCOM_SPMI_ADC5_GEN3");
234
235 /*
236 * Worst case delay from PBS for conversion time can be up to 500ms, when PBS
237 * has timed out twice, once for the initial attempt and once for a retry of
238 * the same transaction.
239 */
240
241 #define ADC5_GEN3_CONV_TIMEOUT_MS 501
242
adc5_gen3_do_conversion(struct adc5_chip * adc,struct adc5_channel_common_prop * prop,u16 * data_volt)243 static int adc5_gen3_do_conversion(struct adc5_chip *adc,
244 struct adc5_channel_common_prop *prop,
245 u16 *data_volt)
246 {
247 unsigned long rc;
248 int ret;
249 u8 val;
250
251 guard(mutex)(&adc->lock);
252 ret = adc5_gen3_poll_wait_hs(&adc->dev_data, ADC5_GEN3_VADC_SDAM);
253 if (ret)
254 return ret;
255
256 ret = adc5_gen3_configure(adc, prop);
257 if (ret) {
258 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
259 return ret;
260 }
261
262 /* No support for polling mode at present */
263 rc = wait_for_completion_timeout(&adc->complete,
264 msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS));
265 if (!rc) {
266 dev_err(adc->dev, "Reading ADC channel %s timed out\n",
267 prop->label);
268 return -ETIMEDOUT;
269 }
270
271 ret = adc5_gen3_read_voltage_data(adc, data_volt);
272 if (ret)
273 return ret;
274
275 val = BIT(0);
276 return adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM,
277 ADC5_GEN3_EOC_CLR, &val, 1);
278 }
279
adc5_gen3_isr(int irq,void * dev_id)280 static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
281 {
282 struct adc5_chip *adc = dev_id;
283 struct device *dev = adc->dev;
284 u8 status, eoc_status, val;
285 int ret;
286
287 ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM,
288 ADC5_GEN3_STATUS1, &status, sizeof(status));
289 if (ret) {
290 dev_err(dev, "adc read status1 failed with %d\n", ret);
291 return IRQ_NONE;
292 }
293
294 ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM,
295 ADC5_GEN3_EOC_STS, &eoc_status, sizeof(eoc_status));
296 if (ret) {
297 dev_err(dev, "adc read eoc status failed with %d\n", ret);
298 return IRQ_NONE;
299 }
300
301 if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
302 dev_err_ratelimited(dev,
303 "Unexpected conversion fault, status:%#x, eoc_status:%#x\n",
304 status, eoc_status);
305 val = ADC5_GEN3_CONV_ERR_CLR_REQ;
306 adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM,
307 ADC5_GEN3_CONV_ERR_CLR, &val, 1);
308 return IRQ_HANDLED;
309 }
310
311 dev_dbg(dev, "Interrupt status:%#x, EOC status:%#x\n", status, eoc_status);
312
313 /* CHAN0 is the preconfigured channel for immediate conversion */
314 if (!(eoc_status & ADC5_GEN3_EOC_CHAN_0))
315 return IRQ_NONE;
316
317 complete(&adc->complete);
318 return IRQ_HANDLED;
319 }
320
adc5_gen3_fwnode_xlate(struct iio_dev * indio_dev,const struct fwnode_reference_args * iiospec)321 static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev,
322 const struct fwnode_reference_args *iiospec)
323 {
324 struct adc5_chip *adc = iio_priv(indio_dev);
325 int i, v_channel;
326
327 for (i = 0; i < adc->nchannels; i++) {
328 v_channel = ADC5_GEN3_V_CHAN(adc->chan_props[i].common_props);
329 if (v_channel == iiospec->args[0])
330 return i;
331 }
332
333 return -ENOENT;
334 }
335
adc5_gen3_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)336 static int adc5_gen3_read_raw(struct iio_dev *indio_dev,
337 struct iio_chan_spec const *chan, int *val,
338 int *val2, long mask)
339 {
340 struct adc5_chip *adc = iio_priv(indio_dev);
341 struct adc5_channel_common_prop *prop;
342 u16 adc_code_volt;
343 int ret;
344
345 prop = &adc->chan_props[chan->address].common_props;
346
347 switch (mask) {
348 case IIO_CHAN_INFO_PROCESSED:
349 ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt);
350 if (ret)
351 return ret;
352
353 ret = qcom_adc5_hw_scale(prop->scale_fn_type, prop->prescale,
354 adc->data, adc_code_volt, val);
355 if (ret)
356 return ret;
357
358 return IIO_VAL_INT;
359 default:
360 return -EINVAL;
361 }
362 }
363
adc5_gen3_read_label(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,char * label)364 static int adc5_gen3_read_label(struct iio_dev *indio_dev,
365 const struct iio_chan_spec *chan, char *label)
366 {
367 struct adc5_chip *adc = iio_priv(indio_dev);
368 struct adc5_channel_prop *prop;
369
370 prop = &adc->chan_props[chan->address];
371 return sprintf(label, "%s\n", prop->common_props.label);
372 }
373
374 static const struct iio_info adc5_gen3_info = {
375 .read_raw = adc5_gen3_read_raw,
376 .read_label = adc5_gen3_read_label,
377 .fwnode_xlate = adc5_gen3_fwnode_xlate,
378 };
379
380 struct adc5_channels {
381 unsigned int prescale_index;
382 enum iio_chan_type type;
383 long info_mask;
384 enum vadc_scale_fn_type scale_fn_type;
385 };
386
387 /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
388 #define ADC5_CHAN(_type, _mask, _pre, _scale) \
389 { \
390 .prescale_index = _pre, \
391 .type = _type, \
392 .info_mask = _mask, \
393 .scale_fn_type = _scale, \
394 }, \
395
396 #define ADC5_CHAN_TEMP(_pre, _scale) \
397 ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
398
399 #define ADC5_CHAN_VOLT(_pre, _scale) \
400 ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
401
402 #define ADC5_CHAN_CUR(_pre, _scale) \
403 ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
404
405 static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = {
406 [ADC5_GEN3_REF_GND] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
407 [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
408 [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
409 [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
410 [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
411 [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
412 [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP(0,
413 SCALE_HW_CALIB_PMIC_THERM_PM7)
414 [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0,
415 SCALE_HW_CALIB_THERM_100K_PU_PM7)
416 [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0,
417 SCALE_HW_CALIB_THERM_100K_PU_PM7)
418 [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0,
419 SCALE_HW_CALIB_THERM_100K_PU_PM7)
420 [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0,
421 SCALE_HW_CALIB_THERM_100K_PU_PM7)
422 [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0,
423 SCALE_HW_CALIB_THERM_100K_PU_PM7)
424 [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0,
425 SCALE_HW_CALIB_THERM_100K_PU_PM7)
426 [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
427 SCALE_HW_CALIB_THERM_100K_PU_PM7)
428 [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
429 SCALE_HW_CALIB_THERM_100K_PU_PM7)
430 [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
431 SCALE_HW_CALIB_THERM_100K_PU_PM7)
432 [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
433 SCALE_HW_CALIB_THERM_100K_PU_PM7)
434 };
435
adc5_gen3_get_fw_channel_data(struct adc5_chip * adc,struct adc5_channel_prop * prop,struct fwnode_handle * fwnode)436 static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc,
437 struct adc5_channel_prop *prop,
438 struct fwnode_handle *fwnode)
439 {
440 const char *name = fwnode_get_name(fwnode);
441 const struct adc5_data *data = adc->data;
442 struct device *dev = adc->dev;
443 const char *channel_name;
444 u32 chan, value, sid;
445 u32 varr[2];
446 int ret;
447
448 ret = fwnode_property_read_u32(fwnode, "reg", &chan);
449 if (ret < 0)
450 return dev_err_probe(dev, ret, "invalid channel number %s\n",
451 name);
452
453 /*
454 * Value read from "reg" is virtual channel number
455 * virtual channel number = sid << 8 | channel number
456 */
457 sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan);
458 chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan);
459
460 if (chan >= ADC5_MAX_CHANNEL)
461 return dev_err_probe(dev, -EINVAL,
462 "%s invalid channel number %d\n",
463 name, chan);
464
465 prop->common_props.channel = chan;
466 prop->common_props.sid = sid;
467
468 if (!adc->data->adc_chans[chan].info_mask)
469 return dev_err_probe(dev, -EINVAL, "Channel %#x not supported\n", chan);
470
471 channel_name = name;
472 fwnode_property_read_string(fwnode, "label", &channel_name);
473 prop->common_props.label = channel_name;
474
475 value = data->decimation[ADC5_DECIMATION_DEFAULT];
476 fwnode_property_read_u32(fwnode, "qcom,decimation", &value);
477 ret = qcom_adc5_decimation_from_dt(value, data->decimation);
478 if (ret < 0)
479 return dev_err_probe(dev, ret, "%#x invalid decimation %d\n",
480 chan, value);
481 prop->common_props.decimation = ret;
482
483 prop->common_props.prescale = adc->data->adc_chans[chan].prescale_index;
484 ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2);
485 if (!ret) {
486 ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
487 if (ret < 0)
488 return dev_err_probe(dev, ret,
489 "%#x invalid pre-scaling <%d %d>\n",
490 chan, varr[0], varr[1]);
491 prop->common_props.prescale = ret;
492 }
493
494 value = data->hw_settle_1[VADC_DEF_HW_SETTLE_TIME];
495 fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
496 ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1);
497 if (ret < 0)
498 return dev_err_probe(dev, ret,
499 "%#x invalid hw-settle-time %d us\n",
500 chan, value);
501 prop->common_props.hw_settle_time_us = ret;
502
503 value = BIT(VADC_DEF_AVG_SAMPLES);
504 fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value);
505 ret = qcom_adc5_avg_samples_from_dt(value);
506 if (ret < 0)
507 return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n",
508 chan, value);
509 prop->common_props.avg_samples = ret;
510
511 if (fwnode_property_read_bool(fwnode, "qcom,ratiometric"))
512 prop->common_props.cal_method = ADC5_RATIOMETRIC_CAL;
513 else
514 prop->common_props.cal_method = ADC5_ABSOLUTE_CAL;
515
516 prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm");
517 if (prop->adc_tm) {
518 adc->n_tm_channels++;
519 if (adc->n_tm_channels > (adc->dev_data.num_sdams * 8 - 1))
520 return dev_err_probe(dev, -EINVAL,
521 "Number of TM nodes %u greater than channels supported:%u\n",
522 adc->n_tm_channels,
523 adc->dev_data.num_sdams * 8 - 1);
524 }
525
526 return 0;
527 }
528
529 static const struct adc5_data adc5_gen3_data_pmic = {
530 .full_scale_code_volt = 0x70e4,
531 .adc_chans = adc5_gen3_chans_pmic,
532 .info = &adc5_gen3_info,
533 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
534 { 85, 340, 1360 },
535 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
536 { 15, 100, 200, 300,
537 400, 500, 600, 700,
538 1000, 2000, 4000, 8000,
539 16000, 32000, 64000, 128000 },
540 };
541
542 static const struct of_device_id adc5_match_table[] = {
543 {
544 .compatible = "qcom,spmi-adc5-gen3",
545 .data = &adc5_gen3_data_pmic,
546 },
547 { }
548 };
549 MODULE_DEVICE_TABLE(of, adc5_match_table);
550
adc5_get_fw_data(struct adc5_chip * adc)551 static int adc5_get_fw_data(struct adc5_chip *adc)
552 {
553 const struct adc5_channels *adc_chan;
554 struct adc5_channel_prop *chan_props;
555 struct iio_chan_spec *iio_chan;
556 struct device *dev = adc->dev;
557 unsigned int index = 0;
558 int ret;
559
560 adc->nchannels = device_get_child_node_count(dev);
561 if (!adc->nchannels)
562 return dev_err_probe(dev, -EINVAL, "No ADC channels found\n");
563
564 adc->iio_chans = devm_kcalloc(dev, adc->nchannels,
565 sizeof(*adc->iio_chans), GFP_KERNEL);
566 if (!adc->iio_chans)
567 return -ENOMEM;
568
569 adc->chan_props = devm_kcalloc(dev, adc->nchannels,
570 sizeof(*adc->chan_props), GFP_KERNEL);
571 if (!adc->chan_props)
572 return -ENOMEM;
573
574 chan_props = adc->chan_props;
575 adc->n_tm_channels = 0;
576 iio_chan = adc->iio_chans;
577 adc->data = device_get_match_data(dev);
578
579 device_for_each_child_node_scoped(dev, child) {
580 ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child);
581 if (ret)
582 return ret;
583
584 chan_props->chip = adc;
585 adc_chan = &adc->data->adc_chans[chan_props->common_props.channel];
586 chan_props->common_props.scale_fn_type = adc_chan->scale_fn_type;
587
588 iio_chan->channel = ADC5_GEN3_V_CHAN(chan_props->common_props);
589 iio_chan->info_mask_separate = adc_chan->info_mask;
590 iio_chan->type = adc_chan->type;
591 iio_chan->address = index;
592 iio_chan->indexed = 1;
593 iio_chan++;
594 chan_props++;
595 index++;
596 }
597
598 return 0;
599 }
600
adc5_gen3_uninit_aux(void * data)601 static void adc5_gen3_uninit_aux(void *data)
602 {
603 auxiliary_device_uninit(data);
604 }
605
adc5_gen3_delete_aux(void * data)606 static void adc5_gen3_delete_aux(void *data)
607 {
608 auxiliary_device_delete(data);
609 }
610
adc5_gen3_aux_device_release(struct device * dev)611 static void adc5_gen3_aux_device_release(struct device *dev) {}
612
adc5_gen3_add_aux_tm_device(struct adc5_chip * adc)613 static int adc5_gen3_add_aux_tm_device(struct adc5_chip *adc)
614 {
615 struct tm5_aux_dev_wrapper *aux_device;
616 int i, ret, i_tm = 0;
617
618 aux_device = devm_kzalloc(adc->dev, sizeof(*aux_device), GFP_KERNEL);
619 if (!aux_device)
620 return -ENOMEM;
621
622 aux_device->aux_dev.name = "adc5_tm_gen3";
623 aux_device->aux_dev.dev.parent = adc->dev;
624 aux_device->aux_dev.dev.release = adc5_gen3_aux_device_release;
625
626 aux_device->tm_props = devm_kcalloc(adc->dev, adc->n_tm_channels,
627 sizeof(*aux_device->tm_props),
628 GFP_KERNEL);
629 if (!aux_device->tm_props)
630 return -ENOMEM;
631
632 aux_device->dev_data = &adc->dev_data;
633
634 for (i = 0; i < adc->nchannels; i++) {
635 if (!adc->chan_props[i].adc_tm)
636 continue;
637 aux_device->tm_props[i_tm] = adc->chan_props[i].common_props;
638 i_tm++;
639 }
640
641 device_set_of_node_from_dev(&aux_device->aux_dev.dev, adc->dev);
642
643 aux_device->n_tm_channels = adc->n_tm_channels;
644
645 ret = auxiliary_device_init(&aux_device->aux_dev);
646 if (ret)
647 return ret;
648
649 ret = devm_add_action_or_reset(adc->dev, adc5_gen3_uninit_aux,
650 &aux_device->aux_dev);
651 if (ret)
652 return ret;
653
654 ret = auxiliary_device_add(&aux_device->aux_dev);
655 if (ret)
656 return ret;
657 ret = devm_add_action_or_reset(adc->dev, adc5_gen3_delete_aux,
658 &aux_device->aux_dev);
659 if (ret)
660 return ret;
661
662 return 0;
663 }
664
adc5_gen3_mutex_lock(struct device * dev)665 void adc5_gen3_mutex_lock(struct device *dev)
666 __acquires(&adc->lock)
667 {
668 struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
669 struct adc5_chip *adc = iio_priv(indio_dev);
670
671 mutex_lock(&adc->lock);
672 }
673 EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_lock, "QCOM_SPMI_ADC5_GEN3");
674
adc5_gen3_mutex_unlock(struct device * dev)675 void adc5_gen3_mutex_unlock(struct device *dev)
676 __releases(&adc->lock)
677 {
678 struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
679 struct adc5_chip *adc = iio_priv(indio_dev);
680
681 mutex_unlock(&adc->lock);
682 }
683 EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_unlock, "QCOM_SPMI_ADC5_GEN3");
684
adc5_gen3_get_scaled_reading(struct device * dev,struct adc5_channel_common_prop * common_props,int * val)685 int adc5_gen3_get_scaled_reading(struct device *dev,
686 struct adc5_channel_common_prop *common_props,
687 int *val)
688 {
689 struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
690 struct adc5_chip *adc = iio_priv(indio_dev);
691 u16 adc_code_volt;
692 int ret;
693
694 ret = adc5_gen3_do_conversion(adc, common_props, &adc_code_volt);
695 if (ret)
696 return ret;
697
698 return qcom_adc5_hw_scale(common_props->scale_fn_type,
699 common_props->prescale,
700 adc->data, adc_code_volt, val);
701 }
702 EXPORT_SYMBOL_NS_GPL(adc5_gen3_get_scaled_reading, "QCOM_SPMI_ADC5_GEN3");
703
adc5_gen3_therm_code_to_temp(struct device * dev,struct adc5_channel_common_prop * common_props,u16 code,int * val)704 int adc5_gen3_therm_code_to_temp(struct device *dev,
705 struct adc5_channel_common_prop *common_props,
706 u16 code, int *val)
707 {
708 struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
709 struct adc5_chip *adc = iio_priv(indio_dev);
710
711 return qcom_adc5_hw_scale(common_props->scale_fn_type,
712 common_props->prescale,
713 adc->data, code, val);
714 }
715 EXPORT_SYMBOL_NS_GPL(adc5_gen3_therm_code_to_temp, "QCOM_SPMI_ADC5_GEN3");
716
adc5_gen3_probe(struct platform_device * pdev)717 static int adc5_gen3_probe(struct platform_device *pdev)
718 {
719 struct device *dev = &pdev->dev;
720 struct iio_dev *indio_dev;
721 struct adc5_chip *adc;
722 struct regmap *regmap;
723 int ret, i;
724 u32 *reg;
725
726 regmap = dev_get_regmap(dev->parent, NULL);
727 if (!regmap)
728 return -ENODEV;
729
730 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
731 if (!indio_dev)
732 return -ENOMEM;
733
734 adc = iio_priv(indio_dev);
735 adc->dev_data.regmap = regmap;
736 adc->dev = dev;
737
738 ret = device_property_count_u32(dev, "reg");
739 if (ret < 0)
740 return ret;
741
742 adc->dev_data.num_sdams = ret;
743
744 reg = devm_kcalloc(dev, adc->dev_data.num_sdams, sizeof(u32),
745 GFP_KERNEL);
746 if (!reg)
747 return -ENOMEM;
748
749 ret = device_property_read_u32_array(dev, "reg", reg,
750 adc->dev_data.num_sdams);
751 if (ret)
752 return dev_err_probe(dev, ret,
753 "Failed to read reg property\n");
754
755 adc->dev_data.base = devm_kcalloc(dev, adc->dev_data.num_sdams,
756 sizeof(*adc->dev_data.base),
757 GFP_KERNEL);
758 if (!adc->dev_data.base)
759 return -ENOMEM;
760
761 platform_set_drvdata(pdev, indio_dev);
762 init_completion(&adc->complete);
763 ret = devm_mutex_init(dev, &adc->lock);
764 if (ret)
765 return ret;
766
767 for (i = 0; i < adc->dev_data.num_sdams; i++) {
768 adc->dev_data.base[i].base_addr = reg[i];
769
770 ret = platform_get_irq(pdev, i);
771 if (ret < 0)
772 return dev_err_probe(dev, ret,
773 "Getting IRQ %d failed\n", i);
774
775 adc->dev_data.base[i].irq = ret;
776
777 adc->dev_data.base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL,
778 "sdam%d", i);
779 if (!adc->dev_data.base[i].irq_name)
780 return -ENOMEM;
781 }
782
783 /*
784 * This interrupt is shared with the ADC_TM auxiliary driver, which
785 * is threaded and uses IRQF_ONESHOT. Since shared interrupts need
786 * to agree on IRQF_ONESHOT configuration and there is a kernel
787 * warning for using IRQF_ONESHOT with non-threaded interrupts,
788 * make this also a threaded IRQ.
789 */
790 ret = devm_request_threaded_irq(dev, adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq,
791 NULL, adc5_gen3_isr, IRQF_ONESHOT | IRQF_SHARED,
792 adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq_name,
793 adc);
794 if (ret)
795 return ret;
796
797 ret = adc5_get_fw_data(adc);
798 if (ret)
799 return ret;
800
801 if (adc->n_tm_channels > 0) {
802 ret = adc5_gen3_add_aux_tm_device(adc);
803 if (ret)
804 dev_err_probe(dev, ret,
805 "Failed to add auxiliary TM device\n");
806 }
807
808 indio_dev->name = "spmi-adc5-gen3";
809 indio_dev->modes = INDIO_DIRECT_MODE;
810 indio_dev->info = &adc5_gen3_info;
811 indio_dev->channels = adc->iio_chans;
812 indio_dev->num_channels = adc->nchannels;
813
814 return devm_iio_device_register(dev, indio_dev);
815 }
816
817 static struct platform_driver adc5_gen3_driver = {
818 .driver = {
819 .name = "qcom-spmi-adc5-gen3",
820 .of_match_table = adc5_match_table,
821 },
822 .probe = adc5_gen3_probe,
823 };
824 module_platform_driver(adc5_gen3_driver);
825
826 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver");
827 MODULE_LICENSE("GPL");
828 MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3");
829