1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_dpm.h"
29 #include "amdgpu_smu.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_atombios.h"
33 #include "smu_v13_0.h"
34 #include "smu13_driver_if_aldebaran.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "aldebaran_ppt.h"
38 #include "smu_v13_0_pptable.h"
39 #include "aldebaran_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "smu_cmn.h"
48 #include "mp/mp_13_0_2_offset.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
61 [smu_feature] = {1, (aldebaran_feature)}
62
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 static const struct smu_feature_bits aldebaran_dpm_features = {
65 .bits = {
66 SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATIONS),
67 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
68 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
69 SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
70 SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
71 SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK_BIT),
72 SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT),
73 SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN_BIT)
74 }
75 };
76
77 #define smnPCIE_ESM_CTRL 0x111003D0
78
79 /*
80 * SMU support ECCTABLE since version 68.42.0,
81 * use this to check ECCTALE feature whether support
82 */
83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
84
85 /*
86 * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0,
87 * use this to check mca_ceumc_addr record whether support
88 */
89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700
90
91 /*
92 * SMU support BAD CHENNEL info MSG since version 68.51.00,
93 * use this to check ECCTALE feature whether support
94 */
95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300
96
97 static const struct smu_temperature_range smu13_thermal_policy[] = {
98 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
99 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
100 };
101
102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
105 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
108 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
109 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
110 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
111 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
112 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
113 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
114 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
115 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
116 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
117 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
118 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
119 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
120 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
121 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
122 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
123 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
124 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
125 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
126 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
127 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
128 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
129 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
130 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
132 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0),
133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
139 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
140 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
142 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
143 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
144 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
145 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
146 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
147 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0),
148 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
149 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
150 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
151 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
152 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0),
153 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0),
154 MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel, PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0),
155 };
156
157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
158 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
159 CLK_MAP(SCLK, PPCLK_GFXCLK),
160 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
161 CLK_MAP(FCLK, PPCLK_FCLK),
162 CLK_MAP(UCLK, PPCLK_UCLK),
163 CLK_MAP(MCLK, PPCLK_UCLK),
164 CLK_MAP(DCLK, PPCLK_DCLK),
165 CLK_MAP(VCLK, PPCLK_VCLK),
166 CLK_MAP(LCLK, PPCLK_LCLK),
167 };
168
169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS),
171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT),
172 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT),
173 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT),
174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT),
175 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT),
176 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
177 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT),
178 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT),
179 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT),
180 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT),
181 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT),
182 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT),
183 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
184 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT),
185 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT),
186 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT),
187 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT),
188 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT),
189 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT),
190 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT),
191 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT),
192 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT),
193 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT),
194 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT),
195 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT),
196 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT),
197 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT),
198 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN),
199 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
200 };
201
202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
203 TAB_MAP(PPTABLE),
204 TAB_MAP(AVFS_PSM_DEBUG),
205 TAB_MAP(AVFS_FUSE_OVERRIDE),
206 TAB_MAP(PMSTATUSLOG),
207 TAB_MAP(SMU_METRICS),
208 TAB_MAP(DRIVER_SMU_CONFIG),
209 TAB_MAP(I2C_COMMANDS),
210 TAB_MAP(ECCINFO),
211 };
212
213 static const uint8_t aldebaran_throttler_map[] = {
214 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
215 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
216 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
217 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
218 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT),
219 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
220 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
221 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
222 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
223 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
224 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
225 };
226
aldebaran_tables_init(struct smu_context * smu)227 static int aldebaran_tables_init(struct smu_context *smu)
228 {
229 struct smu_table_context *smu_table = &smu->smu_table;
230 struct smu_table *tables = smu_table->tables;
231 int ret;
232
233 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
235
236 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
237 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
238
239 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
240 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
241
242 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
243 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
244
245 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
246 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
247
248 smu_table->metrics_table = kzalloc_obj(SmuMetrics_t);
249 if (!smu_table->metrics_table)
250 return -ENOMEM;
251 smu_table->metrics_time = 0;
252
253 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
254 sizeof(struct gpu_metrics_v1_3),
255 SMU_GPU_METRICS_CACHE_INTERVAL);
256 if (ret) {
257 kfree(smu_table->metrics_table);
258 return ret;
259 }
260
261 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
262 if (!smu_table->ecc_table) {
263 kfree(smu_table->metrics_table);
264 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
265 return -ENOMEM;
266 }
267
268 return 0;
269 }
270
aldebaran_select_plpd_policy(struct smu_context * smu,int level)271 static int aldebaran_select_plpd_policy(struct smu_context *smu, int level)
272 {
273 struct amdgpu_device *adev = smu->adev;
274
275 /* The message only works on master die and NACK will be sent
276 * back for other dies, only send it on master die.
277 */
278 if (adev->smuio.funcs->get_socket_id(adev) ||
279 adev->smuio.funcs->get_die_id(adev))
280 return 0;
281
282 if (level == XGMI_PLPD_DEFAULT)
283 return smu_cmn_send_smc_msg_with_param(
284 smu, SMU_MSG_GmiPwrDnControl, 0, NULL);
285 else if (level == XGMI_PLPD_DISALLOW)
286 return smu_cmn_send_smc_msg_with_param(
287 smu, SMU_MSG_GmiPwrDnControl, 1, NULL);
288 else
289 return -EINVAL;
290 }
291
aldebaran_allocate_dpm_context(struct smu_context * smu)292 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
293 {
294 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
295 struct smu_dpm_policy *policy;
296
297 smu_dpm->dpm_context = kzalloc_obj(struct smu_13_0_dpm_context);
298 if (!smu_dpm->dpm_context)
299 return -ENOMEM;
300 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
301
302 smu_dpm->dpm_policies =
303 kzalloc_obj(struct smu_dpm_policy_ctxt);
304
305 if (!smu_dpm->dpm_policies)
306 return -ENOMEM;
307
308 policy = &(smu_dpm->dpm_policies->policies[0]);
309 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
310 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT);
311 policy->current_level = XGMI_PLPD_DEFAULT;
312 policy->set_policy = aldebaran_select_plpd_policy;
313 smu_cmn_generic_plpd_policy_desc(policy);
314 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
315
316 return 0;
317 }
318
aldebaran_init_smc_tables(struct smu_context * smu)319 static int aldebaran_init_smc_tables(struct smu_context *smu)
320 {
321 int ret = 0;
322
323 ret = aldebaran_tables_init(smu);
324 if (ret)
325 return ret;
326
327 ret = aldebaran_allocate_dpm_context(smu);
328 if (ret)
329 return ret;
330
331 return smu_v13_0_init_smc_tables(smu);
332 }
333
aldebaran_init_allowed_features(struct smu_context * smu)334 static int aldebaran_init_allowed_features(struct smu_context *smu)
335 {
336 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
337
338 return 0;
339 }
340
aldebaran_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)341 static int aldebaran_get_dpm_ultimate_freq(struct smu_context *smu,
342 enum smu_clk_type clk_type,
343 uint32_t *min, uint32_t *max)
344 {
345 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
346 struct smu_dpm_table *dpm_table;
347 uint32_t min_clk, max_clk;
348
349 if (amdgpu_sriov_vf(smu->adev)) {
350 switch (clk_type) {
351 case SMU_MCLK:
352 case SMU_UCLK:
353 dpm_table = &dpm_context->dpm_tables.uclk_table;
354 break;
355 case SMU_GFXCLK:
356 case SMU_SCLK:
357 dpm_table = &dpm_context->dpm_tables.gfx_table;
358 break;
359 case SMU_SOCCLK:
360 dpm_table = &dpm_context->dpm_tables.soc_table;
361 break;
362 case SMU_FCLK:
363 dpm_table = &dpm_context->dpm_tables.fclk_table;
364 break;
365 case SMU_VCLK:
366 dpm_table = &dpm_context->dpm_tables.vclk_table;
367 break;
368 case SMU_DCLK:
369 dpm_table = &dpm_context->dpm_tables.dclk_table;
370 break;
371 default:
372 return -EINVAL;
373 }
374
375 min_clk = SMU_DPM_TABLE_MIN(dpm_table);
376 max_clk = SMU_DPM_TABLE_MAX(dpm_table);
377
378 if (min) {
379 if (!min_clk)
380 return -ENODATA;
381 *min = min_clk;
382 }
383 if (max) {
384 if (!max_clk)
385 return -ENODATA;
386 *max = max_clk;
387 }
388
389 } else {
390 return smu_v13_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
391 }
392
393 return 0;
394 }
395
aldebaran_set_default_dpm_table(struct smu_context * smu)396 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
397 {
398 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
399 struct smu_dpm_table *dpm_table = NULL;
400 PPTable_t *pptable = smu->smu_table.driver_pptable;
401 int ret = 0;
402
403 /* socclk dpm table setup */
404 dpm_table = &dpm_context->dpm_tables.soc_table;
405 dpm_table->clk_type = SMU_SOCCLK;
406 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
407 ret = smu_v13_0_set_single_dpm_table(smu,
408 SMU_SOCCLK,
409 dpm_table);
410 if (ret)
411 return ret;
412 } else {
413 dpm_table->count = 1;
414 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
415 dpm_table->dpm_levels[0].enabled = true;
416 }
417
418 /* gfxclk dpm table setup */
419 dpm_table = &dpm_context->dpm_tables.gfx_table;
420 dpm_table->clk_type = SMU_GFXCLK;
421 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
422 /* in the case of gfxclk, only fine-grained dpm is honored */
423 dpm_table->count = 2;
424 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
425 dpm_table->dpm_levels[0].enabled = true;
426 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
427 dpm_table->dpm_levels[1].enabled = true;
428 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
429 } else {
430 dpm_table->count = 1;
431 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
432 dpm_table->dpm_levels[0].enabled = true;
433 }
434
435 /* memclk dpm table setup */
436 dpm_table = &dpm_context->dpm_tables.uclk_table;
437 dpm_table->clk_type = SMU_UCLK;
438 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
439 ret = smu_v13_0_set_single_dpm_table(smu,
440 SMU_UCLK,
441 dpm_table);
442 if (ret)
443 return ret;
444 } else {
445 dpm_table->count = 1;
446 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
447 dpm_table->dpm_levels[0].enabled = true;
448 }
449
450 /* fclk dpm table setup */
451 dpm_table = &dpm_context->dpm_tables.fclk_table;
452 dpm_table->clk_type = SMU_FCLK;
453 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
454 ret = smu_v13_0_set_single_dpm_table(smu,
455 SMU_FCLK,
456 dpm_table);
457 if (ret)
458 return ret;
459 } else {
460 dpm_table->count = 1;
461 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
462 dpm_table->dpm_levels[0].enabled = true;
463 }
464
465 return 0;
466 }
467
aldebaran_check_powerplay_table(struct smu_context * smu)468 static int aldebaran_check_powerplay_table(struct smu_context *smu)
469 {
470 struct smu_table_context *table_context = &smu->smu_table;
471 struct smu_13_0_powerplay_table *powerplay_table =
472 table_context->power_play_table;
473
474 table_context->thermal_controller_type =
475 powerplay_table->thermal_controller_type;
476
477 return 0;
478 }
479
aldebaran_store_powerplay_table(struct smu_context * smu)480 static int aldebaran_store_powerplay_table(struct smu_context *smu)
481 {
482 struct smu_table_context *table_context = &smu->smu_table;
483 struct smu_13_0_powerplay_table *powerplay_table =
484 table_context->power_play_table;
485 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
486 sizeof(PPTable_t));
487
488 return 0;
489 }
490
aldebaran_append_powerplay_table(struct smu_context * smu)491 static int aldebaran_append_powerplay_table(struct smu_context *smu)
492 {
493 struct smu_table_context *table_context = &smu->smu_table;
494 PPTable_t *smc_pptable = table_context->driver_pptable;
495 struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
496 int index, ret;
497
498 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
499 smc_dpm_info);
500
501 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
502 (uint8_t **)&smc_dpm_table);
503 if (ret)
504 return ret;
505
506 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
507 smc_dpm_table->table_header.format_revision,
508 smc_dpm_table->table_header.content_revision);
509
510 if ((smc_dpm_table->table_header.format_revision == 4) &&
511 (smc_dpm_table->table_header.content_revision == 10))
512 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
513 smc_dpm_table, GfxMaxCurrent);
514 return 0;
515 }
516
aldebaran_setup_pptable(struct smu_context * smu)517 static int aldebaran_setup_pptable(struct smu_context *smu)
518 {
519 int ret = 0;
520
521 /* VBIOS pptable is the first choice */
522 smu->smu_table.boot_values.pp_table_id = 0;
523
524 ret = smu_v13_0_setup_pptable(smu);
525 if (ret)
526 return ret;
527
528 ret = aldebaran_store_powerplay_table(smu);
529 if (ret)
530 return ret;
531
532 ret = aldebaran_append_powerplay_table(smu);
533 if (ret)
534 return ret;
535
536 ret = aldebaran_check_powerplay_table(smu);
537 if (ret)
538 return ret;
539
540 return ret;
541 }
542
aldebaran_is_primary(struct smu_context * smu)543 static bool aldebaran_is_primary(struct smu_context *smu)
544 {
545 struct amdgpu_device *adev = smu->adev;
546
547 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
548 return adev->smuio.funcs->get_die_id(adev) == 0;
549
550 return true;
551 }
552
aldebaran_run_board_btc(struct smu_context * smu)553 static int aldebaran_run_board_btc(struct smu_context *smu)
554 {
555 int ret;
556
557 if (!aldebaran_is_primary(smu))
558 return 0;
559
560 if (smu->smc_fw_version <= 0x00441d00)
561 return 0;
562
563 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
564 if (ret)
565 dev_err(smu->adev->dev, "Board power calibration failed!\n");
566
567 return ret;
568 }
569
aldebaran_run_btc(struct smu_context * smu)570 static int aldebaran_run_btc(struct smu_context *smu)
571 {
572 int ret;
573
574 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
575 if (ret)
576 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
577 else
578 ret = aldebaran_run_board_btc(smu);
579
580 return ret;
581 }
582
aldebaran_populate_umd_state_clk(struct smu_context * smu)583 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
584 {
585 struct smu_13_0_dpm_context *dpm_context =
586 smu->smu_dpm.dpm_context;
587 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
588 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
589 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
590 struct smu_umd_pstate_table *pstate_table =
591 &smu->pstate_table;
592
593 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
594 pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);
595 pstate_table->gfxclk_pstate.curr.min = SMU_DPM_TABLE_MIN(gfx_table);
596 pstate_table->gfxclk_pstate.curr.max = SMU_DPM_TABLE_MAX(gfx_table);
597
598 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);
599 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);
600 pstate_table->uclk_pstate.curr.min = SMU_DPM_TABLE_MIN(mem_table);
601 pstate_table->uclk_pstate.curr.max = SMU_DPM_TABLE_MAX(mem_table);
602
603 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);
604 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);
605 pstate_table->socclk_pstate.curr.min = SMU_DPM_TABLE_MIN(soc_table);
606 pstate_table->socclk_pstate.curr.max = SMU_DPM_TABLE_MAX(soc_table);
607
608 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
609 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
610 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
611 pstate_table->gfxclk_pstate.standard =
612 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
613 pstate_table->uclk_pstate.standard =
614 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
615 pstate_table->socclk_pstate.standard =
616 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
617 } else {
618 pstate_table->gfxclk_pstate.standard =
619 pstate_table->gfxclk_pstate.min;
620 pstate_table->uclk_pstate.standard =
621 pstate_table->uclk_pstate.min;
622 pstate_table->socclk_pstate.standard =
623 pstate_table->socclk_pstate.min;
624 }
625
626 return 0;
627 }
628
aldebaran_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)629 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
630 MetricsMember_t member,
631 uint32_t *value)
632 {
633 struct smu_table_context *smu_table = &smu->smu_table;
634 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
635 int ret = 0;
636
637 ret = smu_cmn_get_metrics_table(smu,
638 NULL,
639 false);
640 if (ret)
641 return ret;
642
643 switch (member) {
644 case METRICS_CURR_GFXCLK:
645 *value = metrics->CurrClock[PPCLK_GFXCLK];
646 break;
647 case METRICS_CURR_SOCCLK:
648 *value = metrics->CurrClock[PPCLK_SOCCLK];
649 break;
650 case METRICS_CURR_UCLK:
651 *value = metrics->CurrClock[PPCLK_UCLK];
652 break;
653 case METRICS_CURR_VCLK:
654 *value = metrics->CurrClock[PPCLK_VCLK];
655 break;
656 case METRICS_CURR_DCLK:
657 *value = metrics->CurrClock[PPCLK_DCLK];
658 break;
659 case METRICS_CURR_FCLK:
660 *value = metrics->CurrClock[PPCLK_FCLK];
661 break;
662 case METRICS_AVERAGE_GFXCLK:
663 *value = metrics->AverageGfxclkFrequency;
664 break;
665 case METRICS_AVERAGE_SOCCLK:
666 *value = metrics->AverageSocclkFrequency;
667 break;
668 case METRICS_AVERAGE_UCLK:
669 *value = metrics->AverageUclkFrequency;
670 break;
671 case METRICS_AVERAGE_GFXACTIVITY:
672 *value = metrics->AverageGfxActivity;
673 break;
674 case METRICS_AVERAGE_MEMACTIVITY:
675 *value = metrics->AverageUclkActivity;
676 break;
677 case METRICS_AVERAGE_SOCKETPOWER:
678 /* Valid power data is available only from primary die */
679 if (aldebaran_is_primary(smu))
680 *value = metrics->AverageSocketPower << 8;
681 else
682 ret = -EOPNOTSUPP;
683 break;
684 case METRICS_TEMPERATURE_EDGE:
685 *value = metrics->TemperatureEdge *
686 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
687 break;
688 case METRICS_TEMPERATURE_HOTSPOT:
689 *value = metrics->TemperatureHotspot *
690 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
691 break;
692 case METRICS_TEMPERATURE_MEM:
693 *value = metrics->TemperatureHBM *
694 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
695 break;
696 case METRICS_TEMPERATURE_VRGFX:
697 *value = metrics->TemperatureVrGfx *
698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
699 break;
700 case METRICS_TEMPERATURE_VRSOC:
701 *value = metrics->TemperatureVrSoc *
702 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
703 break;
704 case METRICS_TEMPERATURE_VRMEM:
705 *value = metrics->TemperatureVrMem *
706 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
707 break;
708 case METRICS_THROTTLER_STATUS:
709 *value = metrics->ThrottlerStatus;
710 break;
711 case METRICS_UNIQUE_ID_UPPER32:
712 *value = metrics->PublicSerialNumUpper32;
713 break;
714 case METRICS_UNIQUE_ID_LOWER32:
715 *value = metrics->PublicSerialNumLower32;
716 break;
717 default:
718 *value = UINT_MAX;
719 break;
720 }
721
722 return ret;
723 }
724
aldebaran_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)725 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
726 enum smu_clk_type clk_type,
727 uint32_t *value)
728 {
729 MetricsMember_t member_type;
730 int clk_id = 0;
731
732 if (!value)
733 return -EINVAL;
734
735 clk_id = smu_cmn_to_asic_specific_index(smu,
736 CMN2ASIC_MAPPING_CLK,
737 clk_type);
738 if (clk_id < 0)
739 return -EINVAL;
740
741 switch (clk_id) {
742 case PPCLK_GFXCLK:
743 /*
744 * CurrClock[clk_id] can provide accurate
745 * output only when the dpm feature is enabled.
746 * We can use Average_* for dpm disabled case.
747 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
748 */
749 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
750 member_type = METRICS_CURR_GFXCLK;
751 else
752 member_type = METRICS_AVERAGE_GFXCLK;
753 break;
754 case PPCLK_UCLK:
755 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
756 member_type = METRICS_CURR_UCLK;
757 else
758 member_type = METRICS_AVERAGE_UCLK;
759 break;
760 case PPCLK_SOCCLK:
761 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
762 member_type = METRICS_CURR_SOCCLK;
763 else
764 member_type = METRICS_AVERAGE_SOCCLK;
765 break;
766 case PPCLK_VCLK:
767 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
768 member_type = METRICS_CURR_VCLK;
769 else
770 member_type = METRICS_AVERAGE_VCLK;
771 break;
772 case PPCLK_DCLK:
773 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
774 member_type = METRICS_CURR_DCLK;
775 else
776 member_type = METRICS_AVERAGE_DCLK;
777 break;
778 case PPCLK_FCLK:
779 member_type = METRICS_CURR_FCLK;
780 break;
781 default:
782 return -EINVAL;
783 }
784
785 return aldebaran_get_smu_metrics_data(smu,
786 member_type,
787 value);
788 }
789
aldebaran_emit_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf,int * offset)790 static int aldebaran_emit_clk_levels(struct smu_context *smu,
791 enum smu_clk_type type, char *buf, int *offset)
792 {
793 int ret = 0;
794 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
795 struct smu_dpm_table *single_dpm_table = NULL;
796 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
797 struct smu_13_0_dpm_context *dpm_context = NULL;
798 uint32_t cur_value = 0;
799 static const char attempt_string[] = "Attempt to get current";
800
801 if (amdgpu_ras_intr_triggered()) {
802 *offset += sysfs_emit_at(buf, *offset, "unavailable\n");
803 return -EBUSY;
804 }
805
806 dpm_context = smu_dpm->dpm_context;
807
808 switch (type) {
809 case SMU_OD_SCLK:
810 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK");
811 *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n",
812 pstate_table->gfxclk_pstate.curr.min,
813 pstate_table->gfxclk_pstate.curr.max);
814 return 0;
815 case SMU_OD_MCLK:
816 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK");
817 *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n",
818 pstate_table->uclk_pstate.curr.min,
819 pstate_table->uclk_pstate.curr.max);
820 return 0;
821
822 case SMU_SCLK:
823 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
824 break;
825 case SMU_MCLK:
826 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
827 break;
828 case SMU_SOCCLK:
829 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
830 break;
831 case SMU_FCLK:
832 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
833 break;
834 case SMU_VCLK:
835 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
836 break;
837 case SMU_DCLK:
838 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
839 break;
840 default:
841 return -EINVAL;
842 }
843
844 if (single_dpm_table) {
845 ret = aldebaran_get_current_clk_freq_by_table(smu, type,
846 &cur_value);
847 if (ret) {
848 dev_err(smu->adev->dev, "%s Failed!", attempt_string);
849 return ret;
850 }
851 return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
852 cur_value, buf, offset);
853 }
854
855 return 0;
856 }
857
aldebaran_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)858 static int aldebaran_upload_dpm_level(struct smu_context *smu,
859 bool max,
860 uint32_t feature_mask,
861 uint32_t level)
862 {
863 struct smu_13_0_dpm_context *dpm_context =
864 smu->smu_dpm.dpm_context;
865 uint32_t freq;
866 int ret = 0;
867
868 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
869 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
870 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
871 ret = smu_cmn_send_smc_msg_with_param(smu,
872 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
873 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
874 NULL);
875 if (ret) {
876 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
877 max ? "max" : "min");
878 return ret;
879 }
880 }
881
882 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
883 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
884 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
885 ret = smu_cmn_send_smc_msg_with_param(smu,
886 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
887 (PPCLK_UCLK << 16) | (freq & 0xffff),
888 NULL);
889 if (ret) {
890 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
891 max ? "max" : "min");
892 return ret;
893 }
894 }
895
896 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
897 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
898 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
899 ret = smu_cmn_send_smc_msg_with_param(smu,
900 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
901 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
902 NULL);
903 if (ret) {
904 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
905 max ? "max" : "min");
906 return ret;
907 }
908 }
909
910 return ret;
911 }
912
aldebaran_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)913 static int aldebaran_force_clk_levels(struct smu_context *smu,
914 enum smu_clk_type type, uint32_t mask)
915 {
916 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
917 struct smu_dpm_table *single_dpm_table = NULL;
918 uint32_t soft_min_level, soft_max_level;
919 int ret = 0;
920
921 soft_min_level = mask ? (ffs(mask) - 1) : 0;
922 soft_max_level = mask ? (fls(mask) - 1) : 0;
923
924 switch (type) {
925 case SMU_SCLK:
926 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
927 if (soft_max_level >= single_dpm_table->count) {
928 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
929 soft_max_level, single_dpm_table->count - 1);
930 ret = -EINVAL;
931 break;
932 }
933
934 ret = aldebaran_upload_dpm_level(smu,
935 false,
936 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
937 soft_min_level);
938 if (ret) {
939 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
940 break;
941 }
942
943 ret = aldebaran_upload_dpm_level(smu,
944 true,
945 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
946 soft_max_level);
947 if (ret)
948 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
949
950 break;
951
952 case SMU_MCLK:
953 case SMU_SOCCLK:
954 case SMU_FCLK:
955 /*
956 * Should not arrive here since aldebaran does not
957 * support mclk/socclk/fclk softmin/softmax settings
958 */
959 ret = -EINVAL;
960 break;
961
962 default:
963 break;
964 }
965
966 return ret;
967 }
968
aldebaran_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)969 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
970 struct smu_temperature_range *range)
971 {
972 struct smu_table_context *table_context = &smu->smu_table;
973 struct smu_13_0_powerplay_table *powerplay_table =
974 table_context->power_play_table;
975 PPTable_t *pptable = smu->smu_table.driver_pptable;
976
977 if (!range)
978 return -EINVAL;
979
980 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
981
982 range->hotspot_crit_max = pptable->ThotspotLimit *
983 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
984 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
985 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
986 range->mem_crit_max = pptable->TmemLimit *
987 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
988 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
989 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
990 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
991
992 return 0;
993 }
994
aldebaran_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)995 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
996 enum amd_pp_sensors sensor,
997 uint32_t *value)
998 {
999 int ret = 0;
1000
1001 if (!value)
1002 return -EINVAL;
1003
1004 switch (sensor) {
1005 case AMDGPU_PP_SENSOR_GPU_LOAD:
1006 ret = aldebaran_get_smu_metrics_data(smu,
1007 METRICS_AVERAGE_GFXACTIVITY,
1008 value);
1009 break;
1010 case AMDGPU_PP_SENSOR_MEM_LOAD:
1011 ret = aldebaran_get_smu_metrics_data(smu,
1012 METRICS_AVERAGE_MEMACTIVITY,
1013 value);
1014 break;
1015 default:
1016 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1017 return -EINVAL;
1018 }
1019
1020 return ret;
1021 }
1022
aldebaran_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1023 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1024 enum amd_pp_sensors sensor,
1025 uint32_t *value)
1026 {
1027 int ret = 0;
1028
1029 if (!value)
1030 return -EINVAL;
1031
1032 switch (sensor) {
1033 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1034 ret = aldebaran_get_smu_metrics_data(smu,
1035 METRICS_TEMPERATURE_HOTSPOT,
1036 value);
1037 break;
1038 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1039 ret = aldebaran_get_smu_metrics_data(smu,
1040 METRICS_TEMPERATURE_EDGE,
1041 value);
1042 break;
1043 case AMDGPU_PP_SENSOR_MEM_TEMP:
1044 ret = aldebaran_get_smu_metrics_data(smu,
1045 METRICS_TEMPERATURE_MEM,
1046 value);
1047 break;
1048 default:
1049 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1050 return -EINVAL;
1051 }
1052
1053 return ret;
1054 }
1055
aldebaran_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1056 static int aldebaran_read_sensor(struct smu_context *smu,
1057 enum amd_pp_sensors sensor,
1058 void *data, uint32_t *size)
1059 {
1060 int ret = 0;
1061
1062 if (amdgpu_ras_intr_triggered())
1063 return 0;
1064
1065 if (!data || !size)
1066 return -EINVAL;
1067
1068 switch (sensor) {
1069 case AMDGPU_PP_SENSOR_MEM_LOAD:
1070 case AMDGPU_PP_SENSOR_GPU_LOAD:
1071 ret = aldebaran_get_current_activity_percent(smu,
1072 sensor,
1073 (uint32_t *)data);
1074 *size = 4;
1075 break;
1076 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1077 ret = aldebaran_get_smu_metrics_data(smu,
1078 METRICS_AVERAGE_SOCKETPOWER,
1079 (uint32_t *)data);
1080 *size = 4;
1081 break;
1082 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1083 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1084 case AMDGPU_PP_SENSOR_MEM_TEMP:
1085 ret = aldebaran_thermal_get_temperature(smu, sensor,
1086 (uint32_t *)data);
1087 *size = 4;
1088 break;
1089 case AMDGPU_PP_SENSOR_GFX_MCLK:
1090 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1091 /* the output clock frequency in 10K unit */
1092 *(uint32_t *)data *= 100;
1093 *size = 4;
1094 break;
1095 case AMDGPU_PP_SENSOR_GFX_SCLK:
1096 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1097 *(uint32_t *)data *= 100;
1098 *size = 4;
1099 break;
1100 case AMDGPU_PP_SENSOR_VDDGFX:
1101 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1102 *size = 4;
1103 break;
1104 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1105 default:
1106 ret = -EOPNOTSUPP;
1107 break;
1108 }
1109
1110 return ret;
1111 }
1112
aldebaran_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1113 static int aldebaran_get_power_limit(struct smu_context *smu,
1114 uint32_t *current_power_limit,
1115 uint32_t *default_power_limit,
1116 uint32_t *max_power_limit,
1117 uint32_t *min_power_limit)
1118 {
1119 PPTable_t *pptable = smu->smu_table.driver_pptable;
1120 uint32_t power_limit = 0;
1121 int ret;
1122
1123 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1124 if (current_power_limit)
1125 *current_power_limit = 0;
1126 if (default_power_limit)
1127 *default_power_limit = 0;
1128 if (max_power_limit)
1129 *max_power_limit = 0;
1130 if (min_power_limit)
1131 *min_power_limit = 0;
1132 dev_warn(smu->adev->dev,
1133 "PPT feature is not enabled, power values can't be fetched.");
1134
1135 return 0;
1136 }
1137
1138 /* Valid power data is available only from primary die.
1139 * For secondary die show the value as 0.
1140 */
1141 if (aldebaran_is_primary(smu)) {
1142 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1143 &power_limit);
1144
1145 if (ret) {
1146 /* the last hope to figure out the ppt limit */
1147 if (!pptable) {
1148 dev_err(smu->adev->dev,
1149 "Cannot get PPT limit due to pptable missing!");
1150 return -EINVAL;
1151 }
1152 power_limit = pptable->PptLimit;
1153 }
1154 }
1155
1156 if (current_power_limit)
1157 *current_power_limit = power_limit;
1158 if (default_power_limit)
1159 *default_power_limit = power_limit;
1160
1161 if (max_power_limit) {
1162 if (pptable)
1163 *max_power_limit = pptable->PptLimit;
1164 }
1165
1166 if (min_power_limit)
1167 *min_power_limit = 0;
1168
1169 return 0;
1170 }
1171
aldebaran_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1172 static int aldebaran_set_power_limit(struct smu_context *smu,
1173 enum smu_ppt_limit_type limit_type,
1174 uint32_t limit)
1175 {
1176 /* Power limit can be set only through primary die */
1177 if (aldebaran_is_primary(smu))
1178 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1179
1180 return -EINVAL;
1181 }
1182
aldebaran_system_features_control(struct smu_context * smu,bool enable)1183 static int aldebaran_system_features_control(struct smu_context *smu, bool enable)
1184 {
1185 int ret;
1186
1187 ret = smu_v13_0_system_features_control(smu, enable);
1188 if (!ret && enable)
1189 ret = aldebaran_run_btc(smu);
1190
1191 return ret;
1192 }
1193
aldebaran_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1194 static int aldebaran_set_performance_level(struct smu_context *smu,
1195 enum amd_dpm_forced_level level)
1196 {
1197 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1198 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1199 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1200 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1201 int r;
1202
1203 /* Disable determinism if switching to another mode */
1204 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1205 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1206 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1207 pstate_table->gfxclk_pstate.curr.max =
1208 SMU_DPM_TABLE_MAX(gfx_table);
1209 }
1210
1211 switch (level) {
1212
1213 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1214 return 0;
1215 case AMD_DPM_FORCED_LEVEL_AUTO:
1216 r = smu_v13_0_set_performance_level(smu, level);
1217 if (!r)
1218 smu_v13_0_reset_custom_level(smu);
1219 return r;
1220 case AMD_DPM_FORCED_LEVEL_HIGH:
1221 case AMD_DPM_FORCED_LEVEL_LOW:
1222 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1223 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1224 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1225 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1226 default:
1227 break;
1228 }
1229
1230 return smu_v13_0_set_performance_level(smu, level);
1231 }
1232
aldebaran_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1233 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1234 enum smu_clk_type clk_type,
1235 uint32_t min,
1236 uint32_t max,
1237 bool automatic)
1238 {
1239 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1240 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1241 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1242 struct amdgpu_device *adev = smu->adev;
1243 uint32_t min_clk;
1244 uint32_t max_clk;
1245 int ret = 0;
1246
1247 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1248 return -EINVAL;
1249 min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table);
1250 max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table);
1251 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1252 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1253 return -EINVAL;
1254
1255 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1256 if (min >= max) {
1257 dev_err(smu->adev->dev,
1258 "Minimum GFX clk should be less than the maximum allowed clock\n");
1259 return -EINVAL;
1260 }
1261
1262 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1263 (max == pstate_table->gfxclk_pstate.curr.max))
1264 return 0;
1265
1266 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1267 min, max, false);
1268 if (!ret) {
1269 pstate_table->gfxclk_pstate.curr.min = min;
1270 pstate_table->gfxclk_pstate.curr.max = max;
1271 }
1272
1273 return ret;
1274 }
1275
1276 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1277 if (!max || (max < min_clk) || (max > max_clk)) {
1278 dev_warn(adev->dev,
1279 "Invalid max frequency %d MHz specified for determinism\n", max);
1280 return -EINVAL;
1281 }
1282
1283 /* Restore default min/max clocks and enable determinism */
1284 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk, false);
1285 if (!ret) {
1286 usleep_range(500, 1000);
1287 ret = smu_cmn_send_smc_msg_with_param(smu,
1288 SMU_MSG_EnableDeterminism,
1289 max, NULL);
1290 if (ret) {
1291 dev_err(adev->dev,
1292 "Failed to enable determinism at GFX clock %d MHz\n", max);
1293 } else {
1294 pstate_table->gfxclk_pstate.curr.min = min_clk;
1295 pstate_table->gfxclk_pstate.curr.max = max;
1296 }
1297 }
1298 }
1299
1300 return ret;
1301 }
1302
aldebaran_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1303 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1304 long input[], uint32_t size)
1305 {
1306 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1307 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1308 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1309 uint32_t min_clk;
1310 uint32_t max_clk;
1311 int ret = 0;
1312
1313 /* Only allowed in manual or determinism mode */
1314 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1315 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1316 return -EINVAL;
1317
1318 switch (type) {
1319 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1320 if (size != 2) {
1321 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1322 return -EINVAL;
1323 }
1324 min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table);
1325 max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table);
1326 if (input[0] == 0) {
1327 if (input[1] < min_clk) {
1328 dev_warn(
1329 smu->adev->dev,
1330 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1331 input[1], min_clk);
1332 pstate_table->gfxclk_pstate.custom.min =
1333 pstate_table->gfxclk_pstate.curr.min;
1334 return -EINVAL;
1335 }
1336
1337 pstate_table->gfxclk_pstate.custom.min = input[1];
1338 } else if (input[0] == 1) {
1339 if (input[1] > max_clk) {
1340 dev_warn(
1341 smu->adev->dev,
1342 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1343 input[1], max_clk);
1344 pstate_table->gfxclk_pstate.custom.max =
1345 pstate_table->gfxclk_pstate.curr.max;
1346 return -EINVAL;
1347 }
1348
1349 pstate_table->gfxclk_pstate.custom.max = input[1];
1350 } else {
1351 return -EINVAL;
1352 }
1353 break;
1354 case PP_OD_RESTORE_DEFAULT_TABLE:
1355 if (size != 0) {
1356 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1357 return -EINVAL;
1358 } else {
1359 /* Use the default frequencies for manual and determinism mode */
1360 min_clk = SMU_DPM_TABLE_MIN(
1361 &dpm_context->dpm_tables.gfx_table);
1362 max_clk = SMU_DPM_TABLE_MAX(
1363 &dpm_context->dpm_tables.gfx_table);
1364
1365 ret = aldebaran_set_soft_freq_limited_range(
1366 smu, SMU_GFXCLK, min_clk, max_clk, false);
1367 if (ret)
1368 return ret;
1369 smu_v13_0_reset_custom_level(smu);
1370 }
1371 break;
1372 case PP_OD_COMMIT_DPM_TABLE:
1373 if (size != 0) {
1374 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1375 return -EINVAL;
1376 } else {
1377 if (!pstate_table->gfxclk_pstate.custom.min)
1378 pstate_table->gfxclk_pstate.custom.min =
1379 pstate_table->gfxclk_pstate.curr.min;
1380
1381 if (!pstate_table->gfxclk_pstate.custom.max)
1382 pstate_table->gfxclk_pstate.custom.max =
1383 pstate_table->gfxclk_pstate.curr.max;
1384
1385 min_clk = pstate_table->gfxclk_pstate.custom.min;
1386 max_clk = pstate_table->gfxclk_pstate.custom.max;
1387
1388 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk, false);
1389 }
1390 break;
1391 default:
1392 return -ENOSYS;
1393 }
1394
1395 return ret;
1396 }
1397
aldebaran_is_dpm_running(struct smu_context * smu)1398 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1399 {
1400 int ret;
1401 struct smu_feature_bits feature_enabled;
1402
1403 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1404 if (ret)
1405 return false;
1406 return smu_feature_bits_test_mask(&feature_enabled,
1407 aldebaran_dpm_features.bits);
1408 }
1409
aldebaran_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)1410 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1411 struct i2c_msg *msg, int num_msgs)
1412 {
1413 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1414 struct amdgpu_device *adev = smu_i2c->adev;
1415 struct smu_context *smu = adev->powerplay.pp_handle;
1416 struct smu_table_context *smu_table = &smu->smu_table;
1417 struct smu_table *table = &smu_table->driver_table;
1418 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1419 int i, j, r, c;
1420 u16 dir;
1421
1422 if (!adev->pm.dpm_enabled)
1423 return -EBUSY;
1424
1425 req = kzalloc_obj(*req);
1426 if (!req)
1427 return -ENOMEM;
1428
1429 req->I2CcontrollerPort = smu_i2c->port;
1430 req->I2CSpeed = I2C_SPEED_FAST_400K;
1431 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1432 dir = msg[0].flags & I2C_M_RD;
1433
1434 for (c = i = 0; i < num_msgs; i++) {
1435 for (j = 0; j < msg[i].len; j++, c++) {
1436 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1437
1438 if (!(msg[i].flags & I2C_M_RD)) {
1439 /* write */
1440 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1441 cmd->ReadWriteData = msg[i].buf[j];
1442 }
1443
1444 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1445 /* The direction changes.
1446 */
1447 dir = msg[i].flags & I2C_M_RD;
1448 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1449 }
1450
1451 req->NumCmds++;
1452
1453 /*
1454 * Insert STOP if we are at the last byte of either last
1455 * message for the transaction or the client explicitly
1456 * requires a STOP at this particular message.
1457 */
1458 if ((j == msg[i].len - 1) &&
1459 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1460 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1461 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1462 }
1463 }
1464 }
1465 mutex_lock(&adev->pm.mutex);
1466 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1467 if (r)
1468 goto fail;
1469
1470 for (c = i = 0; i < num_msgs; i++) {
1471 if (!(msg[i].flags & I2C_M_RD)) {
1472 c += msg[i].len;
1473 continue;
1474 }
1475 for (j = 0; j < msg[i].len; j++, c++) {
1476 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1477
1478 msg[i].buf[j] = cmd->ReadWriteData;
1479 }
1480 }
1481 r = num_msgs;
1482 fail:
1483 mutex_unlock(&adev->pm.mutex);
1484 kfree(req);
1485 return r;
1486 }
1487
aldebaran_i2c_func(struct i2c_adapter * adap)1488 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1489 {
1490 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1491 }
1492
1493
1494 static const struct i2c_algorithm aldebaran_i2c_algo = {
1495 .master_xfer = aldebaran_i2c_xfer,
1496 .functionality = aldebaran_i2c_func,
1497 };
1498
1499 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1500 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1501 .max_read_len = MAX_SW_I2C_COMMANDS,
1502 .max_write_len = MAX_SW_I2C_COMMANDS,
1503 .max_comb_1st_msg_len = 2,
1504 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1505 };
1506
aldebaran_i2c_control_init(struct smu_context * smu)1507 static int aldebaran_i2c_control_init(struct smu_context *smu)
1508 {
1509 struct amdgpu_device *adev = smu->adev;
1510 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
1511 struct i2c_adapter *control = &smu_i2c->adapter;
1512 int res;
1513
1514 smu_i2c->adev = adev;
1515 smu_i2c->port = 0;
1516 mutex_init(&smu_i2c->mutex);
1517 control->owner = THIS_MODULE;
1518 control->dev.parent = &adev->pdev->dev;
1519 control->algo = &aldebaran_i2c_algo;
1520 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
1521 control->quirks = &aldebaran_i2c_control_quirks;
1522 i2c_set_adapdata(control, smu_i2c);
1523
1524 res = devm_i2c_add_adapter(adev->dev, control);
1525 if (res) {
1526 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1527 return res;
1528 }
1529
1530 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1531 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1532
1533 return 0;
1534 }
1535
aldebaran_i2c_control_fini(struct smu_context * smu)1536 static void aldebaran_i2c_control_fini(struct smu_context *smu)
1537 {
1538 struct amdgpu_device *adev = smu->adev;
1539
1540 adev->pm.ras_eeprom_i2c_bus = NULL;
1541 adev->pm.fru_eeprom_i2c_bus = NULL;
1542 }
1543
aldebaran_get_unique_id(struct smu_context * smu)1544 static void aldebaran_get_unique_id(struct smu_context *smu)
1545 {
1546 struct amdgpu_device *adev = smu->adev;
1547 uint32_t upper32 = 0, lower32 = 0;
1548
1549 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1550 goto out;
1551 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1552 goto out;
1553
1554 out:
1555 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1556 }
1557
aldebaran_get_bamaco_support(struct smu_context * smu)1558 static int aldebaran_get_bamaco_support(struct smu_context *smu)
1559 {
1560 /* aldebaran is not support baco */
1561
1562 return 0;
1563 }
1564
aldebaran_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)1565 static int aldebaran_set_df_cstate(struct smu_context *smu,
1566 enum pp_df_cstate state)
1567 {
1568 struct amdgpu_device *adev = smu->adev;
1569
1570 /*
1571 * Aldebaran does not need the cstate disablement
1572 * prerequisite for gpu reset.
1573 */
1574 if (amdgpu_in_reset(adev) || adev->in_suspend)
1575 return 0;
1576
1577 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1578 }
1579
1580 static const struct throttling_logging_label {
1581 uint32_t feature_mask;
1582 const char *label;
1583 } logging_label[] = {
1584 {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"},
1585 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1586 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1587 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1588 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1589 };
aldebaran_log_thermal_throttling_event(struct smu_context * smu)1590 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1591 {
1592 int ret;
1593 int throttler_idx, throttling_events = 0, buf_idx = 0;
1594 struct amdgpu_device *adev = smu->adev;
1595 uint32_t throttler_status;
1596 char log_buf[256];
1597
1598 ret = aldebaran_get_smu_metrics_data(smu,
1599 METRICS_THROTTLER_STATUS,
1600 &throttler_status);
1601 if (ret)
1602 return;
1603
1604 memset(log_buf, 0, sizeof(log_buf));
1605 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1606 throttler_idx++) {
1607 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1608 throttling_events++;
1609 buf_idx += snprintf(log_buf + buf_idx,
1610 sizeof(log_buf) - buf_idx,
1611 "%s%s",
1612 throttling_events > 1 ? " and " : "",
1613 logging_label[throttler_idx].label);
1614 if (buf_idx >= sizeof(log_buf)) {
1615 dev_err(adev->dev, "buffer overflow!\n");
1616 log_buf[sizeof(log_buf) - 1] = '\0';
1617 break;
1618 }
1619 }
1620 }
1621
1622 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1623 log_buf);
1624 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1625 smu_cmn_get_indep_throttler_status(throttler_status,
1626 aldebaran_throttler_map));
1627 }
1628
aldebaran_get_current_pcie_link_speed(struct smu_context * smu)1629 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1630 {
1631 struct amdgpu_device *adev = smu->adev;
1632 uint32_t esm_ctrl;
1633
1634 /* TODO: confirm this on real target */
1635 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1636 if ((esm_ctrl >> 15) & 0x1)
1637 return (((esm_ctrl >> 8) & 0x7F) + 128);
1638
1639 return smu_v13_0_get_current_pcie_link_speed(smu);
1640 }
1641
aldebaran_get_gpu_metrics(struct smu_context * smu,void ** table)1642 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1643 void **table)
1644 {
1645 struct gpu_metrics_v1_3 *gpu_metrics =
1646 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr(
1647 smu, SMU_DRIVER_TABLE_GPU_METRICS);
1648 SmuMetrics_t metrics;
1649 int i, ret = 0;
1650
1651 ret = smu_cmn_get_metrics_table(smu,
1652 &metrics,
1653 false);
1654 if (ret)
1655 return ret;
1656
1657 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1658
1659 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1660 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1661 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1662 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1663 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1664 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1665
1666 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1667 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1668
1669 /* Valid power data is available only from primary die */
1670 if (aldebaran_is_primary(smu)) {
1671 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1672 gpu_metrics->energy_accumulator =
1673 (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1674 metrics.EnergyAcc64bitLow;
1675 } else {
1676 gpu_metrics->average_socket_power = 0;
1677 gpu_metrics->energy_accumulator = 0;
1678 }
1679
1680 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1681 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1682 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1683 gpu_metrics->average_vclk0_frequency = 0;
1684 gpu_metrics->average_dclk0_frequency = 0;
1685
1686 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1687 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1688 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1689 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1690 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1691
1692 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1693 gpu_metrics->indep_throttle_status =
1694 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1695 aldebaran_throttler_map);
1696
1697 gpu_metrics->current_fan_speed = 0;
1698
1699 if (!amdgpu_sriov_vf(smu->adev)) {
1700 gpu_metrics->pcie_link_width =
1701 smu_v13_0_get_current_pcie_link_width(smu);
1702 gpu_metrics->pcie_link_speed =
1703 aldebaran_get_current_pcie_link_speed(smu);
1704 }
1705
1706 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1707
1708 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1709 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1710
1711 for (i = 0; i < NUM_HBM_INSTANCES; i++)
1712 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1713
1714 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1715 metrics.TimeStampLow;
1716
1717 *table = (void *)gpu_metrics;
1718
1719 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
1720
1721 return sizeof(struct gpu_metrics_v1_3);
1722 }
1723
aldebaran_check_ecc_table_support(struct smu_context * smu,int * ecctable_version)1724 static int aldebaran_check_ecc_table_support(struct smu_context *smu,
1725 int *ecctable_version)
1726 {
1727 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
1728 return -EOPNOTSUPP;
1729 else if (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_VERSION &&
1730 smu->smc_fw_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)
1731 *ecctable_version = 1;
1732 else
1733 *ecctable_version = 2;
1734
1735 return 0;
1736 }
1737
aldebaran_get_ecc_info(struct smu_context * smu,void * table)1738 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
1739 void *table)
1740 {
1741 struct smu_table_context *smu_table = &smu->smu_table;
1742 EccInfoTable_t *ecc_table = NULL;
1743 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
1744 int i, ret = 0;
1745 int table_version = 0;
1746 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
1747
1748 ret = aldebaran_check_ecc_table_support(smu, &table_version);
1749 if (ret)
1750 return ret;
1751
1752 ret = smu_cmn_update_table(smu,
1753 SMU_TABLE_ECCINFO,
1754 0,
1755 smu_table->ecc_table,
1756 false);
1757 if (ret) {
1758 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
1759 return ret;
1760 }
1761
1762 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
1763
1764 if (table_version == 1) {
1765 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1766 ecc_info_per_channel = &(eccinfo->ecc[i]);
1767 ecc_info_per_channel->ce_count_lo_chip =
1768 ecc_table->EccInfo[i].ce_count_lo_chip;
1769 ecc_info_per_channel->ce_count_hi_chip =
1770 ecc_table->EccInfo[i].ce_count_hi_chip;
1771 ecc_info_per_channel->mca_umc_status =
1772 ecc_table->EccInfo[i].mca_umc_status;
1773 ecc_info_per_channel->mca_umc_addr =
1774 ecc_table->EccInfo[i].mca_umc_addr;
1775 }
1776 } else if (table_version == 2) {
1777 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1778 ecc_info_per_channel = &(eccinfo->ecc[i]);
1779 ecc_info_per_channel->ce_count_lo_chip =
1780 ecc_table->EccInfo_V2[i].ce_count_lo_chip;
1781 ecc_info_per_channel->ce_count_hi_chip =
1782 ecc_table->EccInfo_V2[i].ce_count_hi_chip;
1783 ecc_info_per_channel->mca_umc_status =
1784 ecc_table->EccInfo_V2[i].mca_umc_status;
1785 ecc_info_per_channel->mca_umc_addr =
1786 ecc_table->EccInfo_V2[i].mca_umc_addr;
1787 ecc_info_per_channel->mca_ceumc_addr =
1788 ecc_table->EccInfo_V2[i].mca_ceumc_addr;
1789 }
1790 eccinfo->record_ce_addr_supported = 1;
1791 }
1792
1793 return ret;
1794 }
1795
aldebaran_mode1_reset(struct smu_context * smu)1796 static int aldebaran_mode1_reset(struct smu_context *smu)
1797 {
1798 u32 fatal_err, param;
1799 int ret = 0;
1800 struct amdgpu_device *adev = smu->adev;
1801
1802 fatal_err = 0;
1803 param = SMU_RESET_MODE_1;
1804
1805 /*
1806 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1807 */
1808 if (smu->smc_fw_version < 0x00440700) {
1809 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1810 } else {
1811 /* fatal error triggered by ras, PMFW supports the flag
1812 from 68.44.0 */
1813 if ((smu->smc_fw_version >= 0x00442c00) &&
1814 amdgpu_ras_get_fed_status(adev))
1815 fatal_err = 1;
1816
1817 param |= (fatal_err << 16);
1818 ret = smu_cmn_send_smc_msg_with_param(smu,
1819 SMU_MSG_GfxDeviceDriverReset, param, NULL);
1820 }
1821
1822 if (!ret)
1823 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1824
1825 return ret;
1826 }
1827
aldebaran_mode2_reset(struct smu_context * smu)1828 static int aldebaran_mode2_reset(struct smu_context *smu)
1829 {
1830 struct smu_msg_ctl *ctl = &smu->msg_ctl;
1831 struct amdgpu_device *adev = smu->adev;
1832 int ret = 0;
1833 int timeout = 10;
1834
1835 mutex_lock(&ctl->lock);
1836
1837 if (smu->smc_fw_version >= 0x00441400) {
1838 ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset,
1839 SMU_RESET_MODE_2);
1840 if (ret)
1841 goto out;
1842
1843 /* This is similar to FLR, wait till max FLR timeout */
1844 msleep(100);
1845 dev_dbg(adev->dev, "restore config space...\n");
1846 /* Restore the config space saved during init */
1847 amdgpu_device_load_pci_state(adev->pdev);
1848
1849 dev_dbg(adev->dev, "wait for reset ack\n");
1850 ret = -ETIME;
1851 while (ret == -ETIME && timeout) {
1852 ret = smu_msg_wait_response(ctl, 0);
1853 /* Wait a bit more time for getting ACK */
1854 if (ret == -ETIME) {
1855 --timeout;
1856 usleep_range(500, 1000);
1857 continue;
1858 }
1859
1860 if (ret != 0) {
1861 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1862 SMU_RESET_MODE_2, ret);
1863 goto out;
1864 }
1865 }
1866
1867 } else {
1868 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1869 smu->smc_fw_version);
1870 ret = -EOPNOTSUPP;
1871 }
1872
1873 out:
1874 mutex_unlock(&ctl->lock);
1875
1876 return ret;
1877 }
1878
aldebaran_smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)1879 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1880 {
1881 int ret = 0;
1882 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1883
1884 return ret;
1885 }
1886
aldebaran_is_mode1_reset_supported(struct smu_context * smu)1887 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1888 {
1889 #if 0
1890 struct amdgpu_device *adev = smu->adev;
1891 uint32_t val;
1892 uint32_t smu_version;
1893 int ret;
1894
1895 /**
1896 * PM FW version support mode1 reset from 68.07
1897 */
1898 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1899 if (ret)
1900 return false;
1901
1902 if ((smu_version < 0x00440700))
1903 return false;
1904
1905 /**
1906 * mode1 reset relies on PSP, so we should check if
1907 * PSP is alive.
1908 */
1909 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1910
1911 return val != 0x0;
1912 #endif
1913 return true;
1914 }
1915
aldebaran_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)1916 static int aldebaran_set_mp1_state(struct smu_context *smu,
1917 enum pp_mp1_state mp1_state)
1918 {
1919 switch (mp1_state) {
1920 case PP_MP1_STATE_UNLOAD:
1921 return smu_cmn_set_mp1_state(smu, mp1_state);
1922 default:
1923 return 0;
1924 }
1925 }
1926
aldebaran_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)1927 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1928 uint32_t size)
1929 {
1930 int ret = 0;
1931
1932 /* message SMU to update the bad page number on SMUBUS */
1933 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1934 if (ret)
1935 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1936 __func__);
1937
1938 return ret;
1939 }
1940
aldebaran_check_bad_channel_info_support(struct smu_context * smu)1941 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu)
1942 {
1943 if (smu->smc_fw_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)
1944 return -EOPNOTSUPP;
1945
1946 return 0;
1947 }
1948
aldebaran_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)1949 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,
1950 uint32_t size)
1951 {
1952 int ret = 0;
1953
1954 ret = aldebaran_check_bad_channel_info_support(smu);
1955 if (ret)
1956 return ret;
1957
1958 /* message SMU to update the bad channel info on SMUBUS */
1959 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL);
1960 if (ret)
1961 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n",
1962 __func__);
1963
1964 return ret;
1965 }
1966
1967 static const struct pptable_funcs aldebaran_ppt_funcs = {
1968 /* init dpm */
1969 .init_allowed_features = aldebaran_init_allowed_features,
1970 /* dpm/clk tables */
1971 .set_default_dpm_table = aldebaran_set_default_dpm_table,
1972 .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1973 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1974 .emit_clk_levels = aldebaran_emit_clk_levels,
1975 .force_clk_levels = aldebaran_force_clk_levels,
1976 .read_sensor = aldebaran_read_sensor,
1977 .set_performance_level = aldebaran_set_performance_level,
1978 .get_power_limit = aldebaran_get_power_limit,
1979 .is_dpm_running = aldebaran_is_dpm_running,
1980 .get_unique_id = aldebaran_get_unique_id,
1981 .init_microcode = smu_v13_0_init_microcode,
1982 .load_microcode = smu_v13_0_load_microcode,
1983 .fini_microcode = smu_v13_0_fini_microcode,
1984 .init_smc_tables = aldebaran_init_smc_tables,
1985 .fini_smc_tables = smu_v13_0_fini_smc_tables,
1986 .init_power = smu_v13_0_init_power,
1987 .fini_power = smu_v13_0_fini_power,
1988 .check_fw_status = smu_v13_0_check_fw_status,
1989 /* pptable related */
1990 .setup_pptable = aldebaran_setup_pptable,
1991 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1992 .check_fw_version = smu_cmn_check_fw_version,
1993 .write_pptable = smu_cmn_write_pptable,
1994 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1995 .set_tool_table_location = smu_v13_0_set_tool_table_location,
1996 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1997 .system_features_control = aldebaran_system_features_control,
1998 .get_enabled_mask = smu_cmn_get_enabled_mask,
1999 .feature_is_enabled = smu_cmn_feature_is_enabled,
2000 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2001 .set_power_limit = aldebaran_set_power_limit,
2002 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2003 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2004 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2005 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2006 .register_irq_handler = smu_v13_0_register_irq_handler,
2007 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2008 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2009 .get_bamaco_support = aldebaran_get_bamaco_support,
2010 .get_dpm_ultimate_freq = aldebaran_get_dpm_ultimate_freq,
2011 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2012 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2013 .set_df_cstate = aldebaran_set_df_cstate,
2014 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2015 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2016 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2017 .get_gpu_metrics = aldebaran_get_gpu_metrics,
2018 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2019 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
2020 .mode1_reset = aldebaran_mode1_reset,
2021 .set_mp1_state = aldebaran_set_mp1_state,
2022 .mode2_reset = aldebaran_mode2_reset,
2023 .wait_for_event = smu_v13_0_wait_for_event,
2024 .i2c_init = aldebaran_i2c_control_init,
2025 .i2c_fini = aldebaran_i2c_control_fini,
2026 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2027 .get_ecc_info = aldebaran_get_ecc_info,
2028 .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag,
2029 };
2030
aldebaran_set_ppt_funcs(struct smu_context * smu)2031 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2032 {
2033 smu->ppt_funcs = &aldebaran_ppt_funcs;
2034 smu->clock_map = aldebaran_clk_map;
2035 smu->feature_map = aldebaran_feature_mask_map;
2036 smu->table_map = aldebaran_table_map;
2037 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
2038 smu_v13_0_init_msg_ctl(smu, aldebaran_message_map);
2039 }
2040