1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
6 */
7
8 #include <linux/export.h>
9 #include <linux/module.h>
10 #include <linux/slab.h>
11 #include <linux/remoteproc.h>
12 #include <linux/firmware.h>
13 #include <linux/of.h>
14
15 #include "core.h"
16 #include "dp_tx.h"
17 #include "dp_rx.h"
18 #include "debug.h"
19 #include "hif.h"
20 #include "wow.h"
21 #include "fw.h"
22
23 unsigned int ath11k_debug_mask;
24 EXPORT_SYMBOL(ath11k_debug_mask);
25 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
26 MODULE_PARM_DESC(debug_mask, "Debugging mask");
27
28 static unsigned int ath11k_crypto_mode;
29 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
30 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
31
32 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
33 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
34 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
35 MODULE_PARM_DESC(frame_mode,
36 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
37
38 bool ath11k_ftm_mode;
39 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
40 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
41
42 static const struct ath11k_hw_params ath11k_hw_params[] = {
43 {
44 .hw_rev = ATH11K_HW_IPQ8074,
45 .name = "ipq8074 hw2.0",
46 .fw = {
47 .dir = "IPQ8074/hw2.0",
48 .board_size = 256 * 1024,
49 .cal_offset = 128 * 1024,
50 },
51 .max_radios = 3,
52 .bdf_addr = 0x4B0C0000,
53 .hw_ops = &ipq8074_ops,
54 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
55 .internal_sleep_clock = false,
56 .regs = &ipq8074_regs,
57 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
58 .host_ce_config = ath11k_host_ce_config_ipq8074,
59 .ce_count = 12,
60 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
61 .target_ce_count = 11,
62 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
63 .svc_to_ce_map_len = 21,
64 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
65 .single_pdev_only = false,
66 .rxdma1_enable = true,
67 .num_rxdma_per_pdev = 1,
68 .rx_mac_buf_ring = false,
69 .vdev_start_delay = false,
70 .htt_peer_map_v2 = true,
71
72 .spectral = {
73 .fft_sz = 2,
74 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
75 * so added pad size as 2 bytes to compensate the BIN size
76 */
77 .fft_pad_sz = 2,
78 .summary_pad_sz = 0,
79 .fft_hdr_len = 16,
80 .max_fft_bins = 512,
81 .fragment_160mhz = true,
82 },
83
84 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
85 BIT(NL80211_IFTYPE_AP) |
86 BIT(NL80211_IFTYPE_MESH_POINT),
87 .supports_monitor = true,
88 .full_monitor_mode = false,
89 .supports_shadow_regs = false,
90 .idle_ps = false,
91 .supports_sta_ps = false,
92 .coldboot_cal_mm = true,
93 .coldboot_cal_ftm = true,
94 .cbcal_restart_fw = true,
95 .fw_mem_mode = 0,
96 .num_vdevs = 16 + 1,
97 .num_peers = 512,
98 .supports_suspend = false,
99 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
100 .supports_regdb = false,
101 .fix_l1ss = true,
102 .credit_flow = false,
103 .max_tx_ring = DP_TCL_NUM_RING_MAX,
104 .hal_params = &ath11k_hw_hal_params_ipq8074,
105 .supports_dynamic_smps_6ghz = false,
106 .alloc_cacheable_memory = true,
107 .supports_rssi_stats = false,
108 .fw_wmi_diag_event = false,
109 .current_cc_support = false,
110 .dbr_debug_support = true,
111 .global_reset = false,
112 .bios_sar_capa = NULL,
113 .m3_fw_support = false,
114 .fixed_bdf_addr = true,
115 .fixed_mem_region = true,
116 .static_window_map = false,
117 .hybrid_bus_type = false,
118 .fixed_fw_mem = false,
119 .support_off_channel_tx = false,
120 .supports_multi_bssid = false,
121
122 .sram_dump = {},
123
124 .tcl_ring_retry = true,
125 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
126 .smp2p_wow_exit = false,
127 .support_dual_stations = false,
128 .pdev_suspend = false,
129 },
130 {
131 .hw_rev = ATH11K_HW_IPQ6018_HW10,
132 .name = "ipq6018 hw1.0",
133 .fw = {
134 .dir = "IPQ6018/hw1.0",
135 .board_size = 256 * 1024,
136 .cal_offset = 128 * 1024,
137 },
138 .max_radios = 2,
139 .bdf_addr = 0x4ABC0000,
140 .hw_ops = &ipq6018_ops,
141 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
142 .internal_sleep_clock = false,
143 .regs = &ipq8074_regs,
144 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
145 .host_ce_config = ath11k_host_ce_config_ipq8074,
146 .ce_count = 12,
147 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
148 .target_ce_count = 11,
149 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
150 .svc_to_ce_map_len = 19,
151 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
152 .single_pdev_only = false,
153 .rxdma1_enable = true,
154 .num_rxdma_per_pdev = 1,
155 .rx_mac_buf_ring = false,
156 .vdev_start_delay = false,
157 .htt_peer_map_v2 = true,
158
159 .spectral = {
160 .fft_sz = 4,
161 .fft_pad_sz = 0,
162 .summary_pad_sz = 0,
163 .fft_hdr_len = 16,
164 .max_fft_bins = 512,
165 .fragment_160mhz = true,
166 },
167
168 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
169 BIT(NL80211_IFTYPE_AP) |
170 BIT(NL80211_IFTYPE_MESH_POINT),
171 .supports_monitor = true,
172 .full_monitor_mode = false,
173 .supports_shadow_regs = false,
174 .idle_ps = false,
175 .supports_sta_ps = false,
176 .coldboot_cal_mm = true,
177 .coldboot_cal_ftm = true,
178 .cbcal_restart_fw = true,
179 .fw_mem_mode = 0,
180 .num_vdevs = 16 + 1,
181 .num_peers = 512,
182 .supports_suspend = false,
183 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
184 .supports_regdb = false,
185 .fix_l1ss = true,
186 .credit_flow = false,
187 .max_tx_ring = DP_TCL_NUM_RING_MAX,
188 .hal_params = &ath11k_hw_hal_params_ipq8074,
189 .supports_dynamic_smps_6ghz = false,
190 .alloc_cacheable_memory = true,
191 .supports_rssi_stats = false,
192 .fw_wmi_diag_event = false,
193 .current_cc_support = false,
194 .dbr_debug_support = true,
195 .global_reset = false,
196 .bios_sar_capa = NULL,
197 .m3_fw_support = false,
198 .fixed_bdf_addr = true,
199 .fixed_mem_region = true,
200 .static_window_map = false,
201 .hybrid_bus_type = false,
202 .fixed_fw_mem = false,
203 .support_off_channel_tx = false,
204 .supports_multi_bssid = false,
205
206 .sram_dump = {},
207
208 .tcl_ring_retry = true,
209 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
210 .smp2p_wow_exit = false,
211 .support_fw_mac_sequence = false,
212 .support_dual_stations = false,
213 .pdev_suspend = false,
214 },
215 {
216 .name = "qca6390 hw2.0",
217 .hw_rev = ATH11K_HW_QCA6390_HW20,
218 .fw = {
219 .dir = "QCA6390/hw2.0",
220 .board_size = 256 * 1024,
221 .cal_offset = 128 * 1024,
222 },
223 .max_radios = 3,
224 .bdf_addr = 0x4B0C0000,
225 .hw_ops = &qca6390_ops,
226 .ring_mask = &ath11k_hw_ring_mask_qca6390,
227 .internal_sleep_clock = true,
228 .regs = &qca6390_regs,
229 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
230 .host_ce_config = ath11k_host_ce_config_qca6390,
231 .ce_count = 9,
232 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
233 .target_ce_count = 9,
234 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
235 .svc_to_ce_map_len = 14,
236 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
237 .single_pdev_only = true,
238 .rxdma1_enable = false,
239 .num_rxdma_per_pdev = 2,
240 .rx_mac_buf_ring = true,
241 .vdev_start_delay = true,
242 .htt_peer_map_v2 = false,
243
244 .spectral = {
245 .fft_sz = 0,
246 .fft_pad_sz = 0,
247 .summary_pad_sz = 0,
248 .fft_hdr_len = 0,
249 .max_fft_bins = 0,
250 .fragment_160mhz = false,
251 },
252
253 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
254 BIT(NL80211_IFTYPE_AP) |
255 BIT(NL80211_IFTYPE_P2P_DEVICE) |
256 BIT(NL80211_IFTYPE_P2P_CLIENT) |
257 BIT(NL80211_IFTYPE_P2P_GO),
258 .supports_monitor = false,
259 .full_monitor_mode = false,
260 .supports_shadow_regs = true,
261 .idle_ps = true,
262 .supports_sta_ps = true,
263 .coldboot_cal_mm = false,
264 .coldboot_cal_ftm = false,
265 .cbcal_restart_fw = false,
266 .fw_mem_mode = 0,
267 .num_vdevs = 2 + 1,
268 .num_peers = 512,
269 .supports_suspend = true,
270 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
271 .supports_regdb = false,
272 .fix_l1ss = true,
273 .credit_flow = true,
274 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
275 .hal_params = &ath11k_hw_hal_params_qca6390,
276 .supports_dynamic_smps_6ghz = false,
277 .alloc_cacheable_memory = false,
278 .supports_rssi_stats = true,
279 .fw_wmi_diag_event = true,
280 .current_cc_support = true,
281 .dbr_debug_support = false,
282 .global_reset = true,
283 .bios_sar_capa = NULL,
284 .m3_fw_support = true,
285 .fixed_bdf_addr = false,
286 .fixed_mem_region = false,
287 .static_window_map = false,
288 .hybrid_bus_type = false,
289 .fixed_fw_mem = false,
290 .support_off_channel_tx = true,
291 .supports_multi_bssid = true,
292
293 .sram_dump = {
294 .start = 0x01400000,
295 .end = 0x0171ffff,
296 },
297
298 .tcl_ring_retry = true,
299 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
300 .smp2p_wow_exit = false,
301 .support_fw_mac_sequence = true,
302 .support_dual_stations = true,
303 .pdev_suspend = false,
304 },
305 {
306 .name = "qcn9074 hw1.0",
307 .hw_rev = ATH11K_HW_QCN9074_HW10,
308 .fw = {
309 .dir = "QCN9074/hw1.0",
310 .board_size = 256 * 1024,
311 .cal_offset = 128 * 1024,
312 },
313 .max_radios = 1,
314 .single_pdev_only = false,
315 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
316 .hw_ops = &qcn9074_ops,
317 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
318 .internal_sleep_clock = false,
319 .regs = &qcn9074_regs,
320 .host_ce_config = ath11k_host_ce_config_qcn9074,
321 .ce_count = 6,
322 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
323 .target_ce_count = 9,
324 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
325 .svc_to_ce_map_len = 18,
326 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
327 .rxdma1_enable = true,
328 .num_rxdma_per_pdev = 1,
329 .rx_mac_buf_ring = false,
330 .vdev_start_delay = false,
331 .htt_peer_map_v2 = true,
332
333 .spectral = {
334 .fft_sz = 2,
335 .fft_pad_sz = 0,
336 .summary_pad_sz = 16,
337 .fft_hdr_len = 24,
338 .max_fft_bins = 1024,
339 .fragment_160mhz = false,
340 },
341
342 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
343 BIT(NL80211_IFTYPE_AP) |
344 BIT(NL80211_IFTYPE_MESH_POINT),
345 .supports_monitor = true,
346 .full_monitor_mode = true,
347 .supports_shadow_regs = false,
348 .idle_ps = false,
349 .supports_sta_ps = false,
350 .coldboot_cal_mm = false,
351 .coldboot_cal_ftm = true,
352 .cbcal_restart_fw = true,
353 .fw_mem_mode = 2,
354 .num_vdevs = 8,
355 .num_peers = 128,
356 .supports_suspend = false,
357 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
358 .supports_regdb = false,
359 .fix_l1ss = true,
360 .credit_flow = false,
361 .max_tx_ring = DP_TCL_NUM_RING_MAX,
362 .hal_params = &ath11k_hw_hal_params_ipq8074,
363 .supports_dynamic_smps_6ghz = true,
364 .alloc_cacheable_memory = true,
365 .supports_rssi_stats = false,
366 .fw_wmi_diag_event = false,
367 .current_cc_support = false,
368 .dbr_debug_support = true,
369 .global_reset = false,
370 .bios_sar_capa = NULL,
371 .m3_fw_support = true,
372 .fixed_bdf_addr = false,
373 .fixed_mem_region = false,
374 .static_window_map = true,
375 .hybrid_bus_type = false,
376 .fixed_fw_mem = false,
377 .support_off_channel_tx = false,
378 .supports_multi_bssid = false,
379
380 .sram_dump = {},
381
382 .tcl_ring_retry = true,
383 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
384 .smp2p_wow_exit = false,
385 .support_fw_mac_sequence = false,
386 .support_dual_stations = false,
387 .pdev_suspend = false,
388 },
389 {
390 .name = "wcn6855 hw2.0",
391 .hw_rev = ATH11K_HW_WCN6855_HW20,
392 .fw = {
393 .dir = "WCN6855/hw2.0",
394 .board_size = 256 * 1024,
395 .cal_offset = 128 * 1024,
396 },
397 .max_radios = 3,
398 .bdf_addr = 0x4B0C0000,
399 .hw_ops = &wcn6855_ops,
400 .ring_mask = &ath11k_hw_ring_mask_qca6390,
401 .internal_sleep_clock = true,
402 .regs = &wcn6855_regs,
403 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
404 .host_ce_config = ath11k_host_ce_config_qca6390,
405 .ce_count = 9,
406 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
407 .target_ce_count = 9,
408 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
409 .svc_to_ce_map_len = 14,
410 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
411 .single_pdev_only = true,
412 .rxdma1_enable = false,
413 .num_rxdma_per_pdev = 2,
414 .rx_mac_buf_ring = true,
415 .vdev_start_delay = true,
416 .htt_peer_map_v2 = false,
417
418 .spectral = {
419 .fft_sz = 0,
420 .fft_pad_sz = 0,
421 .summary_pad_sz = 0,
422 .fft_hdr_len = 0,
423 .max_fft_bins = 0,
424 .fragment_160mhz = false,
425 },
426
427 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
428 BIT(NL80211_IFTYPE_AP) |
429 BIT(NL80211_IFTYPE_P2P_DEVICE) |
430 BIT(NL80211_IFTYPE_P2P_CLIENT) |
431 BIT(NL80211_IFTYPE_P2P_GO),
432 .supports_monitor = false,
433 .full_monitor_mode = false,
434 .supports_shadow_regs = true,
435 .idle_ps = true,
436 .supports_sta_ps = true,
437 .coldboot_cal_mm = false,
438 .coldboot_cal_ftm = false,
439 .cbcal_restart_fw = false,
440 .fw_mem_mode = 0,
441 .num_vdevs = 2 + 1,
442 .num_peers = 512,
443 .supports_suspend = true,
444 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
445 .supports_regdb = true,
446 .fix_l1ss = false,
447 .credit_flow = true,
448 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
449 .hal_params = &ath11k_hw_hal_params_qca6390,
450 .supports_dynamic_smps_6ghz = false,
451 .alloc_cacheable_memory = false,
452 .supports_rssi_stats = true,
453 .fw_wmi_diag_event = true,
454 .current_cc_support = true,
455 .dbr_debug_support = false,
456 .global_reset = true,
457 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
458 .m3_fw_support = true,
459 .fixed_bdf_addr = false,
460 .fixed_mem_region = false,
461 .static_window_map = false,
462 .hybrid_bus_type = false,
463 .fixed_fw_mem = false,
464 .support_off_channel_tx = true,
465 .supports_multi_bssid = true,
466
467 .sram_dump = {
468 .start = 0x01400000,
469 .end = 0x0177ffff,
470 },
471
472 .tcl_ring_retry = true,
473 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
474 .smp2p_wow_exit = false,
475 .support_fw_mac_sequence = true,
476 .support_dual_stations = true,
477 .pdev_suspend = false,
478 },
479 {
480 .name = "wcn6855 hw2.1",
481 .hw_rev = ATH11K_HW_WCN6855_HW21,
482 .fw = {
483 .dir = "WCN6855/hw2.1",
484 .board_size = 256 * 1024,
485 .cal_offset = 128 * 1024,
486 },
487 .max_radios = 3,
488 .bdf_addr = 0x4B0C0000,
489 .hw_ops = &wcn6855_ops,
490 .ring_mask = &ath11k_hw_ring_mask_qca6390,
491 .internal_sleep_clock = true,
492 .regs = &wcn6855_regs,
493 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
494 .host_ce_config = ath11k_host_ce_config_qca6390,
495 .ce_count = 9,
496 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
497 .target_ce_count = 9,
498 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
499 .svc_to_ce_map_len = 14,
500 .single_pdev_only = true,
501 .rxdma1_enable = false,
502 .num_rxdma_per_pdev = 2,
503 .rx_mac_buf_ring = true,
504 .vdev_start_delay = true,
505 .htt_peer_map_v2 = false,
506
507 .spectral = {
508 .fft_sz = 0,
509 .fft_pad_sz = 0,
510 .summary_pad_sz = 0,
511 .fft_hdr_len = 0,
512 .max_fft_bins = 0,
513 .fragment_160mhz = false,
514 },
515
516 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
517 BIT(NL80211_IFTYPE_AP) |
518 BIT(NL80211_IFTYPE_P2P_DEVICE) |
519 BIT(NL80211_IFTYPE_P2P_CLIENT) |
520 BIT(NL80211_IFTYPE_P2P_GO),
521 .supports_monitor = false,
522 .supports_shadow_regs = true,
523 .idle_ps = true,
524 .supports_sta_ps = true,
525 .coldboot_cal_mm = false,
526 .coldboot_cal_ftm = false,
527 .cbcal_restart_fw = false,
528 .fw_mem_mode = 0,
529 .num_vdevs = 2 + 1,
530 .num_peers = 512,
531 .supports_suspend = true,
532 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
533 .supports_regdb = true,
534 .fix_l1ss = false,
535 .credit_flow = true,
536 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
537 .hal_params = &ath11k_hw_hal_params_qca6390,
538 .supports_dynamic_smps_6ghz = false,
539 .alloc_cacheable_memory = false,
540 .supports_rssi_stats = true,
541 .fw_wmi_diag_event = true,
542 .current_cc_support = true,
543 .dbr_debug_support = false,
544 .global_reset = true,
545 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
546 .m3_fw_support = true,
547 .fixed_bdf_addr = false,
548 .fixed_mem_region = false,
549 .static_window_map = false,
550 .hybrid_bus_type = false,
551 .fixed_fw_mem = false,
552 .support_off_channel_tx = true,
553 .supports_multi_bssid = true,
554
555 .sram_dump = {
556 .start = 0x01400000,
557 .end = 0x0177ffff,
558 },
559
560 .tcl_ring_retry = true,
561 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
562 .smp2p_wow_exit = false,
563 .support_fw_mac_sequence = true,
564 .support_dual_stations = true,
565 .pdev_suspend = false,
566 },
567 {
568 .name = "wcn6750 hw1.0",
569 .hw_rev = ATH11K_HW_WCN6750_HW10,
570 .fw = {
571 .dir = "WCN6750/hw1.0",
572 .board_size = 256 * 1024,
573 .cal_offset = 128 * 1024,
574 },
575 .max_radios = 1,
576 .bdf_addr = 0x4B0C0000,
577 .hw_ops = &wcn6750_ops,
578 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
579 .internal_sleep_clock = false,
580 .regs = &wcn6750_regs,
581 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
582 .host_ce_config = ath11k_host_ce_config_qca6390,
583 .ce_count = 9,
584 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
585 .target_ce_count = 9,
586 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
587 .svc_to_ce_map_len = 14,
588 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
589 .single_pdev_only = true,
590 .rxdma1_enable = false,
591 .num_rxdma_per_pdev = 1,
592 .rx_mac_buf_ring = true,
593 .vdev_start_delay = true,
594 .htt_peer_map_v2 = false,
595
596 .spectral = {
597 .fft_sz = 0,
598 .fft_pad_sz = 0,
599 .summary_pad_sz = 0,
600 .fft_hdr_len = 0,
601 .max_fft_bins = 0,
602 .fragment_160mhz = false,
603 },
604
605 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
606 BIT(NL80211_IFTYPE_AP),
607 .supports_monitor = false,
608 .supports_shadow_regs = true,
609 .idle_ps = true,
610 .supports_sta_ps = true,
611 .coldboot_cal_mm = true,
612 .coldboot_cal_ftm = true,
613 .cbcal_restart_fw = false,
614 .fw_mem_mode = 0,
615 .num_vdevs = 3,
616 .num_peers = 512,
617 .supports_suspend = false,
618 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
619 .supports_regdb = true,
620 .fix_l1ss = false,
621 .credit_flow = true,
622 .max_tx_ring = DP_TCL_NUM_RING_MAX,
623 .hal_params = &ath11k_hw_hal_params_wcn6750,
624 .supports_dynamic_smps_6ghz = false,
625 .alloc_cacheable_memory = false,
626 .supports_rssi_stats = true,
627 .fw_wmi_diag_event = true,
628 .current_cc_support = true,
629 .dbr_debug_support = false,
630 .global_reset = false,
631 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
632 .m3_fw_support = false,
633 .fixed_bdf_addr = false,
634 .fixed_mem_region = false,
635 .static_window_map = true,
636 .hybrid_bus_type = true,
637 .fixed_fw_mem = true,
638 .support_off_channel_tx = true,
639 .supports_multi_bssid = true,
640
641 .sram_dump = {},
642
643 .tcl_ring_retry = false,
644 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
645 .smp2p_wow_exit = true,
646 .support_fw_mac_sequence = true,
647 .support_dual_stations = false,
648 .pdev_suspend = true,
649 },
650 {
651 .hw_rev = ATH11K_HW_IPQ5018_HW10,
652 .name = "ipq5018 hw1.0",
653 .fw = {
654 .dir = "IPQ5018/hw1.0",
655 .board_size = 256 * 1024,
656 .cal_offset = 128 * 1024,
657 },
658 .max_radios = MAX_RADIOS_5018,
659 .bdf_addr = 0x4BA00000,
660 /* hal_desc_sz and hw ops are similar to qcn9074 */
661 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
662 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
663 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
664 .credit_flow = false,
665 .max_tx_ring = 1,
666 .spectral = {
667 .fft_sz = 2,
668 .fft_pad_sz = 0,
669 .summary_pad_sz = 16,
670 .fft_hdr_len = 24,
671 .max_fft_bins = 1024,
672 },
673 .internal_sleep_clock = false,
674 .regs = &ipq5018_regs,
675 .hw_ops = &ipq5018_ops,
676 .host_ce_config = ath11k_host_ce_config_qcn9074,
677 .ce_count = CE_CNT_5018,
678 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
679 .target_ce_count = TARGET_CE_CNT_5018,
680 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
681 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
682 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
683 .ce_remap = &ath11k_ce_remap_ipq5018,
684 .rxdma1_enable = true,
685 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018,
686 .rx_mac_buf_ring = false,
687 .vdev_start_delay = false,
688 .htt_peer_map_v2 = true,
689 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
690 BIT(NL80211_IFTYPE_AP) |
691 BIT(NL80211_IFTYPE_MESH_POINT),
692 .supports_monitor = false,
693 .supports_sta_ps = false,
694 .supports_shadow_regs = false,
695 .fw_mem_mode = 0,
696 .num_vdevs = 16 + 1,
697 .num_peers = 512,
698 .supports_regdb = false,
699 .idle_ps = false,
700 .supports_suspend = false,
701 .hal_params = &ath11k_hw_hal_params_ipq8074,
702 .single_pdev_only = false,
703 .coldboot_cal_mm = true,
704 .coldboot_cal_ftm = true,
705 .cbcal_restart_fw = true,
706 .fix_l1ss = true,
707 .supports_dynamic_smps_6ghz = false,
708 .alloc_cacheable_memory = true,
709 .supports_rssi_stats = false,
710 .fw_wmi_diag_event = false,
711 .current_cc_support = false,
712 .dbr_debug_support = true,
713 .global_reset = false,
714 .bios_sar_capa = NULL,
715 .m3_fw_support = false,
716 .fixed_bdf_addr = true,
717 .fixed_mem_region = true,
718 .static_window_map = false,
719 .hybrid_bus_type = false,
720 .fixed_fw_mem = false,
721 .support_off_channel_tx = false,
722 .supports_multi_bssid = false,
723
724 .sram_dump = {},
725
726 .tcl_ring_retry = true,
727 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
728 .smp2p_wow_exit = false,
729 .support_fw_mac_sequence = false,
730 .support_dual_stations = false,
731 .pdev_suspend = false,
732 },
733 {
734 .name = "qca2066 hw2.1",
735 .hw_rev = ATH11K_HW_QCA2066_HW21,
736 .fw = {
737 .dir = "QCA2066/hw2.1",
738 .board_size = 256 * 1024,
739 .cal_offset = 128 * 1024,
740 },
741 .max_radios = 3,
742 .bdf_addr = 0x4B0C0000,
743 .hw_ops = &wcn6855_ops,
744 .ring_mask = &ath11k_hw_ring_mask_qca6390,
745 .internal_sleep_clock = true,
746 .regs = &wcn6855_regs,
747 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
748 .host_ce_config = ath11k_host_ce_config_qca6390,
749 .ce_count = 9,
750 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
751 .target_ce_count = 9,
752 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
753 .svc_to_ce_map_len = 14,
754 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
755 .single_pdev_only = true,
756 .rxdma1_enable = false,
757 .num_rxdma_per_pdev = 2,
758 .rx_mac_buf_ring = true,
759 .vdev_start_delay = true,
760 .htt_peer_map_v2 = false,
761
762 .spectral = {
763 .fft_sz = 0,
764 .fft_pad_sz = 0,
765 .summary_pad_sz = 0,
766 .fft_hdr_len = 0,
767 .max_fft_bins = 0,
768 .fragment_160mhz = false,
769 },
770
771 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
772 BIT(NL80211_IFTYPE_AP) |
773 BIT(NL80211_IFTYPE_P2P_DEVICE) |
774 BIT(NL80211_IFTYPE_P2P_CLIENT) |
775 BIT(NL80211_IFTYPE_P2P_GO),
776 .supports_monitor = false,
777 .full_monitor_mode = false,
778 .supports_shadow_regs = true,
779 .idle_ps = true,
780 .supports_sta_ps = true,
781 .coldboot_cal_mm = false,
782 .coldboot_cal_ftm = false,
783 .cbcal_restart_fw = false,
784 .fw_mem_mode = 0,
785 .num_vdevs = 2 + 1,
786 .num_peers = 512,
787 .supports_suspend = true,
788 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
789 .supports_regdb = true,
790 .fix_l1ss = false,
791 .credit_flow = true,
792 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
793 .hal_params = &ath11k_hw_hal_params_qca6390,
794 .supports_dynamic_smps_6ghz = false,
795 .alloc_cacheable_memory = false,
796 .supports_rssi_stats = true,
797 .fw_wmi_diag_event = true,
798 .current_cc_support = true,
799 .dbr_debug_support = false,
800 .global_reset = true,
801 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
802 .m3_fw_support = true,
803 .fixed_bdf_addr = false,
804 .fixed_mem_region = false,
805 .static_window_map = false,
806 .hybrid_bus_type = false,
807 .fixed_fw_mem = false,
808 .support_off_channel_tx = true,
809 .supports_multi_bssid = true,
810
811 .sram_dump = {
812 .start = 0x01400000,
813 .end = 0x0177ffff,
814 },
815
816 .tcl_ring_retry = true,
817 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
818 .smp2p_wow_exit = false,
819 .support_fw_mac_sequence = true,
820 .support_dual_stations = true,
821 },
822 {
823 .name = "qca6698aq hw2.1",
824 .hw_rev = ATH11K_HW_QCA6698AQ_HW21,
825 .fw = {
826 .dir = "QCA6698AQ/hw2.1",
827 .board_size = 256 * 1024,
828 .cal_offset = 128 * 1024,
829 },
830 .max_radios = 3,
831 .bdf_addr = 0x4B0C0000,
832 .hw_ops = &wcn6855_ops,
833 .ring_mask = &ath11k_hw_ring_mask_qca6390,
834 .internal_sleep_clock = true,
835 .regs = &wcn6855_regs,
836 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
837 .host_ce_config = ath11k_host_ce_config_qca6390,
838 .ce_count = 9,
839 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
840 .target_ce_count = 9,
841 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
842 .svc_to_ce_map_len = 14,
843 .single_pdev_only = true,
844 .rxdma1_enable = false,
845 .num_rxdma_per_pdev = 2,
846 .rx_mac_buf_ring = true,
847 .vdev_start_delay = true,
848 .htt_peer_map_v2 = false,
849
850 .spectral = {
851 .fft_sz = 0,
852 .fft_pad_sz = 0,
853 .summary_pad_sz = 0,
854 .fft_hdr_len = 0,
855 .max_fft_bins = 0,
856 .fragment_160mhz = false,
857 },
858
859 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
860 BIT(NL80211_IFTYPE_AP) |
861 BIT(NL80211_IFTYPE_P2P_DEVICE) |
862 BIT(NL80211_IFTYPE_P2P_CLIENT) |
863 BIT(NL80211_IFTYPE_P2P_GO),
864 .supports_monitor = false,
865 .supports_shadow_regs = true,
866 .idle_ps = true,
867 .supports_sta_ps = true,
868 .coldboot_cal_mm = false,
869 .coldboot_cal_ftm = false,
870 .cbcal_restart_fw = false,
871 .fw_mem_mode = 0,
872 .num_vdevs = 2 + 1,
873 .num_peers = 512,
874 .supports_suspend = true,
875 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
876 .supports_regdb = true,
877 .fix_l1ss = false,
878 .credit_flow = true,
879 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
880 .hal_params = &ath11k_hw_hal_params_qca6390,
881 .supports_dynamic_smps_6ghz = false,
882 .alloc_cacheable_memory = false,
883 .supports_rssi_stats = true,
884 .fw_wmi_diag_event = true,
885 .current_cc_support = true,
886 .dbr_debug_support = false,
887 .global_reset = true,
888 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
889 .m3_fw_support = true,
890 .fixed_bdf_addr = false,
891 .fixed_mem_region = false,
892 .static_window_map = false,
893 .hybrid_bus_type = false,
894 .fixed_fw_mem = false,
895 .support_off_channel_tx = true,
896 .supports_multi_bssid = true,
897
898 .sram_dump = {
899 .start = 0x01400000,
900 .end = 0x0177ffff,
901 },
902
903 .tcl_ring_retry = true,
904 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
905 .smp2p_wow_exit = false,
906 .support_fw_mac_sequence = true,
907 .support_dual_stations = true,
908 .pdev_suspend = false,
909 },
910 };
911
912 static const struct dmi_system_id ath11k_pm_quirk_table[] = {
913 {
914 .driver_data = (void *)ATH11K_PM_WOW,
915 .matches = {
916 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
917 DMI_MATCH(DMI_PRODUCT_NAME, "21J4"),
918 },
919 },
920 {
921 .driver_data = (void *)ATH11K_PM_WOW,
922 .matches = {
923 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
924 DMI_MATCH(DMI_PRODUCT_NAME, "21K4"),
925 },
926 },
927 {
928 .driver_data = (void *)ATH11K_PM_WOW,
929 .matches = {
930 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
931 DMI_MATCH(DMI_PRODUCT_NAME, "21K6"),
932 },
933 },
934 {
935 .driver_data = (void *)ATH11K_PM_WOW,
936 .matches = {
937 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
938 DMI_MATCH(DMI_PRODUCT_NAME, "21K8"),
939 },
940 },
941 {
942 .driver_data = (void *)ATH11K_PM_WOW,
943 .matches = {
944 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
945 DMI_MATCH(DMI_PRODUCT_NAME, "21KA"),
946 },
947 },
948 {
949 .driver_data = (void *)ATH11K_PM_WOW,
950 .matches = {
951 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
952 DMI_MATCH(DMI_PRODUCT_NAME, "21F9"),
953 },
954 },
955 {}
956 };
957
ath11k_fw_stats_pdevs_free(struct list_head * head)958 void ath11k_fw_stats_pdevs_free(struct list_head *head)
959 {
960 struct ath11k_fw_stats_pdev *i, *tmp;
961
962 list_for_each_entry_safe(i, tmp, head, list) {
963 list_del(&i->list);
964 kfree(i);
965 }
966 }
967
ath11k_fw_stats_vdevs_free(struct list_head * head)968 void ath11k_fw_stats_vdevs_free(struct list_head *head)
969 {
970 struct ath11k_fw_stats_vdev *i, *tmp;
971
972 list_for_each_entry_safe(i, tmp, head, list) {
973 list_del(&i->list);
974 kfree(i);
975 }
976 }
977
ath11k_fw_stats_bcn_free(struct list_head * head)978 void ath11k_fw_stats_bcn_free(struct list_head *head)
979 {
980 struct ath11k_fw_stats_bcn *i, *tmp;
981
982 list_for_each_entry_safe(i, tmp, head, list) {
983 list_del(&i->list);
984 kfree(i);
985 }
986 }
987
ath11k_fw_stats_init(struct ath11k * ar)988 void ath11k_fw_stats_init(struct ath11k *ar)
989 {
990 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
991 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
992 INIT_LIST_HEAD(&ar->fw_stats.bcn);
993
994 init_completion(&ar->fw_stats_complete);
995 init_completion(&ar->fw_stats_done);
996 }
997
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)998 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
999 {
1000 ath11k_fw_stats_pdevs_free(&stats->pdevs);
1001 ath11k_fw_stats_vdevs_free(&stats->vdevs);
1002 ath11k_fw_stats_bcn_free(&stats->bcn);
1003 }
1004
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)1005 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
1006 {
1007 if (!ath11k_cold_boot_cal)
1008 return false;
1009
1010 if (ath11k_ftm_mode)
1011 return ab->hw_params.coldboot_cal_ftm;
1012
1013 else
1014 return ab->hw_params.coldboot_cal_mm;
1015 }
1016
1017 /* Check if we need to continue with suspend/resume operation.
1018 * Return:
1019 * a negative value: error happens and don't continue.
1020 * 0: no error but don't continue.
1021 * positive value: no error and do continue.
1022 */
ath11k_core_continue_suspend_resume(struct ath11k_base * ab)1023 static int ath11k_core_continue_suspend_resume(struct ath11k_base *ab)
1024 {
1025 struct ath11k *ar;
1026
1027 if (!ab->hw_params.supports_suspend)
1028 return -EOPNOTSUPP;
1029
1030 /* so far single_pdev_only chips have supports_suspend as true
1031 * so pass 0 as a dummy pdev_id here.
1032 */
1033 ar = ab->pdevs[0].ar;
1034 if (!ar || ar->state != ATH11K_STATE_OFF)
1035 return 0;
1036
1037 return 1;
1038 }
1039
ath11k_core_suspend_wow(struct ath11k_base * ab)1040 static int ath11k_core_suspend_wow(struct ath11k_base *ab)
1041 {
1042 int ret;
1043
1044 ret = ath11k_dp_rx_pktlog_stop(ab, true);
1045 if (ret) {
1046 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1047 ret);
1048 return ret;
1049 }
1050
1051 /* So far only single_pdev_only devices can reach here,
1052 * so it is valid to handle the first, and the only, pdev.
1053 */
1054 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar);
1055 if (ret) {
1056 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1057 return ret;
1058 }
1059
1060 ret = ath11k_wow_enable(ab);
1061 if (ret) {
1062 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
1063 return ret;
1064 }
1065
1066 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1067 if (ret) {
1068 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1069 ret);
1070 return ret;
1071 }
1072
1073 ath11k_ce_stop_shadow_timers(ab);
1074 ath11k_dp_stop_shadow_timers(ab);
1075
1076 ath11k_hif_irq_disable(ab);
1077 ath11k_hif_ce_irq_disable(ab);
1078
1079 ret = ath11k_hif_suspend(ab);
1080 if (ret) {
1081 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
1082 return ret;
1083 }
1084
1085 return 0;
1086 }
1087
ath11k_core_suspend_default(struct ath11k_base * ab)1088 static int ath11k_core_suspend_default(struct ath11k_base *ab)
1089 {
1090 int ret;
1091
1092 ret = ath11k_dp_rx_pktlog_stop(ab, true);
1093 if (ret) {
1094 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1095 ret);
1096 return ret;
1097 }
1098
1099 /* So far only single_pdev_only devices can reach here,
1100 * so it is valid to handle the first, and the only, pdev.
1101 */
1102 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar);
1103 if (ret) {
1104 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1105 return ret;
1106 }
1107
1108 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1109 if (ret) {
1110 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1111 ret);
1112 return ret;
1113 }
1114
1115 ath11k_ce_stop_shadow_timers(ab);
1116 ath11k_dp_stop_shadow_timers(ab);
1117
1118 /* PM framework skips suspend_late/resume_early callbacks
1119 * if other devices report errors in their suspend callbacks.
1120 * However ath11k_core_resume() would still be called because
1121 * here we return success thus kernel put us on dpm_suspended_list.
1122 * Since we won't go through a power down/up cycle, there is
1123 * no chance to call complete(&ab->restart_completed) in
1124 * ath11k_core_restart(), making ath11k_core_resume() timeout.
1125 * So call it here to avoid this issue. This also works in case
1126 * no error happens thus suspend_late/resume_early get called,
1127 * because it will be reinitialized in ath11k_core_resume_early().
1128 */
1129 complete(&ab->restart_completed);
1130
1131 return 0;
1132 }
1133
ath11k_core_suspend(struct ath11k_base * ab)1134 int ath11k_core_suspend(struct ath11k_base *ab)
1135 {
1136 int ret;
1137
1138 ret = ath11k_core_continue_suspend_resume(ab);
1139 if (ret <= 0)
1140 return ret;
1141
1142 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1143 return ath11k_core_suspend_wow(ab);
1144
1145 return ath11k_core_suspend_default(ab);
1146 }
1147 EXPORT_SYMBOL(ath11k_core_suspend);
1148
ath11k_core_suspend_late(struct ath11k_base * ab)1149 int ath11k_core_suspend_late(struct ath11k_base *ab)
1150 {
1151 int ret;
1152
1153 ret = ath11k_core_continue_suspend_resume(ab);
1154 if (ret <= 0)
1155 return ret;
1156
1157 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1158 return 0;
1159
1160 ath11k_hif_irq_disable(ab);
1161 ath11k_hif_ce_irq_disable(ab);
1162
1163 ath11k_hif_power_down(ab, true);
1164
1165 return 0;
1166 }
1167 EXPORT_SYMBOL(ath11k_core_suspend_late);
1168
ath11k_core_resume_early(struct ath11k_base * ab)1169 int ath11k_core_resume_early(struct ath11k_base *ab)
1170 {
1171 int ret;
1172
1173 ret = ath11k_core_continue_suspend_resume(ab);
1174 if (ret <= 0)
1175 return ret;
1176
1177 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1178 return 0;
1179
1180 reinit_completion(&ab->restart_completed);
1181 ret = ath11k_hif_power_up(ab);
1182 if (ret)
1183 ath11k_warn(ab, "failed to power up hif during resume: %d\n", ret);
1184
1185 return ret;
1186 }
1187 EXPORT_SYMBOL(ath11k_core_resume_early);
1188
ath11k_core_resume_default(struct ath11k_base * ab)1189 static int ath11k_core_resume_default(struct ath11k_base *ab)
1190 {
1191 struct ath11k *ar;
1192 long time_left;
1193 int ret;
1194
1195 time_left = wait_for_completion_timeout(&ab->restart_completed,
1196 ATH11K_RESET_TIMEOUT_HZ);
1197 if (time_left == 0) {
1198 ath11k_warn(ab, "timeout while waiting for restart complete");
1199 return -ETIMEDOUT;
1200 }
1201
1202 /* So far only single_pdev_only devices can reach here,
1203 * so it is valid to handle the first, and the only, pdev.
1204 */
1205 ar = ab->pdevs[0].ar;
1206 if (ab->hw_params.current_cc_support &&
1207 ar->alpha2[0] != 0 && ar->alpha2[1] != 0) {
1208 ret = ath11k_reg_set_cc(ar);
1209 if (ret) {
1210 ath11k_warn(ab, "failed to set country code during resume: %d\n",
1211 ret);
1212 return ret;
1213 }
1214 }
1215
1216 ret = ath11k_dp_rx_pktlog_start(ab);
1217 if (ret)
1218 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1219 ret);
1220
1221 return ret;
1222 }
1223
ath11k_core_resume_wow(struct ath11k_base * ab)1224 static int ath11k_core_resume_wow(struct ath11k_base *ab)
1225 {
1226 int ret;
1227
1228 ret = ath11k_hif_resume(ab);
1229 if (ret) {
1230 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
1231 return ret;
1232 }
1233
1234 ath11k_hif_ce_irq_enable(ab);
1235 ath11k_hif_irq_enable(ab);
1236
1237 ret = ath11k_dp_rx_pktlog_start(ab);
1238 if (ret) {
1239 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1240 ret);
1241 return ret;
1242 }
1243
1244 ret = ath11k_wow_wakeup(ab);
1245 if (ret) {
1246 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
1247 return ret;
1248 }
1249
1250 return 0;
1251 }
1252
ath11k_core_resume(struct ath11k_base * ab)1253 int ath11k_core_resume(struct ath11k_base *ab)
1254 {
1255 int ret;
1256
1257 ret = ath11k_core_continue_suspend_resume(ab);
1258 if (ret <= 0)
1259 return ret;
1260
1261 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1262 return ath11k_core_resume_wow(ab);
1263
1264 return ath11k_core_resume_default(ab);
1265 }
1266 EXPORT_SYMBOL(ath11k_core_resume);
1267
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)1268 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
1269 {
1270 struct ath11k_base *ab = data;
1271 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
1272 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
1273 ssize_t copied;
1274 size_t len;
1275 int i;
1276
1277 if (ab->qmi.target.bdf_ext[0] != '\0')
1278 return;
1279
1280 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
1281 return;
1282
1283 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
1284 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1285 "wrong smbios bdf ext type length (%d).\n",
1286 hdr->length);
1287 return;
1288 }
1289
1290 spin_lock_bh(&ab->base_lock);
1291
1292 switch (smbios->country_code_flag) {
1293 case ATH11K_SMBIOS_CC_ISO:
1294 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
1295 ab->new_alpha2[1] = smbios->cc_code & 0xff;
1296 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
1297 ab->new_alpha2[0], ab->new_alpha2[1]);
1298 break;
1299 case ATH11K_SMBIOS_CC_WW:
1300 ab->new_alpha2[0] = '0';
1301 ab->new_alpha2[1] = '0';
1302 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
1303 break;
1304 default:
1305 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
1306 smbios->country_code_flag);
1307 break;
1308 }
1309
1310 spin_unlock_bh(&ab->base_lock);
1311
1312 if (!smbios->bdf_enabled) {
1313 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
1314 return;
1315 }
1316
1317 /* Only one string exists (per spec) */
1318 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
1319 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1320 "bdf variant magic does not match.\n");
1321 return;
1322 }
1323
1324 len = min_t(size_t,
1325 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
1326 for (i = 0; i < len; i++) {
1327 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
1328 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1329 "bdf variant name contains non ascii chars.\n");
1330 return;
1331 }
1332 }
1333
1334 /* Copy extension name without magic prefix */
1335 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
1336 sizeof(ab->qmi.target.bdf_ext));
1337 if (copied < 0) {
1338 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1339 "bdf variant string is longer than the buffer can accommodate\n");
1340 return;
1341 }
1342
1343 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1344 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1345 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
1346 }
1347
ath11k_core_check_smbios(struct ath11k_base * ab)1348 int ath11k_core_check_smbios(struct ath11k_base *ab)
1349 {
1350 ab->qmi.target.bdf_ext[0] = '\0';
1351 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
1352
1353 if (ab->qmi.target.bdf_ext[0] == '\0')
1354 return -ENODATA;
1355
1356 return 0;
1357 }
1358
ath11k_core_check_dt(struct ath11k_base * ab)1359 int ath11k_core_check_dt(struct ath11k_base *ab)
1360 {
1361 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1362 const char *variant = NULL;
1363 struct device_node *node;
1364
1365 node = ab->dev->of_node;
1366 if (!node)
1367 return -ENOENT;
1368
1369 of_property_read_string(node, "qcom,calibration-variant",
1370 &variant);
1371 if (!variant)
1372 of_property_read_string(node, "qcom,ath11k-calibration-variant",
1373 &variant);
1374 if (!variant)
1375 return -ENODATA;
1376
1377 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1378 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1379 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1380 variant);
1381
1382 return 0;
1383 }
1384
1385 enum ath11k_bdf_name_type {
1386 ATH11K_BDF_NAME_FULL,
1387 ATH11K_BDF_NAME_BUS_NAME,
1388 ATH11K_BDF_NAME_CHIP_ID,
1389 };
1390
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,enum ath11k_bdf_name_type name_type)1391 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1392 size_t name_len, bool with_variant,
1393 enum ath11k_bdf_name_type name_type)
1394 {
1395 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1396 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = {};
1397
1398 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1399 scnprintf(variant, sizeof(variant), ",variant=%s",
1400 ab->qmi.target.bdf_ext);
1401
1402 switch (ab->id.bdf_search) {
1403 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1404 switch (name_type) {
1405 case ATH11K_BDF_NAME_FULL:
1406 scnprintf(name, name_len,
1407 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1408 ath11k_bus_str(ab->hif.bus),
1409 ab->id.vendor, ab->id.device,
1410 ab->id.subsystem_vendor,
1411 ab->id.subsystem_device,
1412 ab->qmi.target.chip_id,
1413 ab->qmi.target.board_id,
1414 variant);
1415 break;
1416 case ATH11K_BDF_NAME_BUS_NAME:
1417 scnprintf(name, name_len,
1418 "bus=%s",
1419 ath11k_bus_str(ab->hif.bus));
1420 break;
1421 case ATH11K_BDF_NAME_CHIP_ID:
1422 scnprintf(name, name_len,
1423 "bus=%s,qmi-chip-id=%d",
1424 ath11k_bus_str(ab->hif.bus),
1425 ab->qmi.target.chip_id);
1426 break;
1427 }
1428 break;
1429 default:
1430 scnprintf(name, name_len,
1431 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1432 ath11k_bus_str(ab->hif.bus),
1433 ab->qmi.target.chip_id,
1434 ab->qmi.target.board_id, variant);
1435 break;
1436 }
1437
1438 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1439
1440 return 0;
1441 }
1442
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1443 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1444 size_t name_len)
1445 {
1446 return __ath11k_core_create_board_name(ab, name, name_len, true,
1447 ATH11K_BDF_NAME_FULL);
1448 }
1449
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1450 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1451 size_t name_len)
1452 {
1453 return __ath11k_core_create_board_name(ab, name, name_len, false,
1454 ATH11K_BDF_NAME_FULL);
1455 }
1456
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1457 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1458 size_t name_len)
1459 {
1460 return __ath11k_core_create_board_name(ab, name, name_len, false,
1461 ATH11K_BDF_NAME_BUS_NAME);
1462 }
1463
ath11k_core_create_chip_id_board_name(struct ath11k_base * ab,char * name,size_t name_len)1464 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name,
1465 size_t name_len)
1466 {
1467 return __ath11k_core_create_board_name(ab, name, name_len, false,
1468 ATH11K_BDF_NAME_CHIP_ID);
1469 }
1470
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1471 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1472 const char *file)
1473 {
1474 const struct firmware *fw;
1475 char path[100];
1476 int ret;
1477
1478 if (file == NULL)
1479 return ERR_PTR(-ENOENT);
1480
1481 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1482
1483 ret = firmware_request_nowarn(&fw, path, ab->dev);
1484 if (ret)
1485 return ERR_PTR(ret);
1486
1487 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1488 path, fw->size);
1489
1490 return fw;
1491 }
1492
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1493 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1494 {
1495 if (!IS_ERR(bd->fw))
1496 release_firmware(bd->fw);
1497
1498 memset(bd, 0, sizeof(*bd));
1499 }
1500
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1501 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1502 struct ath11k_board_data *bd,
1503 const void *buf, size_t buf_len,
1504 const char *boardname,
1505 int ie_id,
1506 int name_id,
1507 int data_id)
1508 {
1509 const struct ath11k_fw_ie *hdr;
1510 bool name_match_found;
1511 int ret, board_ie_id;
1512 size_t board_ie_len;
1513 const void *board_ie_data;
1514
1515 name_match_found = false;
1516
1517 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1518 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1519 hdr = buf;
1520 board_ie_id = le32_to_cpu(hdr->id);
1521 board_ie_len = le32_to_cpu(hdr->len);
1522 board_ie_data = hdr->data;
1523
1524 buf_len -= sizeof(*hdr);
1525 buf += sizeof(*hdr);
1526
1527 if (buf_len < ALIGN(board_ie_len, 4)) {
1528 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1529 ath11k_bd_ie_type_str(ie_id),
1530 buf_len, ALIGN(board_ie_len, 4));
1531 ret = -EINVAL;
1532 goto out;
1533 }
1534
1535 if (board_ie_id == name_id) {
1536 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1537 board_ie_data, board_ie_len);
1538
1539 if (board_ie_len != strlen(boardname))
1540 goto next;
1541
1542 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1543 if (ret)
1544 goto next;
1545
1546 name_match_found = true;
1547 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1548 "found match %s for name '%s'",
1549 ath11k_bd_ie_type_str(ie_id),
1550 boardname);
1551 } else if (board_ie_id == data_id) {
1552 if (!name_match_found)
1553 /* no match found */
1554 goto next;
1555
1556 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1557 "found %s for '%s'",
1558 ath11k_bd_ie_type_str(ie_id),
1559 boardname);
1560
1561 bd->data = board_ie_data;
1562 bd->len = board_ie_len;
1563
1564 ret = 0;
1565 goto out;
1566 } else {
1567 ath11k_warn(ab, "unknown %s id found: %d\n",
1568 ath11k_bd_ie_type_str(ie_id),
1569 board_ie_id);
1570 }
1571 next:
1572 /* jump over the padding */
1573 board_ie_len = ALIGN(board_ie_len, 4);
1574
1575 buf_len -= board_ie_len;
1576 buf += board_ie_len;
1577 }
1578
1579 /* no match found */
1580 ret = -ENOENT;
1581
1582 out:
1583 return ret;
1584 }
1585
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1586 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1587 struct ath11k_board_data *bd,
1588 const char *boardname,
1589 int ie_id_match,
1590 int name_id,
1591 int data_id)
1592 {
1593 size_t len, magic_len;
1594 const u8 *data;
1595 char *filename, filepath[100];
1596 size_t ie_len;
1597 struct ath11k_fw_ie *hdr;
1598 int ret, ie_id;
1599
1600 filename = ATH11K_BOARD_API2_FILE;
1601
1602 if (!bd->fw)
1603 bd->fw = ath11k_core_firmware_request(ab, filename);
1604
1605 if (IS_ERR(bd->fw))
1606 return PTR_ERR(bd->fw);
1607
1608 data = bd->fw->data;
1609 len = bd->fw->size;
1610
1611 ath11k_core_create_firmware_path(ab, filename,
1612 filepath, sizeof(filepath));
1613
1614 /* magic has extra null byte padded */
1615 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1616 if (len < magic_len) {
1617 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1618 filepath, len);
1619 ret = -EINVAL;
1620 goto err;
1621 }
1622
1623 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1624 ath11k_err(ab, "found invalid board magic\n");
1625 ret = -EINVAL;
1626 goto err;
1627 }
1628
1629 /* magic is padded to 4 bytes */
1630 magic_len = ALIGN(magic_len, 4);
1631 if (len < magic_len) {
1632 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1633 filepath, len);
1634 ret = -EINVAL;
1635 goto err;
1636 }
1637
1638 data += magic_len;
1639 len -= magic_len;
1640
1641 while (len > sizeof(struct ath11k_fw_ie)) {
1642 hdr = (struct ath11k_fw_ie *)data;
1643 ie_id = le32_to_cpu(hdr->id);
1644 ie_len = le32_to_cpu(hdr->len);
1645
1646 len -= sizeof(*hdr);
1647 data = hdr->data;
1648
1649 if (len < ALIGN(ie_len, 4)) {
1650 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1651 ie_id, ie_len, len);
1652 ret = -EINVAL;
1653 goto err;
1654 }
1655
1656 if (ie_id == ie_id_match) {
1657 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1658 ie_len,
1659 boardname,
1660 ie_id_match,
1661 name_id,
1662 data_id);
1663 if (ret == -ENOENT)
1664 /* no match found, continue */
1665 goto next;
1666 else if (ret)
1667 /* there was an error, bail out */
1668 goto err;
1669 /* either found or error, so stop searching */
1670 goto out;
1671 }
1672 next:
1673 /* jump over the padding */
1674 ie_len = ALIGN(ie_len, 4);
1675
1676 len -= ie_len;
1677 data += ie_len;
1678 }
1679
1680 out:
1681 if (!bd->data || !bd->len) {
1682 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1683 "failed to fetch %s for %s from %s\n",
1684 ath11k_bd_ie_type_str(ie_id_match),
1685 boardname, filepath);
1686 ret = -ENODATA;
1687 goto err;
1688 }
1689
1690 return 0;
1691
1692 err:
1693 ath11k_core_free_bdf(ab, bd);
1694 return ret;
1695 }
1696
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1697 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1698 struct ath11k_board_data *bd,
1699 const char *name)
1700 {
1701 bd->fw = ath11k_core_firmware_request(ab, name);
1702
1703 if (IS_ERR(bd->fw))
1704 return PTR_ERR(bd->fw);
1705
1706 bd->data = bd->fw->data;
1707 bd->len = bd->fw->size;
1708
1709 return 0;
1710 }
1711
1712 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1713 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1714 {
1715 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL;
1716 char *filename, filepath[100];
1717 int bd_api;
1718 int ret = 0;
1719
1720 filename = ATH11K_BOARD_API2_FILE;
1721 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1722 if (!boardname) {
1723 ret = -ENOMEM;
1724 goto exit;
1725 }
1726
1727 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1728 if (ret) {
1729 ath11k_err(ab, "failed to create board name: %d", ret);
1730 goto exit;
1731 }
1732
1733 bd_api = 2;
1734 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1735 ATH11K_BD_IE_BOARD,
1736 ATH11K_BD_IE_BOARD_NAME,
1737 ATH11K_BD_IE_BOARD_DATA);
1738 if (!ret)
1739 goto exit;
1740
1741 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1742 if (!fallback_boardname) {
1743 ret = -ENOMEM;
1744 goto exit;
1745 }
1746
1747 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1748 BOARD_NAME_SIZE);
1749 if (ret) {
1750 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1751 goto exit;
1752 }
1753
1754 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1755 ATH11K_BD_IE_BOARD,
1756 ATH11K_BD_IE_BOARD_NAME,
1757 ATH11K_BD_IE_BOARD_DATA);
1758 if (!ret)
1759 goto exit;
1760
1761 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1762 if (!chip_id_boardname) {
1763 ret = -ENOMEM;
1764 goto exit;
1765 }
1766
1767 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname,
1768 BOARD_NAME_SIZE);
1769 if (ret) {
1770 ath11k_err(ab, "failed to create chip id board name: %d", ret);
1771 goto exit;
1772 }
1773
1774 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname,
1775 ATH11K_BD_IE_BOARD,
1776 ATH11K_BD_IE_BOARD_NAME,
1777 ATH11K_BD_IE_BOARD_DATA);
1778
1779 if (!ret)
1780 goto exit;
1781
1782 bd_api = 1;
1783 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1784 if (ret) {
1785 ath11k_core_create_firmware_path(ab, filename,
1786 filepath, sizeof(filepath));
1787 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1788 boardname, filepath);
1789 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1790 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1791 fallback_boardname, filepath);
1792
1793 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1794 chip_id_boardname, filepath);
1795
1796 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1797 ab->hw_params.fw.dir);
1798 }
1799
1800 exit:
1801 kfree(boardname);
1802 kfree(fallback_boardname);
1803 kfree(chip_id_boardname);
1804
1805 if (!ret)
1806 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api);
1807
1808 return ret;
1809 }
1810
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1811 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1812 {
1813 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1814 int ret;
1815
1816 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1817 if (ret) {
1818 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1819 "failed to create board name for regdb: %d", ret);
1820 goto exit;
1821 }
1822
1823 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1824 ATH11K_BD_IE_REGDB,
1825 ATH11K_BD_IE_REGDB_NAME,
1826 ATH11K_BD_IE_REGDB_DATA);
1827 if (!ret)
1828 goto exit;
1829
1830 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1831 BOARD_NAME_SIZE);
1832 if (ret) {
1833 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1834 "failed to create default board name for regdb: %d", ret);
1835 goto exit;
1836 }
1837
1838 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1839 ATH11K_BD_IE_REGDB,
1840 ATH11K_BD_IE_REGDB_NAME,
1841 ATH11K_BD_IE_REGDB_DATA);
1842 if (!ret)
1843 goto exit;
1844
1845 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1846 if (ret)
1847 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1848 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1849
1850 exit:
1851 if (!ret)
1852 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1853
1854 return ret;
1855 }
1856
ath11k_core_stop(struct ath11k_base * ab)1857 static void ath11k_core_stop(struct ath11k_base *ab)
1858 {
1859 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1860 ath11k_qmi_firmware_stop(ab);
1861
1862 ath11k_hif_stop(ab);
1863 ath11k_wmi_detach(ab);
1864 ath11k_dp_pdev_reo_cleanup(ab);
1865
1866 /* De-Init of components as needed */
1867 }
1868
ath11k_core_soc_create(struct ath11k_base * ab)1869 static int ath11k_core_soc_create(struct ath11k_base *ab)
1870 {
1871 int ret;
1872
1873 if (ath11k_ftm_mode) {
1874 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1875 ath11k_info(ab, "Booting in factory test mode\n");
1876 }
1877
1878 ret = ath11k_qmi_init_service(ab);
1879 if (ret) {
1880 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1881 return ret;
1882 }
1883
1884 ret = ath11k_debugfs_soc_create(ab);
1885 if (ret) {
1886 ath11k_err(ab, "failed to create ath11k debugfs\n");
1887 goto err_qmi_deinit;
1888 }
1889
1890 ret = ath11k_hif_power_up(ab);
1891 if (ret) {
1892 ath11k_err(ab, "failed to power up :%d\n", ret);
1893 goto err_debugfs_reg;
1894 }
1895
1896 return 0;
1897
1898 err_debugfs_reg:
1899 ath11k_debugfs_soc_destroy(ab);
1900 err_qmi_deinit:
1901 ath11k_qmi_deinit_service(ab);
1902 return ret;
1903 }
1904
ath11k_core_soc_destroy(struct ath11k_base * ab)1905 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1906 {
1907 ath11k_debugfs_soc_destroy(ab);
1908 ath11k_dp_free(ab);
1909 ath11k_reg_free(ab);
1910 ath11k_qmi_deinit_service(ab);
1911 }
1912
ath11k_core_pdev_create(struct ath11k_base * ab)1913 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1914 {
1915 int ret;
1916
1917 ret = ath11k_debugfs_pdev_create(ab);
1918 if (ret) {
1919 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1920 return ret;
1921 }
1922
1923 ret = ath11k_dp_pdev_alloc(ab);
1924 if (ret) {
1925 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1926 goto err_pdev_debug;
1927 }
1928
1929 ret = ath11k_mac_register(ab);
1930 if (ret) {
1931 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1932 goto err_dp_pdev_free;
1933 }
1934
1935 ret = ath11k_thermal_register(ab);
1936 if (ret) {
1937 ath11k_err(ab, "could not register thermal device: %d\n",
1938 ret);
1939 goto err_mac_unregister;
1940 }
1941
1942 ret = ath11k_spectral_init(ab);
1943 if (ret) {
1944 ath11k_err(ab, "failed to init spectral %d\n", ret);
1945 goto err_thermal_unregister;
1946 }
1947
1948 return 0;
1949
1950 err_thermal_unregister:
1951 ath11k_thermal_unregister(ab);
1952 err_mac_unregister:
1953 ath11k_mac_unregister(ab);
1954 err_dp_pdev_free:
1955 ath11k_dp_pdev_free(ab);
1956 err_pdev_debug:
1957 ath11k_debugfs_pdev_destroy(ab);
1958
1959 return ret;
1960 }
1961
ath11k_core_pdev_suspend_target(struct ath11k_base * ab)1962 static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab)
1963 {
1964 struct ath11k *ar;
1965 struct ath11k_pdev *pdev;
1966 unsigned long time_left;
1967 int ret;
1968 int i;
1969
1970 if (!ab->hw_params.pdev_suspend)
1971 return;
1972
1973 for (i = 0; i < ab->num_radios; i++) {
1974 pdev = &ab->pdevs[i];
1975 ar = pdev->ar;
1976
1977 reinit_completion(&ab->htc_suspend);
1978
1979 ret = ath11k_wmi_pdev_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
1980 pdev->pdev_id);
1981 if (ret) {
1982 ath11k_warn(ab, "could not suspend target :%d\n", ret);
1983 /* pointless to try other pdevs */
1984 return;
1985 }
1986
1987 time_left = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ);
1988
1989 if (!time_left) {
1990 ath11k_warn(ab, "suspend timed out - target pause event never came\n");
1991 /* pointless to try other pdevs */
1992 return;
1993 }
1994 }
1995 }
1996
ath11k_core_pdev_destroy(struct ath11k_base * ab)1997 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1998 {
1999 ath11k_spectral_deinit(ab);
2000 ath11k_thermal_unregister(ab);
2001 ath11k_mac_unregister(ab);
2002 ath11k_core_pdev_suspend_target(ab);
2003 ath11k_hif_irq_disable(ab);
2004 ath11k_dp_pdev_free(ab);
2005 ath11k_debugfs_pdev_destroy(ab);
2006 }
2007
ath11k_core_start(struct ath11k_base * ab)2008 static int ath11k_core_start(struct ath11k_base *ab)
2009 {
2010 int ret;
2011
2012 ret = ath11k_wmi_attach(ab);
2013 if (ret) {
2014 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
2015 return ret;
2016 }
2017
2018 ret = ath11k_htc_init(ab);
2019 if (ret) {
2020 ath11k_err(ab, "failed to init htc: %d\n", ret);
2021 goto err_wmi_detach;
2022 }
2023
2024 ret = ath11k_hif_start(ab);
2025 if (ret) {
2026 ath11k_err(ab, "failed to start HIF: %d\n", ret);
2027 goto err_wmi_detach;
2028 }
2029
2030 ret = ath11k_htc_wait_target(&ab->htc);
2031 if (ret) {
2032 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
2033 goto err_hif_stop;
2034 }
2035
2036 ret = ath11k_dp_htt_connect(&ab->dp);
2037 if (ret) {
2038 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
2039 goto err_hif_stop;
2040 }
2041
2042 ret = ath11k_wmi_connect(ab);
2043 if (ret) {
2044 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
2045 goto err_hif_stop;
2046 }
2047
2048 ret = ath11k_htc_start(&ab->htc);
2049 if (ret) {
2050 ath11k_err(ab, "failed to start HTC: %d\n", ret);
2051 goto err_hif_stop;
2052 }
2053
2054 ret = ath11k_wmi_wait_for_service_ready(ab);
2055 if (ret) {
2056 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
2057 ret);
2058 goto err_hif_stop;
2059 }
2060
2061 ret = ath11k_mac_allocate(ab);
2062 if (ret) {
2063 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
2064 ret);
2065 goto err_hif_stop;
2066 }
2067
2068 ath11k_dp_pdev_pre_alloc(ab);
2069
2070 ret = ath11k_dp_pdev_reo_setup(ab);
2071 if (ret) {
2072 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
2073 goto err_mac_destroy;
2074 }
2075
2076 ret = ath11k_wmi_cmd_init(ab);
2077 if (ret) {
2078 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
2079 goto err_reo_cleanup;
2080 }
2081
2082 ret = ath11k_wmi_wait_for_unified_ready(ab);
2083 if (ret) {
2084 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
2085 ret);
2086 goto err_reo_cleanup;
2087 }
2088
2089 /* put hardware to DBS mode */
2090 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) {
2091 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
2092 if (ret) {
2093 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
2094 goto err_hif_stop;
2095 }
2096 }
2097
2098 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
2099 if (ret) {
2100 ath11k_err(ab, "failed to send htt version request message: %d\n",
2101 ret);
2102 goto err_reo_cleanup;
2103 }
2104
2105 return 0;
2106
2107 err_reo_cleanup:
2108 ath11k_dp_pdev_reo_cleanup(ab);
2109 err_mac_destroy:
2110 ath11k_mac_destroy(ab);
2111 err_hif_stop:
2112 ath11k_hif_stop(ab);
2113 err_wmi_detach:
2114 ath11k_wmi_detach(ab);
2115
2116 return ret;
2117 }
2118
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)2119 static int ath11k_core_start_firmware(struct ath11k_base *ab,
2120 enum ath11k_firmware_mode mode)
2121 {
2122 int ret;
2123
2124 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
2125 &ab->qmi.ce_cfg.shadow_reg_v2_len);
2126
2127 ret = ath11k_qmi_firmware_start(ab, mode);
2128 if (ret) {
2129 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
2130 return ret;
2131 }
2132
2133 return ret;
2134 }
2135
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)2136 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
2137 {
2138 int ret;
2139
2140 switch (ath11k_crypto_mode) {
2141 case ATH11K_CRYPT_MODE_SW:
2142 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
2143 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2144 break;
2145 case ATH11K_CRYPT_MODE_HW:
2146 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
2147 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2148 break;
2149 default:
2150 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
2151 return -EINVAL;
2152 }
2153
2154 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
2155 if (ret) {
2156 ath11k_err(ab, "failed to start firmware: %d\n", ret);
2157 return ret;
2158 }
2159
2160 ret = ath11k_ce_init_pipes(ab);
2161 if (ret) {
2162 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
2163 goto err_firmware_stop;
2164 }
2165
2166 ret = ath11k_dp_alloc(ab);
2167 if (ret) {
2168 ath11k_err(ab, "failed to init DP: %d\n", ret);
2169 goto err_firmware_stop;
2170 }
2171
2172 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
2173 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2174
2175 mutex_lock(&ab->core_lock);
2176 ret = ath11k_core_start(ab);
2177 if (ret) {
2178 ath11k_err(ab, "failed to start core: %d\n", ret);
2179 goto err_dp_free;
2180 }
2181
2182 ret = ath11k_core_pdev_create(ab);
2183 if (ret) {
2184 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
2185 goto err_core_stop;
2186 }
2187 ath11k_hif_irq_enable(ab);
2188 mutex_unlock(&ab->core_lock);
2189
2190 return 0;
2191
2192 err_core_stop:
2193 ath11k_core_stop(ab);
2194 ath11k_mac_destroy(ab);
2195 err_dp_free:
2196 ath11k_dp_free(ab);
2197 mutex_unlock(&ab->core_lock);
2198 err_firmware_stop:
2199 ath11k_qmi_firmware_stop(ab);
2200
2201 return ret;
2202 }
2203
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)2204 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
2205 {
2206 int ret;
2207
2208 mutex_lock(&ab->core_lock);
2209 ath11k_thermal_unregister(ab);
2210 ath11k_dp_pdev_free(ab);
2211 ath11k_spectral_deinit(ab);
2212 ath11k_ce_cleanup_pipes(ab);
2213 ath11k_wmi_detach(ab);
2214 ath11k_dp_pdev_reo_cleanup(ab);
2215 mutex_unlock(&ab->core_lock);
2216
2217 ath11k_dp_free(ab);
2218 ath11k_hal_srng_deinit(ab);
2219
2220 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
2221
2222 ret = ath11k_hal_srng_init(ab);
2223 if (ret)
2224 return ret;
2225
2226 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
2227
2228 ret = ath11k_core_qmi_firmware_ready(ab);
2229 if (ret)
2230 goto err_hal_srng_deinit;
2231
2232 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
2233
2234 return 0;
2235
2236 err_hal_srng_deinit:
2237 ath11k_hal_srng_deinit(ab);
2238 return ret;
2239 }
2240
ath11k_core_halt(struct ath11k * ar)2241 void ath11k_core_halt(struct ath11k *ar)
2242 {
2243 struct ath11k_base *ab = ar->ab;
2244 struct list_head *pos, *n;
2245
2246 lockdep_assert_held(&ar->conf_mutex);
2247
2248 ar->num_created_vdevs = 0;
2249 ar->allocated_vdev_map = 0;
2250
2251 ath11k_mac_scan_finish(ar);
2252 ath11k_mac_peer_cleanup_all(ar);
2253 cancel_delayed_work_sync(&ar->scan.timeout);
2254 cancel_work_sync(&ar->channel_update_work);
2255 cancel_work_sync(&ar->regd_update_work);
2256 cancel_work_sync(&ab->update_11d_work);
2257
2258 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
2259 synchronize_rcu();
2260
2261 spin_lock_bh(&ar->data_lock);
2262 list_for_each_safe(pos, n, &ar->arvifs)
2263 list_del_init(pos);
2264 spin_unlock_bh(&ar->data_lock);
2265
2266 idr_init(&ar->txmgmt_idr);
2267 }
2268
ath11k_update_11d(struct work_struct * work)2269 static void ath11k_update_11d(struct work_struct *work)
2270 {
2271 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
2272 struct ath11k *ar;
2273 struct ath11k_pdev *pdev;
2274 int ret, i;
2275
2276 for (i = 0; i < ab->num_radios; i++) {
2277 pdev = &ab->pdevs[i];
2278 ar = pdev->ar;
2279
2280 spin_lock_bh(&ab->base_lock);
2281 memcpy(&ar->alpha2, &ab->new_alpha2, 2);
2282 spin_unlock_bh(&ab->base_lock);
2283
2284 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n",
2285 ar->alpha2[0], ar->alpha2[1], i);
2286
2287 ret = ath11k_reg_set_cc(ar);
2288 if (ret)
2289 ath11k_warn(ar->ab,
2290 "pdev id %d failed set current country code: %d\n",
2291 i, ret);
2292 }
2293 }
2294
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)2295 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
2296 {
2297 struct ath11k *ar;
2298 struct ath11k_pdev *pdev;
2299 int i;
2300
2301 spin_lock_bh(&ab->base_lock);
2302 ab->stats.fw_crash_counter++;
2303 spin_unlock_bh(&ab->base_lock);
2304
2305 for (i = 0; i < ab->num_radios; i++) {
2306 pdev = &ab->pdevs[i];
2307 ar = pdev->ar;
2308 if (!ar || ar->state == ATH11K_STATE_OFF ||
2309 ar->state == ATH11K_STATE_FTM)
2310 continue;
2311
2312 ieee80211_stop_queues(ar->hw);
2313 ath11k_mac_drain_tx(ar);
2314 ar->state_11d = ATH11K_11D_IDLE;
2315 complete(&ar->completed_11d_scan);
2316 complete(&ar->scan.started);
2317 complete_all(&ar->scan.completed);
2318 complete(&ar->scan.on_channel);
2319 complete(&ar->peer_assoc_done);
2320 complete(&ar->peer_delete_done);
2321 complete(&ar->install_key_done);
2322 complete(&ar->vdev_setup_done);
2323 complete(&ar->vdev_delete_done);
2324 complete(&ar->bss_survey_done);
2325 complete(&ar->thermal.wmi_sync);
2326
2327 wake_up(&ar->dp.tx_empty_waitq);
2328 idr_for_each(&ar->txmgmt_idr,
2329 ath11k_mac_tx_mgmt_pending_free, ar);
2330 idr_destroy(&ar->txmgmt_idr);
2331 wake_up(&ar->txmgmt_empty_waitq);
2332
2333 ar->monitor_vdev_id = -1;
2334 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
2335 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
2336 }
2337
2338 wake_up(&ab->wmi_ab.tx_credits_wq);
2339 wake_up(&ab->peer_mapping_wq);
2340
2341 reinit_completion(&ab->driver_recovery);
2342 }
2343
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)2344 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
2345 {
2346 struct ath11k *ar;
2347 struct ath11k_pdev *pdev;
2348 int i;
2349
2350 for (i = 0; i < ab->num_radios; i++) {
2351 pdev = &ab->pdevs[i];
2352 ar = pdev->ar;
2353 if (!ar || ar->state == ATH11K_STATE_OFF)
2354 continue;
2355
2356 mutex_lock(&ar->conf_mutex);
2357
2358 switch (ar->state) {
2359 case ATH11K_STATE_ON:
2360 ar->state = ATH11K_STATE_RESTARTING;
2361 ath11k_core_halt(ar);
2362 ieee80211_restart_hw(ar->hw);
2363 break;
2364 case ATH11K_STATE_OFF:
2365 ath11k_warn(ab,
2366 "cannot restart radio %d that hasn't been started\n",
2367 i);
2368 break;
2369 case ATH11K_STATE_RESTARTING:
2370 break;
2371 case ATH11K_STATE_RESTARTED:
2372 ar->state = ATH11K_STATE_WEDGED;
2373 fallthrough;
2374 case ATH11K_STATE_WEDGED:
2375 ath11k_warn(ab,
2376 "device is wedged, will not restart radio %d\n", i);
2377 break;
2378 case ATH11K_STATE_FTM:
2379 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
2380 "fw mode reset done radio %d\n", i);
2381 break;
2382 }
2383
2384 mutex_unlock(&ar->conf_mutex);
2385 }
2386 complete(&ab->driver_recovery);
2387 }
2388
ath11k_core_restart(struct work_struct * work)2389 static void ath11k_core_restart(struct work_struct *work)
2390 {
2391 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
2392 int ret;
2393
2394 ret = ath11k_core_reconfigure_on_crash(ab);
2395 if (ret) {
2396 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
2397 return;
2398 }
2399
2400 if (ab->is_reset)
2401 complete_all(&ab->reconfigure_complete);
2402
2403 if (!ab->is_reset)
2404 ath11k_core_post_reconfigure_recovery(ab);
2405
2406 complete(&ab->restart_completed);
2407 }
2408
ath11k_core_reset(struct work_struct * work)2409 static void ath11k_core_reset(struct work_struct *work)
2410 {
2411 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
2412 int reset_count, fail_cont_count;
2413 long time_left;
2414
2415 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
2416 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
2417 return;
2418 }
2419
2420 /* Sometimes the recovery will fail and then the next all recovery fail,
2421 * this is to avoid infinite recovery since it can not recovery success.
2422 */
2423 fail_cont_count = atomic_read(&ab->fail_cont_count);
2424
2425 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
2426 return;
2427
2428 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
2429 time_before(jiffies, ab->reset_fail_timeout))
2430 return;
2431
2432 reset_count = atomic_inc_return(&ab->reset_count);
2433
2434 if (reset_count > 1) {
2435 /* Sometimes it happened another reset worker before the previous one
2436 * completed, then the second reset worker will destroy the previous one,
2437 * thus below is to avoid that.
2438 */
2439 ath11k_warn(ab, "already resetting count %d\n", reset_count);
2440
2441 reinit_completion(&ab->reset_complete);
2442 time_left = wait_for_completion_timeout(&ab->reset_complete,
2443 ATH11K_RESET_TIMEOUT_HZ);
2444
2445 if (time_left) {
2446 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
2447 atomic_dec(&ab->reset_count);
2448 return;
2449 }
2450
2451 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2452 /* Record the continuous recovery fail count when recovery failed*/
2453 atomic_inc(&ab->fail_cont_count);
2454 }
2455
2456 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2457
2458 ab->is_reset = true;
2459 atomic_set(&ab->recovery_count, 0);
2460 reinit_completion(&ab->recovery_start);
2461 atomic_set(&ab->recovery_start_count, 0);
2462
2463 ath11k_coredump_collect(ab);
2464 ath11k_core_pre_reconfigure_recovery(ab);
2465
2466 reinit_completion(&ab->reconfigure_complete);
2467 ath11k_core_post_reconfigure_recovery(ab);
2468
2469 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2470
2471 time_left = wait_for_completion_timeout(&ab->recovery_start,
2472 ATH11K_RECOVER_START_TIMEOUT_HZ);
2473
2474 ath11k_hif_irq_disable(ab);
2475 ath11k_hif_ce_irq_disable(ab);
2476
2477 ath11k_hif_power_down(ab, false);
2478 ath11k_hif_power_up(ab);
2479
2480 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2481 }
2482
ath11k_init_hw_params(struct ath11k_base * ab)2483 static int ath11k_init_hw_params(struct ath11k_base *ab)
2484 {
2485 const struct ath11k_hw_params *hw_params = NULL;
2486 int i;
2487
2488 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2489 hw_params = &ath11k_hw_params[i];
2490
2491 if (hw_params->hw_rev == ab->hw_rev)
2492 break;
2493 }
2494
2495 if (i == ARRAY_SIZE(ath11k_hw_params)) {
2496 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2497 return -EINVAL;
2498 }
2499
2500 ab->hw_params = *hw_params;
2501
2502 ath11k_info(ab, "%s\n", ab->hw_params.name);
2503
2504 return 0;
2505 }
2506
ath11k_core_pre_init(struct ath11k_base * ab)2507 int ath11k_core_pre_init(struct ath11k_base *ab)
2508 {
2509 int ret;
2510
2511 ret = ath11k_init_hw_params(ab);
2512 if (ret) {
2513 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2514 return ret;
2515 }
2516
2517 ret = ath11k_fw_pre_init(ab);
2518 if (ret) {
2519 ath11k_err(ab, "failed to pre init firmware: %d", ret);
2520 return ret;
2521 }
2522
2523 return 0;
2524 }
2525 EXPORT_SYMBOL(ath11k_core_pre_init);
2526
ath11k_core_pm_notify(struct notifier_block * nb,unsigned long action,void * nouse)2527 static int ath11k_core_pm_notify(struct notifier_block *nb,
2528 unsigned long action, void *nouse)
2529 {
2530 struct ath11k_base *ab = container_of(nb, struct ath11k_base,
2531 pm_nb);
2532
2533 switch (action) {
2534 case PM_SUSPEND_PREPARE:
2535 ab->actual_pm_policy = ab->pm_policy;
2536 break;
2537 case PM_HIBERNATION_PREPARE:
2538 ab->actual_pm_policy = ATH11K_PM_DEFAULT;
2539 break;
2540 default:
2541 break;
2542 }
2543
2544 return NOTIFY_OK;
2545 }
2546
ath11k_core_pm_notifier_register(struct ath11k_base * ab)2547 static int ath11k_core_pm_notifier_register(struct ath11k_base *ab)
2548 {
2549 ab->pm_nb.notifier_call = ath11k_core_pm_notify;
2550 return register_pm_notifier(&ab->pm_nb);
2551 }
2552
ath11k_core_pm_notifier_unregister(struct ath11k_base * ab)2553 void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab)
2554 {
2555 int ret;
2556
2557 ret = unregister_pm_notifier(&ab->pm_nb);
2558 if (ret)
2559 /* just warn here, there is nothing can be done in fail case */
2560 ath11k_warn(ab, "failed to unregister PM notifier %d\n", ret);
2561 }
2562 EXPORT_SYMBOL(ath11k_core_pm_notifier_unregister);
2563
ath11k_core_init(struct ath11k_base * ab)2564 int ath11k_core_init(struct ath11k_base *ab)
2565 {
2566 const struct dmi_system_id *dmi_id;
2567 int ret;
2568
2569 dmi_id = dmi_first_match(ath11k_pm_quirk_table);
2570 if (dmi_id)
2571 ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data;
2572 else
2573 ab->pm_policy = ATH11K_PM_DEFAULT;
2574
2575 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy);
2576
2577 ret = ath11k_core_pm_notifier_register(ab);
2578 if (ret) {
2579 ath11k_err(ab, "failed to register PM notifier: %d\n", ret);
2580 return ret;
2581 }
2582
2583 ret = ath11k_core_soc_create(ab);
2584 if (ret) {
2585 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2586 goto err_unregister_pm_notifier;
2587 }
2588
2589 return 0;
2590
2591 err_unregister_pm_notifier:
2592 ath11k_core_pm_notifier_unregister(ab);
2593
2594 return ret;
2595 }
2596 EXPORT_SYMBOL(ath11k_core_init);
2597
ath11k_core_deinit(struct ath11k_base * ab)2598 void ath11k_core_deinit(struct ath11k_base *ab)
2599 {
2600 mutex_lock(&ab->core_lock);
2601
2602 ath11k_core_pdev_destroy(ab);
2603 ath11k_core_stop(ab);
2604
2605 mutex_unlock(&ab->core_lock);
2606
2607 ath11k_hif_power_down(ab, false);
2608 ath11k_mac_destroy(ab);
2609 ath11k_core_soc_destroy(ab);
2610 ath11k_core_pm_notifier_unregister(ab);
2611 }
2612 EXPORT_SYMBOL(ath11k_core_deinit);
2613
ath11k_core_free(struct ath11k_base * ab)2614 void ath11k_core_free(struct ath11k_base *ab)
2615 {
2616 destroy_workqueue(ab->workqueue_aux);
2617 destroy_workqueue(ab->workqueue);
2618
2619 kfree(ab);
2620 }
2621 EXPORT_SYMBOL(ath11k_core_free);
2622
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2623 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2624 enum ath11k_bus bus)
2625 {
2626 struct ath11k_base *ab;
2627
2628 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2629 if (!ab)
2630 return NULL;
2631
2632 init_completion(&ab->driver_recovery);
2633
2634 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2635 if (!ab->workqueue)
2636 goto err_sc_free;
2637
2638 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2639 if (!ab->workqueue_aux)
2640 goto err_free_wq;
2641
2642 mutex_init(&ab->core_lock);
2643 mutex_init(&ab->tbl_mtx_lock);
2644 spin_lock_init(&ab->base_lock);
2645 mutex_init(&ab->vdev_id_11d_lock);
2646 init_completion(&ab->reset_complete);
2647 init_completion(&ab->reconfigure_complete);
2648 init_completion(&ab->recovery_start);
2649
2650 INIT_LIST_HEAD(&ab->peers);
2651 init_waitqueue_head(&ab->peer_mapping_wq);
2652 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2653 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2654 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2655 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2656 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2657 INIT_WORK(&ab->dump_work, ath11k_coredump_upload);
2658 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2659 init_completion(&ab->htc_suspend);
2660 init_completion(&ab->wow.wakeup_completed);
2661 init_completion(&ab->restart_completed);
2662
2663 ab->dev = dev;
2664 ab->hif.bus = bus;
2665
2666 return ab;
2667
2668 err_free_wq:
2669 destroy_workqueue(ab->workqueue);
2670 err_sc_free:
2671 kfree(ab);
2672 return NULL;
2673 }
2674 EXPORT_SYMBOL(ath11k_core_alloc);
2675
2676 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2677 MODULE_LICENSE("Dual BSD/GPL");
2678