1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Andes ATCSPI200 SPI Controller
4 *
5 * Copyright (C) 2025 Andes Technology Corporation.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/dev_printk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/jiffies.h>
16 #include <linux/minmax.h>
17 #include <linux/module.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/mutex.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi-mem.h>
24
25 /* Register definitions */
26 #define ATCSPI_TRANS_FMT 0x10 /* SPI transfer format register */
27 #define ATCSPI_TRANS_CTRL 0x20 /* SPI transfer control register */
28 #define ATCSPI_CMD 0x24 /* SPI command register */
29 #define ATCSPI_ADDR 0x28 /* SPI address register */
30 #define ATCSPI_DATA 0x2C /* SPI data register */
31 #define ATCSPI_CTRL 0x30 /* SPI control register */
32 #define ATCSPI_STATUS 0x34 /* SPI status register */
33 #define ATCSPI_TIMING 0x40 /* SPI interface timing register */
34 #define ATCSPI_CONFIG 0x7C /* SPI configuration register */
35
36 /* Transfer format register */
37 #define TRANS_FMT_CPHA BIT(0)
38 #define TRANS_FMT_CPOL BIT(1)
39 #define TRANS_FMT_DATA_MERGE_EN BIT(7)
40 #define TRANS_FMT_DATA_LEN_MASK GENMASK(12, 8)
41 #define TRANS_FMT_ADDR_LEN_MASK GENMASK(17, 16)
42 #define TRANS_FMT_DATA_LEN(x) FIELD_PREP(TRANS_FMT_DATA_LEN_MASK, (x) - 1)
43 #define TRANS_FMT_ADDR_LEN(x) FIELD_PREP(TRANS_FMT_ADDR_LEN_MASK, (x) - 1)
44
45 /* Transfer control register */
46 #define TRANS_MODE_MASK GENMASK(27, 24)
47 #define TRANS_MODE_W_ONLY FIELD_PREP(TRANS_MODE_MASK, 1)
48 #define TRANS_MODE_R_ONLY FIELD_PREP(TRANS_MODE_MASK, 2)
49 #define TRANS_MODE_NONE_DATA FIELD_PREP(TRANS_MODE_MASK, 7)
50 #define TRANS_MODE_DMY_READ FIELD_PREP(TRANS_MODE_MASK, 9)
51 #define TRANS_FIELD_DECNZ(m, x) ((x) ? FIELD_PREP(m, (x) - 1) : 0)
52 #define TRANS_RD_TRANS_CNT(x) TRANS_FIELD_DECNZ(GENMASK(8, 0), x)
53 #define TRANS_DUMMY_CNT(x) TRANS_FIELD_DECNZ(GENMASK(10, 9), x)
54 #define TRANS_WR_TRANS_CNT(x) TRANS_FIELD_DECNZ(GENMASK(20, 12), x)
55 #define TRANS_DUAL_QUAD(x) FIELD_PREP(GENMASK(23, 22), (x))
56 #define TRANS_ADDR_FMT BIT(28)
57 #define TRANS_ADDR_EN BIT(29)
58 #define TRANS_CMD_EN BIT(30)
59
60 /* Control register */
61 #define CTRL_SPI_RST BIT(0)
62 #define CTRL_RX_FIFO_RST BIT(1)
63 #define CTRL_TX_FIFO_RST BIT(2)
64 #define CTRL_RX_DMA_EN BIT(3)
65 #define CTRL_TX_DMA_EN BIT(4)
66
67 /* Status register */
68 #define ATCSPI_ACTIVE BIT(0)
69 #define ATCSPI_RX_EMPTY BIT(14)
70 #define ATCSPI_TX_FULL BIT(23)
71
72 /* Interface timing setting */
73 #define TIMING_SCLK_DIV_MASK GENMASK(7, 0)
74 #define TIMING_SCLK_DIV_MAX 0xFE
75
76 /* Configuration register */
77 #define RXFIFO_SIZE(x) FIELD_GET(GENMASK(3, 0), (x))
78 #define TXFIFO_SIZE(x) FIELD_GET(GENMASK(7, 4), (x))
79
80 /* driver configurations */
81 #define ATCSPI_MAX_TRANS_LEN 512
82 #define ATCSPI_MAX_SPEED_HZ 50000000
83 #define ATCSPI_RDY_TIMEOUT_US 1000000
84 #define ATCSPI_XFER_TIMEOUT(n) ((n) * 10)
85 #define ATCSPI_MAX_CS_NUM 1
86 #define ATCSPI_DMA_THRESHOLD 256
87 #define ATCSPI_BITS_PER_UINT 8
88 #define ATCSPI_DATA_MERGE_EN 1
89 #define ATCSPI_DMA_SUPPORT 1
90
91 /**
92 * struct atcspi_dev - Andes ATCSPI200 SPI controller private data
93 * @host: Pointer to the SPI controller structure.
94 * @mutex_lock: A mutex to protect concurrent access to the controller.
95 * @dma_completion: A completion to signal the end of a DMA transfer.
96 * @dev: Pointer to the device structure.
97 * @regmap: Register map for accessing controller registers.
98 * @clk: Pointer to the controller's functional clock.
99 * @dma_addr: The physical address of the SPI data register for DMA.
100 * @clk_rate: The cached frequency of the functional clock.
101 * @sclk_rate: The target frequency for the SPI clock (SCLK).
102 * @txfifo_size: The size of the transmit FIFO in bytes.
103 * @rxfifo_size: The size of the receive FIFO in bytes.
104 * @data_merge: A flag indicating if the data merge mode is enabled for
105 * the current transfer.
106 * @use_dma: Enable DMA mode if ATCSPI_DMA_SUPPORT is set and DMA is
107 * successfully configured.
108 */
109 struct atcspi_dev {
110 struct spi_controller *host;
111 struct mutex mutex_lock;
112 struct completion dma_completion;
113 struct device *dev;
114 struct regmap *regmap;
115 struct clk *clk;
116 dma_addr_t dma_addr;
117 unsigned int clk_rate;
118 unsigned int sclk_rate;
119 unsigned int txfifo_size;
120 unsigned int rxfifo_size;
121 bool data_merge;
122 bool use_dma;
123 };
124
atcspi_wait_fifo_ready(struct atcspi_dev * spi,enum spi_mem_data_dir dir)125 static int atcspi_wait_fifo_ready(struct atcspi_dev *spi,
126 enum spi_mem_data_dir dir)
127 {
128 unsigned int val;
129 unsigned int mask;
130 int ret;
131
132 mask = (dir == SPI_MEM_DATA_OUT) ? ATCSPI_TX_FULL : ATCSPI_RX_EMPTY;
133 ret = regmap_read_poll_timeout(spi->regmap,
134 ATCSPI_STATUS,
135 val,
136 !(val & mask),
137 0,
138 ATCSPI_RDY_TIMEOUT_US);
139 if (ret)
140 dev_info(spi->dev, "Timed out waiting for FIFO ready\n");
141
142 return ret;
143 }
144
atcspi_xfer_data_poll(struct atcspi_dev * spi,const struct spi_mem_op * op)145 static int atcspi_xfer_data_poll(struct atcspi_dev *spi,
146 const struct spi_mem_op *op)
147 {
148 void *rx_buf = op->data.buf.in;
149 const void *tx_buf = op->data.buf.out;
150 unsigned int val;
151 int trans_bytes = op->data.nbytes;
152 int num_byte;
153 int ret = 0;
154
155 num_byte = spi->data_merge ? 4 : 1;
156 while (trans_bytes) {
157 if (op->data.dir == SPI_MEM_DATA_OUT) {
158 ret = atcspi_wait_fifo_ready(spi, SPI_MEM_DATA_OUT);
159 if (ret)
160 return ret;
161
162 if (spi->data_merge)
163 val = *(unsigned int *)tx_buf;
164 else
165 val = *(unsigned char *)tx_buf;
166 regmap_write(spi->regmap, ATCSPI_DATA, val);
167 tx_buf = (unsigned char *)tx_buf + num_byte;
168 } else {
169 ret = atcspi_wait_fifo_ready(spi, SPI_MEM_DATA_IN);
170 if (ret)
171 return ret;
172
173 regmap_read(spi->regmap, ATCSPI_DATA, &val);
174 if (spi->data_merge)
175 *(unsigned int *)rx_buf = val;
176 else
177 *(unsigned char *)rx_buf = (unsigned char)val;
178 rx_buf = (unsigned char *)rx_buf + num_byte;
179 }
180 trans_bytes -= num_byte;
181 }
182
183 return ret;
184 }
185
atcspi_set_trans_ctl(struct atcspi_dev * spi,const struct spi_mem_op * op)186 static void atcspi_set_trans_ctl(struct atcspi_dev *spi,
187 const struct spi_mem_op *op)
188 {
189 unsigned int tc = 0;
190
191 if (op->cmd.nbytes)
192 tc |= TRANS_CMD_EN;
193 if (op->addr.nbytes)
194 tc |= TRANS_ADDR_EN;
195 if (op->addr.buswidth > 1)
196 tc |= TRANS_ADDR_FMT;
197 if (op->data.nbytes) {
198 unsigned int width_code;
199
200 width_code = ffs(op->data.buswidth) - 1;
201 if (unlikely(width_code > 3)) {
202 WARN_ON_ONCE(1);
203 width_code = 0;
204 }
205 tc |= TRANS_DUAL_QUAD(width_code);
206
207 if (op->data.dir == SPI_MEM_DATA_IN) {
208 if (op->dummy.nbytes)
209 tc |= TRANS_MODE_DMY_READ |
210 TRANS_DUMMY_CNT(op->dummy.nbytes);
211 else
212 tc |= TRANS_MODE_R_ONLY;
213 tc |= TRANS_RD_TRANS_CNT(op->data.nbytes);
214 } else {
215 tc |= TRANS_MODE_W_ONLY |
216 TRANS_WR_TRANS_CNT(op->data.nbytes);
217 }
218 } else {
219 tc |= TRANS_MODE_NONE_DATA;
220 }
221 regmap_write(spi->regmap, ATCSPI_TRANS_CTRL, tc);
222 }
223
atcspi_set_trans_fmt(struct atcspi_dev * spi,const struct spi_mem_op * op)224 static void atcspi_set_trans_fmt(struct atcspi_dev *spi,
225 const struct spi_mem_op *op)
226 {
227 unsigned int val;
228
229 regmap_read(spi->regmap, ATCSPI_TRANS_FMT, &val);
230 if (op->data.nbytes) {
231 if (ATCSPI_DATA_MERGE_EN && ATCSPI_BITS_PER_UINT == 8 &&
232 !(op->data.nbytes % 4)) {
233 val |= TRANS_FMT_DATA_MERGE_EN;
234 spi->data_merge = true;
235 } else {
236 val &= ~TRANS_FMT_DATA_MERGE_EN;
237 spi->data_merge = false;
238 }
239 }
240
241 val = (val & ~TRANS_FMT_ADDR_LEN_MASK) |
242 TRANS_FMT_ADDR_LEN(op->addr.nbytes);
243 regmap_write(spi->regmap, ATCSPI_TRANS_FMT, val);
244 }
245
atcspi_prepare_trans(struct atcspi_dev * spi,const struct spi_mem_op * op)246 static void atcspi_prepare_trans(struct atcspi_dev *spi,
247 const struct spi_mem_op *op)
248 {
249 atcspi_set_trans_fmt(spi, op);
250 atcspi_set_trans_ctl(spi, op);
251 if (op->addr.nbytes)
252 regmap_write(spi->regmap, ATCSPI_ADDR, op->addr.val);
253 regmap_write(spi->regmap, ATCSPI_CMD, op->cmd.opcode);
254 }
255
atcspi_adjust_op_size(struct spi_mem * mem,struct spi_mem_op * op)256 static int atcspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
257 {
258 struct atcspi_dev *spi;
259
260 spi = spi_controller_get_devdata(mem->spi->controller);
261 op->data.nbytes = min(op->data.nbytes, ATCSPI_MAX_TRANS_LEN);
262
263 /* DMA needs to be aligned to 4 byte */
264 if (spi->use_dma && op->data.nbytes >= ATCSPI_DMA_THRESHOLD)
265 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 4);
266
267 return 0;
268 }
269
atcspi_dma_config(struct atcspi_dev * spi,bool is_rx)270 static int atcspi_dma_config(struct atcspi_dev *spi, bool is_rx)
271 {
272 struct dma_slave_config conf = { 0 };
273 struct dma_chan *chan;
274
275 if (is_rx) {
276 chan = spi->host->dma_rx;
277 conf.direction = DMA_DEV_TO_MEM;
278 conf.src_addr = spi->dma_addr;
279 } else {
280 chan = spi->host->dma_tx;
281 conf.direction = DMA_MEM_TO_DEV;
282 conf.dst_addr = spi->dma_addr;
283 }
284 conf.dst_maxburst = spi->rxfifo_size / 2;
285 conf.src_maxburst = spi->txfifo_size / 2;
286
287 if (spi->data_merge) {
288 conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
289 conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
290 } else {
291 conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
292 conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
293 }
294
295 return dmaengine_slave_config(chan, &conf);
296 }
297
atcspi_dma_callback(void * arg)298 static void atcspi_dma_callback(void *arg)
299 {
300 struct completion *dma_completion = arg;
301
302 complete(dma_completion);
303 }
304
atcspi_dma_trans(struct atcspi_dev * spi,const struct spi_mem_op * op)305 static int atcspi_dma_trans(struct atcspi_dev *spi,
306 const struct spi_mem_op *op)
307 {
308 struct dma_async_tx_descriptor *desc;
309 struct dma_chan *dma_ch;
310 struct sg_table sgt;
311 enum dma_transfer_direction dma_dir;
312 dma_cookie_t cookie;
313 unsigned int ctrl;
314 int timeout;
315 int ret;
316
317 regmap_read(spi->regmap, ATCSPI_CTRL, &ctrl);
318 ctrl |= CTRL_TX_DMA_EN | CTRL_RX_DMA_EN;
319 regmap_write(spi->regmap, ATCSPI_CTRL, ctrl);
320 if (op->data.dir == SPI_MEM_DATA_IN) {
321 ret = atcspi_dma_config(spi, TRUE);
322 dma_dir = DMA_DEV_TO_MEM;
323 dma_ch = spi->host->dma_rx;
324 } else {
325 ret = atcspi_dma_config(spi, FALSE);
326 dma_dir = DMA_MEM_TO_DEV;
327 dma_ch = spi->host->dma_tx;
328 }
329 if (ret)
330 return ret;
331
332 ret = spi_controller_dma_map_mem_op_data(spi->host, op, &sgt);
333 if (ret)
334 return ret;
335
336 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents, dma_dir,
337 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
338 if (!desc) {
339 ret = -ENOMEM;
340 goto exit_unmap;
341 }
342
343 reinit_completion(&spi->dma_completion);
344 desc->callback = atcspi_dma_callback;
345 desc->callback_param = &spi->dma_completion;
346 cookie = dmaengine_submit(desc);
347 ret = dma_submit_error(cookie);
348 if (ret)
349 goto exit_unmap;
350
351 dma_async_issue_pending(dma_ch);
352 timeout = msecs_to_jiffies(ATCSPI_XFER_TIMEOUT(op->data.nbytes));
353 if (!wait_for_completion_timeout(&spi->dma_completion, timeout)) {
354 ret = -ETIMEDOUT;
355 dmaengine_terminate_all(dma_ch);
356 }
357
358 exit_unmap:
359 spi_controller_dma_unmap_mem_op_data(spi->host, op, &sgt);
360
361 return ret;
362 }
363
atcspi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)364 static int atcspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
365 {
366 struct spi_device *spi_dev = mem->spi;
367 struct atcspi_dev *spi;
368 unsigned int val;
369 int ret;
370
371 spi = spi_controller_get_devdata(spi_dev->controller);
372 mutex_lock(&spi->mutex_lock);
373 atcspi_prepare_trans(spi, op);
374 if (op->data.nbytes) {
375 if (spi->use_dma && op->data.nbytes >= ATCSPI_DMA_THRESHOLD)
376 ret = atcspi_dma_trans(spi, op);
377 else
378 ret = atcspi_xfer_data_poll(spi, op);
379 if (ret) {
380 dev_info(spi->dev, "SPI transmission failed\n");
381 goto exec_mem_exit;
382 }
383 }
384
385 ret = regmap_read_poll_timeout(spi->regmap,
386 ATCSPI_STATUS,
387 val,
388 !(val & ATCSPI_ACTIVE),
389 0,
390 ATCSPI_RDY_TIMEOUT_US);
391 if (ret)
392 dev_info(spi->dev, "Timed out waiting for ATCSPI_ACTIVE\n");
393
394 exec_mem_exit:
395 mutex_unlock(&spi->mutex_lock);
396
397 return ret;
398 }
399
400 static const struct spi_controller_mem_ops atcspi_mem_ops = {
401 .exec_op = atcspi_exec_mem_op,
402 .adjust_op_size = atcspi_adjust_op_size,
403 };
404
atcspi_setup(struct atcspi_dev * spi)405 static int atcspi_setup(struct atcspi_dev *spi)
406 {
407 unsigned int ctrl_val;
408 unsigned int val;
409 int actual_spi_sclk_f;
410 int ret;
411 unsigned char div;
412
413 ctrl_val = CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST | CTRL_SPI_RST;
414 regmap_write(spi->regmap, ATCSPI_CTRL, ctrl_val);
415 ret = regmap_read_poll_timeout(spi->regmap,
416 ATCSPI_CTRL,
417 val,
418 !(val & ctrl_val),
419 0,
420 ATCSPI_RDY_TIMEOUT_US);
421 if (ret)
422 return dev_err_probe(spi->dev, ret,
423 "Timed out waiting for ATCSPI_CTRL\n");
424
425 val = TRANS_FMT_DATA_LEN(ATCSPI_BITS_PER_UINT) |
426 TRANS_FMT_CPHA | TRANS_FMT_CPOL;
427 regmap_write(spi->regmap, ATCSPI_TRANS_FMT, val);
428
429 regmap_read(spi->regmap, ATCSPI_CONFIG, &val);
430 spi->txfifo_size = BIT(TXFIFO_SIZE(val) + 1);
431 spi->rxfifo_size = BIT(RXFIFO_SIZE(val) + 1);
432
433 regmap_read(spi->regmap, ATCSPI_TIMING, &val);
434 val &= ~TIMING_SCLK_DIV_MASK;
435
436 /*
437 * The SCLK_DIV value 0xFF is special and indicates that the
438 * SCLK rate should be the same as the SPI clock rate.
439 */
440 if (spi->sclk_rate >= spi->clk_rate) {
441 div = TIMING_SCLK_DIV_MASK;
442 } else {
443 /*
444 * The divider value is determined as follows:
445 * 1. If the divider can generate the exact target frequency,
446 * use that setting.
447 * 2. If an exact match is not possible, select the closest
448 * available setting that is lower than the target frequency.
449 */
450 div = (spi->clk_rate + (spi->sclk_rate * 2 - 1)) /
451 (spi->sclk_rate * 2) - 1;
452
453 /* Check if the actual SPI clock is lower than the target */
454 actual_spi_sclk_f = spi->clk_rate / ((div + 1) * 2);
455 if (actual_spi_sclk_f < spi->sclk_rate)
456 dev_info(spi->dev,
457 "Clock adjusted %d to %d due to divider limitation",
458 spi->sclk_rate, actual_spi_sclk_f);
459
460 if (div > TIMING_SCLK_DIV_MAX)
461 return dev_err_probe(spi->dev, -EINVAL,
462 "Unsupported SPI clock %d\n",
463 spi->sclk_rate);
464 }
465 val |= div;
466 regmap_write(spi->regmap, ATCSPI_TIMING, val);
467
468 return ret;
469 }
470
atcspi_init_resources(struct platform_device * pdev,struct atcspi_dev * spi,struct resource ** mem_res)471 static int atcspi_init_resources(struct platform_device *pdev,
472 struct atcspi_dev *spi,
473 struct resource **mem_res)
474 {
475 void __iomem *base;
476 const struct regmap_config atcspi_regmap_cfg = {
477 .name = "atcspi",
478 .reg_bits = 32,
479 .val_bits = 32,
480 .cache_type = REGCACHE_NONE,
481 .reg_stride = 4,
482 .pad_bits = 0,
483 .max_register = ATCSPI_CONFIG
484 };
485
486 base = devm_platform_get_and_ioremap_resource(pdev, 0, mem_res);
487 if (IS_ERR(base))
488 return dev_err_probe(spi->dev, PTR_ERR(base),
489 "Failed to get ioremap resource\n");
490
491 spi->regmap = devm_regmap_init_mmio(spi->dev, base,
492 &atcspi_regmap_cfg);
493 if (IS_ERR(spi->regmap))
494 return dev_err_probe(spi->dev, PTR_ERR(spi->regmap),
495 "Failed to init regmap\n");
496
497 spi->clk = devm_clk_get(spi->dev, NULL);
498 if (IS_ERR(spi->clk))
499 return dev_err_probe(spi->dev, PTR_ERR(spi->clk),
500 "Failed to get SPI clock\n");
501
502 spi->sclk_rate = ATCSPI_MAX_SPEED_HZ;
503 return 0;
504 }
505
atcspi_configure_dma(struct atcspi_dev * spi)506 static int atcspi_configure_dma(struct atcspi_dev *spi)
507 {
508 spi->host->dma_rx = devm_dma_request_chan(spi->dev, "rx");
509 if (IS_ERR(spi->host->dma_rx))
510 return PTR_ERR(spi->host->dma_rx);
511
512 spi->host->dma_tx = devm_dma_request_chan(spi->dev, "tx");
513 if (IS_ERR(spi->host->dma_tx))
514 return PTR_ERR(spi->host->dma_tx);
515
516 init_completion(&spi->dma_completion);
517
518 return 0;
519 }
520
atcspi_enable_clk(struct atcspi_dev * spi)521 static int atcspi_enable_clk(struct atcspi_dev *spi)
522 {
523 int ret;
524
525 ret = clk_prepare_enable(spi->clk);
526 if (ret)
527 return dev_err_probe(spi->dev, ret,
528 "Failed to enable clock\n");
529
530 spi->clk_rate = clk_get_rate(spi->clk);
531 if (!spi->clk_rate)
532 return dev_err_probe(spi->dev, -EINVAL,
533 "Failed to get SPI clock rate\n");
534
535 return 0;
536 }
537
atcspi_init_controller(struct platform_device * pdev,struct atcspi_dev * spi,struct spi_controller * host,struct resource * mem_res)538 static void atcspi_init_controller(struct platform_device *pdev,
539 struct atcspi_dev *spi,
540 struct spi_controller *host,
541 struct resource *mem_res)
542 {
543 /* Get the physical address of the data register for DMA transfers. */
544 spi->dma_addr = (dma_addr_t)(mem_res->start + ATCSPI_DATA);
545
546 /* Initialize controller properties */
547 host->bus_num = pdev->id;
548 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_QUAD | SPI_TX_QUAD;
549 host->num_chipselect = ATCSPI_MAX_CS_NUM;
550 host->mem_ops = &atcspi_mem_ops;
551 host->max_speed_hz = spi->sclk_rate;
552 }
553
atcspi_probe(struct platform_device * pdev)554 static int atcspi_probe(struct platform_device *pdev)
555 {
556 struct spi_controller *host;
557 struct atcspi_dev *spi;
558 struct resource *mem_res;
559 int ret;
560
561 host = spi_alloc_host(&pdev->dev, sizeof(*spi));
562 if (!host)
563 return -ENOMEM;
564
565 spi = spi_controller_get_devdata(host);
566 spi->host = host;
567 spi->dev = &pdev->dev;
568 dev_set_drvdata(&pdev->dev, host);
569
570 ret = atcspi_init_resources(pdev, spi, &mem_res);
571 if (ret)
572 goto free_controller;
573
574 ret = atcspi_enable_clk(spi);
575 if (ret)
576 goto free_controller;
577
578 atcspi_init_controller(pdev, spi, host, mem_res);
579
580 ret = atcspi_setup(spi);
581 if (ret)
582 goto disable_clk;
583
584 ret = devm_spi_register_controller(&pdev->dev, host);
585 if (ret) {
586 dev_err_probe(spi->dev, ret,
587 "Failed to register SPI controller\n");
588 goto disable_clk;
589 }
590
591 spi->use_dma = false;
592 if (ATCSPI_DMA_SUPPORT) {
593 ret = atcspi_configure_dma(spi);
594 if (ret)
595 dev_info(spi->dev,
596 "Failed to init DMA, fallback to PIO mode\n");
597 else
598 spi->use_dma = true;
599 }
600 mutex_init(&spi->mutex_lock);
601
602 return 0;
603
604 disable_clk:
605 clk_disable_unprepare(spi->clk);
606
607 free_controller:
608 spi_controller_put(host);
609 return ret;
610 }
611
atcspi_suspend(struct device * dev)612 static int atcspi_suspend(struct device *dev)
613 {
614 struct spi_controller *host = dev_get_drvdata(dev);
615 struct atcspi_dev *spi = spi_controller_get_devdata(host);
616
617 spi_controller_suspend(host);
618
619 clk_disable_unprepare(spi->clk);
620
621 return 0;
622 }
623
atcspi_resume(struct device * dev)624 static int atcspi_resume(struct device *dev)
625 {
626 struct spi_controller *host = dev_get_drvdata(dev);
627 struct atcspi_dev *spi = spi_controller_get_devdata(host);
628 int ret;
629
630 ret = clk_prepare_enable(spi->clk);
631 if (ret)
632 return ret;
633
634 ret = atcspi_setup(spi);
635 if (ret)
636 goto disable_clk;
637
638 ret = spi_controller_resume(host);
639 if (ret)
640 goto disable_clk;
641
642 return ret;
643
644 disable_clk:
645 clk_disable_unprepare(spi->clk);
646
647 return ret;
648 }
649
650 static DEFINE_SIMPLE_DEV_PM_OPS(atcspi_pm_ops, atcspi_suspend, atcspi_resume);
651
652 static const struct of_device_id atcspi_of_match[] = {
653 { .compatible = "andestech,qilai-spi", },
654 { .compatible = "andestech,ae350-spi", },
655 { /* sentinel */ }
656 };
657
658 MODULE_DEVICE_TABLE(of, atcspi_of_match);
659
660 static struct platform_driver atcspi_driver = {
661 .probe = atcspi_probe,
662 .driver = {
663 .name = "atcspi200",
664 .owner = THIS_MODULE,
665 .of_match_table = atcspi_of_match,
666 .pm = pm_sleep_ptr(&atcspi_pm_ops)
667 }
668 };
669 module_platform_driver(atcspi_driver);
670
671 MODULE_AUTHOR("CL Wang <cl634@andestech.com>");
672 MODULE_DESCRIPTION("Andes ATCSPI200 SPI controller driver");
673 MODULE_LICENSE("GPL");
674