1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-clock.h> 8#include <dt-bindings/clock/imx8-lpcg.h> 9#include <dt-bindings/dma/fsl-edma.h> 10#include <dt-bindings/firmware/imx/rsrc.h> 11 12audio_ipg_clk: clock-audio-ipg { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <120000000>; 16 clock-output-names = "audio_ipg_clk"; 17}; 18 19clk_ext_aud_mclk0: clock-ext-aud-mclk0 { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <0>; 23 clock-output-names = "ext_aud_mclk0"; 24}; 25 26clk_ext_aud_mclk1: clock-ext-aud-mclk1 { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <0>; 30 clock-output-names = "ext_aud_mclk1"; 31}; 32 33clk_esai0_rx_clk: clock-esai0-rx { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <0>; 37 clock-output-names = "esai0_rx_clk"; 38}; 39 40clk_esai0_rx_hf_clk: clock-esai0-rx-hf { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 clock-output-names = "esai0_rx_hf_clk"; 45}; 46 47clk_esai0_tx_clk: clock-esai0-tx { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <0>; 51 clock-output-names = "esai0_tx_clk"; 52}; 53 54clk_esai0_tx_hf_clk: clock-esai0-tx-hf { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <0>; 58 clock-output-names = "esai0_tx_hf_clk"; 59}; 60 61clk_spdif0_rx: clock-spdif0-rx { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <0>; 65 clock-output-names = "spdif0_rx"; 66}; 67 68clk_sai0_rx_bclk: clock-sai0-rx-bclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 clock-output-names = "sai0_rx_bclk"; 73}; 74 75clk_sai0_tx_bclk: clock-sai0-tx-bclk { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <0>; 79 clock-output-names = "sai0_tx_bclk"; 80}; 81 82clk_sai1_rx_bclk: clock-sai1-rx-bclk { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <0>; 86 clock-output-names = "sai1_rx_bclk"; 87}; 88 89clk_sai1_tx_bclk: clock-sai1-tx-bclk { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 clock-output-names = "sai1_tx_bclk"; 94}; 95 96clk_sai2_rx_bclk: clock-sai2-rx-bclk { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <0>; 100 clock-output-names = "sai2_rx_bclk"; 101}; 102 103clk_sai3_rx_bclk: clock-sai3-rx-bclk { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <0>; 107 clock-output-names = "sai3_rx_bclk"; 108}; 109 110clk_sai4_rx_bclk: clock-sai4-rx-bclk { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <0>; 114 clock-output-names = "sai4_rx_bclk"; 115}; 116 117audio_subsys: bus@59000000 { 118 compatible = "simple-bus"; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges = <0x59000000 0x0 0x59000000 0x1000000>; 122 123 asrc0: asrc@59000000 { 124 compatible = "fsl,imx8qm-asrc"; 125 reg = <0x59000000 0x10000>; 126 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, 128 <&asrc0_lpcg IMX_LPCG_CLK_0>, 129 <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>, 130 <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>, 131 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, 132 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, 133 <&clk_dummy>, 134 <&clk_dummy>, 135 <&clk_dummy>, 136 <&clk_dummy>, 137 <&clk_dummy>, 138 <&clk_dummy>, 139 <&clk_dummy>, 140 <&clk_dummy>, 141 <&clk_dummy>, 142 <&clk_dummy>, 143 <&clk_dummy>, 144 <&clk_dummy>, 145 <&clk_dummy>; 146 clock-names = "mem", "ipg", 147 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 148 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 149 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 150 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 151 "spba"; 152 dmas = <&edma0 0 0 0>, 153 <&edma0 1 0 0>, 154 <&edma0 2 0 0>, 155 <&edma0 3 0 FSL_EDMA_RX>, 156 <&edma0 4 0 FSL_EDMA_RX>, 157 <&edma0 5 0 FSL_EDMA_RX>; 158 /* tx* is output channel of asrc, it is rx channel for eDMA */ 159 dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; 160 fsl,asrc-rate = <8000>; 161 fsl,asrc-width = <16>; 162 fsl,asrc-clk-map = <0>; 163 power-domains = <&pd IMX_SC_R_ASRC_0>; 164 status = "disabled"; 165 }; 166 167 esai0: esai@59010000 { 168 compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; 169 reg = <0x59010000 0x10000>; 170 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&esai0_lpcg IMX_LPCG_CLK_4>, 172 <&esai0_lpcg IMX_LPCG_CLK_0>, 173 <&esai0_lpcg IMX_LPCG_CLK_4>, 174 <&clk_dummy>; 175 clock-names = "core", "extal", "fsys", "spba"; 176 dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; 177 dma-names = "rx", "tx"; 178 power-domains = <&pd IMX_SC_R_ESAI_0>; 179 status = "disabled"; 180 }; 181 182 spdif0: spdif@59020000 { 183 compatible = "fsl,imx8qm-spdif"; 184 reg = <0x59020000 0x10000>; 185 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ 186 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ 187 clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ 188 <&clk_dummy>, /* rxtx0 */ 189 <&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */ 190 <&clk_dummy>, /* rxtx2 */ 191 <&clk_dummy>, /* rxtx3 */ 192 <&clk_dummy>, /* rxtx4 */ 193 <&audio_ipg_clk>, /* rxtx5 */ 194 <&clk_dummy>, /* rxtx6 */ 195 <&clk_dummy>, /* rxtx7 */ 196 <&clk_dummy>; /* spba */ 197 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", 198 "rxtx5", "rxtx6", "rxtx7", "spba"; 199 dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, 200 <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; 201 dma-names = "rx", "tx"; 202 power-domains = <&pd IMX_SC_R_SPDIF_0>; 203 status = "disabled"; 204 }; 205 206 sai0: sai@59040000 { 207 compatible = "fsl,imx8qm-sai"; 208 reg = <0x59040000 0x10000>; 209 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&sai0_lpcg IMX_LPCG_CLK_4>, 211 <&clk_dummy>, 212 <&sai0_lpcg IMX_LPCG_CLK_0>, 213 <&clk_dummy>, 214 <&clk_dummy>; 215 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 216 dma-names = "rx", "tx"; 217 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; 218 power-domains = <&pd IMX_SC_R_SAI_0>; 219 status = "disabled"; 220 }; 221 222 sai1: sai@59050000 { 223 compatible = "fsl,imx8qm-sai"; 224 reg = <0x59050000 0x10000>; 225 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&sai1_lpcg IMX_LPCG_CLK_4>, 227 <&clk_dummy>, 228 <&sai1_lpcg IMX_LPCG_CLK_0>, 229 <&clk_dummy>, 230 <&clk_dummy>; 231 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 232 dma-names = "rx", "tx"; 233 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; 234 power-domains = <&pd IMX_SC_R_SAI_1>; 235 status = "disabled"; 236 }; 237 238 sai2: sai@59060000 { 239 compatible = "fsl,imx8qm-sai"; 240 reg = <0x59060000 0x10000>; 241 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&sai2_lpcg IMX_LPCG_CLK_4>, 243 <&clk_dummy>, 244 <&sai2_lpcg IMX_LPCG_CLK_0>, 245 <&clk_dummy>, 246 <&clk_dummy>; 247 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 248 dma-names = "rx"; 249 dmas = <&edma0 16 0 1>; 250 power-domains = <&pd IMX_SC_R_SAI_2>; 251 status = "disabled"; 252 }; 253 254 sai3: sai@59070000 { 255 compatible = "fsl,imx8qm-sai"; 256 reg = <0x59070000 0x10000>; 257 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&sai3_lpcg IMX_LPCG_CLK_4>, 259 <&clk_dummy>, 260 <&sai3_lpcg IMX_LPCG_CLK_0>, 261 <&clk_dummy>, 262 <&clk_dummy>; 263 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 264 dma-names = "rx"; 265 dmas = <&edma0 17 0 1>; 266 power-domains = <&pd IMX_SC_R_SAI_3>; 267 status = "disabled"; 268 }; 269 270 edma0: dma-controller@591f0000 { 271 compatible = "fsl,imx8qm-edma"; 272 reg = <0x591f0000 0x190000>; 273 #dma-cells = <3>; 274 dma-channels = <24>; 275 dma-channel-mask = <0x5c0c00>; 276 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */ 277 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 278 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 279 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 280 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 281 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 282 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */ 283 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */ 284 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */ 285 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */ 286 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */ 287 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */ 288 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */ 289 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */ 290 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */ 291 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */ 292 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */ 293 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */ 294 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */ 295 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */ 296 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */ 297 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */ 298 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */ 299 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, /* 23 unused */ 300 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 301 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 302 <&pd IMX_SC_R_DMA_0_CH1>, 303 <&pd IMX_SC_R_DMA_0_CH2>, 304 <&pd IMX_SC_R_DMA_0_CH3>, 305 <&pd IMX_SC_R_DMA_0_CH4>, 306 <&pd IMX_SC_R_DMA_0_CH5>, 307 <&pd IMX_SC_R_DMA_0_CH6>, 308 <&pd IMX_SC_R_DMA_0_CH7>, 309 <&pd IMX_SC_R_DMA_0_CH8>, 310 <&pd IMX_SC_R_DMA_0_CH9>, 311 <&pd IMX_SC_R_DMA_0_CH10>, 312 <&pd IMX_SC_R_DMA_0_CH11>, 313 <&pd IMX_SC_R_DMA_0_CH12>, 314 <&pd IMX_SC_R_DMA_0_CH13>, 315 <&pd IMX_SC_R_DMA_0_CH14>, 316 <&pd IMX_SC_R_DMA_0_CH15>, 317 <&pd IMX_SC_R_DMA_0_CH16>, 318 <&pd IMX_SC_R_DMA_0_CH17>, 319 <&pd IMX_SC_R_DMA_0_CH18>, 320 <&pd IMX_SC_R_DMA_0_CH19>, 321 <&pd IMX_SC_R_DMA_0_CH20>, 322 <&pd IMX_SC_R_DMA_0_CH21>, 323 <&pd IMX_SC_R_DMA_0_CH22>, 324 <&pd IMX_SC_R_DMA_0_CH23>; 325 }; 326 327 asrc0_lpcg: clock-controller@59400000 { 328 compatible = "fsl,imx8qxp-lpcg"; 329 reg = <0x59400000 0x10000>; 330 #clock-cells = <1>; 331 clocks = <&audio_ipg_clk>; 332 clock-indices = <IMX_LPCG_CLK_4>; 333 clock-output-names = "asrc0_lpcg_ipg_clk"; 334 power-domains = <&pd IMX_SC_R_ASRC_0>; 335 }; 336 337 esai0_lpcg: clock-controller@59410000 { 338 compatible = "fsl,imx8qxp-lpcg"; 339 reg = <0x59410000 0x10000>; 340 #clock-cells = <1>; 341 clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 342 <&audio_ipg_clk>; 343 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 344 clock-output-names = "esai0_lpcg_extal_clk", 345 "esai0_lpcg_ipg_clk"; 346 power-domains = <&pd IMX_SC_R_ESAI_0>; 347 }; 348 349 spdif0_lpcg: clock-controller@59420000 { 350 compatible = "fsl,imx8qxp-lpcg"; 351 reg = <0x59420000 0x10000>; 352 #clock-cells = <1>; 353 clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, 354 <&audio_ipg_clk>; 355 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 356 clock-output-names = "spdif0_lpcg_tx_clk", 357 "spdif0_lpcg_gclkw"; 358 power-domains = <&pd IMX_SC_R_SPDIF_0>; 359 }; 360 361 sai0_lpcg: clock-controller@59440000 { 362 compatible = "fsl,imx8qxp-lpcg"; 363 reg = <0x59440000 0x10000>; 364 #clock-cells = <1>; 365 clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, 366 <&audio_ipg_clk>; 367 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 368 clock-output-names = "sai0_lpcg_mclk", 369 "sai0_lpcg_ipg_clk"; 370 power-domains = <&pd IMX_SC_R_SAI_0>; 371 }; 372 373 sai1_lpcg: clock-controller@59450000 { 374 compatible = "fsl,imx8qxp-lpcg"; 375 reg = <0x59450000 0x10000>; 376 #clock-cells = <1>; 377 clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, 378 <&audio_ipg_clk>; 379 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 380 clock-output-names = "sai1_lpcg_mclk", 381 "sai1_lpcg_ipg_clk"; 382 power-domains = <&pd IMX_SC_R_SAI_1>; 383 }; 384 385 sai2_lpcg: clock-controller@59460000 { 386 compatible = "fsl,imx8qxp-lpcg"; 387 reg = <0x59460000 0x10000>; 388 #clock-cells = <1>; 389 clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, 390 <&audio_ipg_clk>; 391 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 392 clock-output-names = "sai2_lpcg_mclk", 393 "sai2_lpcg_ipg_clk"; 394 power-domains = <&pd IMX_SC_R_SAI_2>; 395 }; 396 397 sai3_lpcg: clock-controller@59470000 { 398 compatible = "fsl,imx8qxp-lpcg"; 399 reg = <0x59470000 0x10000>; 400 #clock-cells = <1>; 401 clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, 402 <&audio_ipg_clk>; 403 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 404 clock-output-names = "sai3_lpcg_mclk", 405 "sai3_lpcg_ipg_clk"; 406 power-domains = <&pd IMX_SC_R_SAI_3>; 407 }; 408 409 dsp_lpcg: clock-controller@59580000 { 410 compatible = "fsl,imx8qxp-lpcg"; 411 reg = <0x59580000 0x10000>; 412 #clock-cells = <1>; 413 clocks = <&audio_ipg_clk>, 414 <&audio_ipg_clk>, 415 <&audio_ipg_clk>; 416 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 417 <IMX_LPCG_CLK_7>; 418 clock-output-names = "dsp_lpcg_adb_clk", 419 "dsp_lpcg_ipg_clk", 420 "dsp_lpcg_core_clk"; 421 power-domains = <&pd IMX_SC_R_DSP>; 422 }; 423 424 dsp_ram_lpcg: clock-controller@59590000 { 425 compatible = "fsl,imx8qxp-lpcg"; 426 reg = <0x59590000 0x10000>; 427 #clock-cells = <1>; 428 clocks = <&audio_ipg_clk>; 429 clock-indices = <IMX_LPCG_CLK_4>; 430 clock-output-names = "dsp_ram_lpcg_ipg_clk"; 431 power-domains = <&pd IMX_SC_R_DSP_RAM>; 432 }; 433 434 dsp: dsp@596e8000 { 435 compatible = "fsl,imx8qxp-hifi4"; 436 reg = <0x596e8000 0x88000>; 437 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, 438 <&dsp_ram_lpcg IMX_LPCG_CLK_4>, 439 <&dsp_lpcg IMX_LPCG_CLK_7>; 440 clock-names = "ipg", "ocram", "core"; 441 power-domains = <&pd IMX_SC_R_MU_13B>, 442 <&pd IMX_SC_R_MU_2A>; 443 mbox-names = "tx", "rx", "rxdb"; 444 mboxes = <&lsio_mu13 0 0>, 445 <&lsio_mu13 1 0>, 446 <&lsio_mu13 3 0>; 447 firmware-name = "imx/dsp/hifi4.bin"; 448 status = "disabled"; 449 }; 450 451 asrc1: asrc@59800000 { 452 compatible = "fsl,imx8qm-asrc"; 453 reg = <0x59800000 0x10000>; 454 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>, 456 <&asrc1_lpcg IMX_LPCG_CLK_4>, 457 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 458 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 459 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, 460 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, 461 <&clk_dummy>, 462 <&clk_dummy>, 463 <&clk_dummy>, 464 <&clk_dummy>, 465 <&clk_dummy>, 466 <&clk_dummy>, 467 <&clk_dummy>, 468 <&clk_dummy>, 469 <&clk_dummy>, 470 <&clk_dummy>, 471 <&clk_dummy>, 472 <&clk_dummy>, 473 <&clk_dummy>; 474 clock-names = "mem", "ipg", 475 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 476 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 477 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 478 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 479 "spba"; 480 dmas = <&edma1 0 0 0>, 481 <&edma1 1 0 0>, 482 <&edma1 2 0 0>, 483 <&edma1 3 0 FSL_EDMA_RX>, 484 <&edma1 4 0 FSL_EDMA_RX>, 485 <&edma1 5 0 FSL_EDMA_RX>; 486 /* tx* is output channel of asrc, it is rx channel for eDMA */ 487 dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; 488 fsl,asrc-rate = <8000>; 489 fsl,asrc-width = <16>; 490 fsl,asrc-clk-map = <1>; 491 power-domains = <&pd IMX_SC_R_ASRC_1>; 492 status = "disabled"; 493 }; 494 495 sai4: sai@59820000 { 496 compatible = "fsl,imx8qm-sai"; 497 reg = <0x59820000 0x10000>; 498 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&sai4_lpcg IMX_LPCG_CLK_4>, 500 <&clk_dummy>, 501 <&sai4_lpcg IMX_LPCG_CLK_0>, 502 <&clk_dummy>, 503 <&clk_dummy>; 504 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 505 dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; 506 dma-names = "rx", "tx"; 507 power-domains = <&pd IMX_SC_R_SAI_4>; 508 status = "disabled"; 509 }; 510 511 sai5: sai@59830000 { 512 compatible = "fsl,imx8qm-sai"; 513 reg = <0x59830000 0x10000>; 514 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&sai5_lpcg IMX_LPCG_CLK_4>, 516 <&clk_dummy>, 517 <&sai5_lpcg IMX_LPCG_CLK_0>, 518 <&clk_dummy>, 519 <&clk_dummy>; 520 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 521 dmas = <&edma1 10 0 0>; 522 dma-names = "tx"; 523 power-domains = <&pd IMX_SC_R_SAI_5>; 524 status = "disabled"; 525 }; 526 527 amix: amix@59840000 { 528 compatible = "fsl,imx8qm-audmix"; 529 reg = <0x59840000 0x10000>; 530 clocks = <&amix_lpcg IMX_LPCG_CLK_0>; 531 clock-names = "ipg"; 532 power-domains = <&pd IMX_SC_R_AMIX>; 533 dais = <&sai4>, <&sai5>; 534 status = "disabled"; 535 }; 536 537 mqs: mqs@59850000 { 538 compatible = "fsl,imx8qm-mqs"; 539 reg = <0x59850000 0x10000>; 540 clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>; 541 clock-names = "mclk", "core"; 542 power-domains = <&pd IMX_SC_R_MQS_0>; 543 status = "disabled"; 544 }; 545 546 edma1: dma-controller@599f0000 { 547 compatible = "fsl,imx8qm-edma"; 548 reg = <0x599f0000 0xc0000>; 549 #dma-cells = <3>; 550 dma-channels = <11>; 551 dma-channel-mask = <0xc0>; 552 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */ 553 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 554 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 555 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 556 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 557 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 558 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */ 559 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */ 560 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 561 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* sai5 */ 563 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 564 power-domains = <&pd IMX_SC_R_DMA_1_CH0>, 565 <&pd IMX_SC_R_DMA_1_CH1>, 566 <&pd IMX_SC_R_DMA_1_CH2>, 567 <&pd IMX_SC_R_DMA_1_CH3>, 568 <&pd IMX_SC_R_DMA_1_CH4>, 569 <&pd IMX_SC_R_DMA_1_CH5>, 570 <&pd IMX_SC_R_DMA_1_CH6>, 571 <&pd IMX_SC_R_DMA_1_CH7>, 572 <&pd IMX_SC_R_DMA_1_CH8>, 573 <&pd IMX_SC_R_DMA_1_CH9>, 574 <&pd IMX_SC_R_DMA_1_CH10>; 575 }; 576 577 aud_rec0_lpcg: clock-controller@59d00000 { 578 compatible = "fsl,imx8qxp-lpcg"; 579 reg = <0x59d00000 0x10000>; 580 #clock-cells = <1>; 581 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; 582 clock-indices = <IMX_LPCG_CLK_0>; 583 clock-output-names = "aud_rec_clk0_lpcg_clk"; 584 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; 585 }; 586 587 aud_rec1_lpcg: clock-controller@59d10000 { 588 compatible = "fsl,imx8qxp-lpcg"; 589 reg = <0x59d10000 0x10000>; 590 #clock-cells = <1>; 591 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; 592 clock-indices = <IMX_LPCG_CLK_0>; 593 clock-output-names = "aud_rec_clk1_lpcg_clk"; 594 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; 595 }; 596 597 aud_pll_div0_lpcg: clock-controller@59d20000 { 598 compatible = "fsl,imx8qxp-lpcg"; 599 reg = <0x59d20000 0x10000>; 600 #clock-cells = <1>; 601 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; 602 clock-indices = <IMX_LPCG_CLK_0>; 603 clock-output-names = "aud_pll_div_clk0_lpcg_clk"; 604 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; 605 }; 606 607 aud_pll_div1_lpcg: clock-controller@59d30000 { 608 compatible = "fsl,imx8qxp-lpcg"; 609 reg = <0x59d30000 0x10000>; 610 #clock-cells = <1>; 611 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; 612 clock-indices = <IMX_LPCG_CLK_0>; 613 clock-output-names = "aud_pll_div_clk1_lpcg_clk"; 614 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; 615 }; 616 617 mclkout0_lpcg: clock-controller@59d50000 { 618 compatible = "fsl,imx8qxp-lpcg"; 619 reg = <0x59d50000 0x10000>; 620 #clock-cells = <1>; 621 clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; 622 clock-indices = <IMX_LPCG_CLK_0>; 623 clock-output-names = "mclkout0_lpcg_clk"; 624 power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; 625 }; 626 627 mclkout1_lpcg: clock-controller@59d60000 { 628 compatible = "fsl,imx8qxp-lpcg"; 629 reg = <0x59d60000 0x10000>; 630 #clock-cells = <1>; 631 clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; 632 clock-indices = <IMX_LPCG_CLK_0>; 633 clock-output-names = "mclkout1_lpcg_clk"; 634 power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; 635 }; 636 637 acm: acm@59e00000 { 638 compatible = "fsl,imx8qxp-acm"; 639 reg = <0x59e00000 0x1d0000>; 640 #clock-cells = <1>; 641 power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, 642 <&pd IMX_SC_R_AUDIO_CLK_1>, 643 <&pd IMX_SC_R_MCLK_OUT_0>, 644 <&pd IMX_SC_R_MCLK_OUT_1>, 645 <&pd IMX_SC_R_AUDIO_PLL_0>, 646 <&pd IMX_SC_R_AUDIO_PLL_1>, 647 <&pd IMX_SC_R_ASRC_0>, 648 <&pd IMX_SC_R_ASRC_1>, 649 <&pd IMX_SC_R_ESAI_0>, 650 <&pd IMX_SC_R_SAI_0>, 651 <&pd IMX_SC_R_SAI_1>, 652 <&pd IMX_SC_R_SAI_2>, 653 <&pd IMX_SC_R_SAI_3>, 654 <&pd IMX_SC_R_SAI_4>, 655 <&pd IMX_SC_R_SAI_5>, 656 <&pd IMX_SC_R_SPDIF_0>, 657 <&pd IMX_SC_R_MQS_0>; 658 clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, 659 <&aud_rec1_lpcg IMX_LPCG_CLK_0>, 660 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 661 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 662 <&clk_ext_aud_mclk0>, 663 <&clk_ext_aud_mclk1>, 664 <&clk_esai0_rx_clk>, 665 <&clk_esai0_rx_hf_clk>, 666 <&clk_esai0_tx_clk>, 667 <&clk_esai0_tx_hf_clk>, 668 <&clk_spdif0_rx>, 669 <&clk_sai0_rx_bclk>, 670 <&clk_sai0_tx_bclk>, 671 <&clk_sai1_rx_bclk>, 672 <&clk_sai1_tx_bclk>, 673 <&clk_sai2_rx_bclk>, 674 <&clk_sai3_rx_bclk>, 675 <&clk_sai4_rx_bclk>; 676 clock-names = "aud_rec_clk0_lpcg_clk", 677 "aud_rec_clk1_lpcg_clk", 678 "aud_pll_div_clk0_lpcg_clk", 679 "aud_pll_div_clk1_lpcg_clk", 680 "ext_aud_mclk0", 681 "ext_aud_mclk1", 682 "esai0_rx_clk", 683 "esai0_rx_hf_clk", 684 "esai0_tx_clk", 685 "esai0_tx_hf_clk", 686 "spdif0_rx", 687 "sai0_rx_bclk", 688 "sai0_tx_bclk", 689 "sai1_rx_bclk", 690 "sai1_tx_bclk", 691 "sai2_rx_bclk", 692 "sai3_rx_bclk", 693 "sai4_rx_bclk"; 694 }; 695 696 asrc1_lpcg: clock-controller@59c00000 { 697 compatible = "fsl,imx8qxp-lpcg"; 698 reg = <0x59c00000 0x10000>; 699 #clock-cells = <1>; 700 clocks = <&audio_ipg_clk>; 701 clock-indices = <IMX_LPCG_CLK_4>; 702 clock-output-names = "asrc1_lpcg_ipg_clk"; 703 power-domains = <&pd IMX_SC_R_ASRC_1>; 704 }; 705 706 sai4_lpcg: clock-controller@59c20000 { 707 compatible = "fsl,imx8qxp-lpcg"; 708 reg = <0x59c20000 0x10000>; 709 #clock-cells = <1>; 710 clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, 711 <&audio_ipg_clk>; 712 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 713 clock-output-names = "sai4_lpcg_mclk", 714 "sai4_lpcg_ipg_clk"; 715 power-domains = <&pd IMX_SC_R_SAI_4>; 716 }; 717 718 sai5_lpcg: clock-controller@59c30000 { 719 compatible = "fsl,imx8qxp-lpcg"; 720 reg = <0x59c30000 0x10000>; 721 #clock-cells = <1>; 722 clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, 723 <&audio_ipg_clk>; 724 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 725 clock-output-names = "sai5_lpcg_mclk", 726 "sai5_lpcg_ipg_clk"; 727 power-domains = <&pd IMX_SC_R_SAI_5>; 728 }; 729 730 amix_lpcg: clock-controller@59c40000 { 731 compatible = "fsl,imx8qxp-lpcg"; 732 reg = <0x59c40000 0x10000>; 733 #clock-cells = <1>; 734 clocks = <&audio_ipg_clk>; 735 clock-indices = <IMX_LPCG_CLK_0>; 736 clock-output-names = "amix_lpcg_ipg_clk"; 737 power-domains = <&pd IMX_SC_R_AMIX>; 738 }; 739 740 mqs0_lpcg: clock-controller@59c50000 { 741 compatible = "fsl,imx8qxp-lpcg"; 742 reg = <0x59c50000 0x10000>; 743 #clock-cells = <1>; 744 clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, 745 <&audio_ipg_clk>; 746 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 747 clock-output-names = "mqs0_lpcg_mclk", 748 "mqs0_lpcg_ipg_clk"; 749 power-domains = <&pd IMX_SC_R_MQS_0>; 750 }; 751}; 752