1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v13_0.h"
29 #include "smu13_driver_if_yellow_carp.h"
30 #include "yellow_carp_ppt.h"
31 #include "smu_v13_0_1_ppsmc.h"
32 #include "smu_v13_0_1_pmfw.h"
33 #include "smu_cmn.h"
34
35 /*
36 * DO NOT use these for err/warn/info/debug messages.
37 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 * They are more MGPU friendly.
39 */
40 #undef pr_err
41 #undef pr_warn
42 #undef pr_info
43 #undef pr_debug
44
45 #define regSMUIO_GFX_MISC_CNTL 0x00c5
46 #define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0
47 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
48 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1L
49
50 #define SMU_13_0_8_UMD_PSTATE_GFXCLK 533
51 #define SMU_13_0_8_UMD_PSTATE_SOCCLK 533
52 #define SMU_13_0_8_UMD_PSTATE_FCLK 800
53
54 #define SMU_13_0_1_UMD_PSTATE_GFXCLK 700
55 #define SMU_13_0_1_UMD_PSTATE_SOCCLK 678
56 #define SMU_13_0_1_UMD_PSTATE_FCLK 1800
57
58 static const struct smu_feature_bits yellow_carp_dpm_features = {
59 .bits = {
60 SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
61 SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
62 SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
63 SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
64 SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT),
65 SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
66 SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
67 SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
68 SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT)
69 }
70 };
71
72 static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
73 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
74 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
75 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
76 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1),
77 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
78 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
79 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
80 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
81 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
82 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
83 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
84 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
85 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
86 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
87 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
88 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
89 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
90 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
91 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
92 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
93 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
94 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
95 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
96 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
97 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
98 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
99 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
101 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
102 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
103 };
104
105 static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = {
106 FEA_MAP(CCLK_DPM),
107 FEA_MAP(FAN_CONTROLLER),
108 FEA_MAP(PPT),
109 FEA_MAP(TDC),
110 FEA_MAP(THERMAL),
111 FEA_MAP(ULV),
112 FEA_MAP(VCN_DPM),
113 FEA_MAP_REVERSE(FCLK),
114 FEA_MAP_REVERSE(SOCCLK),
115 FEA_MAP(LCLK_DPM),
116 FEA_MAP(SHUBCLK_DPM),
117 FEA_MAP(DCFCLK_DPM),
118 FEA_MAP_HALF_REVERSE(GFX),
119 FEA_MAP(DS_GFXCLK),
120 FEA_MAP(DS_SOCCLK),
121 FEA_MAP(DS_LCLK),
122 FEA_MAP(DS_DCFCLK),
123 FEA_MAP(DS_FCLK),
124 FEA_MAP(DS_MP1CLK),
125 FEA_MAP(DS_MP0CLK),
126 FEA_MAP(GFX_DEM),
127 FEA_MAP(PSI),
128 FEA_MAP(PROCHOT),
129 FEA_MAP(CPUOFF),
130 FEA_MAP(STAPM),
131 FEA_MAP(S0I3),
132 FEA_MAP(PERF_LIMIT),
133 FEA_MAP(CORE_DLDO),
134 FEA_MAP(RSMU_LOW_POWER),
135 FEA_MAP(SMN_LOW_POWER),
136 FEA_MAP(THM_LOW_POWER),
137 FEA_MAP(SMUIO_LOW_POWER),
138 FEA_MAP(MP1_LOW_POWER),
139 FEA_MAP(DS_VCN),
140 FEA_MAP(CPPC),
141 FEA_MAP(DF_CSTATES),
142 FEA_MAP(MSMU_LOW_POWER),
143 FEA_MAP(ATHUB_PG),
144 };
145
146 static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
147 TAB_MAP_VALID(WATERMARKS),
148 TAB_MAP_VALID(SMU_METRICS),
149 TAB_MAP_VALID(CUSTOM_DPM),
150 TAB_MAP_VALID(DPMCLOCKS),
151 };
152
yellow_carp_init_smc_tables(struct smu_context * smu)153 static int yellow_carp_init_smc_tables(struct smu_context *smu)
154 {
155 struct smu_table_context *smu_table = &smu->smu_table;
156 struct smu_table *tables = smu_table->tables;
157 int ret;
158
159 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
160 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
161 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
162 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
163 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
164 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
165
166 smu_table->clocks_table = kzalloc_obj(DpmClocks_t);
167 if (!smu_table->clocks_table)
168 goto err0_out;
169
170 smu_table->metrics_table = kzalloc_obj(SmuMetrics_t);
171 if (!smu_table->metrics_table)
172 goto err1_out;
173 smu_table->metrics_time = 0;
174
175 smu_table->watermarks_table = kzalloc_obj(Watermarks_t);
176 if (!smu_table->watermarks_table)
177 goto err2_out;
178
179 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
180 sizeof(struct gpu_metrics_v2_1),
181 SMU_GPU_METRICS_CACHE_INTERVAL);
182 if (ret)
183 goto err3_out;
184
185 return 0;
186
187 err3_out:
188 kfree(smu_table->watermarks_table);
189 err2_out:
190 kfree(smu_table->metrics_table);
191 err1_out:
192 kfree(smu_table->clocks_table);
193 err0_out:
194 return -ENOMEM;
195 }
196
yellow_carp_fini_smc_tables(struct smu_context * smu)197 static int yellow_carp_fini_smc_tables(struct smu_context *smu)
198 {
199 struct smu_table_context *smu_table = &smu->smu_table;
200
201 kfree(smu_table->clocks_table);
202 smu_table->clocks_table = NULL;
203
204 kfree(smu_table->metrics_table);
205 smu_table->metrics_table = NULL;
206
207 kfree(smu_table->watermarks_table);
208 smu_table->watermarks_table = NULL;
209
210 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
211
212 return 0;
213 }
214
yellow_carp_system_features_control(struct smu_context * smu,bool en)215 static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
216 {
217 struct amdgpu_device *adev = smu->adev;
218 int ret = 0;
219
220 if (!en && !adev->in_s0ix)
221 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
222
223 return ret;
224 }
225
yellow_carp_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)226 static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu,
227 bool enable,
228 int inst)
229 {
230 int ret = 0;
231
232 /* vcn dpm on is a prerequisite for vcn power gate messages */
233 if (enable)
234 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
235 0, NULL);
236 else
237 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
238 0, NULL);
239
240 return ret;
241 }
242
yellow_carp_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)243 static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
244 {
245 int ret = 0;
246
247 if (enable)
248 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
249 0, NULL);
250 else
251 ret = smu_cmn_send_smc_msg_with_param(smu,
252 SMU_MSG_PowerDownJpeg, 0,
253 NULL);
254
255 return ret;
256 }
257
258
yellow_carp_is_dpm_running(struct smu_context * smu)259 static bool yellow_carp_is_dpm_running(struct smu_context *smu)
260 {
261 int ret = 0;
262 struct smu_feature_bits feature_enabled;
263
264 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
265
266 if (ret)
267 return false;
268
269 return smu_feature_bits_test_mask(&feature_enabled,
270 yellow_carp_dpm_features.bits);
271 }
272
yellow_carp_post_smu_init(struct smu_context * smu)273 static int yellow_carp_post_smu_init(struct smu_context *smu)
274 {
275 struct amdgpu_device *adev = smu->adev;
276 int ret = 0;
277
278 /* allow message will be sent after enable message on Yellow Carp*/
279 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
280 if (ret)
281 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
282 return ret;
283 }
284
yellow_carp_mode_reset(struct smu_context * smu,int type)285 static int yellow_carp_mode_reset(struct smu_context *smu, int type)
286 {
287 int ret = 0;
288
289 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
290 if (ret)
291 dev_err(smu->adev->dev, "Failed to mode reset!\n");
292
293 return ret;
294 }
295
yellow_carp_mode2_reset(struct smu_context * smu)296 static int yellow_carp_mode2_reset(struct smu_context *smu)
297 {
298 return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2);
299 }
300
301
yellow_carp_get_ss_power_percent(SmuMetrics_t * metrics,uint32_t * apu_percent,uint32_t * dgpu_percent)302 static void yellow_carp_get_ss_power_percent(SmuMetrics_t *metrics,
303 uint32_t *apu_percent, uint32_t *dgpu_percent)
304 {
305 uint32_t apu_boost = 0;
306 uint32_t dgpu_boost = 0;
307 uint16_t apu_limit = 0;
308 uint16_t dgpu_limit = 0;
309 uint16_t apu_power = 0;
310 uint16_t dgpu_power = 0;
311
312 /* APU and dGPU power values are reported in milli Watts
313 * and STAPM power limits are in Watts */
314 apu_power = metrics->ApuPower/1000;
315 apu_limit = metrics->StapmOpnLimit;
316 if (apu_power > apu_limit && apu_limit != 0)
317 apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
318 apu_boost = (apu_boost > 100) ? 100 : apu_boost;
319
320 dgpu_power = metrics->dGpuPower/1000;
321 if (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)
322 dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOpnLimit;
323 if (dgpu_power > dgpu_limit && dgpu_limit != 0)
324 dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
325 dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
326
327 if (dgpu_boost >= apu_boost)
328 apu_boost = 0;
329 else
330 dgpu_boost = 0;
331
332 *apu_percent = apu_boost;
333 *dgpu_percent = dgpu_boost;
334
335 }
336
yellow_carp_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)337 static int yellow_carp_get_smu_metrics_data(struct smu_context *smu,
338 MetricsMember_t member,
339 uint32_t *value)
340 {
341 struct smu_table_context *smu_table = &smu->smu_table;
342
343 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
344 int ret = 0;
345 uint32_t apu_percent = 0;
346 uint32_t dgpu_percent = 0;
347
348 ret = smu_cmn_get_metrics_table(smu, NULL, false);
349 if (ret)
350 return ret;
351
352 switch (member) {
353 case METRICS_AVERAGE_GFXCLK:
354 *value = metrics->GfxclkFrequency;
355 break;
356 case METRICS_AVERAGE_SOCCLK:
357 *value = metrics->SocclkFrequency;
358 break;
359 case METRICS_AVERAGE_VCLK:
360 *value = metrics->VclkFrequency;
361 break;
362 case METRICS_AVERAGE_DCLK:
363 *value = metrics->DclkFrequency;
364 break;
365 case METRICS_AVERAGE_UCLK:
366 *value = metrics->MemclkFrequency;
367 break;
368 case METRICS_AVERAGE_GFXACTIVITY:
369 *value = metrics->GfxActivity / 100;
370 break;
371 case METRICS_AVERAGE_VCNACTIVITY:
372 *value = metrics->UvdActivity / 100;
373 break;
374 case METRICS_CURR_SOCKETPOWER:
375 *value = metrics->CurrentSocketPower;
376 break;
377 case METRICS_TEMPERATURE_EDGE:
378 *value = metrics->GfxTemperature / 100 *
379 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
380 break;
381 case METRICS_TEMPERATURE_HOTSPOT:
382 *value = metrics->SocTemperature / 100 *
383 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
384 break;
385 case METRICS_THROTTLER_STATUS:
386 *value = metrics->ThrottlerStatus;
387 break;
388 case METRICS_VOLTAGE_VDDGFX:
389 *value = metrics->Voltage[0];
390 break;
391 case METRICS_VOLTAGE_VDDSOC:
392 *value = metrics->Voltage[1];
393 break;
394 case METRICS_SS_APU_SHARE:
395 /* return the percentage of APU power boost
396 * with respect to APU's power limit.
397 */
398 yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
399 *value = apu_percent;
400 break;
401 case METRICS_SS_DGPU_SHARE:
402 /* return the percentage of dGPU power boost
403 * with respect to dGPU's power limit.
404 */
405 yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
406 *value = dgpu_percent;
407 break;
408 default:
409 *value = UINT_MAX;
410 break;
411 }
412
413 return ret;
414 }
415
yellow_carp_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)416 static int yellow_carp_read_sensor(struct smu_context *smu,
417 enum amd_pp_sensors sensor,
418 void *data, uint32_t *size)
419 {
420 int ret = 0;
421
422 if (!data || !size)
423 return -EINVAL;
424
425 switch (sensor) {
426 case AMDGPU_PP_SENSOR_GPU_LOAD:
427 ret = yellow_carp_get_smu_metrics_data(smu,
428 METRICS_AVERAGE_GFXACTIVITY,
429 (uint32_t *)data);
430 *size = 4;
431 break;
432 case AMDGPU_PP_SENSOR_VCN_LOAD:
433 ret = yellow_carp_get_smu_metrics_data(smu,
434 METRICS_AVERAGE_VCNACTIVITY,
435 (uint32_t *)data);
436 *size = 4;
437 break;
438 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
439 ret = yellow_carp_get_smu_metrics_data(smu,
440 METRICS_CURR_SOCKETPOWER,
441 (uint32_t *)data);
442 *size = 4;
443 break;
444 case AMDGPU_PP_SENSOR_EDGE_TEMP:
445 ret = yellow_carp_get_smu_metrics_data(smu,
446 METRICS_TEMPERATURE_EDGE,
447 (uint32_t *)data);
448 *size = 4;
449 break;
450 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
451 ret = yellow_carp_get_smu_metrics_data(smu,
452 METRICS_TEMPERATURE_HOTSPOT,
453 (uint32_t *)data);
454 *size = 4;
455 break;
456 case AMDGPU_PP_SENSOR_GFX_MCLK:
457 ret = yellow_carp_get_smu_metrics_data(smu,
458 METRICS_AVERAGE_UCLK,
459 (uint32_t *)data);
460 *(uint32_t *)data *= 100;
461 *size = 4;
462 break;
463 case AMDGPU_PP_SENSOR_GFX_SCLK:
464 ret = yellow_carp_get_smu_metrics_data(smu,
465 METRICS_AVERAGE_GFXCLK,
466 (uint32_t *)data);
467 *(uint32_t *)data *= 100;
468 *size = 4;
469 break;
470 case AMDGPU_PP_SENSOR_VDDGFX:
471 ret = yellow_carp_get_smu_metrics_data(smu,
472 METRICS_VOLTAGE_VDDGFX,
473 (uint32_t *)data);
474 *size = 4;
475 break;
476 case AMDGPU_PP_SENSOR_VDDNB:
477 ret = yellow_carp_get_smu_metrics_data(smu,
478 METRICS_VOLTAGE_VDDSOC,
479 (uint32_t *)data);
480 *size = 4;
481 break;
482 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
483 ret = yellow_carp_get_smu_metrics_data(smu,
484 METRICS_SS_APU_SHARE,
485 (uint32_t *)data);
486 *size = 4;
487 break;
488 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
489 ret = yellow_carp_get_smu_metrics_data(smu,
490 METRICS_SS_DGPU_SHARE,
491 (uint32_t *)data);
492 *size = 4;
493 break;
494 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
495 default:
496 ret = -EOPNOTSUPP;
497 break;
498 }
499
500 return ret;
501 }
502
yellow_carp_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)503 static int yellow_carp_set_watermarks_table(struct smu_context *smu,
504 struct pp_smu_wm_range_sets *clock_ranges)
505 {
506 int i;
507 int ret = 0;
508 Watermarks_t *table = smu->smu_table.watermarks_table;
509
510 if (!table || !clock_ranges)
511 return -EINVAL;
512
513 if (clock_ranges) {
514 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
515 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
516 return -EINVAL;
517
518 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
519 table->WatermarkRow[WM_DCFCLK][i].MinClock =
520 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
521 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
522 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
523 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
524 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
525 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
526 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
527
528 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
529 clock_ranges->reader_wm_sets[i].wm_inst;
530 }
531
532 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
533 table->WatermarkRow[WM_SOCCLK][i].MinClock =
534 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
535 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
536 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
537 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
538 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
539 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
540 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
541
542 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
543 clock_ranges->writer_wm_sets[i].wm_inst;
544 }
545
546 smu->watermarks_bitmap |= WATERMARKS_EXIST;
547 }
548
549 /* pass data to smu controller */
550 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
551 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
552 ret = smu_cmn_write_watermarks_table(smu);
553 if (ret) {
554 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
555 return ret;
556 }
557 smu->watermarks_bitmap |= WATERMARKS_LOADED;
558 }
559
560 return 0;
561 }
562
yellow_carp_get_gpu_metrics(struct smu_context * smu,void ** table)563 static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
564 void **table)
565 {
566 struct gpu_metrics_v2_1 *gpu_metrics =
567 (struct gpu_metrics_v2_1 *)smu_driver_table_ptr(
568 smu, SMU_DRIVER_TABLE_GPU_METRICS);
569 SmuMetrics_t metrics;
570 int ret = 0;
571
572 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
573 if (ret)
574 return ret;
575
576 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
577
578 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
579 gpu_metrics->temperature_soc = metrics.SocTemperature;
580 memcpy(&gpu_metrics->temperature_core[0],
581 &metrics.CoreTemperature[0],
582 sizeof(uint16_t) * 8);
583 gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
584
585 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
586 gpu_metrics->average_mm_activity = metrics.UvdActivity;
587
588 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
589 gpu_metrics->average_gfx_power = metrics.Power[0];
590 gpu_metrics->average_soc_power = metrics.Power[1];
591 memcpy(&gpu_metrics->average_core_power[0],
592 &metrics.CorePower[0],
593 sizeof(uint16_t) * 8);
594
595 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
596 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
597 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
598 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
599 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
600 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
601
602 memcpy(&gpu_metrics->current_coreclk[0],
603 &metrics.CoreFrequency[0],
604 sizeof(uint16_t) * 8);
605 gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
606
607 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
608
609 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
610
611 *table = (void *)gpu_metrics;
612
613 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
614
615 return sizeof(struct gpu_metrics_v2_1);
616 }
617
618 /**
619 * yellow_carp_get_gfxoff_status - get gfxoff status
620 *
621 * @smu: smu_context pointer
622 *
623 * This function will be used to get gfxoff status
624 *
625 * Returns 0=GFXOFF(default).
626 * Returns 1=Transition out of GFX State.
627 * Returns 2=Not in GFXOFF.
628 * Returns 3=Transition into GFXOFF.
629 */
yellow_carp_get_gfxoff_status(struct smu_context * smu)630 static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
631 {
632 uint32_t reg;
633 uint32_t gfxoff_status = 0;
634 struct amdgpu_device *adev = smu->adev;
635
636 reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
637 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
638 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
639
640 return gfxoff_status;
641 }
642
yellow_carp_set_default_dpm_tables(struct smu_context * smu)643 static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
644 {
645 struct smu_table_context *smu_table = &smu->smu_table;
646
647 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
648 }
649
yellow_carp_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)650 static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
651 long input[], uint32_t size)
652 {
653 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
654 int ret = 0;
655
656 /* Only allowed in manual mode */
657 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
658 return -EINVAL;
659
660 switch (type) {
661 case PP_OD_EDIT_SCLK_VDDC_TABLE:
662 if (size != 2) {
663 dev_err(smu->adev->dev, "Input parameter number not correct\n");
664 return -EINVAL;
665 }
666
667 if (input[0] == 0) {
668 if (input[1] < smu->gfx_default_hard_min_freq) {
669 dev_warn(smu->adev->dev,
670 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
671 input[1], smu->gfx_default_hard_min_freq);
672 return -EINVAL;
673 }
674 smu->gfx_actual_hard_min_freq = input[1];
675 } else if (input[0] == 1) {
676 if (input[1] > smu->gfx_default_soft_max_freq) {
677 dev_warn(smu->adev->dev,
678 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
679 input[1], smu->gfx_default_soft_max_freq);
680 return -EINVAL;
681 }
682 smu->gfx_actual_soft_max_freq = input[1];
683 } else {
684 return -EINVAL;
685 }
686 break;
687 case PP_OD_RESTORE_DEFAULT_TABLE:
688 if (size != 0) {
689 dev_err(smu->adev->dev, "Input parameter number not correct\n");
690 return -EINVAL;
691 } else {
692 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
693 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
694 }
695 break;
696 case PP_OD_COMMIT_DPM_TABLE:
697 if (size != 0) {
698 dev_err(smu->adev->dev, "Input parameter number not correct\n");
699 return -EINVAL;
700 } else {
701 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
702 dev_err(smu->adev->dev,
703 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
704 smu->gfx_actual_hard_min_freq,
705 smu->gfx_actual_soft_max_freq);
706 return -EINVAL;
707 }
708
709 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
710 smu->gfx_actual_hard_min_freq, NULL);
711 if (ret) {
712 dev_err(smu->adev->dev, "Set hard min sclk failed!");
713 return ret;
714 }
715
716 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
717 smu->gfx_actual_soft_max_freq, NULL);
718 if (ret) {
719 dev_err(smu->adev->dev, "Set soft max sclk failed!");
720 return ret;
721 }
722 }
723 break;
724 default:
725 return -ENOSYS;
726 }
727
728 return ret;
729 }
730
yellow_carp_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)731 static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
732 enum smu_clk_type clk_type,
733 uint32_t *value)
734 {
735 MetricsMember_t member_type;
736
737 switch (clk_type) {
738 case SMU_SOCCLK:
739 member_type = METRICS_AVERAGE_SOCCLK;
740 break;
741 case SMU_VCLK:
742 member_type = METRICS_AVERAGE_VCLK;
743 break;
744 case SMU_DCLK:
745 member_type = METRICS_AVERAGE_DCLK;
746 break;
747 case SMU_MCLK:
748 member_type = METRICS_AVERAGE_UCLK;
749 break;
750 case SMU_FCLK:
751 return smu_cmn_send_smc_msg_with_param(smu,
752 SMU_MSG_GetFclkFrequency, 0, value);
753 case SMU_GFXCLK:
754 case SMU_SCLK:
755 return smu_cmn_send_smc_msg_with_param(smu,
756 SMU_MSG_GetGfxclkFrequency, 0, value);
757 break;
758 default:
759 return -EINVAL;
760 }
761
762 return yellow_carp_get_smu_metrics_data(smu, member_type, value);
763 }
764
yellow_carp_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count)765 static int yellow_carp_get_dpm_level_count(struct smu_context *smu,
766 enum smu_clk_type clk_type,
767 uint32_t *count)
768 {
769 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
770
771 switch (clk_type) {
772 case SMU_SOCCLK:
773 *count = clk_table->NumSocClkLevelsEnabled;
774 break;
775 case SMU_VCLK:
776 *count = clk_table->VcnClkLevelsEnabled;
777 break;
778 case SMU_DCLK:
779 *count = clk_table->VcnClkLevelsEnabled;
780 break;
781 case SMU_MCLK:
782 *count = clk_table->NumDfPstatesEnabled;
783 break;
784 case SMU_FCLK:
785 *count = clk_table->NumDfPstatesEnabled;
786 break;
787 default:
788 return -EINVAL;
789 }
790
791 return 0;
792 }
793
yellow_carp_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)794 static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu,
795 enum smu_clk_type clk_type,
796 uint32_t dpm_level,
797 uint32_t *freq)
798 {
799 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
800
801 if (!clk_table || clk_type >= SMU_CLK_COUNT)
802 return -EINVAL;
803
804 switch (clk_type) {
805 case SMU_SOCCLK:
806 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
807 return -EINVAL;
808 *freq = clk_table->SocClocks[dpm_level];
809 break;
810 case SMU_VCLK:
811 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
812 return -EINVAL;
813 *freq = clk_table->VClocks[dpm_level];
814 break;
815 case SMU_DCLK:
816 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
817 return -EINVAL;
818 *freq = clk_table->DClocks[dpm_level];
819 break;
820 case SMU_UCLK:
821 case SMU_MCLK:
822 if (dpm_level >= clk_table->NumDfPstatesEnabled)
823 return -EINVAL;
824 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
825 break;
826 case SMU_FCLK:
827 if (dpm_level >= clk_table->NumDfPstatesEnabled)
828 return -EINVAL;
829 *freq = clk_table->DfPstateTable[dpm_level].FClk;
830 break;
831 default:
832 return -EINVAL;
833 }
834
835 return 0;
836 }
837
yellow_carp_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)838 static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
839 enum smu_clk_type clk_type)
840 {
841 enum smu_feature_mask feature_id = 0;
842
843 switch (clk_type) {
844 case SMU_MCLK:
845 case SMU_UCLK:
846 case SMU_FCLK:
847 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
848 break;
849 case SMU_GFXCLK:
850 case SMU_SCLK:
851 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
852 break;
853 case SMU_SOCCLK:
854 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
855 break;
856 case SMU_VCLK:
857 case SMU_DCLK:
858 feature_id = SMU_FEATURE_VCN_DPM_BIT;
859 break;
860 default:
861 return true;
862 }
863
864 return smu_cmn_feature_is_enabled(smu, feature_id);
865 }
866
yellow_carp_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)867 static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
868 enum smu_clk_type clk_type,
869 uint32_t *min,
870 uint32_t *max)
871 {
872 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
873 uint32_t clock_limit;
874 uint32_t max_dpm_level, min_dpm_level;
875 int ret = 0;
876
877 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
878 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
879 if (ret)
880 return ret;
881
882 /* clock in Mhz unit */
883 if (min)
884 *min = clock_limit / 100;
885 if (max)
886 *max = clock_limit / 100;
887
888 return 0;
889 }
890
891 if (max) {
892 switch (clk_type) {
893 case SMU_GFXCLK:
894 case SMU_SCLK:
895 *max = clk_table->MaxGfxClk;
896 break;
897 case SMU_MCLK:
898 case SMU_UCLK:
899 case SMU_FCLK:
900 max_dpm_level = 0;
901 break;
902 case SMU_SOCCLK:
903 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
904 break;
905 case SMU_VCLK:
906 case SMU_DCLK:
907 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
908 break;
909 default:
910 ret = -EINVAL;
911 goto failed;
912 }
913
914 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
915 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
916 if (ret)
917 goto failed;
918 }
919 }
920
921 if (min) {
922 switch (clk_type) {
923 case SMU_GFXCLK:
924 case SMU_SCLK:
925 *min = clk_table->MinGfxClk;
926 break;
927 case SMU_MCLK:
928 case SMU_UCLK:
929 case SMU_FCLK:
930 min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
931 break;
932 case SMU_SOCCLK:
933 min_dpm_level = 0;
934 break;
935 case SMU_VCLK:
936 case SMU_DCLK:
937 min_dpm_level = 0;
938 break;
939 default:
940 ret = -EINVAL;
941 goto failed;
942 }
943
944 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
945 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
946 if (ret)
947 goto failed;
948 }
949 }
950
951 failed:
952 return ret;
953 }
954
yellow_carp_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)955 static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
956 enum smu_clk_type clk_type,
957 uint32_t min,
958 uint32_t max,
959 bool automatic)
960 {
961 enum smu_message_type msg_set_min, msg_set_max;
962 uint32_t min_clk = min;
963 uint32_t max_clk = max;
964
965 int ret = 0;
966
967 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
968 return -EINVAL;
969
970 switch (clk_type) {
971 case SMU_GFXCLK:
972 case SMU_SCLK:
973 msg_set_min = SMU_MSG_SetHardMinGfxClk;
974 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
975 break;
976 case SMU_FCLK:
977 msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
978 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
979 break;
980 case SMU_SOCCLK:
981 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
982 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
983 break;
984 case SMU_VCLK:
985 case SMU_DCLK:
986 msg_set_min = SMU_MSG_SetHardMinVcn;
987 msg_set_max = SMU_MSG_SetSoftMaxVcn;
988 break;
989 default:
990 return -EINVAL;
991 }
992
993 if (clk_type == SMU_VCLK) {
994 min_clk = min << SMU_13_VCLK_SHIFT;
995 max_clk = max << SMU_13_VCLK_SHIFT;
996 }
997
998 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
999
1000 if (ret)
1001 goto out;
1002
1003 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
1004 if (ret)
1005 goto out;
1006
1007 out:
1008 return ret;
1009 }
1010
yellow_carp_get_umd_pstate_clk_default(struct smu_context * smu,enum smu_clk_type clk_type)1011 static uint32_t yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu,
1012 enum smu_clk_type clk_type)
1013 {
1014 uint32_t clk_limit = 0;
1015 struct amdgpu_device *adev = smu->adev;
1016
1017 switch (clk_type) {
1018 case SMU_GFXCLK:
1019 case SMU_SCLK:
1020 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8))
1021 clk_limit = SMU_13_0_8_UMD_PSTATE_GFXCLK;
1022 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) ||
1023 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3))
1024 clk_limit = SMU_13_0_1_UMD_PSTATE_GFXCLK;
1025 break;
1026 case SMU_SOCCLK:
1027 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8))
1028 clk_limit = SMU_13_0_8_UMD_PSTATE_SOCCLK;
1029 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) ||
1030 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3))
1031 clk_limit = SMU_13_0_1_UMD_PSTATE_SOCCLK;
1032 break;
1033 case SMU_FCLK:
1034 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8))
1035 clk_limit = SMU_13_0_8_UMD_PSTATE_FCLK;
1036 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) ||
1037 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3))
1038 clk_limit = SMU_13_0_1_UMD_PSTATE_FCLK;
1039 break;
1040 default:
1041 break;
1042 }
1043
1044 return clk_limit;
1045 }
1046
yellow_carp_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)1047 static int yellow_carp_emit_clk_levels(struct smu_context *smu,
1048 enum smu_clk_type clk_type, char *buf,
1049 int *offset)
1050 {
1051 int i, idx, size = *offset, ret = 0, start_offset = *offset;
1052 uint32_t cur_value = 0, value = 0, count = 0;
1053 uint32_t min, max;
1054 uint32_t clk_limit = 0;
1055
1056 switch (clk_type) {
1057 case SMU_OD_SCLK:
1058 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1059 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
1060 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
1061 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
1062 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
1063 break;
1064 case SMU_OD_RANGE:
1065 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1066 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1067 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
1068 break;
1069 case SMU_SOCCLK:
1070 case SMU_VCLK:
1071 case SMU_DCLK:
1072 case SMU_MCLK:
1073 case SMU_FCLK:
1074 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1075 if (ret)
1076 return ret;
1077
1078 ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
1079 if (ret)
1080 return ret;
1081
1082 for (i = 0; i < count; i++) {
1083 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
1084 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value);
1085 if (ret)
1086 return ret;
1087
1088 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1089 cur_value == value ? "*" : "");
1090 }
1091 break;
1092 case SMU_GFXCLK:
1093 case SMU_SCLK:
1094 clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);
1095 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1096 if (ret)
1097 return ret;
1098 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
1099 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
1100 if (cur_value == max)
1101 i = 2;
1102 else if (cur_value == min)
1103 i = 0;
1104 else
1105 i = 1;
1106 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
1107 i == 0 ? "*" : "");
1108 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1109 i == 1 ? cur_value : clk_limit,
1110 i == 1 ? "*" : "");
1111 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
1112 i == 2 ? "*" : "");
1113 break;
1114 default:
1115 break;
1116 }
1117
1118 *offset += size - start_offset;
1119
1120 return 0;
1121 }
1122
yellow_carp_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1123 static int yellow_carp_force_clk_levels(struct smu_context *smu,
1124 enum smu_clk_type clk_type, uint32_t mask)
1125 {
1126 uint32_t soft_min_level = 0, soft_max_level = 0;
1127 uint32_t min_freq = 0, max_freq = 0;
1128 int ret = 0;
1129
1130 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1131 soft_max_level = mask ? (fls(mask) - 1) : 0;
1132
1133 switch (clk_type) {
1134 case SMU_SOCCLK:
1135 case SMU_FCLK:
1136 case SMU_VCLK:
1137 case SMU_DCLK:
1138 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1139 if (ret)
1140 goto force_level_out;
1141
1142 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1143 if (ret)
1144 goto force_level_out;
1145
1146 ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
1147 if (ret)
1148 goto force_level_out;
1149 break;
1150 default:
1151 ret = -EINVAL;
1152 break;
1153 }
1154
1155 force_level_out:
1156 return ret;
1157 }
1158
yellow_carp_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk)1159 static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
1160 enum amd_dpm_forced_level level,
1161 enum smu_clk_type clk_type,
1162 uint32_t *min_clk,
1163 uint32_t *max_clk)
1164 {
1165 int ret = 0;
1166 uint32_t clk_limit = 0;
1167
1168 clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);
1169
1170 switch (clk_type) {
1171 case SMU_GFXCLK:
1172 case SMU_SCLK:
1173 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1174 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
1175 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
1176 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
1177 break;
1178 case SMU_SOCCLK:
1179 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1180 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
1181 break;
1182 case SMU_FCLK:
1183 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1184 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
1185 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
1186 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
1187 break;
1188 case SMU_VCLK:
1189 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
1190 break;
1191 case SMU_DCLK:
1192 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
1193 break;
1194 default:
1195 ret = -EINVAL;
1196 break;
1197 }
1198 *min_clk = *max_clk = clk_limit;
1199 return ret;
1200 }
1201
yellow_carp_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1202 static int yellow_carp_set_performance_level(struct smu_context *smu,
1203 enum amd_dpm_forced_level level)
1204 {
1205 struct amdgpu_device *adev = smu->adev;
1206 uint32_t sclk_min = 0, sclk_max = 0;
1207 uint32_t fclk_min = 0, fclk_max = 0;
1208 uint32_t socclk_min = 0, socclk_max = 0;
1209 uint32_t vclk_min = 0, vclk_max = 0;
1210 uint32_t dclk_min = 0, dclk_max = 0;
1211
1212 int ret = 0;
1213
1214 switch (level) {
1215 case AMD_DPM_FORCED_LEVEL_HIGH:
1216 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1217 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
1218 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1219 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1220 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1221 sclk_min = sclk_max;
1222 fclk_min = fclk_max;
1223 socclk_min = socclk_max;
1224 vclk_min = vclk_max;
1225 dclk_min = dclk_max;
1226 break;
1227 case AMD_DPM_FORCED_LEVEL_LOW:
1228 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1229 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
1230 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1231 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1232 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1233 sclk_max = sclk_min;
1234 fclk_max = fclk_min;
1235 socclk_max = socclk_min;
1236 vclk_max = vclk_min;
1237 dclk_max = dclk_min;
1238 break;
1239 case AMD_DPM_FORCED_LEVEL_AUTO:
1240 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1241 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1242 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1243 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1244 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1245 break;
1246 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1247 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1248 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1249 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1250 yellow_carp_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1251 yellow_carp_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
1252 yellow_carp_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
1253 yellow_carp_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1254 yellow_carp_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1255 break;
1256 case AMD_DPM_FORCED_LEVEL_MANUAL:
1257 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1258 return 0;
1259 default:
1260 dev_err(adev->dev, "Invalid performance level %d\n", level);
1261 return -EINVAL;
1262 }
1263
1264 if (sclk_min && sclk_max) {
1265 ret = yellow_carp_set_soft_freq_limited_range(smu,
1266 SMU_SCLK,
1267 sclk_min,
1268 sclk_max,
1269 false);
1270 if (ret)
1271 return ret;
1272
1273 smu->gfx_actual_hard_min_freq = sclk_min;
1274 smu->gfx_actual_soft_max_freq = sclk_max;
1275 }
1276
1277 if (fclk_min && fclk_max) {
1278 ret = yellow_carp_set_soft_freq_limited_range(smu,
1279 SMU_FCLK,
1280 fclk_min,
1281 fclk_max,
1282 false);
1283 if (ret)
1284 return ret;
1285 }
1286
1287 if (socclk_min && socclk_max) {
1288 ret = yellow_carp_set_soft_freq_limited_range(smu,
1289 SMU_SOCCLK,
1290 socclk_min,
1291 socclk_max,
1292 false);
1293 if (ret)
1294 return ret;
1295 }
1296
1297 if (vclk_min && vclk_max) {
1298 ret = yellow_carp_set_soft_freq_limited_range(smu,
1299 SMU_VCLK,
1300 vclk_min,
1301 vclk_max,
1302 false);
1303 if (ret)
1304 return ret;
1305 }
1306
1307 if (dclk_min && dclk_max) {
1308 ret = yellow_carp_set_soft_freq_limited_range(smu,
1309 SMU_DCLK,
1310 dclk_min,
1311 dclk_max,
1312 false);
1313 if (ret)
1314 return ret;
1315 }
1316
1317 return ret;
1318 }
1319
yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)1320 static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1321 {
1322 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1323
1324 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1325 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1326 smu->gfx_actual_hard_min_freq = 0;
1327 smu->gfx_actual_soft_max_freq = 0;
1328
1329 return 0;
1330 }
1331
1332 static const struct pptable_funcs yellow_carp_ppt_funcs = {
1333 .check_fw_status = smu_v13_0_check_fw_status,
1334 .check_fw_version = smu_cmn_check_fw_version,
1335 .init_smc_tables = yellow_carp_init_smc_tables,
1336 .fini_smc_tables = yellow_carp_fini_smc_tables,
1337 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1338 .system_features_control = yellow_carp_system_features_control,
1339 .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,
1340 .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,
1341 .set_default_dpm_table = yellow_carp_set_default_dpm_tables,
1342 .read_sensor = yellow_carp_read_sensor,
1343 .is_dpm_running = yellow_carp_is_dpm_running,
1344 .set_watermarks_table = yellow_carp_set_watermarks_table,
1345 .get_gpu_metrics = yellow_carp_get_gpu_metrics,
1346 .get_enabled_mask = smu_cmn_get_enabled_mask,
1347 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1348 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1349 .gfx_off_control = smu_v13_0_gfx_off_control,
1350 .get_gfx_off_status = yellow_carp_get_gfxoff_status,
1351 .post_init = yellow_carp_post_smu_init,
1352 .mode2_reset = yellow_carp_mode2_reset,
1353 .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
1354 .od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
1355 .emit_clk_levels = yellow_carp_emit_clk_levels,
1356 .force_clk_levels = yellow_carp_force_clk_levels,
1357 .set_performance_level = yellow_carp_set_performance_level,
1358 .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters,
1359 };
1360
yellow_carp_set_ppt_funcs(struct smu_context * smu)1361 void yellow_carp_set_ppt_funcs(struct smu_context *smu)
1362 {
1363 smu->ppt_funcs = &yellow_carp_ppt_funcs;
1364 smu->feature_map = yellow_carp_feature_mask_map;
1365 smu->table_map = yellow_carp_table_map;
1366 smu->is_apu = true;
1367 smu->smc_driver_if_version = SMU13_YELLOW_CARP_DRIVER_IF_VERSION;
1368 smu_v13_0_init_msg_ctl(smu, yellow_carp_message_map);
1369 }
1370