1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31
32 #include <drm/amdgpu_drm.h>
33
34 #include "amdgpu.h"
35 #include "atom.h"
36 #include "amdgpu_trace.h"
37
38 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
39 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000)
40
41 /*
42 * IB
43 * IBs (Indirect Buffers) and areas of GPU accessible memory where
44 * commands are stored. You can put a pointer to the IB in the
45 * command ring and the hw will fetch the commands from the IB
46 * and execute them. Generally userspace acceleration drivers
47 * produce command buffers which are send to the kernel and
48 * put in IBs for execution by the requested ring.
49 */
50
51 /**
52 * amdgpu_ib_get - request an IB (Indirect Buffer)
53 *
54 * @adev: amdgpu_device pointer
55 * @vm: amdgpu_vm pointer
56 * @size: requested IB size
57 * @pool_type: IB pool type (delayed, immediate, direct)
58 * @ib: IB object returned
59 *
60 * Request an IB (all asics). IBs are allocated using the
61 * suballocator.
62 * Returns 0 on success, error on failure.
63 */
amdgpu_ib_get(struct amdgpu_device * adev,struct amdgpu_vm * vm,unsigned int size,enum amdgpu_ib_pool_type pool_type,struct amdgpu_ib * ib)64 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
65 unsigned int size, enum amdgpu_ib_pool_type pool_type,
66 struct amdgpu_ib *ib)
67 {
68 int r;
69
70 if (size) {
71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type],
72 &ib->sa_bo, size);
73 if (r) {
74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
75 return r;
76 }
77
78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
79 /* flush the cache before commit the IB */
80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC;
81
82 if (!vm)
83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
84 }
85
86 return 0;
87 }
88
89 /**
90 * amdgpu_ib_free - free an IB (Indirect Buffer)
91 *
92 * @ib: IB object to free
93 * @f: the fence SA bo need wait on for the ib alloation
94 *
95 * Free an IB (all asics).
96 */
amdgpu_ib_free(struct amdgpu_ib * ib,struct dma_fence * f)97 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f)
98 {
99 amdgpu_sa_bo_free(&ib->sa_bo, f);
100 }
101
102 /**
103 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
104 *
105 * @ring: ring index the IB is associated with
106 * @num_ibs: number of IBs to schedule
107 * @ibs: IB objects to schedule
108 * @job: job to schedule
109 * @f: fence created during this submission
110 *
111 * Schedule an IB on the associated ring (all asics).
112 * Returns 0 on success, error on failure.
113 *
114 * On SI, there are two parallel engines fed from the primary ring,
115 * the CE (Constant Engine) and the DE (Drawing Engine). Since
116 * resource descriptors have moved to memory, the CE allows you to
117 * prime the caches while the DE is updating register state so that
118 * the resource descriptors will be already in cache when the draw is
119 * processed. To accomplish this, the userspace driver submits two
120 * IBs, one for the CE and one for the DE. If there is a CE IB (called
121 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
122 * to SI there was just a DE IB.
123 */
amdgpu_ib_schedule(struct amdgpu_ring * ring,unsigned int num_ibs,struct amdgpu_ib * ibs,struct amdgpu_job * job,struct dma_fence ** f)124 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
125 struct amdgpu_ib *ibs, struct amdgpu_job *job,
126 struct dma_fence **f)
127 {
128 struct amdgpu_device *adev = ring->adev;
129 struct amdgpu_ib *ib = &ibs[0];
130 struct dma_fence *tmp = NULL;
131 bool need_ctx_switch;
132 struct amdgpu_vm *vm;
133 uint64_t fence_ctx;
134 uint32_t status = 0, alloc_size;
135 unsigned int fence_flags = 0;
136 bool secure, init_shadow;
137 u64 shadow_va, csa_va, gds_va;
138 int vmid = AMDGPU_JOB_GET_VMID(job);
139 bool need_pipe_sync = false;
140 unsigned int cond_exec;
141
142 unsigned int i;
143 int r = 0;
144
145 if (num_ibs == 0)
146 return -EINVAL;
147
148 /* ring tests don't use a job */
149 if (job) {
150 vm = job->vm;
151 fence_ctx = job->base.s_fence ?
152 job->base.s_fence->scheduled.context : 0;
153 shadow_va = job->shadow_va;
154 csa_va = job->csa_va;
155 gds_va = job->gds_va;
156 init_shadow = job->init_shadow;
157 } else {
158 vm = NULL;
159 fence_ctx = 0;
160 shadow_va = 0;
161 csa_va = 0;
162 gds_va = 0;
163 init_shadow = false;
164 }
165
166 if (!ring->sched.ready && !ring->is_mes_queue) {
167 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
168 return -EINVAL;
169 }
170
171 if (vm && !job->vmid && !ring->is_mes_queue) {
172 dev_err(adev->dev, "VM IB without ID\n");
173 return -EINVAL;
174 }
175
176 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
177 (!ring->funcs->secure_submission_supported)) {
178 dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
179 return -EINVAL;
180 }
181
182 alloc_size = ring->funcs->emit_frame_size + num_ibs *
183 ring->funcs->emit_ib_size;
184
185 r = amdgpu_ring_alloc(ring, alloc_size);
186 if (r) {
187 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
188 return r;
189 }
190
191 need_ctx_switch = ring->current_ctx != fence_ctx;
192 if (ring->funcs->emit_pipeline_sync && job &&
193 ((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) ||
194 need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) {
195
196 need_pipe_sync = true;
197
198 if (tmp)
199 trace_amdgpu_ib_pipe_sync(job, tmp);
200
201 dma_fence_put(tmp);
202 }
203
204 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
205 ring->funcs->emit_mem_sync(ring);
206
207 if (ring->funcs->emit_wave_limit &&
208 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
209 ring->funcs->emit_wave_limit(ring, true);
210
211 if (ring->funcs->insert_start)
212 ring->funcs->insert_start(ring);
213
214 if (job) {
215 r = amdgpu_vm_flush(ring, job, need_pipe_sync);
216 if (r) {
217 amdgpu_ring_undo(ring);
218 return r;
219 }
220 }
221
222 amdgpu_ring_ib_begin(ring);
223
224 if (ring->funcs->emit_gfx_shadow)
225 amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,
226 init_shadow, vmid);
227
228 if (ring->funcs->init_cond_exec)
229 cond_exec = amdgpu_ring_init_cond_exec(ring,
230 ring->cond_exe_gpu_addr);
231
232 amdgpu_device_flush_hdp(adev, ring);
233
234 if (need_ctx_switch)
235 status |= AMDGPU_HAVE_CTX_SWITCH;
236
237 if (job && ring->funcs->emit_cntxcntl) {
238 status |= job->preamble_status;
239 status |= job->preemption_status;
240 amdgpu_ring_emit_cntxcntl(ring, status);
241 }
242
243 /* Setup initial TMZiness and send it off.
244 */
245 secure = false;
246 if (job && ring->funcs->emit_frame_cntl) {
247 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE;
248 amdgpu_ring_emit_frame_cntl(ring, true, secure);
249 }
250
251 for (i = 0; i < num_ibs; ++i) {
252 ib = &ibs[i];
253
254 if (job && ring->funcs->emit_frame_cntl) {
255 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
256 amdgpu_ring_emit_frame_cntl(ring, false, secure);
257 secure = !secure;
258 amdgpu_ring_emit_frame_cntl(ring, true, secure);
259 }
260 }
261
262 amdgpu_ring_emit_ib(ring, job, ib, status);
263 status &= ~AMDGPU_HAVE_CTX_SWITCH;
264 }
265
266 if (job && ring->funcs->emit_frame_cntl)
267 amdgpu_ring_emit_frame_cntl(ring, false, secure);
268
269 amdgpu_device_invalidate_hdp(adev, ring);
270
271 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
272 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
273
274 /* wrap the last IB with fence */
275 if (job && job->uf_addr) {
276 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
277 fence_flags | AMDGPU_FENCE_FLAG_64BIT);
278 }
279
280 if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) {
281 amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);
282 amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr);
283 }
284
285 r = amdgpu_fence_emit(ring, f, job, fence_flags);
286 if (r) {
287 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
288 if (job && job->vmid)
289 amdgpu_vmid_reset(adev, ring->vm_hub, job->vmid);
290 amdgpu_ring_undo(ring);
291 return r;
292 }
293
294 if (ring->funcs->insert_end)
295 ring->funcs->insert_end(ring);
296
297 amdgpu_ring_patch_cond_exec(ring, cond_exec);
298
299 ring->current_ctx = fence_ctx;
300 if (job && ring->funcs->emit_switch_buffer)
301 amdgpu_ring_emit_switch_buffer(ring);
302
303 if (ring->funcs->emit_wave_limit &&
304 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
305 ring->funcs->emit_wave_limit(ring, false);
306
307 amdgpu_ring_ib_end(ring);
308 amdgpu_ring_commit(ring);
309 return 0;
310 }
311
312 /**
313 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
314 *
315 * @adev: amdgpu_device pointer
316 *
317 * Initialize the suballocator to manage a pool of memory
318 * for use as IBs (all asics).
319 * Returns 0 on success, error on failure.
320 */
amdgpu_ib_pool_init(struct amdgpu_device * adev)321 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
322 {
323 int r, i;
324
325 if (adev->ib_pool_ready)
326 return 0;
327
328 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
329 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i],
330 AMDGPU_IB_POOL_SIZE, 256,
331 AMDGPU_GEM_DOMAIN_GTT);
332 if (r)
333 goto error;
334 }
335 adev->ib_pool_ready = true;
336
337 return 0;
338
339 error:
340 while (i--)
341 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
342 return r;
343 }
344
345 /**
346 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
347 *
348 * @adev: amdgpu_device pointer
349 *
350 * Tear down the suballocator managing the pool of memory
351 * for use as IBs (all asics).
352 */
amdgpu_ib_pool_fini(struct amdgpu_device * adev)353 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
354 {
355 int i;
356
357 if (!adev->ib_pool_ready)
358 return;
359
360 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++)
361 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
362 adev->ib_pool_ready = false;
363 }
364
365 /**
366 * amdgpu_ib_ring_tests - test IBs on the rings
367 *
368 * @adev: amdgpu_device pointer
369 *
370 * Test an IB (Indirect Buffer) on each ring.
371 * If the test fails, disable the ring.
372 * Returns 0 on success, error if the primary GFX ring
373 * IB test fails.
374 */
amdgpu_ib_ring_tests(struct amdgpu_device * adev)375 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
376 {
377 long tmo_gfx, tmo_mm;
378 int r, ret = 0;
379 unsigned int i;
380
381 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
382 if (amdgpu_sriov_vf(adev)) {
383 /* for MM engines in hypervisor side they are not scheduled together
384 * with CP and SDMA engines, so even in exclusive mode MM engine could
385 * still running on other VF thus the IB TEST TIMEOUT for MM engines
386 * under SR-IOV should be set to a long time. 8 sec should be enough
387 * for the MM comes back to this VF.
388 */
389 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
390 }
391
392 if (amdgpu_sriov_runtime(adev)) {
393 /* for CP & SDMA engines since they are scheduled together so
394 * need to make the timeout width enough to cover the time
395 * cost waiting for it coming back under RUNTIME only
396 */
397 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
398 } else if (adev->gmc.xgmi.hive_id) {
399 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT;
400 }
401
402 for (i = 0; i < adev->num_rings; ++i) {
403 struct amdgpu_ring *ring = adev->rings[i];
404 long tmo;
405
406 /* KIQ rings don't have an IB test because we never submit IBs
407 * to them and they have no interrupt support.
408 */
409 if (!ring->sched.ready || !ring->funcs->test_ib)
410 continue;
411
412 if (adev->enable_mes &&
413 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
414 continue;
415
416 /* MM engine need more time */
417 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
418 ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
419 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
420 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
421 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
422 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
423 tmo = tmo_mm;
424 else
425 tmo = tmo_gfx;
426
427 r = amdgpu_ring_test_ib(ring, tmo);
428 if (!r) {
429 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n",
430 ring->name);
431 continue;
432 }
433
434 ring->sched.ready = false;
435 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n",
436 ring->name, r);
437
438 if (ring == &adev->gfx.gfx_ring[0]) {
439 /* oh, oh, that's really bad */
440 adev->accel_working = false;
441 return r;
442
443 } else {
444 ret = r;
445 }
446 }
447 return ret;
448 }
449
450 /*
451 * Debugfs info
452 */
453 #if defined(CONFIG_DEBUG_FS)
454
amdgpu_debugfs_sa_info_show(struct seq_file * m,void * unused)455 static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused)
456 {
457 struct amdgpu_device *adev = m->private;
458
459 seq_puts(m, "--------------------- DELAYED ---------------------\n");
460 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED],
461 m);
462 seq_puts(m, "-------------------- IMMEDIATE --------------------\n");
463 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE],
464 m);
465 seq_puts(m, "--------------------- DIRECT ----------------------\n");
466 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m);
467
468 return 0;
469 }
470
471 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info);
472
473 #endif
474
amdgpu_debugfs_sa_init(struct amdgpu_device * adev)475 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
476 {
477 #if defined(CONFIG_DEBUG_FS)
478 struct drm_minor *minor = adev_to_drm(adev)->primary;
479 struct dentry *root = minor->debugfs_root;
480
481 debugfs_create_file("amdgpu_sa_info", 0444, root, adev,
482 &amdgpu_debugfs_sa_info_fops);
483
484 #endif
485 }
486