1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/acpi.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 20 #include <asm/amd/node.h> 21 22 #include "../ops.h" 23 #include "acp.h" 24 #include "acp-dsp-offset.h" 25 26 static bool enable_fw_debug; 27 module_param(enable_fw_debug, bool, 0444); 28 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 29 30 static struct acp_quirk_entry quirk_valve_galileo = { 31 .signed_fw_image = true, 32 .skip_iram_dram_size_mod = true, 33 .post_fw_run_delay = true, 34 }; 35 36 const struct dmi_system_id acp_sof_quirk_table[] = { 37 { 38 /* Steam Deck OLED device */ 39 .matches = { 40 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 41 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 42 }, 43 .driver_data = &quirk_valve_galileo, 44 }, 45 {} 46 }; 47 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 48 49 static void init_dma_descriptor(struct acp_dev_data *adata) 50 { 51 struct snd_sof_dev *sdev = adata->dev; 52 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 53 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 54 unsigned int addr; 55 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr; 56 57 addr = desc->sram_pte_offset + sdev->debug_box.offset + 58 offsetof(struct scratch_reg_conf, dma_desc); 59 60 switch (acp_data->pci_rev) { 61 case ACP70_PCI_ID: 62 case ACP71_PCI_ID: 63 case ACP72_PCI_ID: 64 case ACP7B_PCI_ID: 65 case ACP7F_PCI_ID: 66 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR; 67 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR; 68 break; 69 default: 70 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR; 71 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR; 72 } 73 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); 74 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); 75 } 76 77 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 78 struct dma_descriptor *dscr_info) 79 { 80 struct snd_sof_dev *sdev = adata->dev; 81 unsigned int offset; 82 83 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 84 offsetof(struct scratch_reg_conf, dma_desc) + 85 idx * sizeof(struct dma_descriptor); 86 87 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 88 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 89 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 90 } 91 92 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 93 unsigned int idx, unsigned int dscr_count) 94 { 95 struct snd_sof_dev *sdev = adata->dev; 96 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 97 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 98 unsigned int val, status; 99 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0; 100 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0; 101 int ret; 102 103 switch (acp_data->pci_rev) { 104 case ACP70_PCI_ID: 105 case ACP71_PCI_ID: 106 case ACP72_PCI_ID: 107 case ACP7B_PCI_ID: 108 case ACP7F_PCI_ID: 109 acp_dma_cntl_0 = ACP70_DMA_CNTL_0; 110 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS; 111 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0; 112 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0; 113 acp_dma_prio_0 = ACP70_DMA_PRIO_0; 114 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0; 115 break; 116 default: 117 acp_dma_cntl_0 = ACP_DMA_CNTL_0; 118 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS; 119 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0; 120 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0; 121 acp_dma_prio_0 = ACP_DMA_PRIO_0; 122 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0; 123 } 124 125 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), 126 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 127 128 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val, 129 val & (1 << ch), ACP_REG_POLL_INTERVAL, 130 ACP_REG_POLL_TIMEOUT_US); 131 if (ret < 0) { 132 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 133 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 + 134 ch * sizeof(u32)); 135 136 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 137 return ret; 138 } 139 140 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); 141 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); 142 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); 143 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); 144 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 145 146 return ret; 147 } 148 149 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 150 unsigned int dscr_count, struct dma_descriptor *dscr_info) 151 { 152 struct snd_sof_dev *sdev = adata->dev; 153 int ret; 154 u16 dscr; 155 156 if (!dscr_info || !dscr_count) 157 return -EINVAL; 158 159 for (dscr = 0; dscr < dscr_count; dscr++) 160 configure_dma_descriptor(adata, dscr, dscr_info++); 161 162 ret = config_dma_channel(adata, ch, 0, dscr_count); 163 if (ret < 0) 164 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 165 166 return ret; 167 } 168 169 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 170 unsigned int dest_addr, int dsp_data_size) 171 { 172 struct snd_sof_dev *sdev = adata->dev; 173 unsigned int desc_count, index; 174 int ret; 175 176 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 177 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 178 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 179 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 180 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 181 if (dsp_data_size < ACP_PAGE_SIZE) 182 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 183 } 184 185 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 186 if (ret) 187 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 188 189 /* Clear descriptor array */ 190 for (index = 0; index < desc_count; index++) 191 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 192 193 return ret; 194 } 195 196 /* 197 * psp_mbox_ready- function to poll ready bit of psp mbox 198 * @adata: acp device data 199 * @ack: bool variable to check ready bit status or psp ack 200 */ 201 202 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 203 { 204 struct snd_sof_dev *sdev = adata->dev; 205 int ret, data; 206 207 ret = read_poll_timeout(smn_read_register, data, data > 0 && data & MBOX_READY_MASK, 208 MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_114_REG); 209 210 if (!ret) 211 return 0; 212 213 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 214 215 if (ack) 216 return -ETIMEDOUT; 217 218 return -EBUSY; 219 } 220 221 /* 222 * psp_send_cmd - function to send psp command over mbox 223 * @adata: acp device data 224 * @cmd: non zero integer value for command type 225 */ 226 227 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 228 { 229 struct snd_sof_dev *sdev = adata->dev; 230 int ret; 231 int data; 232 233 if (!cmd) 234 return -EINVAL; 235 236 /* Get a non-zero Doorbell value from PSP */ 237 ret = read_poll_timeout(smn_read_register, data, data > 0, MBOX_DELAY_US, 238 ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_73_REG); 239 240 if (ret) { 241 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 242 return ret; 243 } 244 245 /* Check if PSP is ready for new command */ 246 ret = psp_mbox_ready(adata, 0); 247 if (ret) 248 return ret; 249 250 ret = amd_smn_write(0, MP0_C2PMSG_114_REG, cmd); 251 if (ret) 252 return ret; 253 254 /* Ring the Doorbell for PSP */ 255 ret = amd_smn_write(0, MP0_C2PMSG_73_REG, data); 256 if (ret) 257 return ret; 258 259 /* Check MBOX ready as PSP ack */ 260 ret = psp_mbox_ready(adata, 1); 261 262 return ret; 263 } 264 265 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 266 unsigned int start_addr, unsigned int dest_addr, 267 unsigned int image_length) 268 { 269 struct snd_sof_dev *sdev = adata->dev; 270 unsigned int tx_count, fw_qualifier, val; 271 int ret; 272 273 if (!image_addr) { 274 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 275 return -EINVAL; 276 } 277 278 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 279 if (val & ACP_SHA_RUN) { 280 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 281 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 282 val, val & ACP_SHA_RESET, 283 ACP_REG_POLL_INTERVAL, 284 ACP_REG_POLL_TIMEOUT_US); 285 if (ret < 0) { 286 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 287 return ret; 288 } 289 } 290 291 if ((adata->quirks && adata->quirks->signed_fw_image) || 292 adata->acp_sof_signed_firmware_image) 293 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 294 295 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 296 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 297 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 298 299 /* psp_send_cmd only required for vangogh platform */ 300 if (adata->pci_rev == ACP_VANGOGH_PCI_ID && 301 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 302 /* Modify IRAM and DRAM size */ 303 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 304 if (ret) 305 return ret; 306 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 307 if (ret) 308 return ret; 309 } 310 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 311 312 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 313 tx_count, tx_count == image_length, 314 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 315 if (ret < 0) { 316 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 317 return ret; 318 } 319 320 /* psp_send_cmd only required for renoir platform*/ 321 if (adata->pci_rev == ACP_RN_PCI_ID) { 322 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 323 if (ret) 324 return ret; 325 } 326 327 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 328 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 329 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 330 if (ret < 0) { 331 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK); 332 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n", 333 fw_qualifier, val); 334 return ret; 335 } 336 337 return 0; 338 } 339 340 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 341 { 342 struct snd_sof_dev *sdev = adata->dev; 343 unsigned int val; 344 unsigned int acp_dma_ch_sts; 345 int ret = 0; 346 347 switch (adata->pci_rev) { 348 case ACP70_PCI_ID: 349 case ACP71_PCI_ID: 350 case ACP72_PCI_ID: 351 case ACP7B_PCI_ID: 352 case ACP7F_PCI_ID: 353 acp_dma_ch_sts = ACP70_DMA_CH_STS; 354 break; 355 default: 356 acp_dma_ch_sts = ACP_DMA_CH_STS; 357 } 358 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 359 if (val & ACP_DMA_CH_RUN) { 360 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val, 361 ACP_REG_POLL_INTERVAL, 362 ACP_DMA_COMPLETE_TIMEOUT_US); 363 if (ret < 0) 364 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 365 } 366 367 return ret; 368 } 369 370 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 371 { 372 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 373 int i, j; 374 375 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 376 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 377 } 378 379 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 380 { 381 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 382 int i, j; 383 384 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 385 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 386 } 387 388 static int acp_init_scratch_mem_ipc_flags(struct snd_sof_dev *sdev) 389 { 390 u32 dsp_msg_write, dsp_ack_write, host_msg_write, host_ack_write; 391 392 dsp_msg_write = sdev->debug_box.offset + 393 offsetof(struct scratch_ipc_conf, sof_dsp_msg_write); 394 dsp_ack_write = sdev->debug_box.offset + 395 offsetof(struct scratch_ipc_conf, sof_dsp_ack_write); 396 host_msg_write = sdev->debug_box.offset + 397 offsetof(struct scratch_ipc_conf, sof_host_msg_write); 398 host_ack_write = sdev->debug_box.offset + 399 offsetof(struct scratch_ipc_conf, sof_host_ack_write); 400 /* Initialize host message write flag */ 401 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg_write, 0); 402 403 /* Initialize host ack write flag */ 404 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_ack_write, 0); 405 406 /* Initialize DSP message write flag */ 407 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write, 0); 408 409 /* Initialize DSP ack write flag */ 410 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write, 0); 411 412 return 0; 413 } 414 415 static int acp_memory_init(struct snd_sof_dev *sdev) 416 { 417 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 418 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 419 420 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 421 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 422 acp_init_scratch_mem_ipc_flags(sdev); 423 init_dma_descriptor(adata); 424 425 return 0; 426 } 427 428 static void amd_sof_handle_acp70_sdw_wake_event(struct acp_dev_data *adata) 429 { 430 struct amd_sdw_manager *amd_manager; 431 432 if (adata->acp70_sdw0_wake_event) { 433 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 434 if (amd_manager) 435 pm_request_resume(amd_manager->dev); 436 adata->acp70_sdw0_wake_event = 0; 437 } 438 439 if (adata->acp70_sdw1_wake_event) { 440 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 441 if (amd_manager) 442 pm_request_resume(amd_manager->dev); 443 adata->acp70_sdw1_wake_event = 0; 444 } 445 } 446 447 static int amd_sof_check_and_handle_acp70_sdw_wake_irq(struct snd_sof_dev *sdev) 448 { 449 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 450 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 451 u32 ext_intr_stat1; 452 int irq_flag = 0; 453 bool sdw_wake_irq = false; 454 455 ext_intr_stat1 = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 456 if (ext_intr_stat1 & ACP70_SDW0_HOST_WAKE_STAT) { 457 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 458 ACP70_SDW0_HOST_WAKE_STAT); 459 adata->acp70_sdw0_wake_event = true; 460 sdw_wake_irq = true; 461 } 462 463 if (ext_intr_stat1 & ACP70_SDW1_HOST_WAKE_STAT) { 464 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 465 ACP70_SDW1_HOST_WAKE_STAT); 466 adata->acp70_sdw1_wake_event = true; 467 sdw_wake_irq = true; 468 } 469 470 if (ext_intr_stat1 & ACP70_SDW0_PME_STAT) { 471 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN, 0); 472 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW0_PME_STAT); 473 adata->acp70_sdw0_wake_event = true; 474 sdw_wake_irq = true; 475 } 476 477 if (ext_intr_stat1 & ACP70_SDW1_PME_STAT) { 478 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN, 0); 479 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW1_PME_STAT); 480 adata->acp70_sdw1_wake_event = true; 481 sdw_wake_irq = true; 482 } 483 484 if (sdw_wake_irq) { 485 amd_sof_handle_acp70_sdw_wake_event(adata); 486 irq_flag = 1; 487 } 488 return irq_flag; 489 } 490 491 static irqreturn_t acp_irq_thread(int irq, void *context) 492 { 493 struct snd_sof_dev *sdev = context; 494 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 495 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 496 497 spin_lock_irq(&sdev->ipc_lock); 498 /* Wait until acquired HW Semaphore lock or timeout */ 499 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 500 ; 501 spin_unlock_irq(&sdev->ipc_lock); 502 503 if (!count) { 504 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 505 return IRQ_NONE; 506 } 507 508 sof_ops(sdev)->irq_thread(irq, sdev); 509 /* Unlock or Release HW Semaphore */ 510 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 511 512 return IRQ_HANDLED; 513 }; 514 515 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 516 { 517 struct amd_sdw_manager *amd_manager; 518 struct snd_sof_dev *sdev = dev_id; 519 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 520 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 521 unsigned int base = desc->dsp_intr_base; 522 unsigned int val; 523 int irq_flag = 0, wake_irq_flag = 0; 524 525 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 526 if (val & ACP_DSP_TO_HOST_IRQ) { 527 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 528 ACP_DSP_TO_HOST_IRQ); 529 return IRQ_WAKE_THREAD; 530 } 531 532 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 533 if (val & ACP_SDW0_IRQ_MASK) { 534 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 535 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 536 if (amd_manager) 537 schedule_work(&amd_manager->amd_sdw_irq_thread); 538 irq_flag = 1; 539 } 540 541 if (val & ACP_ERROR_IRQ_MASK) { 542 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 543 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 544 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 545 switch (adata->pci_rev) { 546 case ACP_RMB_PCI_ID: 547 case ACP63_PCI_ID: 548 case ACP70_PCI_ID: 549 case ACP71_PCI_ID: 550 case ACP72_PCI_ID: 551 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 552 break; 553 default: 554 break; 555 } 556 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 557 irq_flag = 1; 558 } 559 560 if (desc->ext_intr_stat1) { 561 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 562 if (val & ACP_SDW1_IRQ_MASK) { 563 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 564 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 565 ACP_SDW1_IRQ_MASK); 566 if (amd_manager) 567 schedule_work(&amd_manager->amd_sdw_irq_thread); 568 irq_flag = 1; 569 } 570 switch (adata->pci_rev) { 571 case ACP70_PCI_ID: 572 case ACP71_PCI_ID: 573 case ACP72_PCI_ID: 574 wake_irq_flag = amd_sof_check_and_handle_acp70_sdw_wake_irq(sdev); 575 break; 576 } 577 } 578 if (irq_flag || wake_irq_flag) 579 return IRQ_HANDLED; 580 else 581 return IRQ_NONE; 582 } 583 584 static irqreturn_t acp7x_irq_handler(int irq, void *dev_id) 585 { 586 struct snd_sof_dev *sdev = dev_id; 587 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 588 unsigned int base = desc->dsp_intr_base; 589 unsigned int val; 590 unsigned int ext_intr_stat; 591 int irq_flag = 0; 592 593 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 594 if (val & ACP_DSP_TO_HOST_IRQ) { 595 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 596 ACP_DSP_TO_HOST_IRQ); 597 return IRQ_WAKE_THREAD; 598 } 599 600 ext_intr_stat = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 601 if (ext_intr_stat & ACP_ERROR_IRQ_MASK) { 602 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 603 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 604 irq_flag = 1; 605 } 606 607 if (irq_flag) 608 return IRQ_HANDLED; 609 610 return IRQ_NONE; 611 } 612 613 static int acp_power_on(struct snd_sof_dev *sdev) 614 { 615 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 616 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 617 unsigned int base = desc->pgfsm_base; 618 unsigned int val; 619 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask; 620 bool use_masked_status = false; 621 int ret; 622 623 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 624 625 if (val == ACP_POWERED_ON) 626 return 0; 627 628 switch (adata->pci_rev) { 629 case ACP_RN_PCI_ID: 630 case ACP_VANGOGH_PCI_ID: 631 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK; 632 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK; 633 break; 634 case ACP_RMB_PCI_ID: 635 case ACP63_PCI_ID: 636 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK; 637 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK; 638 break; 639 case ACP70_PCI_ID: 640 case ACP71_PCI_ID: 641 case ACP72_PCI_ID: 642 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK; 643 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK; 644 break; 645 case ACP7B_PCI_ID: 646 case ACP7F_PCI_ID: 647 acp_pgfsm_status_mask = ACP7X_PGFSM_STATUS_MASK; 648 acp_pgfsm_cntl_mask = ACP7X_PGFSM_CNTL_POWER_ON_MASK; 649 use_masked_status = true; 650 break; 651 default: 652 return -EINVAL; 653 } 654 655 if (val & acp_pgfsm_status_mask) 656 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 657 acp_pgfsm_cntl_mask); 658 659 if (use_masked_status) 660 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, 661 base + PGFSM_STATUS_OFFSET, val, 662 !(val & acp_pgfsm_status_mask), 663 ACP_REG_POLL_INTERVAL, 664 ACP_REG_POLL_TIMEOUT_US); 665 else 666 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, 667 base + PGFSM_STATUS_OFFSET, val, 668 !val, ACP_REG_POLL_INTERVAL, 669 ACP_REG_POLL_TIMEOUT_US); 670 if (ret < 0) 671 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 672 673 return ret; 674 } 675 676 static int acp_reset(struct snd_sof_dev *sdev) 677 { 678 unsigned int val; 679 int ret; 680 681 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 682 683 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 684 val & ACP_SOFT_RESET_DONE_MASK, 685 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 686 if (ret < 0) { 687 dev_err(sdev->dev, "timeout asserting reset\n"); 688 return ret; 689 } 690 691 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 692 693 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 694 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 695 if (ret < 0) 696 dev_err(sdev->dev, "timeout in releasing reset\n"); 697 698 return ret; 699 } 700 701 static int acp_dsp_reset(struct snd_sof_dev *sdev) 702 { 703 unsigned int val; 704 int ret; 705 706 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 707 708 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 709 val & ACP_DSP_SOFT_RESET_DONE_MASK, 710 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 711 if (ret < 0) { 712 dev_err(sdev->dev, "timeout asserting reset\n"); 713 return ret; 714 } 715 716 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 717 718 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 719 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 720 if (ret < 0) 721 dev_err(sdev->dev, "timeout in releasing reset\n"); 722 723 return ret; 724 } 725 726 static int acp_init(struct snd_sof_dev *sdev) 727 { 728 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 729 struct acp_dev_data *acp_data; 730 unsigned int sdw0_wake_en, sdw1_wake_en; 731 int ret; 732 733 /* power on */ 734 acp_data = sdev->pdata->hw_pdata; 735 ret = acp_power_on(sdev); 736 if (ret) { 737 dev_err(sdev->dev, "ACP power on failed\n"); 738 return ret; 739 } 740 741 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 742 /* Reset */ 743 ret = acp_reset(sdev); 744 if (ret) 745 return ret; 746 747 if (desc->acp_clkmux_sel) 748 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 749 750 if (desc->ext_intr_enb) 751 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 752 753 if (desc->ext_intr_cntl) 754 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 755 756 switch (acp_data->pci_rev) { 757 case ACP70_PCI_ID: 758 case ACP71_PCI_ID: 759 case ACP72_PCI_ID: 760 sdw0_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN); 761 sdw1_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN); 762 if (sdw0_wake_en || sdw1_wake_en) 763 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP70_EXTERNAL_INTR_CNTL1, 764 ACP70_SDW_HOST_WAKE_MASK, ACP70_SDW_HOST_WAKE_MASK); 765 766 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1); 767 break; 768 case ACP7B_PCI_ID: 769 case ACP7F_PCI_ID: 770 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_ZSC_DSP_CTRL, 0); 771 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_PME_EN, 1); 772 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_DSP0_IDMA_ERROR_MASK, 773 ACP7X_IDMA_ERROR_MASK); 774 break; 775 } 776 return 0; 777 } 778 779 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 780 { 781 struct acp_dev_data *acp_data; 782 u32 sdw0_en, sdw1_en; 783 784 acp_data = sdev->pdata->hw_pdata; 785 if (!acp_data->sdw) 786 return false; 787 788 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 789 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 790 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 791 return acp_data->sdw_en_stat; 792 } 793 794 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 795 { 796 struct acp_dev_data *acp_data; 797 int ret; 798 bool enable = false; 799 800 acp_data = sdev->pdata->hw_pdata; 801 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 802 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 803 * be reset to default values which will break the ClockStop Mode functionality. 804 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 805 * is selected. For the rest of the scenarios, apply acp reset sequence. 806 */ 807 if (check_acp_sdw_enable_status(sdev)) 808 return acp_dsp_reset(sdev); 809 810 ret = acp_reset(sdev); 811 if (ret) { 812 dev_err(sdev->dev, "ACP Reset failed\n"); 813 return ret; 814 } 815 switch (acp_data->pci_rev) { 816 case ACP70_PCI_ID: 817 case ACP71_PCI_ID: 818 case ACP72_PCI_ID: 819 enable = true; 820 break; 821 default: 822 break; 823 } 824 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 825 826 return 0; 827 } 828 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, "SND_SOC_SOF_AMD_COMMON"); 829 830 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 831 { 832 int ret; 833 struct acp_dev_data *acp_data; 834 835 acp_data = sdev->pdata->hw_pdata; 836 if (!acp_data->sdw_en_stat) { 837 ret = acp_init(sdev); 838 if (ret) { 839 dev_err(sdev->dev, "ACP Init failed\n"); 840 return ret; 841 } 842 return acp_memory_init(sdev); 843 } 844 switch (acp_data->pci_rev) { 845 case ACP70_PCI_ID: 846 case ACP71_PCI_ID: 847 case ACP72_PCI_ID: 848 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1); 849 break; 850 } 851 852 return acp_dsp_reset(sdev); 853 } 854 EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON"); 855 856 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 857 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 858 { 859 struct acpi_device *sdw_dev; 860 struct acp_dev_data *acp_data; 861 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 862 863 if (!addr) 864 return -ENODEV; 865 866 acp_data = sdev->pdata->hw_pdata; 867 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 868 if (!sdw_dev) 869 return -ENODEV; 870 871 acp_data->info.handle = sdw_dev->handle; 872 acp_data->info.count = desc->sdw_max_link_count; 873 874 return amd_sdw_scan_controller(&acp_data->info); 875 } 876 877 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 878 { 879 struct acp_dev_data *acp_data; 880 struct sdw_amd_res sdw_res; 881 int ret; 882 883 acp_data = sdev->pdata->hw_pdata; 884 885 memset(&sdw_res, 0, sizeof(sdw_res)); 886 sdw_res.addr = acp_data->addr; 887 sdw_res.reg_range = acp_data->reg_range; 888 sdw_res.handle = acp_data->info.handle; 889 sdw_res.parent = sdev->dev; 890 sdw_res.dev = sdev->dev; 891 sdw_res.acp_lock = &acp_data->acp_lock; 892 sdw_res.count = acp_data->info.count; 893 sdw_res.link_mask = acp_data->info.link_mask; 894 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 895 sdw_res.acp_rev = acp_data->pci_rev; 896 897 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 898 if (ret) 899 dev_err(sdev->dev, "SoundWire probe failed\n"); 900 return ret; 901 } 902 903 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 904 { 905 struct acp_dev_data *acp_data; 906 907 acp_data = sdev->pdata->hw_pdata; 908 if (acp_data->sdw) 909 sdw_amd_exit(acp_data->sdw); 910 acp_data->sdw = NULL; 911 912 return 0; 913 } 914 915 #else 916 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 917 { 918 return 0; 919 } 920 921 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 922 { 923 return 0; 924 } 925 926 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 927 { 928 return 0; 929 } 930 #endif 931 932 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 933 { 934 struct pci_dev *pci = to_pci_dev(sdev->dev); 935 struct acp_dev_data *adata; 936 const struct sof_amd_acp_desc *chip; 937 const struct dmi_system_id *dmi_id; 938 unsigned int addr; 939 int ret; 940 941 chip = get_chip_info(sdev->pdata); 942 if (!chip) { 943 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 944 return -EIO; 945 } 946 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 947 GFP_KERNEL); 948 if (!adata) 949 return -ENOMEM; 950 951 adata->dev = sdev; 952 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 953 PLATFORM_DEVID_NONE, NULL, 0); 954 if (IS_ERR(adata->dmic_dev)) { 955 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 956 return PTR_ERR(adata->dmic_dev); 957 } 958 addr = pci_resource_start(pci, ACP_DSP_BAR); 959 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 960 if (!sdev->bar[ACP_DSP_BAR]) { 961 dev_err(sdev->dev, "ioremap error\n"); 962 ret = -ENXIO; 963 goto unregister_dev; 964 } 965 966 pci_set_master(pci); 967 adata->addr = addr; 968 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 969 adata->pci_rev = pci->revision; 970 mutex_init(&adata->acp_lock); 971 sdev->pdata->hw_pdata = adata; 972 973 ret = acp_init(sdev); 974 if (ret < 0) 975 goto unregister_dev; 976 977 sdev->ipc_irq = pci->irq; 978 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 979 IRQF_SHARED, "AudioDSP", sdev); 980 if (ret < 0) { 981 dev_err(sdev->dev, "failed to register IRQ %d\n", 982 sdev->ipc_irq); 983 goto unregister_dev; 984 } 985 986 /* scan SoundWire capabilities exposed by DSDT */ 987 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 988 if (ret < 0) { 989 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 990 goto skip_soundwire; 991 } 992 ret = amd_sof_sdw_probe(sdev); 993 if (ret < 0) { 994 dev_err(sdev->dev, "error: SoundWire probe error\n"); 995 free_irq(sdev->ipc_irq, sdev); 996 return ret; 997 } 998 999 skip_soundwire: 1000 sdev->dsp_box.offset = 0; 1001 sdev->dsp_box.size = BOX_SIZE_512; 1002 1003 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 1004 sdev->host_box.size = BOX_SIZE_512; 1005 1006 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 1007 sdev->debug_box.size = BOX_SIZE_1024; 1008 1009 dmi_id = dmi_first_match(acp_sof_quirk_table); 1010 if (dmi_id) { 1011 adata->quirks = dmi_id->driver_data; 1012 1013 if (adata->quirks->signed_fw_image) { 1014 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1015 "sof-%s-code.bin", 1016 chip->name); 1017 if (!adata->fw_code_bin) { 1018 ret = -ENOMEM; 1019 goto free_ipc_irq; 1020 } 1021 1022 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1023 "sof-%s-data.bin", 1024 chip->name); 1025 if (!adata->fw_data_bin) { 1026 ret = -ENOMEM; 1027 goto free_ipc_irq; 1028 } 1029 } 1030 } 1031 1032 adata->enable_fw_debug = enable_fw_debug; 1033 acp_memory_init(sdev); 1034 1035 acp_dsp_stream_init(sdev); 1036 1037 return 0; 1038 1039 free_ipc_irq: 1040 free_irq(sdev->ipc_irq, sdev); 1041 unregister_dev: 1042 platform_device_unregister(adata->dmic_dev); 1043 return ret; 1044 } 1045 EXPORT_SYMBOL_NS(amd_sof_acp_probe, "SND_SOC_SOF_AMD_COMMON"); 1046 1047 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 1048 { 1049 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 1050 1051 if (adata->sdw) 1052 amd_sof_sdw_exit(sdev); 1053 1054 if (sdev->ipc_irq) 1055 free_irq(sdev->ipc_irq, sdev); 1056 1057 if (adata->dmic_dev) 1058 platform_device_unregister(adata->dmic_dev); 1059 1060 acp_reset(sdev); 1061 } 1062 EXPORT_SYMBOL_NS(amd_sof_acp_remove, "SND_SOC_SOF_AMD_COMMON"); 1063 1064 int amd_sof_acp7x_probe(struct snd_sof_dev *sdev) 1065 { 1066 struct pci_dev *pci = to_pci_dev(sdev->dev); 1067 struct acp_dev_data *adata; 1068 const struct sof_amd_acp_desc *chip; 1069 const union acpi_object *obj; 1070 struct acpi_device *adev; 1071 unsigned int addr; 1072 unsigned int irqflags; 1073 int ret; 1074 1075 chip = get_chip_info(sdev->pdata); 1076 if (!chip) { 1077 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 1078 return -EIO; 1079 } 1080 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), GFP_KERNEL); 1081 if (!adata) 1082 return -ENOMEM; 1083 1084 adata->dev = sdev; 1085 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1086 PLATFORM_DEVID_NONE, NULL, 0); 1087 if (IS_ERR(adata->dmic_dev)) { 1088 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 1089 return PTR_ERR(adata->dmic_dev); 1090 } 1091 1092 addr = pci_resource_start(pci, ACP_DSP_BAR); 1093 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 1094 if (!sdev->bar[ACP_DSP_BAR]) { 1095 dev_err(sdev->dev, "ioremap error\n"); 1096 ret = -ENXIO; 1097 goto unregister_dev; 1098 } 1099 1100 pci_set_master(pci); 1101 adata->addr = addr; 1102 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 1103 adata->pci_rev = pci->revision; 1104 mutex_init(&adata->acp_lock); 1105 sdev->pdata->hw_pdata = adata; 1106 1107 ret = acp_init(sdev); 1108 if (ret < 0) 1109 goto unregister_dev; 1110 1111 adev = ACPI_COMPANION(&pci->dev); 1112 1113 sdev->ipc_irq = pci->irq; 1114 irqflags = IRQF_SHARED; 1115 1116 ret = request_threaded_irq(pci->irq, acp7x_irq_handler, acp_irq_thread, 1117 irqflags, "AudioDSP", sdev); 1118 if (ret < 0) { 1119 dev_err(sdev->dev, "failed to register IRQ %d\n", sdev->ipc_irq); 1120 goto unregister_dev; 1121 } 1122 1123 if (adev) { 1124 if (!acpi_dev_get_property(adev, "acp-sof-signed-firmware-image", 1125 ACPI_TYPE_INTEGER, &obj)) 1126 adata->acp_sof_signed_firmware_image = obj->integer.value; 1127 } 1128 1129 sdev->dsp_box.offset = 0; 1130 sdev->dsp_box.size = BOX_SIZE_512; 1131 1132 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 1133 sdev->host_box.size = BOX_SIZE_512; 1134 1135 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 1136 sdev->debug_box.size = BOX_SIZE_1024; 1137 1138 if (adata->acp_sof_signed_firmware_image) { 1139 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1140 "sof-%s-code.bin", chip->name); 1141 if (!adata->fw_code_bin) { 1142 ret = -ENOMEM; 1143 goto free_ipc_irq; 1144 } 1145 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1146 "sof-%s-data.bin", chip->name); 1147 if (!adata->fw_data_bin) { 1148 ret = -ENOMEM; 1149 goto free_ipc_irq; 1150 } 1151 } 1152 1153 adata->enable_fw_debug = enable_fw_debug; 1154 acp_memory_init(sdev); 1155 acp_dsp_stream_init(sdev); 1156 1157 return 0; 1158 1159 free_ipc_irq: 1160 free_irq(sdev->ipc_irq, sdev); 1161 unregister_dev: 1162 platform_device_unregister(adata->dmic_dev); 1163 return ret; 1164 } 1165 EXPORT_SYMBOL_NS(amd_sof_acp7x_probe, "SND_SOC_SOF_AMD_COMMON"); 1166 1167 void amd_sof_acp7x_remove(struct snd_sof_dev *sdev) 1168 { 1169 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 1170 1171 if (sdev->ipc_irq) 1172 free_irq(sdev->ipc_irq, sdev); 1173 1174 if (adata->dmic_dev) 1175 platform_device_unregister(adata->dmic_dev); 1176 1177 acp_reset(sdev); 1178 } 1179 EXPORT_SYMBOL_NS(amd_sof_acp7x_remove, "SND_SOC_SOF_AMD_COMMON"); 1180 1181 int amd_sof_acp7x_suspend(struct snd_sof_dev *sdev, u32 target_state) 1182 { 1183 struct acp_dev_data *acp_data; 1184 int ret; 1185 bool enable = false; 1186 1187 acp_data = sdev->pdata->hw_pdata; 1188 1189 ret = acp_reset(sdev); 1190 if (ret) { 1191 dev_err(sdev->dev, "ACP Reset failed\n"); 1192 return ret; 1193 } 1194 switch (acp_data->pci_rev) { 1195 case ACP7B_PCI_ID: 1196 case ACP7F_PCI_ID: 1197 enable = true; 1198 break; 1199 default: 1200 break; 1201 } 1202 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 1203 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_ZSC_DSP_CTRL, 1); 1204 1205 return 0; 1206 } 1207 EXPORT_SYMBOL_NS(amd_sof_acp7x_suspend, "SND_SOC_SOF_AMD_COMMON"); 1208 1209 int amd_sof_acp7x_resume(struct snd_sof_dev *sdev) 1210 { 1211 struct acp_dev_data *acp_data; 1212 int ret; 1213 1214 acp_data = sdev->pdata->hw_pdata; 1215 1216 ret = acp_init(sdev); 1217 if (ret) { 1218 dev_err(sdev->dev, "ACP Init failed\n"); 1219 return ret; 1220 } 1221 ret = acp_memory_init(sdev); 1222 if (ret) { 1223 dev_err(sdev->dev, "ACP Memory init failed\n"); 1224 return ret; 1225 } 1226 1227 switch (acp_data->pci_rev) { 1228 case ACP7B_PCI_ID: 1229 case ACP7F_PCI_ID: 1230 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_PME_EN, 1); 1231 break; 1232 default: 1233 break; 1234 } 1235 1236 return 0; 1237 } 1238 EXPORT_SYMBOL_NS(amd_sof_acp7x_resume, "SND_SOC_SOF_AMD_COMMON"); 1239 1240 int amd_sof_acp7x_suspend_runtime(struct snd_sof_dev *sdev) 1241 { 1242 return amd_sof_acp7x_suspend(sdev, 0); 1243 } 1244 EXPORT_SYMBOL_NS(amd_sof_acp7x_suspend_runtime, "SND_SOC_SOF_AMD_COMMON"); 1245 1246 int amd_sof_acp7x_resume_runtime(struct snd_sof_dev *sdev) 1247 { 1248 return amd_sof_acp7x_resume(sdev); 1249 } 1250 EXPORT_SYMBOL_NS(amd_sof_acp7x_resume_runtime, "SND_SOC_SOF_AMD_COMMON"); 1251 1252 MODULE_LICENSE("Dual BSD/GPL"); 1253 MODULE_DESCRIPTION("AMD ACP sof driver"); 1254 MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT"); 1255 MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI"); 1256